Display device

Abstract

The present invention provides a display device including: a plurality of island units spaced apart from each other; a first bridge unit connecting island units adjacent to each other in the first direction among the plurality of island units, and including a first voltage line, a second voltage line, and a third voltage line; and a second bridge unit connecting island units adjacent to each other in a second direction crossing the first direction among the plurality of island units, and including a fourth voltage line electrically connected to the first voltage line, a fifth voltage line electrically connected to the second voltage line, and a sixth voltage line electrically connected to the third voltage line, a first voltage line and a fourth voltage line are disposed on the first conductive layer, and a second voltage line, a fifth voltage line, a third voltage line, and a sixth voltage line are disposed in the second conductive layer on the first conductive layer.

Description

Technical Field

[0001] One or more embodiments relate to a flexible display device. Background Technology

[0002] With the development of display devices that visually display electrical signals, various display devices with excellent characteristics such as thinness, light weight, and low power consumption have been introduced. For example, flexible display devices that are foldable or rollable have been introduced. Recently, stretchable display devices that can be deformed into various shapes have been researched and developed. Summary of the Invention

[0003] Technical issues One or more embodiments include a flexible display device, such as a stretchable display device.

[0004] Solution According to one or more embodiments, a display device includes: a plurality of islands separated from each other; a first bridging portion connecting the islands that are adjacent to each other in a first direction, wherein the first bridging portion includes a first voltage line, a second voltage line, and a third voltage line; and a second bridging portion connecting the islands that are adjacent to each other in a second direction intersecting the first direction, wherein the second bridging portion includes a fourth voltage line electrically connected to the first voltage line, a fifth voltage line electrically connected to the second voltage line, and a sixth voltage line electrically connected to the third voltage line, wherein the first voltage line and the fourth voltage line are disposed in a first conductive layer, and the second voltage line, the fifth voltage line, the third voltage line, and the sixth voltage line are disposed in a second conductive layer on the first conductive layer.

[0005] In an embodiment, the first voltage line and the fourth voltage line may extend to multiple islands and may be electrically connected to each other.

[0006] In an embodiment, the first voltage line may have a first width in a direction perpendicular to the extension direction of the first voltage line, and the fourth voltage line may have a second width greater than the first width in a direction perpendicular to the extension direction of the fourth voltage line.

[0007] In one embodiment, the second bridging portion may include only the fourth voltage line among the fourth, fifth, and sixth voltage lines in the first conductive layer.

[0008] In an embodiment, the first bridging portion may further include a first initialization voltage line and a second initialization voltage line, and the first initialization voltage line and the second initialization voltage line may be arranged in the first conductive layer.

[0009] In an embodiment, each of the plurality of islands may include a voltage connection line, and the second voltage line and the fifth voltage line may be electrically connected to each other in the plurality of islands via the voltage connection line.

[0010] In one embodiment, the voltage connection line may be arranged in a different layer than the layer in which the second voltage line and the fifth voltage line are arranged.

[0011] In an embodiment, the voltage connection line may include a first voltage connection line and a second voltage connection line extending in a first direction and a third voltage connection line extending in a second direction. The first voltage connection line and the second voltage connection line may be disposed in a first conductive layer, and the third voltage connection line may be disposed in a third conductive layer between the first conductive layer and the second conductive layer.

[0012] In an embodiment, the second voltage line and the fifth voltage line may be electrically connected to some of the third voltage connection lines, and the third voltage connection lines may all be electrically connected to the first voltage connection line and the second voltage connection line.

[0013] In an embodiment, the third voltage line and the sixth voltage line may extend to multiple islands and may be electrically connected to each other.

[0014] In an embodiment, the second voltage line and the fifth voltage line may each have a third width in a direction perpendicular to the extension direction of the corresponding voltage line in the second voltage line and the fifth voltage line, and the third voltage line and the sixth voltage line may each have a fourth width, which is less than the third width, in a direction perpendicular to the extension direction of the corresponding voltage line in the third voltage line and the sixth voltage line.

[0015] In an embodiment, the fourth voltage line may have a second width greater than the fourth width in a direction perpendicular to the extension direction of the fourth voltage line.

[0016] In an embodiment, each of the plurality of islands may further include a light-emitting element, a first electrode pad electrically connected to a first electrode of the light-emitting element, and a second electrode pad electrically connected to a second electrode of the light-emitting element, and the first electrode pad and the second electrode pad may be arranged in a fourth conductive layer on the second conductive layer.

[0017] In an embodiment, each of the plurality of islands may include a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element, and the pixel driving circuit may include: a driving transistor having a gate electrode, a second terminal, and a first terminal electrically connected to a first node; a data writing transistor electrically connected to the first node and a data line; a first compensation transistor electrically connected to the gate electrode of the driving transistor and the second terminal of the driving transistor; a first emission control transistor electrically connected to the first node and a second node; a second emission control transistor electrically connected to the light-emitting element and the second terminal of the driving transistor; a third emission control transistor electrically connected to the second node and a driving voltage line; a second compensation transistor electrically connected to the second node and a sustaining voltage line; a storage capacitor electrically connected to the second node and the gate electrode of the driving transistor; and an auxiliary capacitor electrically connected to the sustaining voltage line and the first electrode of the light-emitting element.

[0018] In an embodiment, the sustaining voltage line may include a first voltage line and a fourth voltage line.

[0019] In an embodiment, the auxiliary capacitor may include a first electrode and a second electrode superimposed on the first electrode in a plan view, and a first voltage line and a fourth voltage line may be electrically connected to the second electrode.

[0020] In one embodiment, the second electrode of the auxiliary capacitor may be electrically connected to the first electrode of the light-emitting element.

[0021] In an embodiment, the driving voltage line may include a second voltage line and a fifth voltage line.

[0022] In an embodiment, the second electrode of the light-emitting element may be electrically connected to a common voltage line, and the common voltage line may include a third voltage line and a sixth voltage line.

[0023] In an embodiment, each of the plurality of islands may further include a first electrode pad electrically connected to a first electrode of the light-emitting element and a second electrode pad electrically connected to a second electrode of the light-emitting element, and a third voltage line and a sixth voltage line may extend to the plurality of islands and connect to the second electrode pad.

[0024] Other aspects, features, and advantages disclosed will become better understood through the accompanying drawings, appended claims, and detailed descriptions.

[0025] Beneficial effects of the invention According to one or more embodiments, a display device can be provided that prevents damage due to stress concentration and expands and contracts in various directions. These effects are merely examples, and the scope of disclosure is not limited by these effects. Attached Figure Description

[0026] Figure 1This is a perspective view schematically showing a stretchable display device according to an embodiment.

[0027] Figure 2a and Figure 2b It is shown as stretching in the first direction Figure 1 A perspective view of a stretchable display device.

[0028] Figure 2c It is shown as stretching in the second direction Figure 1 A perspective view of a stretchable display device.

[0029] Figure 2d It shows stretching in the first and second directions. Figure 1 A perspective view of a stretchable display device.

[0030] Figure 2e It shows the upward stretching from a third party. Figure 1 A perspective view of a stretchable display device.

[0031] Figure 3 This is a schematic plan view of a stretchable display device according to an embodiment.

[0032] Figure 4a It is part of the stretchable display device according to the embodiment. Figure 3 A magnified plan view of region IV.

[0033] Figure 4b It is part of the stretchable display device according to the embodiment. Figure 3 A magnified plan view of region IV.

[0034] Figure 4c It is part of the stretchable display device according to the embodiment. Figure 3 A magnified plan view of region IV.

[0035] Figure 5 This is a schematic cross-sectional view showing a first island and a first bridging portion arranged in the display area of ​​a stretchable display device according to an embodiment.

[0036] Figures 6a to 6c This is an equivalent circuit diagram of a sub-pixel of a stretchable display device according to an embodiment.

[0037] Figure 7a and Figure 7b This is a schematic cross-sectional view of the light-emitting element of a stretchable display device according to an embodiment.

[0038] Figures 8a to 8f This is a schematic diagram illustrating the layer-by-layer layout of the island portion of a stretchable display device according to an embodiment.

[0039] Figure 9a This is a schematic diagram showing the layout of the third conductive layer of a stretchable display device according to an embodiment.

[0040] Figure 9b and Figure 9c This is a schematic layout diagram showing a portion of the third conductive layer of a stretchable display device according to an embodiment.

[0041] Figure 9d This is a schematic diagram illustrating the layout of the sustaining voltage lines of a stretchable display device according to an embodiment.

[0042] Figure 10a This is a schematic diagram showing the layout of the fourth conductive layer of a stretchable display device according to an embodiment.

[0043] Figure 10b and Figure 10c This is a schematic layout diagram showing a portion of the fourth conductive layer of a stretchable display device according to an embodiment.

[0044] Figure 11a This is a schematic diagram showing the layout of the fifth conductive layer of a stretchable display device according to an embodiment.

[0045] Figure 11b and Figure 11c This is a schematic layout diagram showing a portion of the fifth conductive layer of a stretchable display device according to an embodiment.

[0046] Figure 11d This is a schematic diagram showing the layout of the drive voltage lines of a stretchable display device according to an embodiment.

[0047] Figure 11e This is a schematic diagram illustrating the layout of the common voltage lines of a stretchable display device according to an embodiment.

[0048] Figures 12a to 12g This is a perspective view schematically illustrating an electronic device including a stretchable display device according to an embodiment. Detailed Implementation

[0049] According to an embodiment, the display device includes: a plurality of islands separated from each other; a first bridging portion connecting the islands that are adjacent to each other in a first direction, wherein the first bridging portion includes a first voltage line, a second voltage line, and a third voltage line; and a second bridging portion connecting the islands that are adjacent to each other in a second direction intersecting the first direction, wherein the second bridging portion includes a fourth voltage line electrically connected to the first voltage line, a fifth voltage line electrically connected to the second voltage line, and a sixth voltage line electrically connected to the third voltage line, wherein the first voltage line and the fourth voltage line are disposed in a first conductive layer, and the second voltage line, the fifth voltage line, the third voltage line, and the sixth voltage line are disposed in a second conductive layer on the first conductive layer.

[0050] Invention scheme Because this specification allows for various modifications and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the written description. The effects and features of the disclosure, as well as methods for achieving them, will be illustrated by referring to the embodiments described in detail below with reference to the accompanying drawings. However, the disclosure is not limited to the following embodiments and can be embodied in various forms.

[0051] In the following description, embodiments will be described in detail with reference to the accompanying drawings. When describing embodiments with reference to the accompanying drawings, the same or corresponding elements are indicated by the same reference numerals.

[0052] It will be understood that although terms such as "first," "second," etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0053] In this specification, terms such as horizontal, vertical, up, down, left, and right are not limiting in meaning but are used for ease of explanation and do not indicate absolute location. Therefore, these terms may vary depending on the observer's position or the arrangement of the display device.

[0054] Unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” used herein are intended to include the plural forms as well.

[0055] It will also be understood that the term “comprising” and / or variations thereof as used herein indicates the presence of the stated features or elements, but does not preclude the presence or addition of one or more other features or elements.

[0056] It will also be understood that when a layer, region, or element is referred to as being "on" another layer, region, or element, it can be directly on said other layer, region, or element, or indirectly on said other layer, region, or element. That is, for example, an intermediary layer, region, or element may exist.

[0057] It will also be understood that when layers, areas, or elements are referred to as being connected to each other, they may be directly connected to each other or indirectly connected to each other with an intermediary layer, area, or element located therebetween. For example, when layers, areas, or elements are referred to as being electrically connected to each other, they may be directly electrically connected to each other or indirectly electrically connected to each other with an intermediary layer, area, or element located therebetween.

[0058] Throughout this disclosure, the phrase "at least one of A and B (species / man)" and "A and / or B" mean only A, only B, or both A and B. In this specification, the phrase "at least one of A and B (species / man)" means only A, only B, or both A and B.

[0059] In this specification, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0060] When an embodiment can be implemented differently, a particular process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0061] Furthermore, for ease of interpretation, the dimensions of the elements in the accompanying drawings may be exaggerated or reduced. For example, the disclosure is not limited thereto because the dimensions and thicknesses of the elements in the drawings have been arbitrarily shown for ease of interpretation.

[0062] Figure 1 This is a perspective view schematically showing a stretchable display device 1 according to an embodiment. Figure 2a and Figure 2b It is shown as stretching in the first direction Figure 1 A perspective view of the stretchable display device 1. Figure 2c It is shown as stretching in the second direction Figure 1 A perspective view of the stretchable display device 1. Figure 2d It shows stretching in the first and second directions. Figure 1 A perspective view of a stretchable display device. Figure 2e It shows the upward stretching from a third party. Figure 1 A perspective view of the stretchable display device 1.

[0063] Reference Figure 1 The stretchable display device 1 may include a display area DA and a non-display area NDA. The display area DA may include multiple pixels. The stretchable display device 1 can provide a specific image by using light emitted from the pixels. The non-display area NDA may be outside the display area DA. The non-display area NDA may completely surround the display area DA.

[0064] The stretchable display device 1 can be stretched or compressed in various directions. The stretchable display device 1 can be stretched in a first direction (e.g., the +x direction and / or the -x direction) by an external force applied by an external object or a user. In an embodiment, as... Figure 2a and Figure 2b As shown, the display area DA and / or non-display area NDA of the stretchable display device 1 can be stretched in a first direction (e.g., the +x direction and / or the -x direction). For example, as Figure 2a As shown, the stretchable display device 1 can be stretched in the +x and -x directions, or as... Figure 2b As shown, the stretchable display device 1 can be stretched in the +x direction while being fixed on one side.

[0065] The stretchable display device 1 can be stretched in a second direction (e.g., the +y direction and / or the -y direction) by an external force applied by an external object or a user. In an embodiment, as... Figure 2c As shown, the display area DA and / or non-display area NDA of the stretchable display device 1 can be stretched in the +y and -y directions. In another embodiment, the stretchable display device 1 can be stretched in the +y or -y direction while being fixed on one side.

[0066] The stretchable display device 1 can be stretched in multiple directions (e.g., a first direction (e.g., +x and / or -x) and a second direction (e.g., +y and / or -y)) by an external force applied by an external object or a part of the human body. Figure 2d As shown, the display area DA and / or non-display area NDA of the stretchable display device 1 can be stretched in the ±x and ±y directions.

[0067] The stretchable display device 1 can be stretched in a third direction (e.g., the +z or -z direction) by an external force applied by an external object or part of the human body. In an embodiment, Figure 2e A portion of the stretchable display device 1 (e.g., a portion of the display area DA) is shown to protrude in the +z direction. In another embodiment, a portion of the stretchable display device 1 (e.g., a portion of the display area DA) may protrude in the -z direction (or may be recessed in the +z direction).

[0068] Figures 2a to 2e A stretchable display device 1 is shown that can be stretched upwards in a first direction, a second direction, and / or a third direction, but the disclosure is not limited thereto. In another embodiment, the stretchable display device 1 can be deformed into various irregular shapes. For example, the stretchable display device 1 can be bent or twisted relative to two or more axes.

[0069] Figure 3This is a schematic plan view of the stretchable display device 1 according to an embodiment. As used herein, "plan view" is a view in a third direction (e.g., the +z or -z direction) that is the thickness direction of the stretchable display device 1.

[0070] Multiple pixels can be arranged in the display area DA of the stretchable display device 1. Each pixel can include sub-pixels configured to emit light points of different colors. Light-emitting elements corresponding to the sub-pixels can be arranged in the display area DA. Circuits configured to provide electrical signals to the light-emitting elements arranged in the display area DA and transistors electrically connected to the light-emitting elements can be located in a non-display area NDA surrounding the display area DA. A gate driving circuit GDC can be arranged in a first non-display area NDA1 and a second non-display area NDA2 respectively arranged on opposite sides of the display area DA. The gate driving circuit GDC can include a driver configured to provide electrical signals to the gate electrode of the transistor electrically connected to the light-emitting element. Although Figure 3 The diagram shows a gate drive circuit GDC arranged in a first non-display area NDA1 and a second non-display area NDA2, but the disclosure is not limited thereto. In another embodiment, the gate drive circuit GDC may be arranged in either the first non-display area NDA1 or the second non-display area NDA2.

[0071] The data drive circuit DDC can be arranged in a third non-display area NDA3 and / or a fourth non-display area NDA4 that connects the first non-display area NDA1 to the second non-display area NDA2. In an embodiment, Figure 3 The diagram shows the data drive circuit DDC arranged in the fourth non-display area NDA4. In another embodiment, the data drive circuit DDC may be arranged in the third non-display area NDA3 and the fourth non-display area NDA4, respectively.

[0072] Although Figure 3 The diagram shows a data drive circuit DDC arranged in a fourth non-display area NDA4 of the stretchable display device 1, but the disclosure is not limited thereto. In another embodiment, the stretchable display device 1 may further include a flexible circuit board (not shown) electrically connected via terminals (not shown) arranged in the fourth non-display area NDA4, and the data drive circuit DDC may be disposed on the flexible circuit board.

[0073] In some embodiments, the elongation rate of the non-display area NDA may be less than or equal to the elongation rate of the display area DA. In embodiments, the elongation rate of the non-display area NDA may be different for each area. For example, the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3 may have substantially the same elongation rate, but the elongation rate of the fourth non-display area NDA4 may be less than the elongation rate of each of the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3.

[0074] Figure 4a It is part of the stretchable display device 1 according to the embodiment. Figure 3 A magnified plan view of region IV.

[0075] Reference Figure 4a The stretchable display device 1 may include main island portions 11 that are separated from each other in a first direction (e.g., +x direction or -x direction) and a second direction (e.g., +y direction or -y direction) in the display area DA, and main bridging portions 12 that connect adjacent main island portions 11 to each other.

[0076] Each of the main island sections 11 can be connected to multiple main bridging sections 12. For example, each of the main island sections 11 can be connected to four main bridging sections 12. Two main bridging sections 12 can be arranged on opposite sides of the main island section 11 in a first direction (e.g., +x or -x direction), and the remaining two main bridging sections 12 can be arranged on opposite sides of the main island section 11 in a second direction (e.g., +y or -y direction). In an embodiment, the four main bridging sections 12 can be connected to the four sides of the main island section 11. The four main bridging sections 12 can be adjacent to the corners of the main island section 11.

[0077] The main bridging portions 12 can be spaced apart from each other by a first opening CS1 between them. In an embodiment, the first opening CS1 having an approximately H-shape and the first opening CS1 having an approximately I-shape obtained by rotating the H-shape by 90 degrees can be arranged alternately and repeatedly in a first direction (e.g., +x direction or -x direction) and a second direction (e.g., +y direction or -y direction). The opposite ends of each of the main bridging portions 12 can be connected to the adjacent main island portion 11 respectively, and one side of each of the main bridging portions 12 can be spaced apart from one side of the adjacent main island portion 11 and / or one side of another main bridging portion 12 by the first opening CS1.

[0078] The stretchable display device 1 may be included in the non-display area (e.g., Figure 4a The first non-display area NDA1 shown includes peripheral island portions 21 that are separated from each other and peripheral bridging portions 22 that connect adjacent peripheral island portions 21 to each other.

[0079] The outer island portions 21 may all extend in a first direction (e.g., +x or -x direction). The outer island portions 21 may be separated from each other in a second direction (e.g., +y or -y direction) intersecting the first direction (e.g., +x or -x direction). The outer island portions 21 may include reference... Figure 3 The described gate drive circuit (see Figure 3 The driver of the GDC.

[0080] The peripheral bridging portion 22 may have a serpentine shape. The length of the peripheral bridging portion 22 may be greater than the shortest distance between adjacent peripheral island portions 21 in a second direction (e.g., +y or -y direction). In an embodiment, the peripheral bridging portion 22 may have an approximately omega (Ω) shape that protrudes in a first direction (e.g., +x or -x direction). The peripheral bridging portion 22 may be between adjacent peripheral island portions 21 and may be separated from each other.

[0081] Peripheral bridging portions 22 between adjacent peripheral island portions 21 can be spaced apart from each other by a second opening CS2. The second opening CS2 and the peripheral bridging portions 22 can be alternately arranged between adjacent peripheral island portions 21 in a first direction (e.g., +x direction or -x direction). The second opening CS2 can have the same shape. The opposite ends of each of the peripheral bridging portions 22 can be connected to the adjacent peripheral island portion 21 respectively, and one side of each of the peripheral bridging portions 22 can be spaced apart from one side of the adjacent peripheral island portion 21 and / or one side of another peripheral bridging portion 22 by the second opening CS2.

[0082] A peripheral island 21 arranged in the first non-display area NDA1 can correspond to a multi-row main island 11 arranged in the display area DA. For example, a peripheral island 21 arranged in the first non-display area NDA1 can correspond to a main island 11 arranged in the i-th row and a main island 11 arranged in the (i+1)-th row in the display area DA (where i is a positive number greater than 0). Although Figure 4a A peripheral island 21 is shown corresponding to two rows of main islands 11, but the disclosure is not limited thereto. In another embodiment, a peripheral island 21 arranged in the first non-display area NDA1 may correspond to n rows of main islands 11 arranged in the display area DA (where n is a positive number greater than or equal to 3).

[0083] The non-display area (e.g., the first non-display area NDA1) may include a first sub-non-display area SNDA1 in which a peripheral island portion 21 and a peripheral bridging portion 22 are arranged, and a second sub-non-display area SNDA2 between the first sub-non-display area SNDA1 and the display area DA. A connecting bridging portion 23 may be arranged in the second sub-non-display area SNDA2 to connect the display area DA to the first sub-non-display area SNDA1. One end of the connecting bridging portion 23 may be connected to the peripheral island portion 21 and / or the peripheral bridging portion 22, and the other end of the connecting bridging portion 23 may be connected to the main island portion 11 and / or the main bridging portion 12.

[0084] The connecting bridging portion 23 may have a serpentine shape. In an embodiment, the shape of the connecting bridging portion 23 may differ from the shape of the main bridging portion 12 and the shape of the peripheral bridging portion 22. In an embodiment, such as... Figure 4a As shown, the connecting bridging portion 23 may have an approximately omega (Ω) shape protruding in a second direction (e.g., the +y or -y direction). The connecting bridging portion 23 may have a symmetrical structure in which one of adjacent connecting bridging portions 23 arranged in the second direction (e.g., the +y or -y direction) protrudes in the +y direction and another adjacent connecting bridging portion 23 protrudes in the -y direction. A third opening CS3 and a fourth opening CS4 having different shapes from each other may be repeated between the connecting bridging portions 23. The width of the connecting bridging portion 23 may differ from the width of the main bridging portion 12 and the width of the peripheral bridging portion 22. In an embodiment, the width of the connecting bridging portion 23 may be greater than the width of the main bridging portion 12 and less than the width of the peripheral bridging portion 22.

[0085] Figure 4a The peripheral island portion 21 and peripheral bridging portion 22 in a non-display area (e.g., a first non-display area NDA1) are shown to have shapes different from the main island portion 11 and main bridging portion 12 in the display area DA. In another embodiment, the peripheral island portion 21 and peripheral bridging portion 22 in the non-display area may have the same shapes as the main island portion 11 and main bridging portion 12 in the display area DA, respectively.

[0086] Figure 4b It is part of the stretchable display device 1 according to the embodiment. Figure 3 A magnified plan view of region IV.

[0087] Reference Figure 4b The stretchable display device 1 may include main island portions 11 that are separated from each other in the display area DA and main bridging portions 12 that are spaced apart from each other through a first opening CS1 and connect adjacent main island portions 11 to each other. Figure 4b The structure of the display area DA in the reference can be compared with that of the reference area. Figure 4aThe structure of the described display area DA is the same.

[0088] The stretchable display device 1 may include a peripheral island portion 21 and a peripheral bridging portion 22 disposed in a non-display area (e.g., a first non-display area NDA1). In an embodiment, the peripheral island portion 21 and the peripheral bridging portion 22 may each have substantially the same shape as the main island portion 11 and the main bridging portion 12.

[0089] The peripheral island portions 21 can be separated from each other in a first direction (e.g., +x or -x direction) and a second direction (e.g., +y or -y direction) within a non-display area (e.g., the first non-display area NDA1). Peripheral bridging portions 22 can each connect adjacent peripheral island portions 21 to each other. The peripheral bridging portions 22 can be spaced apart from each other through a second opening CS2 between them.

[0090] The second opening CS2 may have a shape substantially the same as the first opening CS1. For example, an approximately H-shaped second opening CS2 and an approximately I-shaped second opening CS2 may be arranged alternately and repeatedly in the non-display area (e.g., the first non-display area NDA1). The opposite ends of each of the peripheral bridging portions 22 may be connected to the adjacent peripheral island portion 21 respectively, and one side of each of the peripheral bridging portions 22 may be spaced apart from one side of the adjacent peripheral island portion 21 and / or one side of the other peripheral bridging portion 22 by means of the second opening CS2.

[0091] Each of the peripheral islands 21 can be connected to four peripheral bridges 22. The peripheral island 21 may include reference... Figure 3 The described gate drive circuit (see Figure 3 The driver of the GDC.

[0092] A row of peripheral islands 21 arranged in the first non-display area NDA1 can correspond to a row of main islands 11 arranged in the display area DA. For example, a peripheral island 21 arranged in the i-th row in the first direction (e.g., the +x direction or the -x direction) in the first non-display area NDA1 can correspond to a main island 11 arranged in the same row (e.g., the i-th row) in the display area DA (where i is a positive number greater than 0).

[0093] The stretchable display device 1 may include a connecting bridge 23 disposed in a second sub-non-display area SNDA2 to connect the display area DA to a first sub-non-display area SNDA1. The non-display area (e.g., the first non-display area NDA1) may include a first sub-non-display area SNDA1 in which a peripheral island 21 and a peripheral bridge 22 are disposed, and a second sub-non-display area SNDA2 between the first sub-non-display area SNDA1 and the display area DA and including the connecting bridge 23. The connecting bridge 23 may be substantially the same as the main bridge 12 and the peripheral bridge 22. For example, the width of the connecting bridge 23 may be equal to the width of the main bridge 12 and the width of the peripheral bridge 22.

[0094] Figure 4c It is part of the stretchable display device 1 according to the embodiment. Figure 3 A magnified plan view of region IV.

[0095] Reference Figure 4c The stretchable display device 1 may include main island portions 11 that are separated from each other in a first direction (e.g., +x direction or -x direction) and a second direction (e.g., +y direction or -y direction) in the display area DA, and main bridging portions 12 that connect adjacent main island portions 11 to each other.

[0096] The main bridging portions 12 can be spaced apart from each other through the first opening CS1 between them. The main bridging portions 12 can have a serpentine shape. For example, as... Figure 4c As shown, the main bridging portion 12 may have an approximate S-shape.

[0097] Each of the main island sections 11 can be connected to multiple main bridging sections 12. For example, each of the main island sections 11 can be connected to four main bridging sections 12. Two main bridging sections 12 can be arranged on opposite sides of the main island section 11 in a first direction (e.g., +x or -x direction), and the remaining two main bridging sections 12 can be arranged on opposite sides of the main island section 11 in a second direction (e.g., +y or -y direction). The four main bridging sections 12 can be connected to the four sides of the main island section 11. The four main bridging sections 12 can be adjacent to the corners of the main island section 11.

[0098] The stretchable display device 1 may be included in the non-display area (e.g., Figure 4c The first non-display area NDA1 shown in the diagram has peripheral island portions 21 that are separated from each other in a first direction (e.g., +x direction or -x direction) and a second direction (e.g., +y direction or -y direction), and peripheral bridging portions 22 that connect adjacent peripheral island portions 21 to each other.

[0099] The peripheral bridging portions 22 can be spaced apart from each other through the second opening CS2 between them. The peripheral bridging portions 22 can have a serpentine shape. For example, as... Figure 4c As shown, the peripheral bridging portion 22 may have an approximately S-shaped form. The size and / or width of the peripheral bridging portion 22 may differ from the size and / or width of the main bridging portion 12. For example, the size and / or width of the peripheral bridging portion 22 may be larger than the size and / or width of the main bridging portion 12. The radius of curvature of the circular portion of the peripheral bridging portion 22 may differ from the radius of curvature of the circular portion of the main bridging portion 12. For example, the radius of curvature of the circular portion of the peripheral bridging portion 22 may be larger than the radius of curvature of the circular portion of the main bridging portion 12.

[0100] Each of the peripheral island portions 21 can be connected to a plurality of peripheral bridging portions 22. Each of the peripheral island portions 21 can be connected to four peripheral bridging portions 22. Two peripheral bridging portions 22 can be respectively arranged on opposite sides of the peripheral island portion 21 in a first direction (e.g., +x direction or -x direction), and the remaining two peripheral bridging portions 22 can be respectively arranged on opposite sides of the peripheral island portion 21 in a second direction (e.g., +y direction or -y direction). In an embodiment, the four peripheral bridging portions 22 can be respectively connected to the four sides of the peripheral island portion 21. The peripheral bridging portions 22 can be respectively connected to the central portion of the side of the peripheral island portion 21.

[0101] A row of peripheral islands 21 arranged in the first non-display area NDA1 can correspond to multiple rows of main islands 11 arranged in the display area DA. For example, a row of peripheral islands 21 arranged in the first non-display area NDA1 can correspond to the main islands 11 arranged in the i-th row and the main islands 11 arranged in the (i+1)-th row in the display area DA (where i is a positive number greater than 0). In another embodiment, a row of peripheral islands 21 can correspond to n rows of main islands 11 (where n is a positive number greater than or equal to 3).

[0102] A non-display area (e.g., a first non-display area NDA1) may include a first sub-non-display area SNDA1 in which a peripheral island portion 21 and a peripheral bridging portion 22 are arranged, and a second sub-non-display area SNDA2 between the first sub-non-display area SNDA1 and the display area DA. A connecting bridging portion 23 may be arranged in the second sub-non-display area SNDA2 to connect the display area DA to the first sub-non-display area SNDA1. One end of the connecting bridging portion 23 may be connected to the peripheral island portion 21, and the other end of the connecting bridging portion 23 may be connected to the main island portion 11. For example, one end of the connecting bridging portion 23 may be connected to the center portion of one side of the peripheral island portion 21, and the other end of the connecting bridging portion 23 may be connected to the center portion of one side of the main island portion 11.

[0103] The connecting bridging portion 23 may have a serpentine shape. In an embodiment, the shape of the connecting bridging portion 23 may differ from the shape of the main bridging portion 12 and the shape of the peripheral bridging portion 22. The width of the connecting bridging portion 23 may differ from the width of the main bridging portion 12 and the width of the peripheral bridging portion 22. The width of the connecting bridging portion 23 may be greater than the width of the main bridging portion 12 and less than the width of the peripheral bridging portion 22. A third opening CS3 and a fourth opening CS4 with different shapes may alternate between the connecting bridging portions 23 in a second direction (e.g., the +y direction or the -y direction).

[0104] Figure 5 This is a schematic cross-sectional view showing the main island portion 11 and the main bridging portion 12 arranged in the display area DA of the stretchable display device 1 according to an embodiment.

[0105] Reference Figure 5 The main island portion 11 and the main bridge portion 12 in the display area DA can be separated from each other, and the first opening CS1 is located between the main island portion 11 and the main bridge portion 12. The main island portion 11 may include light-emitting elements (LEDs) and circuitry (e.g., pixel driving circuitry PC) configured to drive the light-emitting elements electrically connected thereto. The main bridge portion 12 may include auxiliary capacitors Ca, which are electrically connected to the pixel driving circuitry PCs arranged in adjacent main island portions 11.

[0106] In the main island section 11, a buffer layer 111 comprising inorganic insulating material can be disposed on the substrate 100, and a pixel driving circuit PC can be disposed on the buffer layer 111. An insulating layer IL comprising inorganic and / or organic insulating material can be disposed between the pixel driving circuit PC and the light-emitting element LED. The light-emitting element LED can be disposed on the insulating layer IL and can be electrically connected to the corresponding pixel driving circuit PC. The light-emitting element LED can be configured to emit light spots of different colors or the same color. In an embodiment, the light-emitting element LED can be configured to emit red light, green light, and blue light. In some embodiments, the light-emitting element LED can be configured to emit white light. In another embodiment, the light-emitting element LED can be configured to emit red light, green light, blue light, and white light.

[0107] The substrate 100 may comprise a polymeric resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate, or cellulose propionate. In one embodiment, the substrate 100 may be a single layer comprising the aforementioned polymeric resin. In another embodiment, the substrate 100 may have a multilayer structure comprising a matrix layer containing the aforementioned polymeric resin and a barrier layer containing an inorganic insulating material. The substrate 100 comprising the polymeric resin may be flexible, rollable, and bendable.

[0108] In the embodiments, although Figure 5 The illustration shows three pixel driving circuits (PCs) arranged in the main island section 11, each with three light-emitting elements (LEDs) connected to the three pixel driving circuits (PCs), but the disclosure is not limited thereto. In another embodiment, the number of pixel driving circuits (PCs) and light-emitting elements (LEDs) arranged in the main island section 11 may be one, two, four, or more.

[0109] The encapsulation layer 300 can be disposed on the light-emitting element (LED) and can protect the LED from external forces and / or moisture penetration. The encapsulation layer 300 may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer 300 may include a structure in which an inorganic encapsulation layer comprising an inorganic insulating material, an organic encapsulation layer comprising an organic insulating material, and inorganic encapsulation layers comprising an inorganic insulating material are stacked in the order stated herein. In another embodiment, the encapsulation layer 300 may include an organic material such as a resin. In some embodiments, the encapsulation layer 300 may include urethane epoxy acrylate. The encapsulation layer 300 may include a photosensitive material such as a photoresist.

[0110] In the main bridging portion 12, an insulating layer IL comprising an organic insulating material may be disposed on the substrate 100. When the stretchable display device 1 is stretched, unlike the main island portion 11, the relatively deformable main bridging portion 12 may not have a layer comprising an inorganic insulating material that is prone to cracking.

[0111] In one embodiment, the substrate 100 corresponding to the main bridging portion 12 may have the same stacking structure as the substrate 100 corresponding to the main island portion 11. In another embodiment, the substrate 100 corresponding to the main bridging portion 12 and the substrate 100 corresponding to the main island portion 11 may be polymer resin layers formed together in the same process. In yet another embodiment, the substrate 100 corresponding to the main bridging portion 12 may have a different stacking structure than the substrate 100 corresponding to the main island portion 11. In some embodiments, the substrate 100 corresponding to the main bridging portion 12 may have a multilayer structure including a matrix layer comprising a polymer resin and a barrier layer comprising an inorganic insulating material, and the substrate 100 corresponding to the main bridging portion 12 may have a structure with a polymer resin layer but without a layer comprising an inorganic insulating material.

[0112] The wiring WL of the main bridge section 12 may be a signal line (e.g., gate line, data line, etc.) configured to provide electrical signals to transistors included in the pixel driving circuit PC of the main island section 11, or it may be a voltage line (e.g., drive voltage line, initialization voltage line, etc.) configured to provide voltage to transistors included in the pixel driving circuit PC of the main island section 11. The encapsulation layer 300 may also be disposed in the main bridge section 12. In another embodiment, the encapsulation layer 300 may not be present in the main bridge section 12.

[0113] Reference Figures 4a to 4c and Figure 5 The base 100 corresponding to the main island portion 11 and the base 100 corresponding to the main bridging portion 12 can be connected to each other. In other words, Figures 4a to 4c The floor plan shown can be compared with Figure 5 The plan view of the base 100 is substantially the same. In other words, the base 100 may include a region corresponding to the main island portion 11, a region corresponding to the main bridging portion 12, and an opening 100OP1 having the same shape as the first opening CS1.

[0114] Similarly, the encapsulation layer 300 corresponding to the main island portion 11 and the encapsulation layer 300 corresponding to the main bridging portion 12 can be connected to each other. For example, Figures 4a to 4c The plan view shown may be substantially the same as the plan view of the encapsulation layer 300. In other words, the encapsulation layer 300 may include a region corresponding to the main island portion 11, a region corresponding to the main bridging portion 12, and an opening 300OP1 having the same shape as the first opening CS1.

[0115] The circuit light-emitting element layer 200 between the substrate 100 and the encapsulation layer 300 may include a buffer layer 111, a pixel driving circuit PC, wiring WL, an insulating layer IL, and a light-emitting element LED. Similar to the substrate 100, Figures 4a to 4c The plan view shown may be substantially the same as the plan view of the circuit light-emitting element layer 200. In other words, the circuit light-emitting element layer 200 may include an opening 200OP1 having the same shape as the first opening CS1.

[0116] Figures 6a to 6c This is an equivalent circuit diagram of a sub-pixel of the stretchable display device 1 according to an embodiment.

[0117] Reference Figure 6a The light-emitting element (LED) corresponding to the sub-pixel can be electrically connected to the pixel driving circuit PC, and the pixel driving circuit PC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The pixel driving circuit PC can be electrically connected to signal lines and voltage lines. The signal lines can include gate lines such as the first scan line SL1 and data lines DL, and the voltage lines can include driving voltage lines VDDL.

[0118] The second transistor T2 can be electrically connected to the first scan line SL1 and the data line DL. The first scan line SL1 can be configured to provide a first scan signal GW to the gate electrode of the second transistor T2. The second transistor T2 can be configured to transmit a data signal Dm input from the data line DL to the first transistor T1 in response to the first scan signal GW input from the first scan line SL1.

[0119] The storage capacitor Cst can be electrically connected to the second transistor T2 and the drive voltage line VDDL, and can be configured to store a voltage corresponding to the difference between the voltage received from the second transistor T2 and the drive power supply voltage VDD supplied through the drive voltage line VDDL.

[0120] The first transistor T1 can be used as a "driving transistor" and can be configured to control the driving current flowing through the light-emitting element LED. The first transistor T1 can be connected to the driving voltage line VDDL and the storage capacitor Cst. The first transistor T1 can be configured to control the driving current flowing from the driving voltage line VDDL to the light-emitting element LED based on the voltage value stored in the storage capacitor Cst. The light-emitting element LED can be configured to emit light with a specific brightness according to the driving current. The first electrode of the light-emitting element LED can be electrically connected to the first transistor T1, and the second electrode of the light-emitting element LED can be electrically connected to the common voltage line VSSL, which is configured to supply a common power supply voltage VSS.

[0121] Figure 6a The illustrated pixel driving circuit PC includes two transistors and a storage capacitor, but in another embodiment, the pixel driving circuit PC may include three or more transistors.

[0122] Reference Figure 6b The pixel driving circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0123] The pixel driving circuit PC can be electrically connected to signal lines and voltage lines. Signal lines may include data lines DL and gate lines (such as the first scan line SL1, the second scan line SL2, the third scan line SL3, and the emit control line EML). Voltage lines may include the first initialization voltage line VIL1, the second initialization voltage line VIL2, and the drive voltage line VDDL.

[0124] The driving voltage line VDDL can be configured to transmit the driving power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 can be configured to transmit the first initialization voltage Vint used to initialize the first transistor T1 to the pixel driving circuit PC. The second initialization voltage line VIL2 can be configured to transmit the second initialization voltage Vaint used to initialize the first electrode of the light-emitting element LED to the pixel driving circuit PC.

[0125] The first transistor T1 can be electrically connected to the drive voltage line VDDL via the fifth transistor T5, and can be electrically connected to the light-emitting element LED via the sixth transistor T6. The first transistor T1 can be used as a drive transistor and can be configured to receive the data signal Dm according to the switching operation of the second transistor T2, and supply drive current to the light-emitting element LED.

[0126] The second transistor T2 can be used as a "data write transistor" and can be electrically connected to the first scan line SL1 and the data line DL. The second transistor T2 can be electrically connected to the drive voltage line VDDL via the fifth transistor T5. The second transistor T2 can be configured to turn on in response to the first scan signal GW received through the first scan line SL1 and perform a switching operation to transmit the data signal Dm received through the data line DL to the first node N1.

[0127] The third transistor T3 can be electrically connected to the first scan line SL1 and to the light-emitting element LED via the sixth transistor T6. The third transistor T3 can be configured to turn on in response to the first scan signal GW received through the first scan line SL1 and to connect the first transistor T1 diode.

[0128] The fourth transistor T4 can be used as the first initialization transistor and can be electrically connected to the third scan line SL3 and the first initialization voltage line VIL1. The fourth transistor T4 can be configured to turn on in response to the third scan signal GI received through the third scan line SL3, and to initialize the voltage of the gate electrode of the first transistor T1 by transferring the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1. The third scan signal GI can correspond to the first scan signal of another pixel driving circuit arranged in the row preceding the corresponding pixel driving circuit PC.

[0129] The fifth transistor T5 can be used as an operation control transistor, and the sixth transistor T6 can be used as an emitter control transistor. The fifth transistor T5 and the sixth transistor T6 can be electrically connected to the emitter control line EML, and can be configured to simultaneously conduct in response to the emitter control signal EM received through the emitter control line EML, forming a current path through which the drive current flows from the drive voltage line VDDL to the light-emitting element LED.

[0130] The seventh transistor T7 can be used as the second initialization transistor and can be electrically connected to the second scan line SL2, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be configured to turn on in response to the second scan signal GB received through the second scan line SL2 and initialize the first electrode of the light-emitting element LED by transmitting the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting element LED.

[0131] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 may be electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 may be electrically connected to the drive voltage line VDDL. The storage capacitor Cst can store and maintain a voltage corresponding to the voltage difference between the drive voltage line VDDL and the gate electrode of the first transistor T1, thus maintaining the voltage applied to the gate electrode of the first transistor T1.

[0132] Reference Figure 6c The pixel driving circuit PC may include a first transistor T1 (“driving transistor”), a second transistor T2 (“data writing transistor”), a third transistor T3 (“first compensation transistor”), a fourth transistor T4 (“first initialization transistor”), a fifth transistor T5 (“first emission control transistor”), a sixth transistor T6 (“second emission control transistor”), a seventh transistor T7 (“second initialization transistor”), an eighth transistor T8 (“third emission control transistor”), a ninth transistor T9 (“second compensation transistor”), a storage capacitor Cst, and an auxiliary capacitor Ca.

[0133] The pixel driving circuit PC can be electrically connected to signal lines and voltage lines. Signal lines may include data lines DL and gate lines (such as the first scan line SL1, the second scan line SL2, the third scan line SL3, and the emit control line EML). Voltage lines may include the first initialization voltage line VIL1 and the second initialization voltage line VIL2, the sustain voltage line VSL, and the drive voltage line VDDL.

[0134] The drive voltage line VDDL can be configured to transmit the drive power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 can be configured to transmit a first initialization voltage Vint used to initialize the first transistor T1 to the pixel driving circuit PC. The second initialization voltage line VIL2 can be configured to transmit a second initialization voltage Vaint used to initialize the first electrode of the light-emitting element LED to the pixel driving circuit PC. The sustaining voltage line VSL can be configured to provide a sustaining voltage VSUS to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst) during the initialization period and the data write period.

[0135] The first transistor T1 may have a gate electrode, a second terminal, and a first terminal electrically connected to the first node N1. The first terminal of the first transistor T1 may be electrically connected to the drive voltage line VDDL via the fifth transistor T5 and the eighth transistor T8, and the second terminal of the first transistor T1 may be electrically connected to the light-emitting element LED via the sixth transistor T6. The first transistor T1 may function as a drive transistor and may be configured to receive the data signal Dm according to the switching operation of the second transistor T2 and supply drive current to the light-emitting element LED.

[0136] The second transistor T2 can be electrically connected to the first scan line SL1, the data line DL, and the first node N1. The second transistor T2 can be electrically connected to the drive voltage line VDDL via the fifth transistor T5 and the eighth transistor T8 through the first node N1. The second transistor T2 can be configured to turn on in response to the first scan signal GW received through the first scan line SL1 and perform a switching operation to transmit the data signal Dm transmitted through the data line DL to the first node N1.

[0137] The third transistor T3 can be electrically connected to the gate electrode of the first transistor T1 and the second terminal of the first transistor T1. The gate of the third transistor T3 can be electrically connected to the first scan line SL1 and to the light-emitting element LED via the sixth transistor T6. The third transistor T3 can be configured to turn on in response to the first scan signal GW received through the first scan line SL1 and to compensate the threshold voltage of the first transistor T1 by connecting the diode of the first transistor T1.

[0138] The fourth transistor T4 can be electrically connected to the third scan line SL3 and the first initialization voltage line VIL1, and can be configured to turn on in response to the third scan signal GI received through the third scan line SL3, and to initialize the voltage of the gate electrode of the first transistor T1 by transmitting the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1. The third scan signal GI can correspond to the first scan signal of another pixel driving circuit arranged in the row preceding the corresponding pixel driving circuit PC.

[0139] The fifth transistor T5 can be electrically connected to the first node N1 and the second node N2, the sixth transistor T6 can be electrically connected to the second terminal of the first transistor T1 and the light-emitting element LED, and the eighth transistor T8 can be electrically connected to the second node N2 and the drive voltage line VDDL. The fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 can be electrically connected to the emitter control line EML and can be configured to simultaneously conduct in response to the emitter control signal EM received through the emitter control line EML, forming a current path through which the drive current flows from the drive voltage line VDDL to the light-emitting element LED.

[0140] The seventh transistor T7 can be used as the second initialization transistor and can be electrically connected to the second scan line SL2, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be configured to turn on in response to the second scan signal GB received through the second scan line SL2 and initialize the first electrode of the light-emitting element LED by transmitting the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting element LED.

[0141] The ninth transistor T9 can be electrically connected to the second scan line SL2, the second node N2, and the sustaining voltage line VSL. The ninth transistor T9 can be electrically connected to the second electrode CE2 of the storage capacitor Cst through the second node N2. The ninth transistor T9 can be configured to turn on in response to the second scan signal GB received through the second scan line SL2, and to transmit the sustaining voltage VSUS to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst) during the initialization period and the data write period.

[0142] The eighth transistor T8 and the ninth transistor T9 may be electrically connected to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst). In some embodiments, during the initialization and data write periods, the eighth transistor T8 may be turned off and the ninth transistor T9 may be turned on, and during the transmit period, the eighth transistor T8 may be turned on and the ninth transistor T9 may be turned off. Because the sustaining voltage VSUS is transmitted to the second node N2 during the initialization and data write periods, the brightness uniformity (e.g., long-distance uniformity (“LRU”) of the stretchable display device according to the voltage drop in the drive voltage line VDDL can be improved.

[0143] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 of the storage capacitor Cst may be electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 of the storage capacitor Cst may be electrically connected to the eighth transistor T8 and the ninth transistor T9.

[0144] The auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the sustaining voltage line VSL, and the first electrode of the light-emitting element LED. While the seventh transistor T7 and the ninth transistor T9 are turned on, the auxiliary capacitor Ca can store and maintain a voltage corresponding to the voltage difference between the first electrode of the light-emitting element LED and the sustaining voltage line VSL. Therefore, it can prevent the problem of increased black brightness when the sixth transistor T6 is turned off.

[0145] Figure 7a This is a schematic cross-sectional view of the light-emitting element of a stretchable display device according to an embodiment.

[0146] Reference Figure 7a According to the embodiments, the light-emitting element may include an organic light-emitting diode 220 comprising organic materials. The organic light-emitting diode 220 may include a first electrode 221 disposed on an insulating layer, a second electrode 225 facing the first electrode 221, and an emitting layer 223 between the first electrode 221 and the second electrode 225. A first functional layer 222 may be located between the first electrode 221 and the emitting layer 223, and a second functional layer 224 may be located between the emitting layer 223 and the second electrode 225.

[0147] The edge of the first electrode 221 may be covered by a dam layer BKL comprising an insulating material. The dam layer BKL may include an opening B-OP that overlaps with the central portion of the first electrode 221 in a plan view.

[0148] The first electrode 221 may include a conductive oxide such as indium tin oxide (“ITO”), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), or zinc aluminum oxide (“AZO”). In another embodiment, the first electrode 221 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound thereof. In another embodiment, the first electrode 221 may also include a layer comprising ITO, IZO, ZnO, AZO, or In2O3 above and / or below the reflective layer.

[0149] The emitting layer 223 may include a high-molecular-weight organic material or a low-molecular-weight organic material that emits light of a specific color. The first functional layer 222 may include a hole transport layer (“HTL”) and / or a hole injection layer (“HIL”). The second functional layer 224 may include an electron transport layer (“ETL”) and / or an electron injection layer (“EIL”).

[0150] The second electrode 225 may include a conductive material with low work function. For example, the second electrode 225 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or any alloy thereof. Optionally, the second electrode 225 may also include a layer comprising ITO, IZO, ZnO, AZO, or In2O3 on a (semi-)transparent layer comprising the above-described materials.

[0151] Figure 7b This is a schematic cross-sectional view of the light-emitting element of a stretchable display device according to an embodiment.

[0152] Reference Figure 7b According to the embodiments, the light-emitting element may include an inorganic light-emitting diode 230 comprising inorganic materials. The inorganic light-emitting diode 230 may include a first semiconductor layer 231, a second semiconductor layer 232, an intermediate layer 233 between the first semiconductor layer 231 and the second semiconductor layer 232, a first electrode 235 electrically connected to the first semiconductor layer 231, and a second electrode 238 electrically connected to the second semiconductor layer 232. The first electrode 235 and the second electrode 238 of the inorganic light-emitting diode 230 may be electrically connected to a first electrode pad 241 and a second electrode pad 242 disposed in the same layer, respectively.

[0153] In some embodiments, the first semiconductor layer 231 may include a p-type semiconductor layer. The p-type semiconductor layer may be selected from those having In x Al y Ga 1-x-y Semiconductor materials with a composition of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) (e.g., GaN, AlN, AlGaN, InGaN, InN, InAlGaN, or AlInN) and may be doped with p-type dopants such as Mg, Zn, Ca, Sr, or Ba.

[0154] The second semiconductor layer 232 may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be selected from those having In... x Al y Ga 1-x-y Semiconductor materials with a composition of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) (e.g., GaN, AlN, AlGaN, InGaN, InN, InAlGaN, or AlInN) and may be doped with n-type dopants such as Si, Ge, or Sn.

[0155] The intermediate layer 233 is the region in which electrons and holes recombine. When electrons and holes recombine, the intermediate layer 233 can transition to a low energy level to generate light with a corresponding wavelength. For example, the intermediate layer 233 may include a region with In... x Al y Ga 1-x-y The semiconductor material is composed of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) and can have a single quantum well structure or a multiple quantum well (“MQW”) structure. Additionally, the intermediate layer 233 can have a quantum wire structure or a quantum dot structure.

[0156] Although Figure 7b The illustration shows a first semiconductor layer 231 comprising a p-type semiconductor layer and a second semiconductor layer 232 comprising an n-type semiconductor layer, but the disclosure is not limited thereto. In another embodiment, the first semiconductor layer 231 may comprise an n-type semiconductor layer and the second semiconductor layer 232 may comprise a p-type semiconductor layer.

[0157] Figures 8a to 8f This is a schematic diagram showing the layer-by-layer layout of the main island portion of a stretchable display device according to an embodiment.

[0158] For reference Figures 4a to 4c As described, the stretchable display device 1 may include a main island portion 11 disposed in a display area DA and a plurality of main bridging portions 12 connected to the main island portion 11. The main island portion 11 may include a plurality of sub-pixels, and the main bridging portions 12 may include lines electrically connected to the sub-pixels.

[0159] The main island portion 11 may have a first boundary E1, a second boundary E2, a third boundary E3, and a fourth boundary E4. The first boundary E1 and the second boundary E2 both extend in a second direction (e.g., the +y direction and / or the -y direction) and are respectively arranged on opposite sides of the main island portion 11. The third boundary E3 and the fourth boundary E4 both extend in a first direction (e.g., the +x direction and / or the -x direction) and connect the first boundary E1 to the second boundary E2.

[0160] In an embodiment, a first sub-pixel, a second sub-pixel, and a third sub-pixel configured to emit light spots of different colors can be arranged in the main island portion 11. The first sub-pixel may include a first light-emitting element and a first pixel driving circuit connected to the first light-emitting element; the second sub-pixel may include a second light-emitting element and a second pixel driving circuit connected to the second light-emitting element; and the third sub-pixel may include a third light-emitting element and a third pixel driving circuit connected to the third light-emitting element. The disclosure is not limited thereto, and one, two, or four sub-pixels may be arranged in the main island portion 11.

[0161] A first pixel driving circuit can be arranged in a first circuit region PCA1, a second pixel driving circuit can be arranged in a second circuit region PCA2, and a third pixel driving circuit can be arranged in a third circuit region PCA3. The first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3 can be arranged side-by-side in a first direction (e.g., the +x direction and / or the -x direction). A first connecting region CA1 can be located between the first boundary E1 of the main island portion 11 and the first circuit region PCA1, and a second connecting region CA2 can be located between the second boundary E2 of the main island portion 11 and the third circuit region PCA3. Lines extending from the main bridging portion 12 to the main island portion 11 can be arranged in the first connecting region CA1 and the second connecting region CA2.

[0162] The first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit may have substantially the same or similar structures. In the following description, the first pixel driving circuit arranged in the first circuit region PCA1 will be the focus, and descriptions of the same or similar structures arranged in the second circuit region PCA2 and the third circuit region PCA3 will be omitted.

[0163] The main island portion 11 may include a semiconductor layer 1100, a first conductive layer 1200, a second conductive layer 1300, a third conductive layer 1400, a fourth conductive layer 1500, a fifth conductive layer 1600, and a sixth conductive layer 1700, which are stacked sequentially on the substrate in the order stated herein (see [link to documentation]). Figure 5 On (100). Semiconductor layer 1100, first conductive layer 1200, second conductive layer 1300, third conductive layer 1400, fourth conductive layer 1500, fifth conductive layer 1600 and sixth conductive layer 1700 can be formed and connected to pixel driving circuit (see 100). Figure 6c The signal and voltage lines of the PC and the connection to the pixel drive circuit (see PC) Figure 6c Transistors and capacitors in a PC.

[0164] Figure 8a A semiconductor layer 1100 and a first conductive layer 1200 disposed on the semiconductor layer 1100 are shown. The semiconductor layer 1100 may be disposed on a substrate (see Figure 1200). Figure 5 On 100), and the buffer layer (see 100) Figure 5 111) can be in semiconductor layer 1100 and substrate (see 111) Figure 5 Between the semiconductor layer 1100 and the first conductive layer 1200. One or more insulating layers (e.g., a first gate insulating layer) may be between the semiconductor layer 1100 and the first conductive layer 1200.

[0165] Reference Figure 8aThe semiconductor layer 1100 may include a first semiconductor pattern 1101, a second semiconductor pattern 1102, and a third semiconductor pattern 1103. The first pixel driving circuit may include the first semiconductor pattern 1101, the second pixel driving circuit may include the second semiconductor pattern 1102, and the third pixel driving circuit may include the third semiconductor pattern 1103.

[0166] The first semiconductor pattern 1101 can be arranged in the first circuit region PCA1, the second semiconductor pattern 1102 can be arranged in the second circuit region PCA2, and the third semiconductor pattern 1103 can be arranged in the third circuit region PCA3.

[0167] In one embodiment, the semiconductor layer 1100 may include a silicon-based semiconductor material (e.g., polycrystalline silicon). In another embodiment, the semiconductor layer 1100 may include an oxide-based semiconductor material (e.g., an oxide selected from at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0168] The first conductive layer 1200 may include a first conductive pattern 1201, a second conductive pattern 1202, a third conductive pattern 1203, a fourth conductive pattern 1204, a fifth conductive pattern 1205, and a sixth conductive pattern 1206. The first conductive layer 1200 may include a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers containing the above-mentioned conductive material.

[0169] The first conductive pattern 1201 can be arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The first conductive pattern 1201 arranged in the first circuit region PCA1 can extend to the first connection region CA1. The first conductive pattern 1201 arranged in the third circuit region PCA3 can extend to the second connection region CA2. The first conductive pattern 1201 can be arranged adjacent to the third boundary E3 of the main island portion 11. The first conductive pattern 1201 can be used as an auxiliary capacitor (see...). Figure 6c The first electrode (lower electrode) of Ca).

[0170] The second conductive pattern 1202 can be arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The second conductive pattern 1202 can be superimposed on the first semiconductor pattern 1101, the second semiconductor pattern 1102, or the third semiconductor pattern 1103 in a planar view to form the first transistor T1. Each of the second conductive patterns 1202 can include the gate electrode of the first transistor T1. That is, the portion of the first semiconductor pattern 1101 superimposed on the second conductive pattern 1202 in a planar view can be the channel region of the first transistor T1, and the impurity region serving as the first terminal or the second terminal can extend to the opposite side of the channel region of the first transistor T1.

[0171] In an embodiment, the width of the first semiconductor pattern 1101 serving as the channel region of the first transistor T1 in the second direction (e.g., the +y direction and / or the -y direction) may be greater than the widths of the second semiconductor pattern 1102 and the third semiconductor pattern 1103 serving as the channel region of the first transistor T1 in the second direction (e.g., the +y direction and / or the -y direction). In an embodiment, the width of the second conductive pattern 1202 disposed in the first circuit region PCA1 in the first direction (e.g., the +x direction and / or the -x direction) may be smaller than the width of the second conductive pattern 1202 disposed in the second circuit region PCA2 and the third circuit region PCA3 in the first direction (e.g., the +x direction and / or the -x direction).

[0172] The third conductive pattern 1203 can extend from the first connection region CA1 to the second connection region CA2, spanning the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The third conductive pattern 1203 can be superimposed on the first semiconductor pattern 1101, the second semiconductor pattern 1102, and the third semiconductor pattern 1103 in a planar view. The third conductive pattern 1203 can be superimposed on the first semiconductor pattern 1101, the second semiconductor pattern 1102, and the third semiconductor pattern 1103 in a planar view to form a seventh transistor T7 and a ninth transistor T9. The third conductive pattern 1203 may include the gate electrode of the seventh transistor T7 and the gate electrode of the ninth transistor T9.

[0173] The fourth conductive pattern 1204 can extend from the first connection region CA1 to the second connection region CA2, spanning the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The fourth conductive pattern 1204 can be superimposed on the first semiconductor pattern 1101, the second semiconductor pattern 1102, and the third semiconductor pattern 1103 in a planar view to form the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8. That is, the fourth conductive pattern 1204 can include the gate electrode of the fifth transistor T5, the gate electrode of the sixth transistor T6, and the gate electrode of the eighth transistor T8.

[0174] The fifth conductive pattern 1205 can extend from the first connection region CA1 to the second connection region CA2, spanning the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The fifth conductive pattern 1205 can be superimposed on the first semiconductor pattern 1101, the second semiconductor pattern 1102, and the third semiconductor pattern 1103 in a planar view to form the second transistor T2 and the third transistor T3. The fifth conductive pattern 1205 may include the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3.

[0175] The sixth conductive pattern 1206 may extend from the first connection region CA1 to the third circuit region PCA3, spanning the first circuit region PCA1 and the second circuit region PCA2. The sixth conductive pattern 1206 may be superimposed on the first semiconductor pattern 1101, the second semiconductor pattern 1102, and the third semiconductor pattern 1103 in a planar view to form the fourth transistor T4. The sixth conductive pattern 1206 may include the gate electrode of the fourth transistor T4.

[0176] Reference Figure 8b The second conductive layer 1300 may include a seventh conductive pattern 1301, an eighth conductive pattern 1302, a ninth conductive pattern 1303, a tenth conductive pattern 1304, and an eleventh conductive pattern 1305. The second conductive layer 1300 may be disposed on the first conductive layer 1200, and one or more insulating layers (e.g., a second gate insulating layer) may be located between the first conductive layer 1200 and the second conductive layer 1300. The second conductive layer 1300 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers comprising the aforementioned conductive material.

[0177] The seventh conductive pattern 1301 can extend from the first connection region CA1 to the second connection region CA2, spanning the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The seventh conductive pattern 1301 can be arranged to overlap with the first conductive pattern 1201 in a planar view and can be used as an auxiliary capacitor (see...). Figure 6cThe second electrode (upper electrode) of Ca).

[0178] The eighth conductive pattern 1302 can be arranged in the first connection region CA1 and the first circuit region PCA1. The eighth conductive pattern 1302 can be a connection electrode for connecting the sustaining voltage line VSL and the seventh conductive pattern 1301.

[0179] The ninth conductive pattern 1303 can be disposed in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The ninth conductive pattern 1303 can be configured to overlap with the second conductive pattern 1202 of the first conductive layer 1200 in a planar view, and can define an opening that exposes a portion of the second conductive pattern 1202. The ninth conductive pattern 1303 can be used as a storage capacitor (see...). Figure 6c The second electrode of Cst) (see Figure 6c CE2), and the second conductive pattern 1202 superimposed on the ninth conductive pattern 1303 in the plan view can be used as the first electrode of the storage capacitor Cst (see CE2). Figure 6c CE1).

[0180] The tenth conductive pattern 1304 can be arranged in the third circuit region PCA3 and the second connection region CA2. The tenth conductive pattern 1304 can be a connection electrode for connecting the 2-1 initialization voltage line VIL2a to the 2-2 initialization voltage line VIL2b.

[0181] The eleventh conductive pattern 1305 can be arranged in the third circuit region PCA3 and the second connection region CA2. The eleventh conductive pattern 1305 can be a connection electrode for connecting the first-1 initialization voltage line VIL1a to the first-2 initialization voltage line VIL1b.

[0182] Reference Figure 8c The third conductive layer 1400 may include twelfth conductive patterns 1401 to twenty-fifth conductive patterns 1414, a first voltage connection line VCL1, and a second voltage connection line VCL2. The third conductive layer 1400 may also include wiring extending from the main island portion 11 to the main bridging portion (see...). Figure 5 The third conductive layer 1400 may be disposed on the second conductive layer 1300, and one or more insulating layers (e.g., interlayer insulating layers) may be disposed between the second conductive layer 1300 and the third conductive layer 1400.

[0183] The third conductive layer 1400 may include a stretchable conductive material. The third conductive layer 1400 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers comprising the aforementioned conductive material. For example, the third conductive layer 1400 may include multiple layers of Ti / Al / Ti.

[0184] The twelfth conductive pattern 1401 can be arranged in the first connection region CA1 and the first circuit region PCA1. The twelfth conductive pattern 1401 can be connected to the seventh conductive pattern 1301 and the eighth conductive pattern 1302 of the second conductive layer 1300 through contact holes.

[0185] The thirteenth conductive pattern 1402 can be arranged in the first connection region CA1, and the twenty-fourth conductive pattern 1413 can be arranged in the second connection region CA2. The thirteenth conductive pattern 1402 and the twenty-fourth conductive pattern 1413 can be connected to the fourth conductive pattern 1204 of the first conductive layer 1200 through contact holes. The thirteenth conductive pattern 1402 can be connected to the first emission control line EMLa of the fourth conductive layer 1500 through contact holes, and the twenty-fourth conductive pattern 1413 can be connected to the second emission control line EMLb of the fourth conductive layer 1500 through contact holes.

[0186] The fourteenth conductive pattern 1403 can be arranged in the first connection region CA1, and the twenty-fifth conductive pattern 1414 can be arranged in the third circuit region PCA3. The fourteenth conductive pattern 1403 and the twenty-fifth conductive pattern 1414 can be connected to the sixth conductive pattern 1206 of the first conductive layer 1200 through contact holes. The fourteenth conductive pattern 1403 can be connected to the third-first scan line SL3a of the fourth conductive layer 1500 through contact holes, and the twenty-fifth conductive pattern 1414 can be connected to the third-second scan line SL3b of the fourth conductive layer 1500 through contact holes.

[0187] The fifteenth conductive pattern 1404 can be arranged in the first circuit region PCA1, and the twenty-third conductive pattern 1412 can be arranged in the second connection region CA2. The fifteenth conductive pattern 1404 and the twenty-third conductive pattern 1412 can be connected to the third conductive pattern 1203 of the first conductive layer 1200 through contact holes. The fifteenth conductive pattern 1404 can be connected to the second-first scan line SL2a of the fourth conductive layer 1500 through contact holes, and the twenty-third conductive pattern 1412 can be connected to the second-second scan line SL2b of the fourth conductive layer 1500 through contact holes.

[0188] The sixteenth conductive pattern 1405 can be arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The sixteenth conductive pattern 1405 can be connected to the first semiconductor pattern 1101, the second semiconductor pattern 1102, or the third semiconductor pattern 1103 of the semiconductor layer 1100 via contact holes. The sixteenth conductive pattern 1405 can be connected to the first conductive pattern 1201 of the first conductive layer 1200 and the twenty-sixth conductive pattern 1501 of the fourth conductive layer 1500 via contact holes. The sixteenth conductive pattern 1405 can connect to the sixth transistor T6, the seventh transistor T7, and the light-emitting element (see...). Figure 6c The first electrode pad 241 of the LED and the auxiliary capacitor (see Figure 6c (Ca).

[0189] The seventeenth conductive pattern 1406 can be disposed in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The seventeenth conductive pattern 1406 can be connected to the first semiconductor pattern 1101, the second semiconductor pattern 1102, or the third semiconductor pattern 1103 of the semiconductor layer 1100 via contact holes. The seventeenth conductive pattern 1406 can also be connected to the seventh conductive pattern 1301 of the second conductive layer 1300 via contact holes. The seventeenth conductive pattern 1406 can be configured to maintain a voltage (see...). Figure 6c The VSUS is transmitted to the ninth transistor T9.

[0190] The eighteenth conductive pattern 1407 can be arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The eighteenth conductive pattern 1407 can be connected to the first semiconductor pattern 1101, the second semiconductor pattern 1102, or the third semiconductor pattern 1103 of the semiconductor layer 1100 via contact holes. The eighteenth conductive pattern 1407 can each be connected to the third voltage connection line VCL3 of the fourth conductive layer 1500 via contact holes. The eighteenth conductive pattern 1407 can be configured to receive the drive power supply voltage (see...) Figure 6c The VDD is transmitted to the eighth transistor T8.

[0191] The nineteenth conductive pattern 1408 can be arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The nineteenth conductive pattern 1408 can be connected to the first semiconductor pattern 1101, the second semiconductor pattern 1102, or the third semiconductor pattern 1103 of the semiconductor layer 1100 via contact holes. The nineteenth conductive pattern 1408 can also be connected to the ninth conductive pattern 1303 of the second conductive layer 1300 via contact holes. The nineteenth conductive pattern 1408 can connect the eighth transistor T8 to the storage capacitor (see...). Figure 6c The second electrode of Cst) (see Figure 6c CE2).

[0192] The twentieth conductive pattern 1409 can be arranged in the first circuit region PCA1. The twentieth conductive pattern 1409 can be connected to the first semiconductor pattern 1101 of the semiconductor layer 1100 through a contact hole. The twentieth conductive pattern 1409 can connect the second transistor T2 of the first pixel driving circuit to the fifth transistor T5.

[0193] The 21st conductive pattern 1410 can be arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The 21st conductive pattern 1410 can be connected to the first semiconductor pattern 1101, the second semiconductor pattern 1102, and the third semiconductor pattern 1103 of the semiconductor layer 1100 via contact holes. The 21st conductive pattern 1410 can also be connected to the second conductive pattern 1202 of the first conductive layer 1200 via contact holes. The 21st conductive pattern 1410 can also connect the third transistor T3, the fourth transistor T4, and the storage capacitor (see...) Figure 6c The first electrode of Cst) (see Figure 6c The CE1s are connected to each other.

[0194] The twenty-second conductive pattern 1411 can be arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. For example, the twenty-second conductive pattern 1411 arranged in the first circuit region PCA1 can be connected to the first semiconductor pattern 1101 of the semiconductor layer 1100 and the first data line DL1 of the fourth conductive layer 1500 through contact holes. Similarly, the twenty-second conductive pattern 1411 arranged in the second circuit region PCA2 can be connected to the second semiconductor pattern 1102 of the semiconductor layer 1100 and the second data line DL2 of the fourth conductive layer 1500 through contact holes, and the twenty-second conductive pattern 1411 arranged in the third circuit region PCA3 can be connected to the third semiconductor pattern 1103 of the semiconductor layer 1100 and the third data line DL3 of the fourth conductive layer 1500 through contact holes. The twenty-second conductive pattern 1411 can connect the second transistor T2 to the data line DL.

[0195] The first voltage connection line VCL1 can extend from the first circuit region PCA1 to the third circuit region PCA3, spanning the second circuit region PCA2. The first voltage connection line VCL1 can be connected to the third voltage connection line VCL3 of the fourth conductive layer 1500 through a contact hole.

[0196] The second voltage connection line VCL2 can extend from the first connection area CA1 to the third circuit area PCA3, spanning the first circuit area PCA1 and the second circuit area PCA2. The second voltage connection line VCL2 can be connected to the third voltage connection line VCL3 of the fourth conductive layer 1500 through a contact hole.

[0197] The main bridging portion may include a first bridging portion extending from the first boundary E1 of the main island portion 11, a second bridging portion extending from the second boundary E2, a third bridging portion extending from the third boundary E3, and a fourth bridging portion extending from the fourth boundary E4.

[0198] The third conductive layer 1400 may include a first-1 initialization voltage line VIL1a, a second-1 initialization voltage line VIL2a, a first-1 scan line SL1a, and a first sustaining voltage line VSLa extending from the main island portion 11 to the first bridging portion. The third conductive layer 1400 may also include a first-2 initialization voltage line VIL1b, a second-2 initialization voltage line VIL2b, a first-2 scan line SL1b, and a second sustaining voltage line VSLb extending from the main island portion 11 to the second bridging portion. Furthermore, the third conductive layer 1400 may include a third sustaining voltage line VSLc extending from the main island portion 11 to the third bridging portion and a fourth sustaining voltage line VSLd extending from the main island portion 11 to the fourth bridging portion.

[0199] Constructed as a transmission sustaining voltage (see) Figure 6c The sustaining voltage line VSL of the VSUS may include a first sustaining voltage line VSLa, a second sustaining voltage line VSLb, a third sustaining voltage line VSLc, and a fourth sustaining voltage line VSLd. The first sustaining voltage line VSLa, the second sustaining voltage line VSLb, the third sustaining voltage line VSLc, and the fourth sustaining voltage line VSLd may extend along the first boundary E1, the second boundary E2, and the fourth boundary E4 of the main island portion 11, and may be connected to each other.

[0200] The first sustaining voltage line VSLa and the second sustaining voltage line VSLb, which are adjacent to each other in the first direction (e.g., the +x direction and / or the -x direction), and the third sustaining voltage line VSLc and the fourth sustaining voltage line VSLd, which are adjacent to each other in the second direction (e.g., the +y direction and / or the -y direction), can be connected to each other in the main island portion 11. The first sustaining voltage line VSLa, the second sustaining voltage line VSLb, the third sustaining voltage line VSLc, and the fourth sustaining voltage line VSLd can be integrally formed into a single body in the third conductive layer 1400. Therefore, the sustaining voltage line VSL can be integrated into the stretchable display device (see...). Figure 1 The display area of ​​1) (see Figure 1 The DA has a network structure.

[0201] The first sustaining voltage line VSLa can be connected to the eighth conductive pattern 1302 of the second conductive layer 1300 via a contact hole. The eighth conductive pattern 1302 can be connected to the twelfth conductive pattern 1401 of the third conductive layer 1400, and the twelfth conductive pattern 1401 can be connected to the seventh conductive pattern 1301 of the second conductive layer 1300. The seventh conductive pattern 1301 can be connected to the first semiconductor pattern 1101 and the second semiconductor pattern 1102 of the semiconductor layer 1100 via the seventeenth conductive pattern 1406. The third sustaining voltage line VSLc can be connected to the third semiconductor pattern 1103 of the semiconductor layer 1100 and the seventh conductive pattern 1301 of the second conductive layer 1300 via a contact hole.

[0202] Constructed to transmit the first initialization voltage (see Figure 6c The first initialization voltage line of Vint (see Vint) Figure 6c The VIL1 may include a first-1 initialization voltage line VIL1a and a first-2 initialization voltage line VIL1b connected to each other in a first direction (e.g., the +x direction and / or the -x direction). The first-1 initialization voltage line VIL1a may extend approximately parallel to the first boundary E1 in the first connection region CA1 and may extend from the first connection region CA1 to the third circuit region PCA3, crossing the first circuit region PCA1 and the second circuit region PCA2. The first-1 initialization voltage line VIL1a may be connected to the first semiconductor pattern 1101, the second semiconductor pattern 1102, and the third semiconductor pattern 1103 of the semiconductor layer 1100 through contact holes. The first-1 initialization voltage line VIL1a and the first-2 initialization voltage line VIL1b may be connected to each other in the main island 11 through the eleventh conductive pattern 1305 of the second conductive layer 1300.

[0203] Constructed to transmit the second initialization voltage (see Figure 6c The second initialization voltage line of Vaint (see Vaint) Figure 6cThe VIL2 may include a second-1 initialization voltage line VIL2a and a second-2 initialization voltage line VIL2b connected to each other in a first direction (e.g., the +x direction and / or the -x direction). The second-1 initialization voltage line VIL2a may extend from the first connection region CA1 to the third circuit region PCA3, spanning the first circuit region PCA1 and the second circuit region PCA2. The second-2 initialization voltage line VIL2b may extend from the second connection region CA2 along the second boundary E2. The second-1 initialization voltage line VIL2a may be connected to the first semiconductor pattern 1101, the second semiconductor pattern 1102, and the third semiconductor pattern 1103 through contact holes. The second-1 initialization voltage line VIL2a and the second-2 initialization voltage line VIL2b may be connected to each other in the main island 11 through the tenth conductive pattern 1304 of the second conductive layer 1300.

[0204] Constructed to transmit the first scan signal (see Figure 6c The first scan line of GW) (see Figure 6c The SL1 may include a first-1 scan line SL1a and a first-2 scan line SL1b connected to each other in a first direction (e.g., the +x direction and / or the -x direction). The first-1 scan line SL1a may extend substantially parallel to the first boundary E1 in the first connection region CA1. The first-2 scan line SL1b may be arranged in the second connection region CA2, and the first-1 scan line SL1a and the first-2 scan line SL1b may be connected to each other through the fifth conductive pattern 1205 of the first conductive layer 1200.

[0205] Reference Figure 8d The fourth conductive layer 1500 may include a twenty-sixth conductive pattern 1501 and a third voltage connection line VCL3. Additionally, the fourth conductive layer 1500 may also include wiring extending from the main island portion 11 to the main bridging portion (see...). Figure 5 The fourth conductive layer 1500 may be disposed on the third conductive layer 1400, and one or more organic insulating layers (e.g., the first organic insulating layer) may be disposed between the third conductive layer 1400 and the fourth conductive layer 1500.

[0206] The fourth conductive layer 1500 may include a stretchable conductive material. The fourth conductive layer 1500 may include conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers comprising the aforementioned conductive materials. For example, the fourth conductive layer 1500 may include multiple layers of Ti / Al / Ti.

[0207] The 26th conductive pattern 1501 can be arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The 26th conductive pattern 1501 can be connected via contact holes to the 16th conductive pattern 1405 of the third conductive layer 1400 and the 27th conductive pattern 1601 of the fifth conductive layer 1600. The 26th conductive pattern 1501 can be connected to the sixth transistor T6, the seventh transistor T7, and the light-emitting element (see...). Figure 6c The first electrode and auxiliary capacitor of the LED (see Figure 6c (Ca).

[0208] Each of the third voltage connection lines VCL3 can be connected to a first pixel driving circuit, a second pixel driving circuit, or a third pixel driving circuit. The third voltage connection line VCL3 of the first pixel driving circuit can extend from the first circuit region PCA1 to the first connection region CA1; the third voltage connection line VCL3 of the second pixel driving circuit can extend from the second circuit region PCA2 to the first circuit region PCA1; and the third voltage connection line VCL3 of the third pixel driving circuit can extend from the third circuit region PCA3 to the second circuit region PCA2. Each of the third voltage connection lines VCL3 can be connected via a contact hole to the eighteenth conductive pattern 1407 of the third conductive layer 1400, the first voltage connection line VCL1, and the second voltage connection line VCL2.

[0209] The third voltage connection line VCL3 of the first pixel driving circuit can be connected to the first driving voltage line VDDLa of the fifth conductive layer 1600 through a contact hole. The third voltage connection line VCL3 of the third pixel driving circuit can also be connected to the second driving voltage line VDDLb, the third driving voltage line VDDLc, and the fourth driving voltage line VDDLd of the fifth conductive layer 1600 through contact holes. The first driving voltage lines VDDLa to the fourth driving voltage line VDDLd can be connected to each other in the main island portion 11 through the first voltage connection line VCL1, the second voltage connection line VCL2, and the third voltage connection line VCL3. Therefore, the driving voltage line VDDL, including the first driving voltage line VDDLa to the fourth driving voltage line VDDLd, can be connected in the display area of ​​the stretchable display device (see...). Figure 1 The DA has a network structure.

[0210] The fourth conductive layer 1500 may include a second-first scan line SL2a, a first emission control line EMLa, and a third-first scan line SL3a, each extending from the main island portion 11 to the first bridging portion. The fourth conductive layer 1500 may also include a second-second scan line SL2b, a second emission control line EMLb, and a third-second scan line SL3b, each extending from the main island portion 11 to the second bridging portion. The fourth conductive layer 1500 may also include a data line DL that crosses the main island portion 11 and extends from the third bridging portion to the fourth bridging portion.

[0211] Constructed to transmit the second scan signal (see Figure 6c The second scan line of GB (see GB) Figure 6c The SL2 may include a second-1 scan line SL2a and a second-2 scan line SL2b connected to each other in a first direction (e.g., the +x direction and / or the -x direction). The second-1 scan line SL2a may extend from the first connection region CA1 to the first circuit region PCA1 along the third boundary E3, and the second-2 scan line SL2b may extend from the second connection region CA2 along the second boundary E2. The second-1 scan line SL2a and the second-2 scan line SL2b may be connected to each other in the main island 11 via the fifteenth conductive pattern 1404 of the third conductive layer 1400, the third conductive pattern 1203 of the first conductive layer 1200, and the twenty-third conductive pattern 1412 of the third conductive layer 1400.

[0212] Constructed to transmit transmit control signals (see) Figure 6c The transmit control line of the EM (see) Figure 6c The EML (Emission Control Line) may include a first transmission control line EML11 and a second transmission control line EMLb connected to each other in a first direction (e.g., the +x direction and / or the -x direction). The first transmission control line EML11 may extend substantially parallel to the first boundary E1 in the first connection region CA1, and the second transmission control line EMLb may extend substantially parallel to the second boundary E2 in the second connection region CA2. The first transmission control line EML11 and the second transmission control line EMLb may be connected to each other in the main island 11 via the thirteenth conductive pattern 1402 of the third conductive layer 1400, the fourth conductive pattern 1204 of the first conductive layer 1200, and the twenty-fourth conductive pattern 1413 of the third conductive layer 1400.

[0213] Constructed to transmit the third scan signal (see Figure 6c The third scan line of the GI (see GI) Figure 6cThe SL3 may include a third-1 scan line SL3a and a third-2 scan line SL3b connected to each other in a first direction (e.g., the +x direction and / or the -x direction). The third-1 scan line SL3a may extend from the first connection region CA1 along the first boundary E1, and the third-2 scan line SL3b may extend from the second connection region CA2 along the fourth boundary E4 to the third circuit region PCA3. The third-1 scan line SL3a and the third-2 scan line SL3b may be connected to each other in the main island 11 via the fourteenth conductive pattern 1403 of the third conductive layer 1400, the sixth conductive pattern 1206 of the first conductive layer 1200, and the twenty-fifth conductive pattern 1414 of the third conductive layer 1400.

[0214] The data line DL may include a first data line DL1 connected to the first pixel driving circuit, a second data line DL2 connected to the second pixel driving circuit, and a third data line DL3 connected to the third pixel driving circuit.

[0215] The first data line DL1, the second data line DL2, and the third data line DL3 can extend from the first connection region CA1 to the second connection region CA2, spanning the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. In this case, the first data line DL1 can approximately cross the first circuit region PCA1 in a second direction (e.g., the +y direction and / or the -y direction), the second data line DL2 can approximately cross the second circuit region PCA2 in a second direction (e.g., the +y direction and / or the -y direction), and the third data line DL3 can approximately cross the third circuit region PCA3 in a second direction (e.g., the +y direction and / or the -y direction). Each of the first data line DL1, the second data line DL2, and the third data line DL3 can be connected to the first semiconductor pattern 1101, the second semiconductor pattern 1102, or the third semiconductor pattern 1103 of the semiconductor layer 1100 via the twenty-second conductive pattern 1411. Each of the first data line DL1, the second data line DL2, and the third data line DL3 can be configured to carry a data signal (see...) Figure 6c The Dm is transmitted to the second transistor T2 of the corresponding pixel driving circuit.

[0216] Reference Figure 8e The fifth conductive layer 1600 may include a twenty-seventh conductive pattern 1601 and a common voltage line VSSL and a drive voltage line VDDL, each extending from the main island portion 11 to the main bridge portion. The fifth conductive layer 1600 may be disposed on the fourth conductive layer 1500, and one or more organic insulating layers (e.g., a second organic insulating layer) may be disposed between the fourth conductive layer 1500 and the fifth conductive layer 1600.

[0217] The fifth conductive layer 1600 may include a stretchable conductive material. The fifth conductive layer 1600 may include conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers comprising the aforementioned conductive materials. For example, the fifth conductive layer 1600 may include multiple layers of Ti / Al / Ti.

[0218] The 27th conductive pattern 1601 can be arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The 27th conductive pattern 1601 of the first pixel driving circuit can extend from the first circuit region PCA1 to the first connection region CA1, and the 27th conductive pattern 1601 of the third pixel driving circuit can extend from the third circuit region PCA3 to the second connection region CA2. The 27th conductive pattern 1601 can be connected to the 26th conductive pattern 1501 of the fourth conductive layer 1500 and the first electrode pad 241 of the sixth conductive layer 1700 through contact holes. The 27th conductive pattern 1601 can connect the light-emitting element (see...) through the 16th conductive pattern 1405 of the third conductive layer 1400 and the 26th conductive pattern 1501 of the fourth conductive layer 1500. Figure 6c The first electrode pad 241 of the LED is connected to the sixth transistor T6, the seventh transistor T7, and the auxiliary capacitor (see...). Figure 6c The first electrode of Ca).

[0219] Constructed to transmit drive power supply voltage (see) Figure 6c The driving voltage line VDDL of VDD may include a first driving voltage line VDDLa extending from the main island 11 to the first bridge portion, a second driving voltage line VDDLb extending from the main island 11 to the second bridge portion, a third driving voltage line VDDLc extending from the main island 11 to the third bridge portion, and a fourth driving voltage line VDDLd extending from the main island 11 to the fourth bridge portion.

[0220] The first driving voltage line VDDLa can be connected to the third voltage connection line VCL3 of the first pixel circuit driver through a contact hole. The second driving voltage line VDDLb, the third driving voltage line VDDLc, and the fourth driving voltage line VDDLd can each be connected to the third voltage connection line VCL3 of the third pixel circuit driver through a contact hole. The third voltage connection line VCL3 can be connected to the first voltage connection line VCL1 and the second voltage connection line VCL2 of the third conductive layer 1400 through a contact hole.

[0221] The first driving voltage line VDDLa and the second driving voltage line VDDLb, which are adjacent to each other in the first direction (e.g., the +x direction and / or the -x direction), and the third driving voltage line VDDLc and the fourth driving voltage line VDDLd, which are adjacent to each other in the second direction (e.g., the +y direction and / or the -y direction), can be connected to each other in the main island 11 via voltage connection lines VCL1, VCL2, and VCL3. The voltage connection lines VCL1, VCL2, and VCL3 can be arranged in a different layer than the layer in which the first driving voltage line VDDLa, the second driving voltage line VDDLb, the third driving voltage line VDDLc, and the fourth driving voltage line VDDLd are arranged.

[0222] Constructed to transmit common power supply voltage (see) Figure 6c The common voltage line VSSL of the VSS may include a first common voltage line VSSLa extending from the main island 11 to the first bridging portion, a second common voltage line VSSLb extending from the main island 11 to the second bridging portion, a third common voltage line VSSLc extending from the main island 11 to the third bridging portion, and a fourth common voltage line VSSLd extending from the main island 11 to the fourth bridging portion.

[0223] The first common voltage line VSSLa, the second common voltage line VSSLb, the third common voltage line VSSLc, and the fourth common voltage line VSSLd may extend within the main island portion 11 in a first direction (e.g., +x and / or -x) and a second direction (e.g., +y and / or -y), and may be connected to each other. The first common voltage line VSSLa, the second common voltage line VSSLb, the third common voltage line VSSLc, and the fourth common voltage line VSSLd may be integrally formed into a single body. The opening OP may be defined between the first common voltage line VSSLa, the second common voltage line VSSLb, the third common voltage line VSSLc, and the fourth common voltage line VSSLd.

[0224] The first common voltage line VSSLa and the second common voltage line VSSLb, which are connected to each other in the first direction (e.g., the +x direction and / or the -x direction), and the third common voltage line VSSLc and the fourth common voltage line VSSLd, which are connected to each other in the second direction (e.g., the +y direction and / or the -y direction), can be connected to each other in the main island 11. Therefore, the common voltage line VSSL can be connected to each other in the stretchable display device (see...). Figure 1 The display area of ​​1) (see Figure 1 The DA has a network structure.

[0225] Reference Figure 8fThe sixth conductive layer 1700 may include a first electrode pad 241 and a second electrode pad 242. The sixth conductive layer 1700 may be disposed on the fifth conductive layer 1600, and one or more organic insulating layers (e.g., a third organic insulating layer) may be present between the fifth conductive layer 1600 and the sixth conductive layer 1700. The sixth conductive layer 1700 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers comprising the aforementioned conductive material. In an embodiment, when the first electrode pad 241 and the second electrode pad 242 are connected to the light-emitting element via eutectic bonding (see...), Figure 6c When used as an electrode for an LED, the sixth conductive layer 1700 may have a multilayer structure including a copper (Cu) layer, or may include a copper (Cu) alloy. In another embodiment, the sixth conductive layer 1700 may include a conductive organic material. For example, the sixth conductive layer 1700 may include carbon black. In another embodiment, the sixth conductive layer 1700 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). Optionally, the sixth conductive layer 1700 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound thereof. In another embodiment, the sixth conductive layer 1700 may also include a layer comprising ITO, IZO, ZnO, AZO, or In2O3 above and / or below the reflective layer. For example, the sixth conductive layer 1700 may include an ITO layer, an Ag layer, and an ITO layer stacked in the order stated herein.

[0226] The first electrode pad 241 can be connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively. The first electrode pad 241 can all have an island shape. The first electrode pad 241 can be connected to the twenty-seventh conductive pattern 1601 of the fifth conductive layer 1600 through contact holes. The first electrode pad 241 can connect to the light-emitting element (see...) Figure 6c The first electrode of the LED is connected to the sixth transistor T6, the seventh transistor T7, and the auxiliary capacitor (see...). Figure 6c The first electrode of Ca).

[0227] The second electrode pad 242 can extend from the first connection region CA1 to the second connection region CA2, spanning the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The second electrode pad 242 can have an island shape in which its length in a first direction (e.g., +x and / or -x) is greater than its length in a second direction (e.g., +y and / or -y). The second electrode pad 242 can be commonly disposed within the light-emitting elements arranged in the main island portion 11. For example, the second electrode of each of the first, second, and third light-emitting elements can be connected to the second electrode pad 242. The second electrode pad 242 can be connected to the common voltage line VSSL of the fifth conductive layer 1600 via contact holes.

[0228] exist Figure 8f In the embodiments shown, the light-emitting element may include an inorganic light-emitting diode (see Figure 7b (230), but in other embodiments, the light-emitting element may include an organic light-emitting diode (see 230). Figure 7a (220). For example, the sixth conductive layer 1700 may include a first electrode (see 220). Figure 7a Instead of the first electrode pad 241, the sixth conductive layer 1700 may comprise a conductive oxide such as ITO, IZO, ZnO, In2O3, IGO, or AZO. Alternatively, the sixth conductive layer 1700 may comprise a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound thereof. In another embodiment, the sixth conductive layer 1700 may also comprise a layer comprising ITO, IZO, ZnO, AZO, or In2O3 above and / or below the reflective layer.

[0229] Figure 9a This is a schematic diagram illustrating the layout of the third conductive layer of a stretchable display device according to an embodiment. Figure 9b and Figure 9c This is a schematic layout diagram showing a portion of the third conductive layer of a stretchable display device according to an embodiment, and Figure 9d This is a schematic diagram illustrating the layout of the sustaining voltage lines of a stretchable display device according to an embodiment.

[0230] Reference Figures 9a to 9dThe stretchable display device may include a main island portion 11 and a plurality of main bridging portions 12 connected to the main island portion 11 in the display area DA. The main bridging portions 12 may include horizontal bridging portions BRh on opposite sides of the main island portion 11 in a first direction (e.g., the +x direction and / or the -x direction) and vertical bridging portions BRv on opposite sides of the main island portion 11 in a second direction (e.g., the +y direction and / or the -y direction).

[0231] The horizontal bridging portion BRh may include a first bridging portion BRh1 disposed at a first boundary E1 of the main island portion 11 and a second bridging portion BRh2 disposed at a second boundary E2 of the main island portion 11. The first bridging portion BRh1 may be arranged adjacent to the corner where the first boundary E1 of the main island portion 11 intersects with the third boundary E3 of the main island portion 11. The second bridging portion BRh2 may be arranged adjacent to the corner where the second boundary E2 of the main island portion 11 intersects with the fourth boundary E4 of the main island portion 11. The first bridging portion BRh1 and the second bridging portion BRh2 may connect the main island portions 11 that are adjacent to each other in a first direction (e.g., the +x direction and / or the -x direction).

[0232] Outside the first boundary E1 and the second boundary E2 of the main island portion 11, the first bridging portion BRh1 and the second bridging portion BRh2 may have the same shape. For example... Figure 9b As shown, the horizontal bridging portion BRh may include a first curved portion CNP1, a second curved portion CNP2, and a straight portion SP connecting the first curved portion CNP1 to the second curved portion CNP2. The straight portion SP of the horizontal bridging portion BRh may extend on a fourth direction DR4 that intersects a first direction (e.g., +x and / or -x) and a second direction (e.g., +y and / or -y) and is parallel to the plane defined by the first direction (e.g., +x and / or -x) and the second direction (e.g., +y and / or -y).

[0233] The first bridging portion BRh1 may include a first-1 initialization voltage line VIL1a, a second-1 initialization voltage line VIL2a, a first-1 scan line SL1a, and a first sustaining voltage line VSLa, all disposed in the third conductive layer 1400. The second bridging portion BRh2 may include a first-2 initialization voltage line VIL1b, a second-2 initialization voltage line VIL2b, a first-2 scan line SL1b, and a second sustaining voltage line VSLb, all disposed in the third conductive layer 1400.

[0234] Initialization voltage lines VIL1a (1-1) and VIL1b (1-2) can pass through the second conductive layer (see...). Figure 8b The eleventh conductive pattern of (1300) (see) Figure 8b(1305) are connected to each other in the main island section 11. The first-1 initialization voltage line VIL1a and the first-2 initialization voltage line VIL1b can be configured to apply the first initialization voltage (see Figure 6c The Vint) is transferred to the fourth transistor (see Vint) Figure 8a The first initialization voltage line VIL1 of one terminal of T4).

[0235] Initialization voltage lines VIL2a (2-1) and VIL2b (2-2) can pass through the second conductive layer (see...). Figure 8b The tenth conductive pattern of (1300) (see Figure 8b (1304) are connected to each other in the main island section 11. The 2-1 initialization voltage line VIL2a and the 2-2 initialization voltage line VIL2b can be configured to apply the second initialization voltage (see Figure 6c Vaint) is transmitted to the seventh transistor (see Vaint) Figure 8a The second initialization voltage line VIL2 of one terminal of T7).

[0236] Scan line SL1a (1-1) and scan line SL1b (1-2) can pass through the first conductive layer (see...). Figure 8a The fifth conductive pattern of 1200 (see Figure 8a (1205) are connected to each other in the main island section 11. The first-1 scan line SL1a and the first-2 scan line SL1b can be configured to transmit the first scan signal (see Figure 6c The GW) is transmitted to the second transistor (see Figure 8a The gate electrode of T2 and the third transistor (see T2) Figure 8a The first scan line SL1 of the gate electrode of T3).

[0237] The horizontal bridging portion BRh may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a first scan line SL1 connected to each other in the main island portion 11 in the third conductive layer 1400 in a first direction (e.g., the +x direction and / or the -x direction).

[0238] The first sustaining voltage line VSLa and the second sustaining voltage line VSLb can be horizontal sustaining voltage lines (or "first voltage lines") VSLh. The horizontal bridging portion BRh can include horizontal sustaining voltage lines VSLh connected to each other in a first direction (e.g., the +x direction and / or the -x direction). The horizontal sustaining voltage lines VSLh can have a first width w1 in a direction perpendicular to the extension direction of the horizontal sustaining voltage lines VSLh.

[0239] like Figure 9bAs shown, the horizontal sustaining voltage line VSLh, the first initialization voltage line VIL1, the first scan line SL1, and the second initialization voltage line VIL2 can be sequentially separated from each other in the first bend CNP1 of the horizontal bridging portion BRh in the direction from the inner bend boundary CIE to the outer bend boundary COE, and the second initialization voltage line VIL2, the first scan line SL1, the first initialization voltage line VIL1, and the horizontal sustaining voltage line VSLh can be sequentially separated from each other in the second bend CNP2 in the direction from the inner bend boundary CIE to the outer bend boundary COE.

[0240] The routing closest to the inner boundary (CIE) of the bend can be separated from the inner boundary (CIE) by a first distance d1, and the routing closest to the outer boundary (COE) of the bend can be separated from the outer boundary (COE) of the bend by a second distance d2. For example, as... Figure 9b As shown, in the second bend CNP2, the second initialization voltage line VIL2, which is the wiring closest to the inner bend boundary CIE, can be separated from the inner bend boundary CIE by a first distance d1, and the horizontal maintenance voltage line VSLh, which is the wiring closest to the outer bend boundary COE, can be separated from the outer bend boundary COE by a second distance d2. When a stretchable display device (see...) Figure 1 1) When stretched by an external force, a greater stress can be applied to the inner boundary CIE of the bend than to the outer boundary COE of the bend. Therefore, the first distance d1 can be greater than the second distance d2.

[0241] The vertical bridging portion BRv may include a third bridging portion BRv1 located at the third boundary E3 of the main island portion 11 and a fourth bridging portion BRv2 located at the fourth boundary E4 of the main island portion 11. The third bridging portion BRv1 may be arranged adjacent to the corner where the third boundary E3 of the main island portion 11 intersects with the second boundary E2 of the main island portion 11. The fourth bridging portion BRv2 may be arranged adjacent to the corner where the first boundary E1 of the main island portion 11 intersects with the fourth boundary E4 of the main island portion 11. The third bridging portion BRv1 and the fourth bridging portion BRv2 may connect the main island portions 11 that are adjacent to each other in a second direction (e.g., the +y direction and / or the -y direction).

[0242] Outside the third boundary E3 and the fourth boundary E4 of the main island section 11, the third bridging section BRv1 and the fourth bridging section BRv2 may have the same shape. For example... Figure 9c As shown, the vertical bridging portion BRv may include a third bend CNP3, a fourth bend CNP4, and a straight portion SP connecting the third bend CNP3 to the fourth bend CNP4. The straight portion SP of the vertical bridging portion BRv may extend in a fifth direction DR5 that intersects the first direction (e.g., the +x direction and / or the -x direction) and the second direction (e.g., the +y direction and / or the -y direction).

[0243] The third bridging portion BRv1 may include a third sustaining voltage line VSLc disposed in the third conductive layer 1400, and the fourth bridging portion BRv2 may include a fourth sustaining voltage line VSLd disposed in the third conductive layer 1400. The third sustaining voltage line VSLc and the fourth sustaining voltage line VSLd may be a vertical sustaining voltage line (or "fourth voltage line") VSLv. The vertical sustaining voltage line VSLv may have a second width w2 in a direction perpendicular to the extension direction of the vertical sustaining voltage line VSLv. The second width w2 of the vertical sustaining voltage line VSLv may be greater than the first width w1 of the horizontal sustaining voltage line VSLh.

[0244] In an embodiment, the vertical bridging portion BRv may consist only of the vertical sustaining voltage line VSLv in the third conductive layer 1400. Therefore, the second width w2 of the vertical sustaining voltage line VSLv may be included in the main bridging portion (see...). Figure 5 The wiring WL in 12) has the maximum width.

[0245] In an embodiment, the ratio of the first width w1 of the horizontal sustaining voltage line VSLh to the second width w2 of the vertical sustaining voltage line VSLv can be determined according to the display area (see [link]). Figure 1 The length of the DA in the first direction (e.g., the +x direction and / or the -x direction) and the display area (see Figure 1 The length of the display area DA in the second direction (e.g., the +y direction and / or the -y direction) varies. For example, when the display area DA has an elongated shape in the second direction (e.g., the +y direction and / or the -y direction), the stress applied to the vertical sustaining voltage line VSLv can be greater than the stress applied to the horizontal sustaining voltage line VSLh. Therefore, the second width w2 of the vertical sustaining voltage line VSLv can be greater than the first width w1 of the horizontal sustaining voltage line VSLh.

[0246] like Figure 9c As shown, the vertical bridging portion BRv can be separated from the inner curved boundary CIE by a first distance d1, and can be separated from the outer curved boundary COE by a second distance d2. The first distance d1 can be greater than the second distance d2.

[0247] like Figure 9dAs shown, the first sustaining voltage line VSLa, the second sustaining voltage line VSLb, the third sustaining voltage line VSLc, and the fourth sustaining voltage line VSLd can extend along the first boundary E1, the second boundary E2, and the fourth boundary E4 of the main island portion 11, and can be connected to each other. The first sustaining voltage line VSLa, the second sustaining voltage line VSLb, the third sustaining voltage line VSLc, and the fourth sustaining voltage line VSLd can be integrally formed into a single body in the third conductive layer 1400, and can have a mesh structure that connects the main island portions 11 adjacent to each other in the first direction (e.g., the +x direction and / or the -x direction) to the main island portions 11 adjacent to each other in the second direction (e.g., the +y direction and / or the -y direction).

[0248] Figure 10a This is a schematic layout diagram of the fourth conductive layer 1500 of the stretchable display device according to an embodiment, and Figure 10b and Figure 10c This is a layout diagram schematically showing a portion of the fourth conductive layer 1500 of a stretchable display device according to an embodiment.

[0249] Reference Figures 10a to 10c The stretchable display device may include a main island portion 11 and a plurality of main bridge portions 12 connected to the main island portion 11 in the display area DA.

[0250] The main bridging portion 12 may include a horizontal bridging portion BRh and a vertical bridging portion BRv. The first bridging portion BRh1, which is arranged at the first boundary E1 of the main island portion 11, and the second bridging portion BRh2, which is arranged at the second boundary E2, may be horizontal bridging portions BRh with the same shape outside the first boundary E1 and the second boundary E2 of the main island portion 11.

[0251] The first bridging portion BRh1 may include a second-first scan line SL2a, a first emission control line EMLa, and a third-first scan line SL3a disposed in the fourth conductive layer 1500. The second bridging portion BRh2 may include a second-second scan line SL2b, a second emission control line EMLb, and a third-second scan line SL3b disposed in the fourth conductive layer 1500.

[0252] Scan lines SL2a and SL2b, 2-1 and 2-2 respectively, can be connected to each other in the main island section 11 via the fifteenth conductive pattern 1404 and the twenty-third conductive pattern 1412 of the third conductive layer 1400 and the third conductive pattern 1203 of the first conductive layer 1200. Scan lines SL2a and SL2b can be configured to carry the second scan signal (see...) Figure 6c The GB) is transmitted to the seventh transistor (see GB) Figure 8a The gate electrode of T7 and the ninth transistor (see T7) Figure 8aThe second scan line SL2 of the gate electrode of T9).

[0253] The first transmission control line EMLa and the second transmission control line EMLb can be connected to each other in the main island portion 11 via the thirteenth conductive pattern 1402 of the third conductive layer 1400, the fourth conductive pattern 1204 of the first conductive layer 1200, and the twenty-fourth conductive pattern 1413 of the third conductive layer 1400. The first transmission control line EMLa and the second transmission control line EMLb can be configured to transmit control signals (see...) Figure 6c The EM is transmitted to the fifth transistor (see EM). Figure 8a The gate electrode of T5, the sixth transistor (see T5) Figure 8a The gate electrode of T6 and the eighth transistor (see T6) Figure 8a The emitter control line EML of the gate electrode of T8).

[0254] Scan lines SL3a (3-1) and SL3b (3-2) can be connected to each other in the main island section 11 via the fourteenth conductive pattern 1403 of the third conductive layer 1400, the sixth conductive pattern 1206 of the first conductive layer 1200, and the twenty-fifth conductive pattern 1414 of the third conductive layer 1400. Scan lines SL3a (3-1) and SL3b (3-2) can be configured to transmit the third scan signal (see...) Figure 6c The GI) is transmitted to the fourth transistor (see GI) Figure 8a The third scan line SL3 of the gate electrode of T4).

[0255] In other words, such as Figure 10b As shown, the horizontal bridging portion BRh may include a second scan line SL2, an emission control line EML, and a third scan line SL3 connected to each other in the main island portion 11 in the fourth conductive layer 1500 in a first direction (e.g., the +x direction and / or the -x direction).

[0256] The third scan line SL3, the emission control line EML, and the second scan line SL2 can be sequentially separated from each other in the first bend CNP1 in the direction from the inner boundary CIE to the outer boundary COE of the bend, and the second scan line SL2, the emission control line EML, and the third scan line SL3 can be sequentially separated from each other in the second bend CNP2 in the direction from the inner boundary CIE to the outer boundary COE of the bend.

[0257] The routing closest to the inner boundary (CIE) of the bend can be separated from the inner boundary (CIE) by a first distance d1, and the routing closest to the outer boundary (COE) of the bend can be separated from the outer boundary (COE) of the bend by a second distance d2. For example, as... Figure 10bAs shown, in the second bend CNP2, the second scan line SL2 can be separated from the inner boundary CIE of the bend by a first distance d1, and the third scan line SL3 can be separated from the outer boundary COE of the bend by a second distance d2. The first distance d1 can be greater than the second distance d2.

[0258] The third bridging part BRv1, which is arranged at the third boundary E3 of the main island 11, and the fourth bridging part BRv2, which is arranged at the fourth boundary E4, can be vertical bridging parts BRv with the same shape outside the third boundary E3 and the fourth boundary E4 of the main island 11.

[0259] The third bridging portion BRv1 and the fourth bridging portion BRv2 may include a first data line DL1, a second data line DL2, and a third data line DL3 arranged in the fourth conductive layer 1500. The first data line DL1, the second data line DL2, and the third data line DL3 may intersect with the main island portion 11, and the first data line DL1, the second data line DL2, and the third data line DL3 may be integrally formed into a single body. That is, the vertical bridging portion BRv may include data lines DL in the fourth conductive layer 1500 that connect to adjacent main island portions 11 in a second direction (e.g., the +y direction and / or the -y direction).

[0260] Each of the first data line DL1, the second data line DL2, and the third data line DL3 can pass through the third conductive layer (see...). Figure 8c The 22nd conductive pattern of (1400) (see) Figure 8c (1411) is connected to the first semiconductor pattern 1101, the second semiconductor pattern 1102, or the third semiconductor pattern 1103 of the semiconductor layer 1100, and can be configured to transmit data signals (see 1411) Figure 6c The Dm is transmitted to the second transistor of the corresponding pixel driving circuit (see Dm). Figure 8a One terminal of T2).

[0261] like Figure 10c As shown, the third data line DL3, the second data line DL2, and the first data line DL1 can be sequentially separated from each other in the third bend CNP3 in the direction from the inner boundary CIE of the bend to the outer boundary COE of the bend, and the first data line DL1, the second data line DL2, and the third data line DL3 can be sequentially separated from each other in the fourth bend CNP4 in the direction from the inner boundary CIE of the bend to the outer boundary COE of the bend.

[0262] The wiring closest to the inner boundary (CIE) of the bend can be separated from the inner boundary (CIE) by a first distance d1, and the wiring closest to the outer boundary (COE) of the bend can be separated from the outer boundary (COE) of the bend by a second distance d2. For example, in the fourth bend (CNP4), the first data line DL1 can be separated from the inner boundary (CIE) by a first distance d1, and the third data line DL3 can be separated from the outer boundary (COE) of the bend by a second distance d2. The first distance d1 can be greater than the second distance d2.

[0263] Figure 11a This is a schematic diagram illustrating the layout of the fifth conductive layer of a stretchable display device according to an embodiment. Figure 11b and Figure 11c This is a schematic layout diagram showing a portion of the fifth conductive layer of a stretchable display device according to an embodiment. Figure 11d This is a schematic diagram illustrating the layout of the drive voltage lines of a stretchable display device according to an embodiment, and Figure 11e This is a schematic diagram illustrating the layout of the common voltage lines of a stretchable display device according to an embodiment.

[0264] Reference Figures 11a to 11e The stretchable display device may include a main island portion 11 and a plurality of main bridge portions 12 connected to the main island portion 11 in the display area DA.

[0265] The main bridging portion 12 may include a first bridging portion BRh1 disposed at a first boundary E1 of the main island portion 11, a second bridging portion BRh2 disposed at a second boundary E2, a third bridging portion BRv1 disposed at a third boundary E3 of the main island portion 11, and a fourth bridging portion BRv2 disposed at a fourth boundary E4. Outside the boundaries of the main island portion 11, the first bridging portion BRh1 and the second bridging portion BRh2 may have the same shape, and the third bridging portion BRv1 and the fourth bridging portion BRv2 may have the same shape.

[0266] The first bridging portion BRh1 and the second bridging portion BRh2 can be horizontal bridging portions BRh that connect adjacent main island portions 11 in the first direction (e.g., the +x direction and / or the -x direction), and the third bridging portion BRv1 and the fourth bridging portion BRv2 can be vertical bridging portions BRv that connect adjacent main island portions 11 in the second direction (e.g., the +y direction and / or the -y direction).

[0267] The first bridging portion BRh1 may include a first driving voltage line VDDLa and a first common voltage line VSSLa disposed in the fifth conductive layer 1600, and the second bridging portion BRh2 may include a second driving voltage line VDDLb and a second common voltage line VSSLb disposed in the fifth conductive layer 1600. The third bridging portion BRv1 may include a third driving voltage line VDDLc and a third common voltage line VSSLc disposed in the fifth conductive layer 1600, and the fourth bridging portion BRv2 may include a fourth driving voltage line VDDLd and a fourth common voltage line VSSLd disposed in the fifth conductive layer 1600.

[0268] The first driving voltage line VDDLa and the second driving voltage line VDDLb can be horizontal driving voltage lines (or "second voltage lines") VDDLh connected to adjacent main island portions 11 in the first direction (e.g., the +x direction and / or the -x direction). The third driving voltage line VDDLc and the fourth driving voltage line VDDLd can be vertical driving voltage lines (or "fifth voltage lines") VDDLv connected to adjacent main island portions 11 in the second direction (e.g., the +y direction and / or the -y direction).

[0269] The first common voltage line VSSLa and the second common voltage line VSSLb can be horizontal common voltage lines (or "third voltage lines") VSSLh connecting adjacent main island sections 11 in a first direction (e.g., +x direction and / or -x direction). The third common voltage line VSSLc and the fourth common voltage line VSSLd can be vertical common voltage lines (or "sixth voltage lines") VSSLv connecting adjacent main island sections 11 in a second direction (e.g., +y direction and / or -y direction).

[0270] In other words, such as Figure 11b and Figure 11c As shown, the horizontal bridging section BRh may include a horizontal drive voltage line VDDLh and a horizontal common voltage line VSSLh, and the vertical bridging section BRv may include a vertical drive voltage line VDDLv and a vertical common voltage line VSSLv.

[0271] The horizontal common voltage line VSSLh and the horizontal drive voltage line VDDLh can be separated from each other in the first bend CNP1 in the direction from the inner boundary CIE of the bend to the outer boundary COE of the bend, and the horizontal drive voltage line VDDLh and the horizontal common voltage line VSSLh can be separated from each other in the second bend CNP2 in the direction from the inner boundary CIE of the bend to the outer boundary COE of the bend.

[0272] The vertical drive voltage line VDDLv and the vertical common voltage line VSSLv can be separated from each other in the third bend CNP3 in the direction from the inner boundary CIE of the bend to the outer boundary COE of the bend, and the vertical common voltage line VSSLv and the vertical drive voltage line VDDLv can be separated from each other in the fourth bend CNP4 in the direction from the inner boundary CIE of the bend to the outer boundary COE of the bend.

[0273] The routing closest to the inner boundary (CIE) of the bend can be separated from the inner boundary (CIE) by a first distance d1, and the routing closest to the outer boundary (COE) of the bend can be separated from the outer boundary (COE) of the bend by a second distance d2. For example, as... Figure 11b As shown, in the second bend CNP2, the horizontal drive voltage line VDDLh can be separated from the inner boundary CIE of the bend by a first distance d1, and the horizontal common voltage line VSSLh can be separated from the outer boundary COE of the bend by a second distance d2. The first distance d1 can be greater than the second distance d2. Similarly, as Figure 11c As shown, in the fourth bend CNP4, the vertical common voltage line VSSLv can be separated from the inner boundary CIE of the bend by a first distance d1, and the vertical drive voltage line VDDLv can be separated from the outer boundary COE of the bend by a second distance d2 less than the first distance d1.

[0274] Both the horizontal drive voltage line VDDLh and the vertical drive voltage line VDDLv may have a third width w3 in a direction perpendicular to the extension direction of the corresponding voltage lines in the horizontal drive voltage line VDDLh and the vertical drive voltage line VDDLv. Both the horizontal common voltage line VSSLh and the vertical common voltage line VSSLv may have a fourth width w4 in a direction perpendicular to the extension direction of the corresponding voltage lines in the horizontal common voltage line VSSLh and the vertical common voltage line VSSLv. The third width w3 may be greater than the fourth width w4 when the change in brightness uniformity caused by the voltage drop in the drive voltage line VDDLh is greater than the change in brightness uniformity caused by the voltage drop in the common voltage line VSSLh. For example, the third width w3 may be approximately 1.2 to approximately 2 times the fourth width w4. In an embodiment, the third width w3 may be approximately 1.5 times the fourth width w4.

[0275] In another embodiment, when the change in brightness uniformity caused by the voltage drop in the common voltage line VSSL is greater than the change in brightness uniformity caused by the voltage drop in the drive voltage line VDDL, the third width w3 may be less than or equal to the fourth width w4.

[0276] Maintaining voltage line (see) Figure 9a The VSL can maintain the voltage during the initialization and data write phases (see...). Figure 6c VSUS) transmits to the second node (see VSUS) Figure 6cN2) is used to compensate for the voltage drop in the drive voltage line VDDL. Therefore, to maximize the width, the voltage line (see N2) is maintained. Figure 9a The VSL can be arranged in a different layer (e.g., third conductive layer 1400) than the layer in which the common voltage line VSSL and the drive voltage line VDDL are arranged, and can be configured as a single trace in the vertical bridging section BRv. Second width (see...) Figure 9c The second width (w2) can be greater than the third width w3 and the fourth width w4. In the embodiment, the second width (see...) Figure 9c The width w2 can be approximately 1.2 to approximately 2 times the width w4 of the fourth width.

[0277] like Figure 11d As shown, the main island portion 11 may include a first voltage connection line VCL1, a second voltage connection line VCL2, and a third voltage connection line VCL3. The first voltage connection line VCL1, the second voltage connection line VCL2, and the third voltage connection line VCL3 may be arranged in a different layer than the layer in which the first driving voltage line VDDLa, the second driving voltage line VDDLb, the third driving voltage line VDDLc, and the fourth driving voltage line VDDLd are arranged. For example, the first driving voltage line VDDLa, the second driving voltage line VDDLb, the third driving voltage line VDDLc, and the fourth driving voltage line VDDLd may be arranged in a third conductive layer (see...). Figure 8c The first voltage connection line VCL1 and the second voltage connection line VCL2 in (1400) and arranged in the fourth conductive layer (see Figure 8d The third voltage connection line VCL3 in the 1500) is electrically connected to each other in the main island section 11.

[0278] The third voltage connection line VCL3 can pass through the third conductive layer (see...). Figure 8c The eighteenth conductive pattern 1407 of (1400) is electrically connected to the semiconductor layer (see 1400). Figure 8a The first semiconductor pattern 1101, the second semiconductor pattern 1102, or the third semiconductor pattern 1103 (of 1100) can be configured to drive the power supply voltage (see Figure 6c The VDD is transmitted to the eighth transistor of the corresponding pixel driving circuit (see VDD). Figure 8a One terminal of T8).

[0279] The drive voltage line VDDL may have a mesh structure in which main island portions 11 adjacent to each other in a first direction (e.g., +x direction and / or -x direction) are connected to main island portions 11 adjacent to each other in a second direction (e.g., +y direction and / or -y direction).

[0280] Because the drive voltage line VDDL will drive the power supply voltage (see...) Figure 6c VDD) is transmitted to the semiconductor layer (see Figure 8a The eighth transistor in (1100) (see Figure 8a The first driving voltage line VDDLa, the second driving voltage line VDDLb, the third driving voltage line VDDLc, and the fourth driving voltage line VDDLd can be formed in the main island 11 by using a layer between the fifth conductive layer 1600 and the semiconductor layer 1100 as a terminal of the T8, so that the driving voltage line VDDL can be formed in the main island 11 by using a layer between the fifth conductive layer 1600 and the semiconductor layer 1100. Figure 8c The first voltage connection line VCL1 and the second voltage connection line VCL2 in (1400) and arranged in the fourth conductive layer (see Figure 8d The third voltage connection lines VCL3 in (1500) are electrically connected to each other so as not to come into contact with the common voltage line VSSL.

[0281] like Figure 11e As shown, the first common voltage line VSSLa, the second common voltage line VSSLb, the third common voltage line VSSLc, and the fourth common voltage line VSSLd can extend within the main island portion 11 in a first direction (e.g., +x direction and / or -x direction) and a second direction (e.g., +y direction and / or -y direction), and can be electrically connected to each other. The first common voltage line VSSLa, the second common voltage line VSSLb, the third common voltage line VSSLc, and the fourth common voltage line VSSLd can be electrically connected to each other in the fifth conductive layer 1600 and integrally formed into a single body.

[0282] The common voltage line VSSL may have a mesh structure in which main island portions 11 adjacent to each other in a first direction (e.g., +x direction and / or -x direction) are connected to main island portions 11 adjacent to each other in a second direction (e.g., +y direction and / or -y direction).

[0283] Because the common voltage line VSSL is only electrically connected to the sixth conductive layer (see...) Figure 8f The second electrode pad of (1700) (see) Figure 8f Therefore, the first common voltage line VSSLa, the second common voltage line VSSLb, the third common voltage line VSSLc, and the fourth common voltage line VSSLd can be arranged as the closest to the sixth conductive layer (see 242). Figure 8f In the fifth conductive layer 1600 of the conductive layer (1700), it can extend within the main island portion 11 and can be electrically connected to each other.

[0284] Because the common voltage line VSSL has a mesh structure and is configured to pass through the second electrode pad (see...) Figure 8f 242) will use the common power supply voltage (see 242) Figure 6c The VSS (Voltage Suppression) is transmitted to each of the light-emitting elements, so it is not necessary to arrange for the common power supply voltage to be transmitted to the non-display area (see VSS). Figure 1The common power supply voltage line of the NDA. Therefore, the stretchable display device according to the embodiment can reduce dead space where no image is displayed.

[0285] In an embodiment, when one electrode of the light-emitting element is electrically connected to the driving voltage line VDDL, for example, when the light-emitting element has an inverted structure, the first driving voltage line VDDLa, the second driving voltage line VDDLb, the third driving voltage line VDDLc, and the fourth driving voltage line VDDLd can be electrically connected to each other in the fifth conductive layer 1600 and integrally formed into a single body. At this time, the first common voltage line VSSLa, the second common voltage line VSSLb, the third common voltage line VSSLc, and the fourth common voltage line VSSLd can be electrically connected to each other in the main island portion 11 through voltage connection lines arranged in a layer different from the layer in which the first common voltage line VSSLa, the second common voltage line VSSLb, the third common voltage line VSSLc, and the fourth common voltage line VSSLd are arranged.

[0286] The stretchable display device according to the above embodiments can be used in various electronic devices capable of providing images. Electronic devices refer to devices that use electricity and provide specific images.

[0287] Figures 12a to 12g This is a perspective view schematically illustrating an electronic device including a stretchable display device according to an embodiment.

[0288] Reference Figure 12a The stretchable display device according to an embodiment can be used in a wearable electronic device 3100 that is worn on a part of a user's body. The wearable electronic device 3100 may include a main body 3110 and a display 3120 disposed on the main body 3110. The stretchable display device according to an embodiment can be used as the display 3120 of the wearable electronic device 3100. Figure 12a As shown, the wearable electronic device 3100 can be modified in various ways. In one embodiment, the wearable electronic device 3100 can be used as a smartwatch or a smartphone, depending on the user's choice.

[0289] Figure 12b A medical electronic device 3200 is illustrated. In an embodiment, the medical electronic device 3200 may include a body 3210 and a light emitter 3220. A stretchable display device according to an embodiment can be used as the light emitter 3220 of the medical electronic device 3200. The light emitter 3220 can emit light of a specific wavelength (e.g., infrared light, visible light, etc.) toward a patient's body. In an embodiment, the body 3210 may include a stretchable fiber material and may have a structure that can be worn on the body of a user using the light emitter.

[0290] Figure 12cAn educational electronic device 3300 is illustrated. In an embodiment, the educational electronic device 3300 may include a display 3320 disposed in a frame 3310. The display 3320 may use a stretchable display device according to an embodiment. The display 3320 may provide images such as a sea with waves, a snow-covered mountain, or a volcano with flowing lava. In this case, the display 3320 may extend in the height direction (e.g., the +z direction) to reflect the height of the waves, mountain, or volcano. In some embodiments, a portion of the display 3320 may display the movement of lava in three dimensions by sequentially changing the height in the direction along which the lava flows. The educational electronic device 3300 may include a plurality of pins (or strokes, 3330) disposed on the rear surface of the display 3320 such that the display 3320 extends in the height direction. When the pins 3330 move in a third direction (e.g., the +z direction or the -z direction), the image displayed on the display 3320 may be implemented to have three-dimensional height. Although Figure 12c An educational electronic device 3300 is shown, but there are no restrictions on the use of the educational electronic device 3300, as long as the educational electronic device 3300 provides specific image information.

[0291] Figures 12a to 12c The electronic device shown is described as having a variable shape, but the disclosure is not limited thereto. As in the embodiments described below, the stretchable display device according to the embodiments can be used in electronic devices in which the portion capable of displaying images (e.g., a screen) is fixed.

[0292] Figure 12d A robot 3400 as an electronic device according to an embodiment is shown. The robot 3400 can identify movement or objects using a camera 3440 and can display specific images to a user on displays 3420 and 3430. In some embodiments, because the stretchable display device according to the embodiment can be stretched in various directions as described above, the stretchable display device can be assembled into a main frame having a hemispherical shape. Therefore, the robot 3400 may include hemispherical displays 3420 and 3430.

[0293] Figure 12e A vehicle display device 3500 as an electronic device according to an embodiment is shown. The vehicle display device 3500 may include an instrument cluster 3510, a central information display (“CID”) 3520, and / or a front passenger display (or a passenger monitor). Because the stretchable display device according to the embodiment can be stretched in various directions, the stretchable display device can be used in the instrument cluster 3510, the CID 3520, and / or the front passenger monitor, regardless of the shape of the vehicle's internal frame.

[0294] Although Figure 12eThe instrument panel 3510, CID 3520, and / or the passenger display are shown to be separate from each other, but the disclosure is not limited thereto. In another embodiment, two or more of the instrument panel 3510, CID 3520, and passenger display may be integrally connected to each other.

[0295] In some embodiments, the vehicle display device 3500 may include a button 3540 configured to display a specific image. (See also...) Figure 12e The enlarged view shows that the hemispherical button 3540 may include an object 3542 configured to provide a button feel while moving along the +z or -z direction, and a stretchable display device disposed on the object 3542. In some embodiments, when the object 3542 has a three-dimensional circular surface, the stretchable display device may also have a three-dimensional circular surface.

[0296] Figure 12f An electronic device according to an embodiment is shown as an advertising or display electronic device 3600. In some embodiments, the advertising or display electronic device 3600 may be mounted on a fixed structure 3610 (such as a wall or column). When the structure 3610 includes, for example, Figure 8f When the surface is uneven as shown, the advertising or display electronic device 3600 can also be arranged along the uneven surface of the structure 3610. In some embodiments, the advertising or display electronic device 3600 can be mounted on the structure 3610 using a heat-shrink film or the like.

[0297] Figure 12g An electronic device according to an embodiment is shown as a controller 3700. The controller 3700 may include image-type buttons. For example, the controller 3700 may include a first button area 3720, a second button area 3730, and a third button area 3740 in which a portion of a display 3710 protrudes in the +z direction or protrudes in the -z direction (or is recessed in the +z direction). In some embodiments, the first button area 3720 and the third button area 3740 may protrude in the +z direction, and the second button area 3730 may protrude in the -z direction (or may be recessed in the +z direction).

[0298] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, the display device comprising: Multiple islands, separated from each other; A plurality of first bridging portions connect adjacent islands in a first direction among the plurality of islands, wherein the plurality of first bridging portions include a first voltage line, a second voltage line, and a third voltage line; and A plurality of second bridging portions connect adjacent island portions in a second direction intersecting the first direction, wherein the plurality of second bridging portions include a fourth voltage line electrically connected to the first voltage line, a fifth voltage line electrically connected to the second voltage line, and a sixth voltage line electrically connected to the third voltage line. The first voltage line and the fourth voltage line are arranged in the first conductive layer, and The second voltage line, the fifth voltage line, the third voltage line, and the sixth voltage line are arranged in the second conductive layer on the first conductive layer.

2. The display device according to claim 1, wherein, The first voltage line and the fourth voltage line extend to the plurality of islands and are electrically connected to each other.

3. The display device according to claim 1, wherein, The first voltage line has a first width in a direction perpendicular to its extension direction, and The fourth voltage line has a second width greater than the first width in a direction perpendicular to the extension direction of the fourth voltage line.

4. The display device according to claim 1, wherein, The plurality of second bridging portions in the first conductive layer include only the fourth voltage line among the fourth voltage line, the fifth voltage line, and the sixth voltage line.

5. The display device according to claim 1, wherein, The plurality of first bridging sections further include a first initialization voltage line and a second initialization voltage line, and The first initialization voltage line and the second initialization voltage line are arranged in the first conductive layer.

6. The display device according to claim 1, wherein, Each of the plurality of islands includes multiple voltage connection lines, and The second voltage line and the fifth voltage line are electrically connected to each other in the plurality of islands via the plurality of voltage connection lines.

7. The display device according to claim 6, wherein, The multiple voltage connection lines are arranged in a different layer than the layer in which the second voltage line and the fifth voltage line are arranged.

8. The display device according to claim 6, wherein, The plurality of voltage connection lines include a first voltage connection line and a second voltage connection line, both extending in the first direction, and a plurality of third voltage connection lines extending in the second direction. The first voltage connection line and the second voltage connection line are arranged in the first conductive layer, and The plurality of third voltage connection lines are arranged in the third conductive layer between the first conductive layer and the second conductive layer.

9. The display device according to claim 8, wherein, The second voltage line and the fifth voltage line are electrically connected to some of the plurality of third voltage connection lines, and The plurality of third voltage connection lines are all electrically connected to the first voltage connection line and the second voltage connection line.

10. The display device according to claim 1, wherein, The third voltage line and the sixth voltage line extend to the plurality of islands and are electrically connected to each other.

11. The display device according to claim 1, wherein, Both the second voltage line and the fifth voltage line have a third width in a direction perpendicular to the extension direction of the corresponding voltage line in the second voltage line and the fifth voltage line, and Both the third voltage line and the sixth voltage line have a fourth width that is smaller than the third width in a direction perpendicular to the extension direction of the corresponding voltage line in the third voltage line and the sixth voltage line.

12. The display device according to claim 11, wherein, The fourth voltage line has a second width that is greater than the fourth width in a direction perpendicular to the extension direction of the fourth voltage line.

13. The display device according to claim 1, wherein, Each of the plurality of islands further includes a light-emitting element, a first electrode pad electrically connected to a first electrode of the light-emitting element, and a second electrode pad electrically connected to a second electrode of the light-emitting element. The first electrode pad and the second electrode pad are disposed in a fourth conductive layer on the second conductive layer.

14. The display device according to claim 1, wherein, Each of the plurality of islands includes a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element, and The pixel driving circuit includes: a driving transistor having a gate electrode, a second terminal, and a first terminal electrically connected to a first node; a data writing transistor electrically connected to the first node and a data line; a first compensation transistor electrically connected to the gate electrode of the driving transistor and the second terminal of the driving transistor; a first emission control transistor electrically connected to the first node and a second node; a second emission control transistor electrically connected to the light-emitting element and the second terminal of the driving transistor; a third emission control transistor electrically connected to the second node and a driving voltage line; a second compensation transistor electrically connected to the second node and a sustaining voltage line; a storage capacitor electrically connected to the second node and the gate electrode of the driving transistor; and an auxiliary capacitor electrically connected to the sustaining voltage line and the first electrode of the light-emitting element.

15. The display device according to claim 14, wherein, The sustaining voltage line includes the first voltage line and the fourth voltage line.

16. The display device according to claim 14, wherein, The auxiliary capacitor includes a first electrode and a second electrode that is superimposed on the first electrode in a plan view, and The first voltage line and the fourth voltage line are electrically connected to the second electrode.

17. The display device according to claim 14, wherein, The second electrode of the auxiliary capacitor is electrically connected to the first electrode of the light-emitting element.

18. The display device according to claim 14, wherein, The driving voltage line includes the second voltage line and the fifth voltage line.

19. The display device according to claim 14, wherein, The second electrode of the light-emitting element is electrically connected to the common voltage line, and The common voltage line includes the third voltage line and the sixth voltage line.

20. The display device according to claim 19, wherein, Each of the plurality of islands further includes a first electrode pad electrically connected to the first electrode of the light-emitting element and a second electrode pad electrically connected to the second electrode of the light-emitting element, and The third voltage line and the sixth voltage line extend to the plurality of islands and connect to the second electrode pad.

Images