Method for bonding wafers of known good dies and assembly produced in such method

Abstract

A method of forming a semiconductor wafer is provided. The method includes dicing a wafer into dies, testing the dies to pick out known good dies, and bonding the known good dies to a carrier wafer to form a top KGD wafer. The method also includes filling gaps between top dies to form a top gap fill layer around and over each of the top dies, and bonding the top dies with a dummy silicon wafer. The method also includes bonding a known good die to a carrier wafer to form one or more core KGD wafers, and filling gaps between the core dies to form a core gap fill layer around each of the core dies. Next, the method includes bonding the one or more core KGD wafers to the top KGD wafer to form a KGD wafer stack.

Description

Technical Field

[0001] The present invention generally relates to semiconductor device assemblies, and more specifically to methods for bonding wafers of known good quality dies and assemblies produced by such methods. Background Technology

[0002] Microelectronic devices typically have dies (i.e., chips) containing integrated circuit systems with a high density of extremely small components. Typically, a die contains an array of very small bonding pads electrically coupled to the integrated circuit system. These bonding pads are external electrical contacts through which voltage, signals, etc., are transmitted to and from the integrated circuit system. After the die is formed, it is “encapsulated” to couple the bonding pads to a larger array of electrical terminals that can be more easily coupled to various power lines, signal lines, and ground lines. A typical process for encapsulating a die involves electrically coupling the bonding pads on the die to lead, ball pads, or other types of electrical terminal arrays, and encapsulating the die to protect it from environmental factors such as moisture, particles, static electricity, and physical shock. Attached Figure Description

[0003] Figure 1 This is a simplified schematic cross-sectional view of an exemplary semiconductor device assembly.

[0004] Figure 2 These are a series of cross-sectional views illustrating a method for manufacturing wafer stacks according to an embodiment of the present technology.

[0005] Figure 3 This is a partial schematic cross-sectional view of a wafer according to an embodiment of the present technology.

[0006] Figure 4 This is a simplified schematic cross-sectional view of a semiconductor device assembly according to an embodiment of the present technology.

[0007] Figure 5 This is a schematic diagram illustrating a system comprising a semiconductor device assembly configured according to embodiments of the present technology.

[0008] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor device assembly according to an embodiment of the present technology. Detailed Implementation

[0009] The electronics industry relies on continuous innovation in semiconductor packaging to meet global demand for higher-performance technologies. This demand requires more complex assemblies of semiconductor devices, which may vary in terms of planar area, thickness, and interconnect methodologies. One approach to accommodating such varied devices into a single assembly is to bond wafers to a stack and then dicing the wafer stack into discrete stacked assemblies.

[0010] Figure 1 This illustrates an example of a 100-chip stack. See reference [link / reference]. Figure 1 As can be seen, the wafer stack 100 may include a first wafer 102 including a top DRAM device 110, which is bonded to a second wafer 104 including a core DRAM device 112. A scribe region 114 may exist between the top DRAM device 110 and the core DRAM device 112. The scribe region 114 may contain scribe marks to assist in wafer alignment and bonding. The core DRAM device 112 and the top DRAM device 110 may have similar orientations, with the faces of devices 110 and 112 pointing downwards. Bonding between the wafers may be achieved via a hybrid bonding 118, where the face of the top DRAM device 110 is bonded to the back face of the core DRAM device 112, the bonding being achieved through pads 120 exposed on the bonding surfaces of the two devices. Additionally, a fusion bonding 116 may exist between the second wafer 104 and its underlying silicon carrier wafer 108.

[0011] However, the wafer stack 100 has many disadvantages. One disadvantage of stacking wafers is the random distribution of defective dies 122 across the wafer surface. The presence of a single defective die 122 is sufficient to ruin the final device assembly formed by the single-die stack 100. Therefore, as the number of wafers in the wafer stack 100 increases, the probability of at least one defective die 122 being introduced into the final device assembly increases exponentially.

[0012] To address these and other drawbacks, various embodiments of the present invention provide methods for bonding wafers with known good bare dies and assemblies produced by such methods. Figure 2 This describes a method for bonding known good die (KGD) wafers to form a known good die (KGD) wafer stack. Figure 2 These are a series of cross-sectional views illustrating a method 200 for manufacturing a wafer stack according to an embodiment of the present technology.

[0013] Method 200 may include a first step 201. The first step 201 may include dicing the top semiconductor wafer into top semiconductor dies, and then testing the top semiconductor dies to select known good dies. Method 200 may include a second step 203. The second step 203 may include bonding the known good dies to a top silicon carrier wafer 208a to form a top KGD wafer 202 including top dies 210. In some embodiments, bonding the known good dies to the first silicon carrier wafer 208a may include fusing the facet of each known good die (e.g., top die 210) to the facet of the silicon carrier wafer 208a.

[0014] The second step 203 may further include filling the gaps between the top dies 208a with a gap-filling material, such that the gap-filling material forms a top gap-filling layer 222 around and above each of the top dies 210. The gap-filling material may comprise silicon oxide. Additionally, the second step 203 may include planarizing the top gap-filling layer 222 to form a horizontal surface for bonding. The second step 203 may include bonding the top dies 210 to the dummy silicon wafer 206. In some embodiments, bonding the top dies 210 to the dummy silicon wafer 206 may include fusing the back side of each top die 210 to a face of the dummy silicon wafer 206, the back side of each top die including a portion of the top gap-filling layer 222. Alternatively or additionally, forming the top KGD wafer 202 including the top dies 210 may include thinning the dummy silicon wafer 206 of the top KGD wafer 202 to a desired height.

[0015] The method may include a third step 205, which may include removing the top silicon carrier wafer 208a to expose the face of each top die 210. The third step 205 may include forming a pad 220 on the face of the top die 210. The method may include a fourth step 207. The fourth step 207 may include dicing the core semiconductor wafer into core semiconductor dies, and then testing the core semiconductor dies to select known good dies.

[0016] Method 200 may include a fifth step 209, which may include bonding known good dies to a core silicon carrier wafer 208b to form one or more core KGD wafers 204 including core dies 212. In some embodiments, bonding known good dies (e.g., core dies 212) to the core silicon carrier wafer 208b may include fusing the facet of each core die 212 to the facet of the core silicon carrier wafer 208b. Alternatively or additionally, forming one or more core KGD wafers 204 including core dies 212 may include thinning the core silicon carrier wafer 208b to a desired height.

[0017] Step 209 may include filling the gaps between the core dies 212 with a gap-filling material, such that the gap-filling material forms a core gap-filling layer 224 around each of the core dies 212. Additionally, in some embodiments, forming the core gap-filling layer may further include planarizing the core gap-filling layer such that the layer is coplanar with the top and bottom of the core dies. Step 209 may also include forming a pad 220 on the back side of each core die 212.

[0018] Method 200 may include a sixth step 211, in which one or more core KGD wafers 204 are bonded to a top KGD wafer 202 to form a KGD wafer stack. Method 200 may include a seventh step 213. The seventh step 213 may include removing the core silicon carrier wafer 208b to expose the face of each core die 212. The seventh step 213 may include forming a pad 220 on the exposed face of the core die 212. Additionally, dummy pads 420 may be formed on the top gap fill layer 222 and the core gap fill layer to aid planarization and prevent or reduce depressions in the gap fill layer. Such dummy pads 420 may serve as evidence of manufacturing steps in which they are disposed on a silicon oxide material to aid planarization (e.g., chemical mechanical planarization (CMP)) and prevent or reduce depressions in the silicon oxide material.

[0019] In some embodiments, steps four through seven may be performed on a single core KGD wafer selected from one or more KGD wafers 204, or steps four through seven may be performed on all one or more core KGD wafers 204 in parallel or sequentially. In an embodiment where one or more core KGD wafers 204 are manufactured in parallel, step seven 213 may include mixing and bonding pads 220 disposed on the back side of the lower core die 212, pads disposed on the surface of the upper core die 212, and fusing and bonding core gap filler 224 layers together such that one or more core KGD wafers 204 form a stack of core KGD wafers. Next, step seven 213 may include bonding this stack of core KGD wafers 204 to a top KGD wafer 202. Alternatively, bonding one or more core KGD wafers 204 to the top KGD wafer 202 may include selecting core KGD wafers from one or more core KGD wafers 204. In these embodiments, bonding may include co-bonding pads 220 on the back side of core die 212 to pads on the face of top die 210, and fusing top gap filler layer 222 to core gap filler layer 224. Additionally, in certain embodiments, the bonded core KGD wafer may be the bottom wafer in a KGD wafer stack, and method 200 may include removing core silicon carrier wafer 208b from the bottom wafer to expose the face of each core die 212 on the bottom wafer. These embodiments may include forming pads 220 on the face of the core die 212 on the bottom wafer, and bonding the bottom wafer to core KGD wafers from one or more core KGD wafers 204. The one or more core KGD wafers 204 may be sequentially bonded in a similar manner until the desired height of the KGD wafer stack is reached. In these embodiments, bonding the bottom wafer to the core KGD wafer may include: co-bonding a pad 220 on the back side of the core die 212 belonging to the core KGD wafer to a pad 220 on the surface of the core die 212 belonging to the bottom wafer, and fusing the core gap filler layers 224 of the two wafers together.

[0020] After step 213, method 200 may include bonding an IF logic wafer to the bottom of a KGD wafer stack. Alternatively, method 200 may include dicing the KGD wafer stack into multiple stacked semiconductor device assemblies, each assembly having fusion bonding between gap filler layers and hybrid bonding between dies.

[0021] Figure 3 The diagram illustrates a partial schematic cross-sectional view of a wafer 300 according to an embodiment of the present technology. This wafer 300 can be produced by the aforementioned method 200, specifically by producing a detailed snapshot of the wafer 300 via step six 211. The wafer may include one or more core wafers 304, each core wafer 304 including a core die 312, and each core die having a downward-facing front side. Each core die 312 may be peripherally surrounded by a first silicon oxide material 324 coplanar with the top and bottom of the core die 312. Although illustrated only as having a single core wafer 304, the wafer 300 may include multiple core wafers 304 stacked alternately with each other, and each core wafer 304 may include a core die 312 separated and surrounded by the first silicon oxide material 324. The wafer 300 may also include a top wafer 302 including a top die 310 having a downward-facing front side and peripherally surrounded by a second silicon oxide material 322 coplanar with the bottom of the top die 310. The second silicon oxide material 322 may also be overlaid on the top die 310. The wafer 300 may include a dummy silicon wafer 306 separated from the top die 310 by the second silicon oxide material 322 overlaid on the top die 310. The wafer 300 may include a hybrid bonding 318 between each top die 310 and a core die 312. Additionally, in embodiments where multiple core wafers 304 are stacked below the top wafer 302, hybrid bonding 318 is also present between the core dies 312. The hybrid bonding 318 may include a top hybrid bonding between the core dies 312 of one or more core wafers 304 and the top die 310, and a core hybrid bonding between a core die belonging to one or more core wafers disposed below the top wafer 302 and the core wafer with which it is hybrid bonded. The wafer 300 includes fusion bonding 316 between silicon oxide materials and between each top die 310 and the dummy silicon wafer 306. Additionally, as described, the wafer may include a silicon carrier wafer 308 disposed below the bottom core wafer 304. In such embodiments, a fusion bond 316 may exist between the silicon carrier wafer 308 and the bottom core wafer 304. The fusion bond 316 may include a top fusion bond between the top die 310 and the dummy silicon wafer 306, and a core fusion bond between the first silicon oxide material 322 and the second silicon oxide material 324.

[0022] Additionally, the front side of the top die 310 may have a pad 320. Each core die 312 may have a back side opposite its front side. Each core die 312 may have pads 320 on both its back and front sides. In such embodiments, top hybrid bonding may be between the pad 320 on the front side of the top die 310 and the back side of the core die 312 disposed below it. Core hybrid bonding may be between the pad 320 on the front side of the core die 312 and the pad on the back side of the core die 312 disposed below it. Further comprising a silicon carrier wafer disposed below one or more core dies, wherein the silicon carrier wafer is fused to the front side of the bottommost core die. In a particular embodiment, an IF logic wafer may be disposed below the bottommost core die 412 and connected to the semiconductor device assembly 400.

[0023] This wafer 300 can be individually cut into multiple stacked semiconductor device assemblies, as discussed in method 200 as an optional step following step 213 of the seventh step. Figure 4This is a simplified schematic cross-sectional view of an example semiconductor device assembly 400 produced according to an embodiment of the present technology. The assembly 400 includes one or more core dies 412, each core die 412 having a downward-facing front side, and each core die 412 is peripherally surrounded by a first silicon oxide material 424 coplanar with the top and bottom of the core die 412. The assembly 400 also includes a top die 410, the top die 410 having a downward-facing front side, and the top die 410 is peripherally surrounded by a second silicon oxide material 422 coplanar with the bottom of the top die 410 and also covering the top of the top die 410. The assembly 400 may also include a dummy silicon chip 406 above the top die 410, separated from the top die 410 by the second silicon oxide material 422 covering the top die 410. The dummy silicon chip 406 may have sidewalls coplanar with the outer edges of the peripheral first and second silicon oxide materials 424 and 422. As illustrated, assembly 400 includes a hybrid bonding 418 between a top die 410 and a core die 412. Additionally, in embodiments where multiple core dies 412 are stacked below the top die 410, the assembly may include a hybrid bonding 418 between the core dies 412. The hybrid bonding 418 may include a top hybrid bonding between the core dies 412 and the top die 410, and core hybrid bonding between the underlying core dies 412. Assembly 400 also includes fusion bonding between silicon oxide materials and between the top die 410 and the dummy silicon wafer 406. Additionally, as illustrated, assembly 400 may include a silicon carrier wafer 408 disposed below the bottommost core die 412. In such embodiments, a fusion bonding 416 may exist between the silicon carrier wafer 408 and the bottommost core die 412. In a particular embodiment, a controller device may be disposed below the bottommost core die 412 and connected to the semiconductor device assembly 400. The fusion bond 416 may include a top fusion bond between the top die 410 and the dummy silicon chip 406, and a core fusion bond between the first silicon oxide material 422 and the second silicon oxide material 424.

[0024] Additionally, in certain embodiments, the front side of the top die 410 may have a pad 420. Each core die 412 may have a back side opposite its front side. In such embodiments, both the back and front sides of each core die 412 may have pads 420. In such embodiments, a top hybrid bonding may be between the pad 420 on the front side of the top die 410 and the back side of the core die 412 disposed below it. A core hybrid bonding may be between the pad 420 on the front side of the core die 412 and the pad 420 disposed on the back side of the core die 412 below it. Additionally, dummy pads 426 may be present on the first and second silicon oxide materials 424 and 422, as illustrated. Such dummy pads 420 may serve as evidence of manufacturing steps in which they are disposed on the silicon oxide material to aid planarization (e.g., chemical mechanical planarization (CMP)) and reduce depressions in the silicon oxide material.

[0025] Although the semiconductor device assembly has been described and depicted in the foregoing exemplary embodiments as comprising a single semiconductor device, in other embodiments, the assembly may include additional semiconductor devices. For example, with appropriate modifications (mutatis mutandis), Figure 2 , 3 And / or the single semiconductor device described in 4 can be replaced by, for example, a vertical stack of semiconductor devices or multiple semiconductor devices.

[0026] According to one aspect of the invention, Figures 2 to 4 The semiconductor devices described in the assemblies may be memory dies, such as dynamic random access memory (DRAM) dies, NOT-AND (NAND) memory dies, NOT-OR (NOR) memory dies, magnetic random access memory (MRAM) dies, phase-change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, or the like. In embodiments where multiple dies are provided in a single assembly, the semiconductor devices may be memory dies of the same type (e.g., two NAND, two DRAM, etc.) or memory dies of different types (e.g., one DRAM and one NAND, etc.). According to another aspect of the invention, the semiconductor dies of the assemblies described above may be logic dies (e.g., controller dies, processor dies, etc.), or a mixture of logic and memory dies (e.g., memory controller dies and memory dies controlled by them).

[0027] The above text is about Figures 2 to 4 Any of the described semiconductor devices and semiconductor device assemblies can be incorporated into any of a multitude of larger and / or more complex systems, a representative example of which is... Figure 5The system 500 is schematically shown in the diagram. System 500 may include a semiconductor device assembly (e.g., or discrete semiconductor device) 502, a power supply 504, a driver 506, a processor 508, and / or other subsystems or components 510. The semiconductor device assembly 502 may include components similar to those referenced above. Figures 2 to 4 The described semiconductor devices are generally similar in characteristics. The resulting system 500 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 500 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, home appliances, and other products. Components of system 500 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 500 may also include remote devices and any of a variety of computer-readable media.

[0028] Figure 6 This is a flowchart illustrating a method 6000 for manufacturing a semiconductor device assembly. The method includes dicing a semiconductor wafer into semiconductor dies (box 6010). The method includes testing the semiconductor dies to select known good dies (box 6020). The method includes bonding the known good dies to a top silicon carrier wafer to form a top KGD wafer including the top dies (box 6030). The method includes filling the gaps between the top dies with a gap-filling material such that the gap-filling material forms a top gap-fill layer around and over each of the top dies (box 6040). The method includes planarizing the top gap-fill layer to form a horizontal surface for bonding (box 6050). The method includes bonding the top dies to a dummy silicon wafer (box 6060). The method includes removing the top silicon carrier wafer to expose the face of each top die (box 6070). The method includes forming a pad on the face of the top die (box 6080). The method includes bonding known good dies to a core silicon carrier wafer to form one or more core KGD wafers including core dies (box 6090). The method includes filling the gaps between core dies with a gap-filling material such that the gap-filling material forms a core gap-filling layer around each of the core dies (box 6100). The method includes forming a pad on the back side of each core die (box 6110). The method includes bonding one or more core KGD wafers to a top KGD wafer to form a KGD wafer stack (box 6120).

[0029] The foregoing describes specific details of several embodiments of semiconductor devices and associated systems and methods. Those skilled in the art will recognize that suitable stages of the methods described herein can be performed at the wafer or die level. Therefore, depending on the context in which the term "substrate" is used, it can refer to a wafer-level substrate or a single-cut die-level substrate. Furthermore, unless the context otherwise indicates, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0030] The devices discussed herein (including memory devices) can be formed on a semiconductor substrate or die (e.g., silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0031] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this invention and the appended claims. Features implementing the functions can also be physically located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0032] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the invention. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0033] As used herein, the terms “vertical,” “horizontal,” “up,” “down,” “above,” and “below” can refer to the relative orientation or position of a feature in a semiconductor device given the orientation shown in the figures. For example, “up” or “top” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices with other orientations (e.g., inverted or tilted orientations), where top / bottom, above / below, above / below, up / down, and left / right can be interchanged depending on the orientation.

[0034] It should be noted that the methods described above describe feasible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are feasible. Furthermore, embodiments from two or more methods can be combined.

[0035] As stated above, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Indeed, numerous specific details are set forth in the foregoing description to provide a thorough and effective description of embodiments of the present invention. However, those skilled in the art will recognize that the invention may be practiced without one or more of these specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the present invention. Generally, it should be understood that various other devices, systems, and methods, in addition to the specific embodiments disclosed herein, are also within the scope of the present invention.

Claims

1. A method for bonding known good die (KGD) wafers to form a known good die (KGD) wafer stack, comprising: Multiple previously tested top dies are bonded to a top silicon carrier wafer to form a temporary KGD wafer including the multiple top dies; The gaps between the plurality of top blanks are filled with a gap filler material, such that the gap filler material forms a top gap filler layer around and above each of the plurality of top blanks; Flatten the top gap filler layer to form a horizontal surface for bonding; The temporary KGD wafer is bonded to the dummy silicon wafer, wherein the horizontal surface of the top gap filler layer directly contacts the dummy silicon wafer; Remove the top silicon carrier wafer to form a top KGD wafer and expose the face of each of the plurality of top dies; Planarize the top KGD wafer to prepare it for bonding; Multiple previously tested core dies are bonded to one or more core silicon carrier wafers to form one or more core KGD wafers including the multiple core dies. The gaps between the plurality of core dies are filled with the gap-filling material, such that the gap-filling material forms a core gap-filling layer around each of the plurality of core dies. Planarize the one or more core KGD wafers to prepare them for bonding; and A KGD wafer stack is formed by bonding one or more core KGD wafers to a top KGD wafer, wherein the bonding includes blending the back side of the core die to the face of the top die and fusion bonding the core gap filler layer to the top gap filler layer.

2. The method of claim 1, wherein forming the KGD wafer stack further comprises: Remove the core silicon carrier wafer from the one or more core KGD wafers to expose the face of each of the corresponding plurality of core dies; and Each core KGD wafer from the one or more core KGD wafers is bonded to the bottommost core KGD wafer on the KGD wafer stack, wherein the bonding includes blending and bonding the face of the core die from the bottommost core KGD wafer to the back face of the core die from the core KGD wafer added to the KGD wafer stack, and fusing the core gap filler layers together, wherein the core KGD wafer added to the KGD wafer stack becomes the new bottommost core KGD wafer.

3. The method of claim 1, wherein bonding the plurality of previously tested top dies to the top silicon carrier wafer comprises: Each previously tested top die face is fused to the surface of the silicon carrier wafer.

4. The method of claim 1, wherein bonding the temporary KGD wafer to the dummy silicon wafer comprises: The back side of each of the plurality of top dies is fused to the surface of the dummy silicon wafer, and the back side of each top die includes a portion of the top gap fill layer.

5. The method of claim 1, wherein bonding the plurality of previously tested core dies to the one or more core silicon carrier wafers comprises: The surfaces of each of the plurality of core dies are fused together to the surface of the core silicon carrier wafer.

6. The method of claim 1, further comprising forming a dummy pad on the top gap filler layer, wherein the dummy pad is configured to prevent depression of the top gap filler layer during planarization.

7. The method of claim 1, further comprising forming a dummy pad on the core gap fill layer, wherein the dummy pad is configured to prevent depression of the core gap fill layer during planarization.

8. The method of claim 1, further comprising bonding an IF logic wafer to the bottom of the KGD wafer stack.

9. The method of claim 1, wherein forming one or more core KGD wafers further comprises: The core silicon carrier wafer of each of the one or more core KGD wafers is thinned to the desired height.

10. The method of claim 1, further comprising dicing the KGD wafer stack into a plurality of stacked semiconductor device assemblies, wherein each assembly has fusion bonding between adjacent gap fill layers and hybrid bonding between opposing dies.

11. The method of claim 1, wherein forming the core gap-filling layer further comprises: The core gap filler layer is planarized such that the layer is coplanar with the back surface of the plurality of core dies.

12. A semiconductor device assembly comprising: Multiple core dies, each core die having a downward-facing working side, and each core die being surrounded by a first silicon oxide material coplanar with the working side and back side of the core die, the multiple core dies being vertically stacked and connected by hybrid bonding between adjacent core dies; A top die, which is disposed above and co-bonded to the plurality of core dies, the top die having a downward-facing functional side, and the top die being surrounded on the periphery by a second silicon oxide material coplanar with the functional side of the top die and overlapping with the back side of the top die, the second silicon oxide material being fused to the first silicon oxide material; and A dummy silicon chip is disposed above the top die and fused to a second oxide material overlapping the top die, the dummy silicon chip having sidewalls coplanar with the outer edges of the peripheral first and second silicon oxide materials.

13. The semiconductor device assembly of claim 12, wherein the functional side of the top die includes a first plurality of pads.

14. The semiconductor device assembly of claim 13, wherein the back side of each core die includes a second plurality of pads, and wherein the active side of each core die includes a third plurality of pads.

15. The semiconductor device assembly of claim 14, wherein a subset of each of the first, second, and third plurality of pads is electrically disconnected from any active circuitry system in the semiconductor device assembly.

16. The semiconductor device assembly of claim 12, wherein the dummy silicon chip does not include circuitry.

17. The semiconductor device assembly of claim 12, wherein each of the plurality of core dies includes a plurality of through-silicon vias (TSVs) extending therebetween the active side and the back side.

18. The semiconductor device assembly of claim 12, wherein the top die does not contain any through-silicon vias (TSVs).

19. The semiconductor device assembly of claim 12, wherein the first silicon oxide material surrounding each of the plurality of core dies is fused to the first silicon oxide material surrounding adjacent ones of the plurality of core dies.

20. A semiconductor device assembly comprising: A first semiconductor die has a downward-facing functional side and is surrounded on the periphery by a first silicon oxide material that is coplanar with the functional side and the back side of the first semiconductor die. A second semiconductor die is disposed above and co-bonded to the first semiconductor die. The second semiconductor die has a downward-facing functional side and is surrounded on the periphery by a second silicon oxide material that is coplanar with the functional side of the second semiconductor die and overlaps with the back side of the second semiconductor die. The second silicon oxide material is fused to the first silicon oxide material. and A dummy silicon chip is disposed above the second semiconductor die and fused to the second oxide material overlapping the second semiconductor die, the dummy silicon chip having sidewalls coplanar with the outer edges of the peripheral first and second silicon oxide materials.

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