Universe transmission line pulse test system and method

Abstract

The invention discloses a global transmission line pulse test system and method, and belongs to the technical field of semiconductor integrated circuit reliability test. The system adopts a circuit structure in which double coaxial lines are matched with double electric control switches, and comprises a direct-current voltage source, a first electric control switch, a second electric control switch, a first coaxial line, a second coaxial line, an impedance matching resistor and an output capacitor. Through specific time sequence control, a step waveform containing a first voltage platform V1 and a second voltage platform V2 is generated in a single pulse event, starting characteristic data of the device are extracted on the V1 platform, and transient regression characteristic data of the device are extracted on the V2 platform. According to the method, the problem that a traditional TLP test can only represent the opening process of the device and cannot effectively evaluate the turn-off behavior and the dynamic latch risk of the complex ESD device is solved, the physical mechanism of the device in the process from opening the high-resistance state to recovering the low-resistance state can be completely analyzed, and the method has important significance for optimizing the anti-latch design of a high-voltage integrated circuit.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit reliability testing technology, specifically relating to a full-domain transmission line pulse test system and method for evaluating the characteristics of electrostatic discharge (ESD) protection devices. Background Technology

[0002] Transmission line pulse (TLP) testing technology, introduced in the 1980s, has become the industry standard method for semiconductor electrostatic discharge (ESD) protection design and reliability assessment. Traditional TLP systems, such as... Figure 1 As shown, by charging the suspended cable to a predetermined voltage, passing it through an attenuator (to reduce reflected voltage), a series of rectangular short pulses are injected into the device under test (DUT) (pulse waveforms are shown in the diagram). Figure 2 As shown in the figure, voltage and current data are extracted during the stable phase of the pulse (typically 70% to 90% of the time window) to construct the quasi-static IV characteristic curve of the device. This method is useful for analyzing the device's turn-on voltage (V). t1 ), dynamic resistance (R) on ) and failure current (I t2 It has significant advantages in terms of simulation and is widely used to simulate device behavior under the human body discharge model (HBM).

[0003] While traditional TLP (Transient Latch-Up) technology is mature in characterizing ESD turn-on characteristics, its limitations are becoming increasingly apparent when facing ESD protection designs for modern high-voltage, high-power, and complex structures (such as deep hysteresis SCRs and high holding current devices). Traditional TLP testing is essentially a "quasi-static" test. Its parameter extraction relies entirely on the stable plateau after the voltage rise edge, meaning it can only capture the "transient turn-on" process of the device. Traditional TLP cannot provide intuitive data support for the device's turn-off behavior after stress disappearance, carrier recombination processes, and thermal relaxation characteristics. Currently, the industry typically uses a simple static criterion to determine whether an ESD device has latch-up risk, namely comparing the holding voltage (V) in the TLP curve. h ) and circuit power supply voltage (V DD If V h >V DD If the current condition is stable, it is considered safe. However, recent research has found that for devices with strong hysteresis, the turn-on and turn-off paths often do not coincide due to factors such as the nonlinearity of the internal positive feedback, temperature effects, and recombination effects after carrier injection. Under certain extreme conditions, even if the static V... h Slightly higher than V DD During dynamic shutdown, the device may still be unable to leave the low-resistance state due to slow transient recovery, thus inducing "dynamic latch-up".

[0004] While rapid trigger response (TLP) has emerged in recent years to meet CDM testing requirements, or multi-pulse test systems have been used to simulate specific stress environments, these solutions mostly focus on improving test speed or simulating specific waveforms. They lack a systematic approach that can simultaneously quantify both "trigger response" and "regression / shutdown characteristics" in a single test event. The trigger behavior information of ESD devices is contained in the rising edge and first voltage plateau of the TLP, while crucial information regarding latch-up risk is hidden in the transient regression characteristics after the pulse ends.

[0005] Therefore, a novel test waveform and system is urgently needed that retains the standard TLP's ability to accurately capture trigger voltages while introducing controllable testing of the "voltage fall-off phase." This involves constructing a "global" voltage-time window to fully analyze the physical mechanism of a device transitioning from a high-resistivity state to a low-resistivity state and then attempting to recover to the high-resistivity state. This has significant engineering value for optimizing latch-up protection in high-voltage integrated circuits and reducing the risk of failure after actual board deployment. Summary of the Invention

[0006] The purpose of this invention is to provide a global transmission line pulse (TLP) test method and system, which aims to solve the problem that existing TLP tests cannot fully reflect the device's turn-off characteristics and transient regression characteristics.

[0007] The technical solution adopted in this invention is as follows:

[0008] A global transmission line pulse test system includes: a DC voltage source 01, a first electronically controlled switch 02, a second electronically controlled switch 03, a first coaxial cable 04, a second coaxial cable 05, a first resistor 06, a second resistor 07, an output capacitor 08, and a device under test (DUT).

[0009] The positive terminal of the DC voltage source 01 is connected to the positive terminal of the first electronically controlled switch 02, and the negative terminal of the DC voltage source 01 is grounded; the positive terminal of the first electronically controlled switch 02 is connected to the positive terminal of the DC voltage source 01, and the negative terminal of the first electronically controlled switch 02 is simultaneously connected to the upper end of the first coaxial line 04 and the positive terminal of the second electronically controlled switch 03; the lower end of the first coaxial line 04 is floating; the negative terminal of the second electronically controlled switch 03 is connected to the upper end of the first resistor 06, and the lower end of the first resistor 06 is grounded; the negative terminal of the second electronically controlled switch 03, the upper end of the second coaxial line 05, the upper end of the first resistor 06, and the left end of the second resistor 07 are all connected to node B; the lower end of the second coaxial line 05 is floating; the lower end of the first resistor 06 is grounded. The right end of the second resistor 07, the positive end of the output capacitor 08, and the positive end of the device under test (DUT) are all connected to a single point; the negative ends of the output capacitor 08 and the DUT are both grounded; that is, the output capacitor 08 and the DUT are connected in parallel.

[0010] In a preferred embodiment, the first coaxial cable 04 is used for delayed transmission of a square wave pulse signal; the second coaxial cable 05 is used to generate a second voltage platform through signal reflection; the first resistor 06, the second resistor 07, and the output capacitor 08 form an impedance matching network for distributing the pulse signal voltage reaching the node B.

[0011] The second objective of this invention is to provide a method for generating a global transmission line pulse (TLP) waveform using the aforementioned test system, comprising the following steps: Controlling the first electronically controlled switch 02 to close, causing the DC voltage source 01 to transmit a square wave pulse signal with a pulse width of tp1 to the first coaxial line 04; after the pulse signal enters the first coaxial line 04 and is delayed by tp1, closing the second electronically controlled switch 03, at which point the pulse signal, after having its reflected voltage reduced by the impedance matching network composed of the first resistor 06, the second resistor 07, and the output capacitor 08 at node B, couples the voltage to the device under test (DUT), forming a first voltage platform V1; after a duration of tp1, opening the second electronically controlled switch 03, at which point the pulse signal entering the second coaxial line 05 is reflected within the coaxial line and returns to node B for a second distribution, being loaded onto the DUT through the impedance matching network, forming a second voltage platform V2; wherein the average voltage value of the first voltage platform V1 is always greater than the average voltage value of the second voltage platform V2.

[0012] A third objective of this invention is to provide a global transmission line pulse test method, which utilizes the aforementioned test system to test the device under test (DUT). The method includes the following steps:

[0013] S1: Set the global TLP waveform parameters. The waveform includes the rise time tr, the first voltage plateau V1 and its duration tp1, the falling edge, the second voltage plateau V2 and its duration tp2, and always keep V1 greater than V2.

[0014] S2: Initialize pulse number n, and control the test system to send the nth global TLP pulse signal to the device under test (DUT); n≥1.

[0015] S3: Acquire the time-domain waveforms of the voltage and current across the device under test (DUT); extract the average transient voltage and current values ​​within the stable region t1 of the first voltage plateau, denoted as (V n1 , I n1 The average transient voltage and current are extracted from the stable region t2 of the second voltage plateau and denoted as (V). n2 , I n2 );

[0016] S4: Perform a leakage current test on the device under test (DUT); if the leakage current does not exceed the preset failure threshold, increase the pulse number n and increase the amplitude of the first voltage platform V1 and the second voltage platform V2, and repeat steps S2 to S4; if the leakage current exceeds the preset failure threshold, stop the test.

[0017] S5: Based on the data points recorded in step S3, plot the on-state characteristic curve and the transient regression characteristic curve in the IV coordinate system respectively.

[0018] As a preferred embodiment, in step S5, the turn-on characteristic curve is obtained from the points (V) obtained in previous tests. 11 , I 11 ) to (V n1 , I n1 The transient regression characteristic curve is formed by connecting the points (V) obtained from each test in sequence; 12 , I 12 ) to (V n2 ,I n2 It is formed by connecting them sequentially.

[0019] The working principle of this invention is as follows: DC voltage source 01 transmits a pulse with a width of t to the first coaxial line 04 through the first electronically controlled switch 02. p1 A square wave pulse signal enters the coaxial line t. p1 After a certain time, the second electronically controlled switch 03 closes, and the pulse signal enters node B. After the reflected voltage is reduced by the impedance matching network composed of the first resistor 06, the second resistor 07, and the output capacitor 08, the voltage is coupled to the device under test (DUT). The reflected voltage enters the second coaxial line 05. The voltage of the DUT pulse signal is the voltage V1 of the first platform, and the pulse width is t. p1 . t p1 After a certain time, the second electronic control switch 03 is opened, and the pulse signal entering the second coaxial line 05 returns to node B after total reflection within the coaxial line. After passing through the impedance matching network composed of the first resistor 06, the second resistor 07, and the output capacitor 08 for the second time, the voltage is coupled to the device under test (DUT) for the second time. The voltage of the pulse signal on the DUT is the voltage V2 of the second platform.

[0020] The beneficial effects of this invention are as follows: The proposed full-domain TLP system not only retains the triggering characteristics of traditional TLP test devices, but also successfully extracts the transient regression characteristics of devices by introducing a second voltage platform. This method can more accurately assess the latch-up risk of complex ESD devices and high holding current devices, overcoming the limitations of traditional methods that rely solely on the holding voltage V. h Inadequate judgment. Attached Figure Description

[0021] Figure 1This is a classic TLP generator circuit;

[0022] Figure 2 This is a classic TLP waveform diagram;

[0023] Figure 3 This is a schematic diagram of the global TLP waveform of the present invention;

[0024] Figure 4 This is a circuit diagram of the global TLP waveform generation circuit of the present invention;

[0025] Figure 5 This is a flowchart of the global TLP test process of this invention.

[0026] The symbols in the attached diagram have the following meanings:

[0027] 01 is a DC voltage source, 02 is the first electronically controlled switch, 03 is the second electronically controlled switch, 04 is the first coaxial cable, 05 is the second coaxial cable, 06 is the first resistor, 07 is the second resistor, 08 is the output capacitor, and DUT is the device under test.

[0028] tr represents the rise time, t represents the rise time. p1 t is the duration of the first voltage plateau. p2 The duration of the second voltage plateau after the first falling edge, t f2 The time required for the voltage to drop from the second plateau to 0V is given by V1, where V1 is the average voltage value of the first voltage plateau and V2 is the average voltage value of the second voltage plateau. t1 is the time window corresponding to the pulse steady-state segment (70%~90%) in the first voltage plateau, and t2 is the time window corresponding to the pulse steady-state segment (70%~90%) in the second voltage plateau. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Example 1

[0031] One such Figure 3 The global TLP waveform shown is defined as follows: rise time t r The duration of the first voltage plateau is t p1 The duration t of the second voltage plateau after the first falling edge p2 And the time t required for the waveform to drop from the second plateau to 0V. f2 Among them, t r With t p1The values ​​are set consistent with the standard TLP system parameters to ensure test compatibility. The average voltage values ​​of the first and second voltage platforms are V1 and V2, respectively, with V1 always being greater than V2. t1 is defined as the time window corresponding to the pulse steady-state segment (70%~90%) in the first voltage platform, used to determine the turn-on curve; t2 is defined as the time window corresponding to the pulse steady-state segment (70%~90%) in the second voltage platform, used to determine the transient regression curve.

[0032] like Figure 4 As shown, a global transmission line pulse test system is proposed to generate the above waveform, including: a DC voltage source 01, a first electronically controlled switch 02, a second electronically controlled switch 03, a first coaxial cable 04, a second coaxial cable 05, a first resistor 06, a second resistor 07, an output capacitor 08, and a device under test (DUT).

[0033] The positive terminal of the DC voltage source 01 is connected to the positive terminal of the first electronically controlled switch 02, and the negative terminal of the DC voltage source 01 is grounded; the positive terminal of the first electronically controlled switch 02 is connected to the positive terminal of the DC voltage source 01, and the negative terminal of the first electronically controlled switch 02 is simultaneously connected to the upper end of the first coaxial line 04 and the positive terminal of the second electronically controlled switch 03; the lower end of the first coaxial line 04 is floating; the negative terminal of the second electronically controlled switch 03 is connected to the upper end of the first resistor 06, and the lower end of the first resistor 06 is grounded; the negative terminal of the second electronically controlled switch 03, the upper end of the second coaxial line 05, the upper end of the first resistor 06, and the left end of the second resistor 07 are all connected to node B; the lower end of the second coaxial line 05 is floating; the lower end of the first resistor 06 is grounded. The right end of the second resistor 07, the positive end of the output capacitor 08, and the positive end of the device under test (DUT) are all connected to a single point; the negative ends of the output capacitor 08 and the DUT are both grounded; that is, the output capacitor 08 and the DUT are connected in parallel.

[0034] The second coaxial cable 05 is used to generate a second voltage platform through signal reflection;

[0035] The DC voltage source 01 and the first electronically controlled switch 02 are used to generate a square wave pulse signal with a pulse width of tp1.

[0036] The first coaxial cable 04 is used for delayed transmission of square wave pulse signals, so that when the second electronic control switch 03 is turned on, the square wave pulse signal is voltage-distributed at point B to generate a second voltage platform.

[0037] The second electronic control switch 03 is used to control the time when the pulse signal is transmitted to the device under test (DUT).

[0038] The impedance matching network, consisting of the first resistor 06, the second resistor 07, and the output capacitor 08, is used to attenuate the pulse signal arriving at node B, determining how much voltage can be distributed to the device under test (DUT).

[0039] The working principle of this invention is as follows: DC voltage source 01 transmits a pulse with a width of t to the first coaxial line 04 through the first electronically controlled switch 02. p1 The square wave pulse signal enters the first coaxial line and is delayed by t. p1 Afterwards, the second electronically controlled switch 03 closes, and the pulse signal enters node B. The reflected voltage is reduced by the impedance matching network composed of the first resistor 06, the second resistor 07, and the output capacitor 08, and then coupled to the device under test (DUT). The reflected voltage enters the second coaxial line 05. The voltage of the DUT pulse signal is the voltage V1 of the first platform, and the pulse width is t. p1 . t p1 After a certain period of time, the second electronic control switch 03 is opened, and the pulse signal entering the second coaxial line 05 returns to node B after total reflection within the coaxial line. After passing through the impedance matching network composed of the first resistor 06, the second resistor 07, and the output capacitor 08 for the second time, the voltage is coupled to the device under test (DUT) for the second time. The voltage of the pulse signal on the DUT is the voltage V2 of the second platform.

[0040] Example 2:

[0041] This embodiment provides a global transmission line pulse testing method, utilizing... Figure 4 The test system shown tests the device under test (DUT). The global TLP test procedure is as follows: Figure 5 As shown, this embodiment provides a specific procedure for performing global TLP testing using the above circuit. This procedure aims to fully acquire the electrical characteristics of the device under test (DUT) during the turn-on and reset phases by gradually increasing pulse stress. The specific steps are as follows:

[0042] S1: Set the global TLP waveform parameters. The waveform includes the rise time tr, the first voltage plateau V1 and its duration tp1, the falling edge, the second voltage plateau V2 and its duration tp2, and always keep V1 greater than V2.

[0043] S2: Parameter initialization sets the initial value of pulse number n to 1 (i.e., n=1), and sets the initial test voltage amplitude and step increment according to the specifications of the device under test (DUT).

[0044] S3: Acquire the time-domain waveforms of voltage and current across the device under test (DUT) using an oscilloscope or other testing instruments; extract the average transient voltage and current values ​​within the stable region t1 of the first voltage plateau, denoted as (V... n1 , I n1The average transient voltage and current are extracted from the stable region t2 of the second voltage plateau and denoted as (V). n2 , I n2 );

[0045] S4: Perform a leakage current test on the device under test (DUT). If the measured leakage current exceeds a preset failure threshold, the device is determined to be faulty, the test is stopped, and all extracted current-voltage data is saved. Then proceed to step S5. If the measured leakage current does not exceed the preset failure threshold, the device is determined to be intact. Let n = n + 1, and synchronously increase the pulse amplitude of the first-order voltage V1 and the second-order voltage V2 according to a preset step size. Then return to step S2 until the device fails.

[0046] S5: Based on the data points recorded in step S3, connect the points obtained from each test in the IV coordinate system sequentially (V... 11 ,I 11 ) to (V n1 , I n1 The turn-on characteristic curve of the device is obtained; the points (V) obtained from each test are connected sequentially. 12 , I 12 ) to (V n2 ,I n2 The transient regression characteristic curve of the device is obtained.

[0047] The circuit structure, test method, and accompanying drawings proposed in this invention are merely a demonstration and illustration of global transmission line pulse testing. Apart from the structure shown in the accompanying drawings, anyone skilled in the art can modify or change the above structure without departing from the spirit and scope of this invention. For example, the circuit structure described above can be transformed into equivalent forms, components can be replaced, or the test method described above can be simply modified for different application scenarios. These modifications should obviously be within the protection scope of this invention.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A global transmission line pulse testing system, characterized in that, include: DC voltage source (01), first electronic control switch (02), second electronic control switch (03), first coaxial cable (04), second coaxial cable (05), first resistor (06), second resistor (07), output capacitor (08), and device under test (DUT); The positive terminal of the DC voltage source (01) is connected to the positive terminal of the first electronically controlled switch (02), and the negative terminal of the DC voltage source (01) is grounded; the positive terminal of the first electronically controlled switch (02) is connected to the positive terminal of the DC voltage source (01), and the negative terminal of the first electronically controlled switch (02) is simultaneously connected to the upper end of the first coaxial line (04) and the positive terminal of the second electronically controlled switch (03); the lower end of the first coaxial line (04) is floating; the negative terminal of the second electronically controlled switch (03) is connected to the upper end of the first resistor (06), and the lower end of the first resistor (06) is grounded; the second electronically controlled switch ( The negative end of the second coaxial line (03), the upper end of the second coaxial line (05), the upper end of the first resistor (06), and the left end of the second resistor (07) are all connected to node B; the lower end of the second coaxial line (05) is floating; the lower end of the first resistor (06) is grounded; the right end of the second resistor (07), the positive end of the output capacitor (08), and the positive end of the device under test (DUT) are all connected to one point; the negative end of the output capacitor (08) and the negative end of the device under test (DUT) are both grounded; that is, the output capacitor (08) and the device under test (DUT) are connected in parallel.

2. The global transmission line pulse testing system according to claim 1, characterized in that, The first coaxial cable (04) is used for delayed transmission of square wave pulse signals; the second coaxial cable (05) is used to generate a second voltage platform through signal reflection; the first resistor (06), the second resistor (07) and the output capacitor (08) form an impedance matching network for distributing the pulse signal voltage reaching the node B.

3. A method for generating a global transmission line pulse (TLP) waveform using the test system as described in claim 1 or 2, characterized in that, Includes the following steps: The first electronic control switch (02) is closed, causing the DC voltage source (01) to emit a square wave pulse signal with a pulse width of tp1 to the first coaxial line (04); after the pulse signal enters the first coaxial line (04) and is delayed by tp1, the second electronic control switch (03) is closed. At this time, the pulse signal is coupled to the device under test (DUT) by the impedance matching network composed of the first resistor (06), the second resistor (07), and the output capacitor (08) at node B, forming a first voltage platform V1; after a time of tp1, the second electronic control switch (03) is opened. At this time, the pulse signal entering the second coaxial line (05) is reflected in the coaxial line and returns to node B for a second distribution. It is loaded onto the device under test (DUT) through the impedance matching network, forming a second voltage platform V2; wherein, the average voltage value of the first voltage platform V1 is always greater than the average voltage value of the second voltage platform V2.

4. A method for testing pulses across a global transmission line, characterized in that, The method of testing the device under test (DUT) using the test system as described in claim 1 or 2 includes the following steps: S1: Set the global TLP waveform parameters. The waveform includes the rise time tr, the first voltage plateau V1 and its duration tp1, the falling edge, the second voltage plateau V2 and its duration tp2, and always keep V1 greater than V2. S2: Initialize pulse number n, and control the test system to send the nth global TLP pulse signal to the device under test (DUT); n≥1; S3: Acquire the time-domain waveforms of the voltage and current across the device under test (DUT); extract the average transient voltage and current values ​​within the stable region t1 of the first voltage plateau, denoted as (V n1 , I n1 The average transient voltage and current are extracted from the stable region t2 of the second voltage plateau and denoted as (V). n2 , I n2 ); S4: Perform a leakage current test on the device under test (DUT); if the leakage current does not exceed the preset failure threshold, increase the pulse number n and increase the amplitude of the first voltage platform V1 and the second voltage platform V2, and repeat steps S2 to S4; if the leakage current exceeds the preset failure threshold, stop the test. S5: Based on the data points recorded in step S3, plot the on-state characteristic curve and the transient regression characteristic curve in the IV coordinate system respectively.

5. The global transmission line pulse test method according to claim 4, characterized in that, In step S5, the turn-on characteristic curve is obtained from the points (V) obtained in each test. 11 , I 11 ) to (V n1 , I n1 The transient regression characteristic curve is formed by connecting the points (V) obtained from each test in sequence; 12 , I 12 ) to (V n2 , I n2 It is formed by connecting them sequentially.

Images