System for realizing data acquisition and signal source based on FPGA (Field Programmable Gate Array) integration

Abstract

The invention provides a system for realizing high-speed data acquisition and a high-precision signal source based on FPGA (Field Programmable Gate Array) integration. The invention aims to integrate a plurality of functional modules such as a high-speed ADC interface, real-time data processing, high-precision DAC control and complex waveform generation into a single chip through the high programmability and parallel processing capability of the FPGA, so that the miniaturization of the system is realized, and the real-time performance of data processing, the multi-channel synchronization precision and the flexibility of signal generation are remarkably improved. The core of the embodiment of the invention is that an FPGA (Field Programmable Gate Array) chip is used as a master control and data processing center, and a high-speed ADC (Analog to Digital Converter) chip, a high-precision DAC (Digital to Analog Converter) chip, a clock circuit, an external memory (such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory)) and necessary interface circuits (such as gigabit Ethernet, SFP (Small Form-factor Pluggable) + optical ports and the like) are peripherally connected to form a highly integrated hardware platform.

Description

Technical Field

[0001] This invention belongs to the field of sonar system receiving and transmitting, specifically relating to a system for data acquisition and signal generation based on FPGA integration. In particular, it relates to the design and implementation method of a high-speed data acquisition and high-precision signal source based on FPGA integration. Background Technology

[0002] Sonar systems are core equipment in modern marine exploration, underwater navigation, resource exploration, and underwater security. Their performance directly depends on the accuracy of signal reception and data acquisition, as well as the accuracy of signal transmission and waveform generation. Traditional sonar systems typically employ a discrete architecture, where data acquisition (ADC), signal processing (such as DSP), and signal generation (DAC) functions are performed collaboratively by multiple independent dedicated chips or modules.

[0003] In terms of data acquisition, as sonar technology advances towards higher resolution and wider bandwidth, the requirements for sampling rate and number of channels are increasing. Existing solutions often employ dedicated ADC chips with interface logic to transmit high-speed data to backend processors (such as DSPs or GPUs) via protocols like JESD204B. However, this architecture suffers from problems such as long data transmission paths, uncertain latency, and complex multi-channel synchronous calibration. Furthermore, the massive amounts of data pose a significant challenge to the processor's real-time processing capabilities, easily creating a system bottleneck.

[0004] In terms of signal generation, high-precision, multi-waveform, and real-time reconfigurable signal sources are crucial for high-performance sonar transmitters. Traditional technologies often rely on dedicated DAC chips or direct digital frequency synthesis (DDS) chips, using microcontrollers or DSPs to configure waveform parameters and load data. While this approach can achieve basic functions, it suffers from slow waveform switching speed, poor flexibility, difficulty in generating complex modulation waveforms, and low system integration due to communication between multiple chips, resulting in unsatisfactory power consumption and PCB area.

[0005] More importantly, the aforementioned discrete architecture results in the acquisition and transmission functions being physically and logically independent. When working together, they require complex synchronization and timing management mechanisms, increasing the complexity and unreliability of the system design. The system is also bulky and consumes a lot of power, making it difficult to meet the urgent needs of modern portable and embedded sonar devices for miniaturization, low power consumption, and high reliability.

[0006] Patent document CN111736517A discloses a synchronous acquisition and processing card system based on a multi-channel ADC and FPGA, including a clock management unit, multiple ADC chips, two FPGA chips, multiple sets of DDR3 chips, and a power distribution network. The clock management unit generates multiple synchronous sampling clocks and reference clocks, and the multiple ADC chips are used to acquire and convert intermediate frequency signals from SMP inputs. However, the integration level of patent document CN111736517A still needs further improvement.

[0007] Therefore, there is an urgent need in this field for a highly integrated solution that can collaboratively manage high-speed data acquisition and high-precision signal generation, in order to optimize system design, improve synchronization accuracy, enhance real-time processing, and effectively reduce system size, power consumption, and cost. Summary of the Invention

[0008] To address the shortcomings of existing technologies, the purpose of this invention is to provide a system for data acquisition and signal generation based on FPGA integration.

[0009] According to the present invention, a system for data acquisition and signal generation based on FPGA integration is provided, comprising: an FPGA chip, an ADC module, a DAC module, a clock circuit, and a communication interface; The FPGA chip implements digital logic functions and can be directly connected to multiple ADC chips and multiple DAC chips. The clock circuit provides synchronization, sampling, and reference clocks for the ADC module, DAC module, and FPGA chip; External memory serves as a data cache unit; The communication interface is used for command interaction and data transmission with the host computer.

[0010] Preferably, the FPGA integrates the following: The data acquisition path includes an ADC interface controller, a multi-channel data buffer unit, and a real-time preprocessing unit. The signal generation path includes a direct digital frequency synthesis (DDS) waveform generator, a waveform data storage RAM, complex modulation logic, and a DAC interface controller. The collaborative management and communication unit includes a global synchronization and timing controller for providing a synchronization clock and trigger signal for the acquisition and transmission paths; Embedded processors are used for system configuration, task scheduling, and external communication.

[0011] Preferably, the embedded processor dynamically configures the sampling rate and gain of the acquisition channel, as well as the type, parameters, and output timing of the transmitted waveform, to realize online reconfiguration of system functions and adapt to different sonar operating modes.

[0012] Preferably, the global synchronization and timing controller receives an external clock source and generates a strictly phase-aligned acquisition clock and transmission clock inside the FPGA to ensure that the inherent delay between the ADC module sampling and the DAC module output is fixed and measurable, thereby achieving nanosecond-level synchronization of the acquisition and transmission links.

[0013] Preferably, the ADC module uses a high-speed ADC chip with a sampling rate of ≥100MSPS and a resolution of ≥14 bits, and its digital output interface is directly connected to the FPGA; The DAC module uses a high-precision DAC chip with a refresh rate of ≥500MSPS and a resolution of ≥16 bits, and its digital input interface is directly connected to the FPGA.

[0014] Preferably, in the acquisition path, after the ADC data is received by the interface controller, it is directly sent to the preprocessing unit for real-time processing. The processed data is efficiently transferred to the external memory or directly used in the internal algorithm via DMA. In the transmission path, by configuring the frequency, phase, and amplitude control words of the DDS waveform generator, or by reading pre-stored arbitrary waveform data from the waveform RAM, and combining it with modulation logic, the required simple or complex modulation arbitrary waveforms are generated in real time, and then driven by the DAC interface controller to output the DAC chip.

[0015] Preferably, the FPGA chip includes: The ADC data receiving and processing module establishes a high-speed serial link with the ADC chip, receives and deframes the raw sampled data from the ADC; performs real-time processing on the received raw data, including offset correction and gain correction, and can optionally perform digital down-conversion (DDC) and filtering operations to extract useful signals or reduce the data rate; and packages the processed data into data frames according to a custom protocol. The data caching and scheduling module instantiates the DDR controller IP core of the FPGA to realize read and write control of the off-chip DDR SDRAM; it is responsible for scheduling two data streams. The receiving data stream writes data from the ADC to the DDR in real time through the AXI4 bus for caching, realizing temporary storage of massive amounts of data; the transmitting data stream reads pre-stored waveform data from the DDR or real-time received data from the host computer according to the instructions and sends it to the DAC transmitting channel. The DAC signal generation module implements a DDS core within the FPGA logic to generate standard sine and triangular waveforms with programmable frequency, phase, and amplitude in real time; it reads arbitrary waveform data pre-downloaded by the host computer from the DDR cache, or receives waveform data streams sent by the host computer in real time; it configures and instantiates the IP core provided by the DAC manufacturer, frames the generated waveform data according to the protocol, and sends it to the DAC chip through a high-speed serial link. The system control and communication interface module receives control commands from the host computer and uploads status information or collected data to the host computer. Based on the core state machine, it parses the host computer commands, coordinates and controls the working status and timing of the ADC module, DAC module, and data buffer and scheduling module to ensure the synchronous triggering and orderly execution of acquisition and transmission.

[0016] Preferably, the sampling clocks of the ADC module and the DAC module are essentially synchronized; The FPGA's global controller receives external hard trigger signals or software trigger signals. When a trigger event occurs, the controller simultaneously sends a synchronization enable signal Sync to both the ADC data receiving path and the DAC signal generating path, ensuring that the acquisition and transmission actions start simultaneously at a defined clock edge, achieving nanosecond-level time synchronization accuracy.

[0017] Preferably, the communication interface implements a Gigabit Ethernet or PCIe interface.

[0018] Preferably, an FPGA chip is used as the main control and data processing center.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention integrates the functions of multiple discrete chips in traditional solutions into a single FPGA chip, which greatly simplifies the design of peripheral circuits, reduces the difficulty of PCB layout and routing, and reduces the system size and the number of components. 2. This invention utilizes the internal hardware logic and global clock network of the FPGA to achieve clock synchronization and precise synchronization between the acquisition and transmission links, solving the problems of difficult synchronization and uncertain delays between discrete architectures. Data preprocessing is completed internally, resulting in extremely low latency and significantly enhanced real-time performance. 3. The waveform generation algorithm and data processing flow of this invention are implemented in hardware logic language. The system function can be quickly changed by reconfiguring the FPGA bitstream file, easily adapting to the sonar signal requirements of different frequencies, waveforms and modulation methods, and the development cycle is short. 4. This invention reduces the number of external processing chips, and the single-chip solution also reduces overall material costs and supply chain management complexity. Attached Figure Description

[0020] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a block diagram of the hardware functional components of the present invention; Figure 2 This is a functional block diagram of the ADC data receiving and processing module of the present invention; Figure 3 This is a functional block diagram of the data caching and scheduling module of the present invention; Figure 4 This is a functional block diagram of the DAC signal generation module of the present invention; Figure 5 This is a functional block diagram of the system control and communication interface module of the present invention; Figure 6 This is a system workflow diagram of the present invention. Detailed Implementation

[0021] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0022] The purpose of this invention is to overcome the shortcomings of the discrete design of data acquisition and signal generation in existing sonar systems, and to provide a system based on FPGA integration to achieve high-speed data acquisition and high-precision signal generation. This invention aims to leverage the high programmability and parallel processing capabilities of FPGAs to integrate multiple functional modules, such as high-speed ADC interfaces, real-time data processing, high-precision DAC control, and complex waveform generation, into a single chip. This achieves system miniaturization and significantly improves the real-time performance of data processing, multi-channel synchronization accuracy, and signal generation flexibility.

[0023] The core of this invention lies in using an FPGA chip as the main control and data processing center, and connecting it to a high-speed ADC chip, a high-precision DAC chip, a clock circuit, an external memory (such as DDR SDRAM), and necessary interface circuits (such as Gigabit Ethernet, SFP+ optical port, etc.) to form a highly integrated hardware platform.

[0024] The present invention will now be described in detail.

[0025] The system for data acquisition and signal generation based on FPGA integration provided by the present invention includes: 1. FPGA chips implement all digital logic functions.

[0026] Specifically, a hardware platform centered on an FPGA is constructed, which directly connects to multiple high-speed ADC chips and multiple high-precision DAC chips. The FPGA integrates: a high-speed data acquisition path, including an ADC interface controller, a multi-channel data buffer unit, and a real-time preprocessing unit (such as digital down-conversion DDC, filtering, and decimation); a high-precision signal generation path, including a direct digital frequency synthesis (DDS) waveform generator, waveform data storage RAM, complex modulation logic, and a DAC interface controller; a collaborative management and communication unit, including a global synchronization and timing controller to provide high-precision, low-jitter synchronization clocks and trigger signals for the acquisition and transmission paths; and an on-chip embedded processor (such as an ARM Cortex-M / A series hard core or a MicroBlaze soft core) for system configuration, task scheduling, and external communication. Through the embedded processor or an external host, the sampling rate and gain of the acquisition channels, as well as the type, parameters, and output timing of the transmitted waveforms, can be dynamically configured, enabling online reconfiguration of system functions to adapt to different sonar operating modes.

[0027] The global synchronization and timing controller receives an external high-precision clock source and generates a strictly phase-aligned acquisition clock and transmission clock inside the FPGA to ensure that the inherent delay between ADC sampling and DAC output is fixed and measurable, thereby achieving nanosecond-level synchronization of the acquisition and transmission links.

[0028] 2. High-speed ADC module: It adopts a high-speed ADC chip with a sampling rate of ≥100MSPS and a resolution of ≥14 bits. Its digital output interface (such as JESD204B / C or LVDS) is directly connected to the FPGA.

[0029] 3. High-precision DAC module: It adopts a high-precision DAC chip with a refresh rate of ≥500MSPS and a resolution of ≥16 bits. Its digital input interface (such as JESD204B / C or LVDS) is directly connected to the FPGA.

[0030] Specifically, in the acquisition path, after the ADC data is received by the interface controller, it is directly sent to the preprocessing unit for real-time processing. The processed data can be efficiently transferred to external memory via DMA or directly used in internal algorithms. In the transmission path, by configuring the frequency, phase and amplitude control words of the DDS waveform generator, or reading pre-stored arbitrary waveform data from the waveform RAM, and combining it with modulation logic, the required simple or complex modulation arbitrary waveforms are generated in real time and driven by the DAC interface controller to output the DAC chip.

[0031] 4. High-precision clock circuit, using a low-phase-noise clock generator or jitter canceller, provides synchronous, low-jitter sampling clock and reference clock for ADC, DAC and FPGA.

[0032] 5. External memory: Connect one or more DDR3 / 4 SDRAM chips to serve as a cache unit for massive amounts of data.

[0033] 6. Communication interface: Implement Gigabit Ethernet (UDP protocol) or PCIe interface for command interaction and data transmission with the host computer.

[0034] 7. Power management circuit, providing stable, low-noise power supply for various chips, modules, circuits and devices with multiple voltages.

[0035] The implementation method of this invention mainly includes the following steps: Step 1: Hardware Platform Construction and Clock System Design 1. Select ADC, DAC and FPGA chips based on system performance indicators (sampling rate, bandwidth, accuracy).

[0036] 2. Design the PCB circuit board to ensure the integrity of the high-speed signal link between the ADC, DAC and FPGA (such as impedance matching, differential routing, and length matching).

[0037] 3. Design a clock tree. Specifically, use a high-performance crystal or oscillator as the reference clock source, inputting it to a clock generator chip (such as Si5338 or AD9528). This clock generator produces: one low-jitter clock synchronized with the reference clock, used as the ADC sampling clock (S_CLK); one clock synchronized with S_CLK, used as the DAC update clock (D_CLK); and one or more reference clocks provided to the FPGA's high-speed transceiver (e.g., for the JESD204B interface). This design ensures that the ADC sampling and DAC transmission clocks are from the same source and in phase, laying the foundation for system synchronization.

[0038] Step 2: FPGA Internal Logic Function Module Design and Integration Inside the FPGA, the following core functional modules are implemented using hardware description languages ​​(such as Verilog / VHDL): 1. ADC data receiving and processing module ① Interface protocol layer (such as JESD204B IP Core). Configure and instantiate the JESD204B IP core provided by the ADC manufacturer to establish a high-speed serial link with the ADC chip, and receive and deframe the raw sampling data from the ADC; ② Data calibration and preprocessing. Real-time processing of received raw data, including offset correction and gain correction, and optional digital down-conversion (DDC), filtering, etc., to extract useful signals or reduce the data rate; ③ Data Packaging and Framing. The processed data is packaged into data frames according to a custom protocol (such as adding timestamps, frame headers, channel numbers, etc.).

[0039] 2. Data caching and scheduling module ①DDR memory controller. Instantiate the FPGA's DDR controller IP core (such as MIG-Memory Interface Generator) to implement read and write control of off-chip DDR SDRAM; ② Data Stream Arbitration Module. This module acts as a data crossover switch, responsible for scheduling two data streams. The receiving data stream writes data from the ADC to the DDR in real time via the AXI4 bus for buffering, enabling temporary storage of massive amounts of data. The transmitting data stream reads pre-stored waveform data from the DDR or real-time received data from the host computer according to instructions and sends it to the DAC transmitting channel.

[0040] 3. DAC signal generation module ① Waveform generation and scheduling. Direct digital synthesis (DDS) implements the DDS core within the FPGA logic to generate standard waveforms such as sine waves and triangle waves with programmable frequency, phase, and amplitude in real time; Arbitrary waveform generator (ARB) reads arbitrary waveform data pre-downloaded by the host computer from the DDR cache, or receives waveform data streams sent by the host computer in real time; ② Interface protocol layer (such as JESD204B IP Core). Configure and instantiate the JESD204B IP core provided by the DAC manufacturer, frame the generated waveform data according to the protocol, and send it to the DAC chip through a high-speed serial link.

[0041] 4. System control and communication interface module ① Host computer communication. Implement a UDP / IP protocol stack or PCIe endpoint module to receive control commands from the host computer (such as starting acquisition, setting the sampling rate, setting the DDS frequency, selecting the waveform source, etc.), and upload status information or acquired data to the host computer; ② Global Controller. This is a core state machine that parses instructions from the host computer, coordinates and controls the working state and timing of the ADC module, DAC module, and buffer scheduling module, ensuring synchronized and orderly triggering of data acquisition and transmission. For example, upon receiving an external trigger signal, ADC acquisition and DAC transmission are started simultaneously.

[0042] Step 3: Implementation of System Synchronization and Triggering Mechanism 1. Clock synchronization. By sharing the same source clock as described in step one, the sampling clocks of the ADC and DAC are essentially synchronized.

[0043] 2. Trigger Synchronization. The FPGA's global controller receives external hard trigger signals or software trigger signals. When a trigger event occurs, the controller simultaneously sends a synchronization enable signal (Sync) to both the ADC data receiving path and the DAC signal generating path, ensuring that the acquisition and transmission actions start simultaneously at a defined clock edge, achieving nanosecond-level time synchronization accuracy.

[0044] Step 4: System Workflow 1. Initialization. After the system is powered on, the FPGA configures the registers of the clock generator, ADC and DAC chips through the SPI / I2C interface, initializes the JESD204B link, and establishes stable communication; it also initializes the DDR controller and various internal functional modules.

[0045] 2. Command Reception. The host computer sends control command packets via Ethernet. The FPGA parses the commands and determines whether to execute a data acquisition task, a transmission task, or a synchronization task.

[0046] 3. Example of Execution Mode: Synchronous Acquisition and Transmission. The host computer sends a "synchronous trigger" command and specifies the parameters; the FPGA reads the pre-stored transmission waveform data from the DDR into the FIFO and prepares it; upon receiving the external trigger signal, the global controller immediately starts the ADC data stream and DAC data stream simultaneously; the ADC data is stored in a specific area of ​​the DDR in real time, while the DAC transmits the waveform; after acquisition is completed, the FPGA transmits the acquired data stored in the DDR back to the host computer via Ethernet for analysis and processing.

[0047] Through the above-described embodiments, this invention integrates the high-speed acquisition and high-precision signal generation functions, which traditionally require multiple boards, into a single board. Furthermore, it utilizes FPGA to achieve software-defined hardware and deep collaborative processing, resulting in significant advantages such as high integration, high synchronization accuracy, strong real-time performance, and good flexibility. It is particularly suitable for fields with extremely high requirements for synchronization and real-time performance, such as sonar systems.

[0048] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0049] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A system for data acquisition and signal generation based on FPGA integration, characterized in that, include: FPGA chip, ADC module, DAC module, clock circuit, communication interface; The FPGA chip implements digital logic functions and can be directly connected to multiple ADC chips and multiple DAC chips. The clock circuit provides synchronization, sampling, and reference clocks for the ADC module, DAC module, and FPGA chip; External memory serves as a data cache unit; The communication interface is used for command interaction and data transmission with the host computer.

2. The system for data acquisition and signal generation based on FPGA integration according to claim 1, characterized in that, The FPGA internal integration includes: The data acquisition path includes an ADC interface controller, a multi-channel data buffer unit, and a real-time preprocessing unit. The signal generation path includes a direct digital frequency synthesis (DDS) waveform generator, a waveform data storage RAM, complex modulation logic, and a DAC interface controller. The collaborative management and communication unit includes a global synchronization and timing controller for providing a synchronization clock and trigger signal for the acquisition and transmission paths; Embedded processors are used for system configuration, task scheduling, and external communication.

3. The system for data acquisition and signal generation based on FPGA integration according to claim 2, characterized in that, The embedded processor dynamically configures the sampling rate and gain of the acquisition channel, as well as the type, parameters, and output timing of the transmitted waveform, to realize online reconfiguration of system functions and adapt to different sonar operating modes.

4. The system for data acquisition and signal generation based on FPGA integration according to claim 2, characterized in that, The global synchronization and timing controller receives an external clock source and generates acquisition and transmission clocks with strictly aligned phase relationships within the FPGA, ensuring that the inherent delay between the ADC module sampling and the DAC module output is fixed and measurable, thereby achieving nanosecond-level synchronization of the acquisition and transmission links.

5. The system for data acquisition and signal generation based on FPGA integration according to claim 1, characterized in that, The ADC module uses a high-speed ADC chip with a sampling rate of ≥100MSPS and a resolution of ≥14 bits, and its digital output interface is directly connected to the FPGA. The DAC module uses a high-precision DAC chip with a refresh rate of ≥500MSPS and a resolution of ≥16 bits, and its digital input interface is directly connected to the FPGA.

6. The system for data acquisition and signal generation based on FPGA integration according to claim 1, characterized in that, In the acquisition path, after the ADC data is received by the interface controller, it is directly sent to the preprocessing unit for real-time processing. The processed data is efficiently transferred to the external memory or directly used in the internal algorithm via DMA. In the transmission path, by configuring the frequency, phase, and amplitude control words of the DDS waveform generator, or by reading pre-stored arbitrary waveform data from the waveform RAM, and combining it with modulation logic, the required simple or complex modulation arbitrary waveforms are generated in real time, and then driven by the DAC interface controller to output the DAC chip.

7. The system for data acquisition and signal generation based on FPGA integration according to claim 1, characterized in that, The FPGA chip includes: The ADC data receiving and processing module establishes a high-speed serial link with the ADC chip, receives and deframes the raw sampled data from the ADC; performs real-time processing on the received raw data, including offset correction and gain correction, and can optionally perform digital down-conversion (DDC) and filtering operations to extract useful signals or reduce the data rate; and packages the processed data into data frames according to a custom protocol. The data caching and scheduling module instantiates the DDR controller IP core of the FPGA to realize read and write control of the off-chip DDR SDRAM; it is responsible for scheduling two data streams. The receiving data stream writes data from the ADC to the DDR in real time through the AXI4 bus for caching, realizing temporary storage of massive amounts of data; the transmitting data stream reads pre-stored waveform data from the DDR or real-time received data from the host computer according to the instructions and sends it to the DAC transmitting channel. The DAC signal generation module implements a DDS core within the FPGA logic to generate standard sine and triangular waveforms with programmable frequency, phase, and amplitude in real time; it reads arbitrary waveform data pre-downloaded by the host computer from the DDR cache, or receives waveform data streams sent by the host computer in real time; it configures and instantiates the IP core provided by the DAC manufacturer, frames the generated waveform data according to the protocol, and sends it to the DAC chip through a high-speed serial link. The system control and communication interface module receives control commands from the host computer and uploads status information or collected data to the host computer. Based on the core state machine, it parses the host computer commands, coordinates and controls the working status and timing of the ADC module, DAC module, and data buffer and scheduling module to ensure the synchronous triggering and orderly execution of acquisition and transmission.

8. The system for data acquisition and signal generation based on FPGA integration according to claim 1, characterized in that, The sampling clocks of the ADC module and the DAC module are essentially synchronized; The FPGA's global controller receives external hard trigger signals or software trigger signals. When a trigger event occurs, the controller simultaneously sends a synchronization enable signal Sync to both the ADC data receiving path and the DAC signal generating path, ensuring that the acquisition and transmission actions start simultaneously at a defined clock edge, achieving nanosecond-level time synchronization accuracy.

9. The system for data acquisition and signal generation based on FPGA integration according to claim 1, characterized in that, The communication interface implements Gigabit Ethernet or PCIe interface.

10. The system for data acquisition and signal generation based on FPGA integration according to claim 1, characterized in that, An FPGA chip is used as the main control and data processing center.

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