Hardware mainboard based on Panchaeu M900 processor

Abstract

The invention relates to a hardware mainboard based on a Pantou M900 processor, and belongs to the field of computer hardware design. According to the scheme, a main processor, power management, a memory, an expansion interface and an embedded control module are integrated through a modular architecture. The core technical means comprises the following steps of: disclosing hierarchical power supply time sequence control logic, and determining an enabling dependency relationship of each voltage domain and an execution process of an embedded controller; a decoupling capacitor network of the LPDDR4 memory subsystem and a PCB layout are forcibly stipulated to completely copy the verified design; quantitative physical design parameters of the high-speed differential interface are provided; and hardware interfaces of the embedded controller and each controlled unit are completely disclosed. The system has the technical effects that the problems of power supply time sequence black box, high-speed signal rule deficiency and opaque system management interface in high-end SoC platform development are solved, the reliability, performance consistency and manufacturability of a hardware platform are ensured, and intelligent power supply and thermal management are realized.

Description

Technical Field

[0001] This invention relates to the field of computer hardware technology, specifically to a hardware motherboard based on the Pangu M900 processor. Background Technology

[0002] With the continuous evolution of semiconductor technology, high-performance System-on-Chip (SoC) devices have widely integrated multi-core CPUs (GPUs), graphics processing units (GPUs), high-speed interconnect controllers, and various dedicated acceleration units, resulting in ever-increasing performance and functional complexity. However, the design of the hardware motherboard supporting such SoCs has evolved from traditional functional interconnects to a comprehensive systems engineering project involving precise power timing management, gigabit-level signal integrity design, efficient thermodynamic control, and complex system state coordination. Currently, the development of hardware platforms based on such high-end SoCs in this field generally faces the following prominent technical bottlenecks: First, system-level power management design suffers from a severe "black box" phenomenon. Modern SoCs contain dozens of independent power domains, such as CPU cores, GPU cores, various physical layer interfaces (PHYs), and memory controllers. The power-on and power-off of these voltage domains must follow extremely strict timing and dependencies; any deviation can lead to latch-up, logic malfunctions, or permanent damage to the silicon chip. Although SoC manufacturers provide a basic list of power requirements, the logic for generating enable signals for each voltage domain, their interlocking relationships, and the specific hardware control circuits and firmware processes for implementing this strict timing are usually considered core design secrets and not disclosed. This forces downstream hardware developers to engage in lengthy, expensive, and high-risk trial-and-error processes, not only extending product development cycles but also creating potential system reliability vulnerabilities.

[0003] Secondly, the lack of physical implementation rules for high-speed subsystems leads to a high degree of uncertainty in performance and reliability. For high-speed interfaces such as LPDDR4 / 4X memory, PCIe, USB 3.0, and HDMI 2.0, stable operation depends on much more than the correctness of schematic connections. It hinges on the design of transmission line impedance control, trace length and topology, timing matching accuracy, crosstalk suppression, and power distribution network (PDN) at the printed circuit board (PCB) level. Especially for the memory subsystem, its high-frequency stable operation is highly dependent on the optimized layout of the decoupling capacitor network, a core design element heavily reliant on experience. Existing publicly available reference designs typically only provide schematic block diagrams or simplified connection guidelines, completely lacking the aforementioned quantitative physical design constraints and proven layout schemes. As a result, products that are copied or further developed often suffer from persistent problems such as degraded signal integrity, high data error rates, and inability to meet memory operating frequencies. Furthermore, the debugging process is extremely difficult, severely impacting product performance consistency and mass production yield.

[0004] Furthermore, the ambiguous interfaces of the intelligent management unit in the hardware platform hinder the implementation of advanced functions. A stable and reliable system requires an embedded controller (EC) or similar management unit to perform real-time temperature monitoring, dynamic thermal control, precise power state switching, and fault emergency response. However, existing technologies typically treat such management units and their firmware as closed "black boxes," not disclosing the specific hardware interface definitions, communication protocols, and control flows between them and actuators such as the main SoC, power management chip, temperature sensors, and fans. Therefore, developers struggle to achieve refined energy efficiency management, build effective thermal control loops, and implement rapid and safe protection mechanisms for abnormal states (such as overheating and overcurrent), thus limiting the improvement of the hardware platform's intelligence and reliability.

[0005] In summary, significant information barriers and technological gaps exist in the current high-end hardware platform design field: core power timing logic, key physical implementation rules, and system management interfaces are not fully disclosed. This "knowing what but not why" situation forces developers to engage in inefficient reverse engineering and trial-and-error, becoming a major obstacle to rapid innovation, product reliability, and performance consistency improvements in the industry. Therefore, there is an urgent need in this field for a deeply disclosed, complete hardware platform design solution that covers the entire chain of details from architecture definition to physical implementation, providing a clear and reliable technical implementation path and reducing development barriers and risks. Summary of the Invention

[0006] In order to solve the problems of the prior art, the present invention provides a hardware motherboard based on the Pangu M900 processor.

[0007] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: a hardware motherboard based on the Pangu M900 processor, characterized in that it includes: The Pangu M900 main processor (U1) has multiple power domain pins, ground pins, high-speed interface pins, and general-purpose input / output pins. The power management module is connected to the power domain pins of the Pangu M900 main processor and is used to convert the external input voltage into multiple independent voltage domains required by the main processor and control the power-on and power-off timing of each voltage domain. The memory module is connected to the memory controller pins of the Pangu M900 main processor via an LPDDR4 / 4X interface; An expansion interface module is connected to the high-speed interface pins of the Pangu M900 main processor to provide peripheral device connectivity. The expansion interface module includes at least a storage interface expanded by a PCIe interface, multiple downstream USB ports expanded by a USB interface, and a network interface expanded by an RGMII interface. An embedded control module is connected to some general-purpose input / output pins of the Pangu M900 main processor, the power management module, and the power control terminal in the expansion interface module. It is used to monitor the system status, control the heat dissipation unit, respond to user input, and coordinate with the power management module to manage power timing. The layout and wiring of the power management module, memory module, expansion interface module and embedded control module follow the electrical design rules preset by the Pangu M900 main processor.

[0008] In one specific embodiment of the first aspect, the power management module includes: A multi-channel DC / DC converter is used to generate power rails with different voltage values ​​required by the main processor, memory module and expansion interface module; Multiple load switches, controlled by an enable signal from the embedded control module or the main processor, are used to control the switching of some power rails. The power-on sequence of the power rails follows the order from standby power, core power, to input / output power, and the power-off sequence is the reverse.

[0009] In one specific implementation of the first aspect, the extended interface module includes: The SATA expansion submodule includes a SATA bridge chip, wherein the upstream port of the bridge chip is connected to the PCIe or SATA port of the main processor, and the downstream port is used to connect at least one SATA storage device. The USB hub submodule includes a USB 3.0 hub chip. The upstream port of the hub chip is connected to the USB port of the main processor, and the downstream port provides multiple independent USB 3.0 connection points. The power supply of each downstream port is independently controlled by the embedded control module. The video input switching submodule includes an HDMI switch chip and a microcontroller that communicates with it. The multiple input ports of the HDMI switch chip are used to receive external HDMI signals, and the output port is connected to the HDMIRX port of the main processor. The microcontroller receives switching commands and controls the HDMI switch chip through the I2C bus.

[0010] In one specific embodiment of the first aspect, the embedded control module includes a control unit with a microcontroller as its core. The microcontroller is connected to multiple negative temperature coefficient thermistors distributed in key locations on the motherboard via an ADC channel for monitoring temperature; and is connected to at least one fan via a PWM output channel for adjusting the fan speed according to the monitored temperature.

[0011] In one specific embodiment of the first aspect, a boot configuration circuit is further included. The boot configuration circuit is connected to the BOOT_SEL0, BOOT_SEL1, and BOOT_SEL2 pins of the Pangu M900 main processor via pull-up or pull-down resistors, and is used to configure the boot source of the main processor as one of SPINOR Flash, eMMC, or UFS.

[0012] In one specific implementation of the first aspect, the wiring between the memory module and the Pangu M900 main processor, including address command lines, data lines and differential clock lines, has a topology, line length matching and decoupling capacitor placement that fully comply with the physical design of the reference design board.

[0013] In one specific implementation of the first aspect, the high-speed differential signal interface in the expansion interface module, including USB, HDMI and SATA interfaces, has differential pairs that meet the following design rules on the printed circuit board: routing on a specified signal layer, controlling characteristic impedance, limiting maximum trace length, and maintaining minimum spacing between differential pairs.

[0014] Secondly, a power timing control method for a hardware motherboard, characterized by comprising the following steps: S1: After receiving an external power input, the embedded control module first enables the power conversion circuit in the standby voltage domain to supply power to itself and part of the standby circuit of the main processor. S2: After initialization, the embedded control module sends enable signals in sequence according to the system status to control multiple load switches and DC / DC converters in the power management module to establish the core voltage domain, memory voltage domain and peripheral interface voltage domain in a preset order. S3: After all power rails are stable and a power good signal is received, the embedded control module releases the reset signal of the main processor, and the main processor begins to load and execute code from the configured boot source; S4: When the system is powered off or enters a low-power state, the embedded control module or the main processor controls the power management module to turn off the power of each voltage domain in the reverse order of power-on or a specific power-off sequence.

[0015] In one specific implementation of the second aspect, in step S2, the preset sequence includes at least: enabling the memory voltage domain after the core voltage domain has stabilized; and enabling the voltage domain that powers the expansion interface module after the main voltage domain has stabilized.

[0016] In one specific embodiment of the second aspect, the embedded control module continuously monitors the power good signal of each voltage domain and the temperature sensed by the negative temperature coefficient thermistor; when a power abnormality is detected or the temperature exceeds the threshold, the embedded control module performs a protective power-down operation or adjusts the fan speed.

[0017] The beneficial effects of this invention are as follows: 1. By decoupling and parameterizing the systematic hardware design knowledge, this invention fundamentally solves the reliability, consistency, and manufacturability challenges faced in the development of high-end SoC platforms. Specifically, the hierarchical power timing control scheme disclosed in this invention clarifies the enable dependencies of each voltage domain and the specific execution logic of the embedded controller. This allows any implementer to achieve a power-on / power-off sequence completely consistent with the original design, completely eliminating the risk of SoC latch-up or functional abnormalities due to timing errors, and significantly improving the inherent reliability of the hardware platform. Furthermore, for the LPDDR4 memory subsystem, the scheme mandates the replication of verified decoupling capacitor networks and PCB layouts. The disclosure of this key rule ensures that the replicated design achieves the same power integrity and signal timing margins as the original design, thereby guaranteeing the stability of memory performance at high frequencies and avoiding data errors and system crashes. In addition, the full set of quantitative design constraints (including impedance, line length, matching and spacing) provided for high-speed differential interfaces (such as HDMI, USB) transforms the original experience-based signal integrity design into an engineering specification that can be followed, so that every motherboard in mass production can have consistent and excellent high-speed signal quality, which significantly improves product yield and performance consistency. 2. By disclosing the complete hardware interface and collaborative management logic of the embedded controller, this patent achieves a leap from passive power supply to intelligent management of the hardware platform, resulting in significant energy efficiency optimization and improved user experience. As the "nerve center" of the system, the embedded controller, based on the connection method disclosed in this solution, can collect data from multiple temperature sensors in real time and dynamically adjust fan speed, constructing an efficient thermal management closed loop. This ensures the system's heat dissipation requirements under high loads while reducing noise and power consumption under low loads. More importantly, its direct interaction with the power management network enables the platform to perform fine-grained peripheral power management (such as individually cutting off power to idle hard drives) and achieve rapid sleep wake-up and safe fault-protected shutdown. This intelligent control system, combining hardware and software, not only improves the overall energy efficiency ratio of the system and extends the lifespan of the equipment but also provides users with a more stable, quieter, and more responsive user experience. In summary, this patent provides a complete and reproducible "blueprint-style" solution, enabling those skilled in the art to efficiently and reliably replicate a high-performance, highly stable hardware platform, possessing extremely high industrial practical value. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the system framework of the present invention.

[0019] Figure 2 This is a schematic diagram of the electrical connection of the motherboard in this invention.

[0020] Figure 3 This is the power tree diagram of the present invention.

[0021] Figure 4 This is the LPDDR4 design guide and interface diagram of the present invention.

[0022] Figure 5 This is the HDMI design guide and related interface diagram of the present invention.

[0023] Figure 6 This is a schematic diagram of the embedded controller circuit of the present invention.

[0024] Figure 7 This is a schematic diagram of the overall system workflow of the present invention. Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0026] like Figures 1 to 7 The image shows a hardware motherboard based on the Pangu M900 processor.

[0027] The following will focus on the core technical solution of this invention, and, in conjunction with the original design materials, will provide a thorough and coherent explanation of the technical features protected by the claims.

[0028] I. Overall Implementation of Modular Hardware Architecture The hardware motherboard of this invention adopts a core-driven, module-decoupled design philosophy. The entire system uses the Pangu M900SoC as the main computing and control hub, around which five core functional modules are built: a power management module, a memory module, an expansion interface module, an embedded control module, and a printed circuit board as the carrier.

[0029] The Pangu M900SoC serves as the core, with its pin functions precisely defined and grouped for utilization. Through its high-speed SerDes interface, it connects PCIe devices to the network PHY; through a dedicated DDRPHY interface, it connects to low-power memory; and through abundant GPIO, I2C, UART, and other low-speed buses, it communicates with embedded controllers and other management chips. This architectural design is clearly reflected in the system block diagram of the original materials, providing a top-level plan for the overall motherboard functionality.

[0030] II. Specific Construction and Control Process of Precision Power Management System Power management is the cornerstone of system stability. This invention designs a power architecture with clear hierarchy, strict timing, and independent controllability. Its core lies in the collaboration between the "power tree" and the "embedded controller".

[0031] (a) Hardware construction of power network The power management module is not a simple single-stage conversion, but a complex system that includes input filtering, multi-stage DC / DC conversion, load switching network and monitoring feedback.

[0032] Input and Constant Voltage Domain: After the external DC power supply (e.g., +19V) is connected, it first passes through a filtering and overvoltage protection circuit, and then a high-efficiency switching regulator generates a constant +12V_AON voltage. This constant voltage, along with another independent +3V3_RTC_EC power supply, ensures that the embedded controller (EC) and part of the SoC's wake-up circuitry can still operate in the system's soft shutdown state, enabling fast startup and timed wake-up functions.

[0033] Core and memory voltage domains: This is the part with the highest power consumption and accuracy requirements. For the multiple core voltage domains of the SoC (such as DVDD_CPU and DVDD_GPU), high-current, programmable multi-phase or single-phase switching regulators are used for power supply. The enable pins of all core regulators are controlled by a set of synchronization signals (such as STANDBY_PWROFF). The memory voltage domains (VDDIO_DDR_1V2 and DDR_1V8_PLL) are at the next stage, generated by independent regulators, and their enable signal (CPU_DDR_EN) is logically later than the core voltage enable.

[0034] System and Peripheral Voltage Domains: The system's main I / O voltages (+3V3_S3, +5V0_S3) are generated by regulators controlled by the EC. Power supplies for peripheral devices (such as hard drives, USB hubs, and video switchers) are derived from the system I / O voltages through multiple load switches. The enable pin of each load switch (e.g., EC_HDD_PWR_EN, EC_LT_PWR_EN) is connected to an independent GPIO pin of the EC, enabling independent switching control of power to each peripheral device. This forms the hardware foundation for advanced power management features such as device hibernation and hot-swapping.

[0035] (ii) Control method for power-on / power-off timing The execution subject of this method is an embedded controller (EC), whose firmware logic and hardware connection together constitute a deterministic state machine.

[0036] Power-on procedure: Standby phase: Constant power is established, EC initialization is completed, and the system waits for power-on trigger (such as a button press or signal).

[0037] System basic power supply: EC sets its GPIO, outputs EC_5V0_EN and EC_3V3_EN signals, and enables +5V0_S3 and +3V3_S3.

[0038] Core and memory power supply: The EC (Engineer Control) notifies the SoC (System-on-Chips) via specific GPIOs or communication buses, or directly controls relevant circuits, to enable signal groups such as STANDBY_PWROFF, thus activating all core voltage regulators. After confirming that the core voltage is stable (or waiting for a fixed delay), the EC then enables the CPU_DDR_EN signal, activating the memory voltage domain. This sequence is crucial to preventing logical instability during system startup.

[0039] Power supply for peripheral devices: The EC sequentially enables the enable signals of each peripheral load switch to power on hard drives, expansion chips, etc.

[0040] Release Reset: After all power supplies are confirmed to be stable, the EC cancels the SoC reset signal, and the system enters the software boot phase.

[0041] Power-down and protection process: Normal power-down is the reverse of the above sequence. The EC continuously monitors the temperature through its connected temperature sensor network (multiple ADC channels connected to thermistors distributed in key locations on the motherboard). Once any part of the temperature exceeds the limit, the EC will immediately interrupt the current task and execute an emergency power-down sequence: first, cut off the power to all peripheral devices, then shut down the memory power, and finally shut down the core power, thereby achieving hardware protection.

[0042] III. Engineering Implementation of High-Performance Memory Subsystem Memory performance directly determines the overall system performance. The memory module implementation scheme of this invention emphasizes the complete engineering requirements from circuit design to physical layout.

[0043] Circuit Design: Strictly adhering to the LPDDR4 / 4X specification, the SoC's DDRPHY is connected to the memory chips in a point-to-point manner. The design includes a complete address / command bus, data bus (including differential data strobe DQS), and power network. Finely matched resistors are connected in series on the data lines near the SoC to improve signal quality.

[0044] Power integrity design: This is one of the core values ​​of the publicly available solution. The original material not only provides connectivity but also mandates in the memory design section: "The decoupling capacitor design of the demo board must be completely replicated." This means that implementers must use the exact same capacitor types, values, and packages as the reference design, and place them according to their precise physical layout. This requirement stems from the fact that at high frequencies, the impedance characteristics of the power distribution network are extremely sensitive to the placement and parasitic parameters of the decoupling capacitors. Directly replicating the proven solution is the most reliable way to ensure stable operation of the memory subsystem at the target high frequency, avoiding memory errors caused by power supply noise.

[0045] Layout and routing guidelines: The published layout recommendations require a “complete copy of the demo board”, which further ensures the integrity of the signal reference plane and the optimality of the signal line topology and timing length.

[0046] IV. Signal Integrity Guarantee Design for High-Speed ​​Expansion Interfaces To ensure the transmission quality of high-speed differential signals such as USB, HDMI, SATA, and PCIe, this invention establishes a set of specific and quantifiable physical layer design constraints, which are explained in detail using the HDMI interface as an example. These constraints can be directly applied to PCB design software: Impedance control: It is specified that differential signal lines must achieve a specific characteristic impedance (e.g., HDMI requires 100Ω).

[0047] Trace length constraints: Set maximum trace lengths for the transmit and receive channels respectively (e.g., HDMI TX < 127mm, RX < 102mm) to control signal attenuation and delay.

[0048] Internal timing matching: The length deviation between the positive and negative signal lines of the differential pair must be controlled within a very small range (e.g., ≤0.127mm) to ensure the common-mode rejection capability of the signal.

[0049] Inter-pair spacing requirements: It is stipulated that a minimum spacing (e.g., ≥0.38mm) must be maintained between adjacent differential pairs to suppress crosstalk.

[0050] Component selection constraints: The parasitic capacitance of interface protection devices must be below a threshold (e.g., <0.5pF) to prevent degradation of high-speed signal edges. These specific parameters and rules enable those skilled in the art to perform PCB layout and routing with unambiguity, ensuring signal integrity for all high-speed interfaces.

[0051] V. Hardware Resource Integration and Function Implementation of Embedded Control Module The embedded controller, as the system's "intelligent manager," has its hardware connection scheme fully disclosed.

[0052] Core selection and interface allocation: A microcontroller with an ARM Cortex-M4 core (such as the HC32F460) is used. Its specific pin functions are clearly assigned: Power control group: Multiple GPIO pins are defined as outputs and directly connected to the enable terminals of each regulator and load switch in the power tree.

[0053] Sensor input group: Multiple ADC input channels are respectively connected to temperature monitoring circuits in the CPU, system environment, chipset, SSD, etc.

[0054] Actuator output group: The PWM output pin is connected to the speed control terminals of the CPU and system fan; it is also equipped with a fan speed feedback input pin to form a closed-loop control.

[0055] Communication interface group: The UART interface is used to interact with the main processor; the I2C interface can be used to access other sensors.

[0056] System management function integration: Based on the above hardware connections, the EC firmware implements: Dynamic thermal management: Temperature is periodically collected, and the fan PWM duty cycle is dynamically adjusted through an algorithm.

[0057] Precise power control: Responds to power on / off commands and strictly executes the aforementioned power sequence.

[0058] Fault monitoring and handling: Monitor whether the fan speed is normal and whether the temperature exceeds the limit, and trigger the corresponding protection actions.

[0059] The technical solution provided by this invention discloses fully, clearly and unambiguously everything from system architecture design, power management logic, high-speed interface constraints, memory implementation details to embedded control interface.

[0060] In summary, the technical solution provided by this invention, through its modular architecture, executable power timing control method, mandatory high-speed physical design rules, and fully transparent system management interface, fully discloses the Pangu M900 high-performance hardware platform. Based on this specification, those skilled in the art can overcome the design blind spots and black-box obstacles described in the background art without inventive effort, successfully reproducing a stable and high-performance hardware motherboard. This fully complies with the requirements of patent law for specification drafting and provides solid support for all technical features in the claims.

[0061] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A hardware motherboard based on the Pangu M900 processor, characterized in that, include: The Pangu M900 main processor (U1) has multiple power domain pins, ground pins, high-speed interface pins, and general-purpose input / output pins. The power management module is connected to the power domain pins of the Pangu M900 main processor and is used to convert the external input voltage into multiple independent voltage domains required by the main processor and control the power-on and power-off timing of each voltage domain. The memory module is connected to the memory controller pins of the Pangu M900 main processor via an LPDDR4 / 4X interface; An expansion interface module is connected to the high-speed interface pins of the Pangu M900 main processor to provide peripheral device connectivity. The expansion interface module includes at least a storage interface expanded by a PCIe interface, multiple downstream USB ports expanded by a USB interface, and a network interface expanded by an RGMII interface. An embedded control module is connected to some general-purpose input / output pins of the Pangu M900 main processor, the power management module, and the power control terminal in the expansion interface module. It is used to monitor the system status, control the heat dissipation unit, respond to user input, and coordinate with the power management module to manage power timing. The layout and wiring of the power management module, memory module, expansion interface module and embedded control module follow the electrical design rules preset by the Pangu M900 main processor.

2. The hardware motherboard according to claim 1, characterized in that, The power management module includes: A multi-channel DC / DC converter is used to generate power rails with different voltage values ​​required by the main processor, memory module and expansion interface module; Multiple load switches, controlled by an enable signal from the embedded control module or the main processor, are used to control the switching of some power rails. The power-on sequence of the power rails follows the order from standby power, core power, to input / output power, and the power-off sequence is the reverse.

3. The hardware motherboard according to claim 1, characterized in that, The extended interface module includes: The SATA expansion submodule includes a SATA bridge chip, wherein the upstream port of the bridge chip is connected to the PCIe or SATA port of the main processor, and the downstream port is used to connect at least one SATA storage device. The USB hub submodule includes a USB 3.0 hub chip. The upstream port of the hub chip is connected to the USB port of the main processor, and the downstream port provides multiple independent USB 3.0 connection points. The power supply of each downstream port is independently controlled by the embedded control module. The video input switching submodule includes an HDMI switch chip and a microcontroller that communicates with it. The multiple input ports of the HDMI switch chip are used to receive external HDMI signals, and the output port is connected to the HDMIRX port of the main processor. The microcontroller receives switching commands and controls the HDMI switch chip through the I2C bus.

4. The hardware motherboard according to claim 1, characterized in that, The embedded control module includes a control unit with a microcontroller at its core. The microcontroller is connected to multiple negative temperature coefficient thermistors distributed in key locations on the motherboard via an ADC channel for temperature monitoring; and is connected to at least one fan via a PWM output channel for adjusting the fan speed according to the monitored temperature.

5. The hardware motherboard according to claim 1, characterized in that, It also includes a boot configuration circuit, which is connected to the BOOT_SEL0, BOOT_SEL1, and BOOT_SEL2 pins of the Pangu M900 main processor via pull-up or pull-down resistors, and is used to configure the boot source of the main processor as one of SPINOR Flash, eMMC, or UFS.

6. The hardware motherboard according to claim 1, characterized in that, The wiring between the memory module and the Pangu M900 main processor, including address command lines, data lines and differential clock lines, follows the physical design of the reference design board in terms of topology, line length matching and decoupling capacitor placement.

7. The hardware motherboard according to claim 1, characterized in that, The high-speed differential signal interfaces in the expansion interface module include USB, HDMI and SATA interfaces. The differential pairs meet the following design rules on the printed circuit board: routing on a specified signal layer, controlling characteristic impedance, limiting the maximum trace length, and maintaining the minimum spacing between differential pairs.

8. A power supply timing control method for a hardware motherboard as described in any one of claims 1-7, characterized in that, Includes the following steps: S1: After receiving an external power input, the embedded control module first enables the power conversion circuit in the standby voltage domain to supply power to itself and part of the standby circuit of the main processor. S2: After initialization, the embedded control module sends enable signals in sequence according to the system status to control multiple load switches and DC / DC converters in the power management module to establish the core voltage domain, memory voltage domain and peripheral interface voltage domain in a preset order. S3: After all power rails are stable and a power good signal is received, the embedded control module releases the reset signal of the main processor, and the main processor begins to load and execute code from the configured boot source; S4: When the system is powered off or enters a low-power state, the embedded control module or the main processor controls the power management module to turn off the power of each voltage domain in the reverse order of power-on or a specific power-off sequence.

9. The power supply timing control method according to claim 8, characterized in that, In step S2, the preset sequence includes at least: enabling the memory voltage domain after the core voltage domain has stabilized; and enabling the voltage domain that powers the expansion interface module after the main voltage domain has stabilized.

10. The power supply timing control method according to claim 8, characterized in that, The embedded control module continuously monitors the power good signal of each voltage domain and the temperature sensed by the negative temperature coefficient thermistor; when a power abnormality is detected or the temperature exceeds the threshold, the embedded control module performs a protective power-down operation or adjusts the fan speed.

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