Inverter parallel operation synchronization method

Abstract

The invention relates to an inverter parallel operation synchronization method and device, electronic equipment and a storage medium. The method comprises the following steps: based on a CAN parallel operation bus, according to a preset master-slave judgment logic, completing configuration within a half power frequency period, and updating the master-slave state of an inverter; the inverter host sends a power frequency signal to the power frequency bus, and the inverter slave receives the power frequency signal on the power frequency bus and performs secondary phase locking to realize power frequency synchronization; and the inverter host sends the periodic carrier signal to the PWM bus, and the inverter slave receives the periodic carrier signal on the PWM bus and performs time base adjustment to realize PWM synchronization. The logic host can be competed in the 1 / 4 power frequency period, the logic host decides in real time according to the parallel operation system and the state of the inverter, a certain inverter does not need to be used as a host, and non-centralized parallel operation is achieved in a logic master-slave mode. And high-precision and rapid synchronization of inverter information is realized by adopting a synchronization signal bus.

Description

Technical Field

[0001] This disclosure relates to the field of inverter technology, and more specifically, to an inverter parallel synchronization method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] In a parallel inverter system, if the phases and PWM signals of the inverters are not synchronized, circulating currents and high-frequency circulating currents will occur between the inverters. These circulating currents and high-frequency circulating currents can lead to parallel operation failure or even damage to the inverters. Therefore, to achieve parallel operation of multiple inverters, the phases and PWM signals of the inverters must be synchronized.

[0003] Currently, the main method for parallel synchronization of inverters in the market is master-slave synchronization. In this method, one inverter is designated as the master, and the rest are slaves. The master inverter generates a reference signal, and the slaves follow this signal. This synchronization method is simple but has low reliability and is susceptible to single-point-of-failure failure. A failure of the master inverter can cause the parallel system to collapse, preventing parallel operation among the remaining inverters. Furthermore, this method typically requires a host computer or other facilities to configure the inverters.

[0004] Therefore, one or more methods are needed to solve the above problems.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide an inverter parallel synchronization method, apparatus, electronic device, and computer-readable storage medium, thereby overcoming, at least to some extent, one or more problems caused by limitations and defects in related technologies.

[0007] According to one aspect of this disclosure, a method for parallel synchronization of inverters is provided, comprising:

[0008] Based on the CAN parallel bus, according to the preset master-slave judgment logic, the configuration and update of the inverter's master-slave status are completed within half a power frequency cycle;

[0009] The inverter master sends the power frequency signal to the power frequency bus, and the inverter slave receives the power frequency signal on the power frequency bus and performs two-stage phase locking to achieve power frequency synchronization.

[0010] The inverter master sends a periodic carrier signal to the PWM bus, and the inverter slave receives the periodic carrier signal on the PWM bus and performs time base adjustment to achieve PWM synchronization.

[0011] In one exemplary embodiment of this disclosure, the master-slave determination method further includes:

[0012] Step 101: Discretize the inverter address value;

[0013] Process 102 discretizes the inverter's operating state;

[0014] Judgment condition 101: When the inverter is working normally, judgment condition 102 is executed; when the inverter is faulty, execution process 103 is executed.

[0015] Process 103: Inverter exits parallel system;

[0016] If condition 102 is met, and the parallel system has two or more inverters operating in parallel, then proceed to condition 103. If the system has only one inverter, then proceed to process 104.

[0017] If the parallel system already has a logical host, execute the process 105; otherwise, execute the condition 104.

[0018] If the inverter's physical address is the smallest in the parallel system, then execute process 104; otherwise, execute process 105.

[0019] Step 104: Set this inverter as the logic master;

[0020] Step 105: Set this inverter as a logic slave.

[0021] In one exemplary embodiment of this disclosure, the method further includes:

[0022] The inverter's normal operation, fault, and shutdown states are discretized into a single byte and encoded to represent the inverter's operating state.

[0023] In one exemplary embodiment of this disclosure, the power frequency synchronization of the method further includes:

[0024] Judgment condition 201: If the local machine is the master, execute flow 201; if the local machine is the slave, execute flow 203.

[0025] Process 201: This inverter generates a power frequency signal based on the power frequency;

[0026] Process 202: This inverter sends the power frequency signal from Process 201 to the power frequency bus;

[0027] Process 203: This inverter generates a power frequency signal based on the phase information generated in process 208;

[0028] Process 204: This inverter is prohibited from sending the power frequency signal from Process 203 to the power frequency bus;

[0029] Procedure 205: This inverter receives the power frequency signal on the power frequency bus;

[0030] Process 206: This inverter converts the power frequency synchronization signal from Process 205 into phase information;

[0031] Process 207: The inverter performs a two-stage phase-locked loop;

[0032] Procedure 208: Phase is generated by phase locking according to procedure 207.

[0033] In one exemplary embodiment of this disclosure, the method further includes:

[0034] Each inverter converts the power frequency synchronization signal into phase information through the power frequency synchronization controller, and then uses a two-stage phase-locked loop algorithm to achieve phase synchronization of each inverter in the parallel system.

[0035] In one exemplary embodiment of this disclosure, the PWM synchronization of the method further includes:

[0036] Decision condition 301: If this machine is the master, execute flow 301; if this machine is the slave, execute flow 303.

[0037] Process 301: This inverter converts the PWM time base into a periodic carrier signal;

[0038] Process 302: This inverter sends the carrier signal from process 301 to the PWM bus;

[0039] Process 303: This inverter generates a carrier signal based on the time base signal generated in process 306;

[0040] Process 304: This inverter is prohibited from sending the carrier signal from Process 303 to the PWM bus;

[0041] Process 305: This inverter receives the carrier signal on the PWM bus;

[0042] Process 306: This inverter converts the carrier signal from process 305 into a time base signal;

[0043] Process 307: Adjust the time base of this inverter.

[0044] In one exemplary embodiment of this disclosure, the method further includes:

[0045] After the inverter's master-slave status is updated, the master is adjusted according to the inverter's physical address, and then the power frequency synchronization and PWM synchronization are re-executed.

[0046] In one aspect of this disclosure, an inverter parallel synchronization device is provided, comprising:

[0047] The CAN bus module is used to complete the configuration and update the master-slave status of the inverter within half a power frequency cycle based on the CAN parallel bus and according to the preset master-slave judgment logic.

[0048] The power frequency synchronization module is used by the inverter master to send the power frequency signal to the power frequency bus, and the inverter slave receives the power frequency signal on the power frequency bus and performs two-stage phase locking to achieve power frequency synchronization.

[0049] The PWM synchronization module is used by the inverter master to send the periodic carrier signal to the PWM bus, and the inverter slave to receive the periodic carrier signal on the PWM bus and perform time base adjustment to achieve PWM synchronization.

[0050] In one aspect of this disclosure, an electronic device is provided, comprising:

[0051] Processor; and

[0052] A memory storing computer-readable instructions that, when executed by the processor, implement the method according to any one of the preceding claims.

[0053] In one aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method according to any one of the preceding claims.

[0054] An exemplary embodiment of this disclosure provides a parallel synchronization method for inverters. The method includes: based on a CAN parallel bus, and according to preset master-slave judgment logic, completing the configuration and updating the master-slave status of the inverters within half a power frequency cycle; the inverter master sending a power frequency signal to the power frequency bus, and the inverter slave receiving the power frequency signal on the power frequency bus and performing secondary phase-locked loop (PLL) to achieve power frequency synchronization; the inverter master sending a periodic carrier signal to the PWM bus, and the inverter slave receiving the periodic carrier signal on the PWM bus and performing time base adjustment to achieve PWM synchronization. This disclosure enables the logical master to compete for a position within 1 / 4 of a power frequency cycle. The logical master is determined in real time based on the parallel system and the inverter's own status, without relying on a specific inverter as the master, achieving decentralized parallel operation using a logical master-slave approach. Simultaneously, the use of a bus-based synchronization signal ensures that each inverter receives the synchronization signal indiscriminately, thereby achieving high-precision and rapid synchronization of inverter information.

[0055] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0056] The above and other features and advantages of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0057] Figure 1 A flowchart of an inverter parallel synchronization method according to an exemplary embodiment of the present disclosure is shown;

[0058] Figure 2 A schematic diagram of inverter synchronization in a parallel system according to an exemplary embodiment of the present disclosure is shown.

[0059] Figure 3 A master-slave competition flowchart of an inverter parallel synchronization method according to an exemplary embodiment of the present disclosure is shown;

[0060] Figure 4 A power frequency synchronization flowchart of an inverter parallel synchronization method according to an exemplary embodiment of the present disclosure is shown;

[0061] Figure 5 A PWM synchronization flowchart of an inverter parallel synchronization method according to an exemplary embodiment of the present disclosure is shown;

[0062] Figure 6 A structural block diagram of an inverter parallel synchronization device according to an exemplary embodiment of the present disclosure is shown;

[0063] Figure 7 A block diagram of an electronic device according to an exemplary embodiment of the present disclosure is shown schematically;

[0064] Figure 8 The illustration shows a schematic diagram of a computer-readable storage medium according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0065] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0066] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, materials, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0067] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0068] In this example embodiment, a method for parallel synchronization of inverters is first provided; see reference. Figure 1 As shown, the inverter parallel synchronization method may include the following steps:

[0069] Step S110: Based on the CAN parallel bus, according to the preset master-slave judgment logic, the configuration and update of the inverter's master-slave status are completed within half a power frequency cycle.

[0070] In step S120, the inverter master sends the power frequency signal to the power frequency bus, and the inverter slave receives the power frequency signal on the power frequency bus and performs secondary phase-locking to achieve power frequency synchronization.

[0071] In step S130, the inverter master sends the periodic carrier signal to the PWM bus, and the inverter slave receives the periodic carrier signal on the PWM bus and performs time base adjustment to achieve PWM synchronization.

[0072] An exemplary embodiment of this disclosure provides a parallel synchronization method for inverters. The method includes: based on a CAN parallel bus, and according to preset master-slave judgment logic, completing the configuration and updating the master-slave status of the inverters within half a power frequency cycle; the inverter master sending a power frequency signal to the power frequency bus, and the inverter slave receiving the power frequency signal on the power frequency bus and performing secondary phase-locked loop (PLL) to achieve power frequency synchronization; the inverter master sending a periodic carrier signal to the PWM bus, and the inverter slave receiving the periodic carrier signal on the PWM bus and performing time base adjustment to achieve PWM synchronization. This disclosure enables the logical master to compete for a position within 1 / 4 of a power frequency cycle. The logical master is determined in real time based on the parallel system and the inverter's own status, without relying on a specific inverter as the master, achieving decentralized parallel operation using a logical master-slave approach. Simultaneously, the use of a bus-based synchronization signal ensures that each inverter receives the synchronization signal indiscriminately, thereby achieving high-precision and rapid synchronization of inverter information.

[0073] The following will further explain an inverter parallel synchronization method in this example embodiment.

[0074] Example 1:

[0075] In step S110, the configuration and update of the inverter's master-slave status can be completed within half a power frequency cycle based on the CAN parallel bus and according to the preset master-slave judgment logic.

[0076] In this example embodiment, the master-slave determination method further includes:

[0077] Step 101: Discretize the inverter address value;

[0078] Process 102 discretizes the inverter's operating state;

[0079] Judgment condition 101: When the inverter is working normally, judgment condition 102 is executed; when the inverter is faulty, execution process 103 is executed.

[0080] Process 103: Inverter exits parallel system;

[0081] If condition 102 is met, and the parallel system has two or more inverters operating in parallel, then proceed to condition 103. If the system has only one inverter, then proceed to process 104.

[0082] If the parallel system already has a logical host, execute the process 105; otherwise, execute the condition 104.

[0083] If the inverter's physical address is the smallest in the parallel system, then execute process 104; otherwise, execute process 105.

[0084] Step 104: Set this inverter as the logic master;

[0085] Step 105: Set this inverter as a logic slave.

[0086] In this example embodiment, the method further includes:

[0087] The inverter's normal operation, fault, and shutdown states are discretized into a single byte and encoded to represent the inverter's operating state.

[0088] In step S120, the inverter master can send the power frequency signal to the power frequency bus, and the inverter slave can receive the power frequency signal on the power frequency bus and perform secondary phase-locking to achieve power frequency synchronization.

[0089] In this example embodiment, the power frequency synchronization of the method further includes:

[0090] Judgment condition 201: If the local machine is the master, execute flow 201; if the local machine is the slave, execute flow 203.

[0091] Process 201: This inverter generates a power frequency signal based on the power frequency;

[0092] Process 202: This inverter sends the power frequency signal from Process 201 to the power frequency bus;

[0093] Process 203: This inverter generates a power frequency signal based on the phase information generated in process 208;

[0094] Process 204: This inverter is prohibited from sending the power frequency signal from Process 203 to the power frequency bus;

[0095] Procedure 205: This inverter receives the power frequency signal on the power frequency bus;

[0096] Process 206: This inverter converts the power frequency synchronization signal from Process 205 into phase information;

[0097] Process 207: The inverter performs a two-stage phase-locked loop;

[0098] Procedure 208: Phase is generated by phase locking according to procedure 207.

[0099] In this example embodiment, the method further includes:

[0100] Each inverter converts the power frequency synchronization signal into phase information through the power frequency synchronization controller, and then uses a two-stage phase-locked loop algorithm to achieve phase synchronization of each inverter in the parallel system.

[0101] In step S130, the inverter master can send the periodic carrier signal to the PWM bus, and the inverter slave can receive the periodic carrier signal on the PWM bus and perform time base adjustment to achieve PWM synchronization.

[0102] In this example embodiment, the PWM synchronization of the method further includes:

[0103] Decision condition 301: If this machine is the master, execute flow 301; if this machine is the slave, execute flow 303.

[0104] Process 301: This inverter converts the PWM time base into a periodic carrier signal;

[0105] Process 302: This inverter sends the carrier signal from process 301 to the PWM bus;

[0106] Process 303: This inverter generates a carrier signal based on the time base signal generated in process 306;

[0107] Process 304: This inverter is prohibited from sending the carrier signal from Process 303 to the power frequency bus;

[0108] Process 305: This inverter receives the power frequency signal on the power frequency bus;

[0109] Process 306: This inverter converts the carrier signal from process 305 into a time base signal;

[0110] Process 307: Adjust the time base of this inverter.

[0111] In this example embodiment, the method further includes:

[0112] After the inverter's master-slave status is updated, the master is adjusted according to the inverter's physical address, and then the power frequency synchronization and PWM synchronization are re-executed.

[0113] In this example embodiment, the inverter parallel system synchronization method disclosed herein can synchronize information such as phase, voltage amplitude, and frequency among inverters in the inverter parallel system, ensuring high-precision and high-reliability synchronous operation of the inverters. This invention employs a virtual logic master-slave method for synchronization. The parallel system can compete for the logical master within a quarter of the power frequency cycle. The logical master is determined in real time based on the state of the parallel system and the inverter itself, without relying on a specific inverter as the master, achieving decentralized parallel operation using a logical master-slave approach. Simultaneously, a synchronization signal bus is used, enabling each inverter to receive the synchronization signal indiscriminately, thereby achieving high-precision and rapid synchronization of inverter information. This invention avoids the risk of single-point failure and can achieve high-precision and rapid synchronization, greatly improving the reliability of the parallel system.

[0114] Example 2:

[0115] In the embodiments of this example, as Figure 2 The diagram shown is a block diagram of the logic system of the present invention. The system consists of a synchronous bus module and a synchronous control module.

[0116] The synchronization bus module is the system hardware component, consisting of a power frequency synchronization bus and power frequency synchronization circuit, a PWM synchronization bus and PWM synchronization circuit, a CAN bus and CAN communication circuit. The inverters participating in parallel operation are connected together through the synchronization bus module. The inverters obtain synchronization signals from the three buses, and the synchronization control module processes these signals to achieve synchronization of the parallel operation signals.

[0117] The synchronization control module is the system software component, consisting of a power frequency synchronization controller, a PWM synchronization controller, and a CAN communication controller. The synchronization control module generates and receives power frequency synchronization bus signals and PWM synchronization bus carrier signals, and implements CAN communication. The power frequency synchronization controller generates, receives, and processes power frequency synchronization signals to achieve phase synchronization of the parallel inverters. The PWM synchronization controller generates, receives, and processes PWM synchronization carrier signals to achieve high-frequency synchronization of the PWM waves of the parallel inverters. The CAN bus controller transmits and processes inverter status information to achieve synchronization of the status information of the parallel inverters.

[0118] In this example embodiment, the CAN communication controller and the CAN bus form a CAN parallel bus module. The CAN parallel bus module transmits inverter status information, including the inverter's physical address, operating status, and master / slave status. This module's function is to compete for the logical master and slave positions. To achieve real-time transmission of this information, it is discretized, using only one byte to transmit each piece of information. Through the CAN parallel bus module, seamless competition for the inverter's parallel operation logic master and slave positions can be achieved. If a logic failure occurs and the inverter exits the parallel operation, the remaining normally operating inverters in the parallel system can re-compete for the master position within less than a quarter of the power frequency cycle, thus achieving seamless switching of the system master and ensuring the normal operation of the parallel system. The master and slave positions are determined based on the inverter's physical address, inverter operating status, and parallel system status. The master / slave competition process in the parallel system is as follows: Figure 3 As shown, the description is as follows:

[0119] Step 101: Discretize the inverter address value;

[0120] Process 102 discretizes the inverter's operating states (normal operation, fault, shutdown);

[0121] Judgment condition 101: When the inverter is working normally, judgment condition 102 is executed; when the inverter is faulty, execution process 103 is executed.

[0122] Process 103: Inverter exits parallel system;

[0123] If condition 102 is met, and the parallel system has two or more inverters operating in parallel, then proceed to condition 103. If the system has only one inverter, then proceed to process 104.

[0124] If the parallel system already has a logical host, execute the process 105; otherwise, execute the condition 104.

[0125] If the physical address of this inverter is the smallest in the parallel system, then execute process 104; otherwise, execute process 105.

[0126] Step 104: Set this inverter as the logic master;

[0127] Step 105: Set this inverter as a logic slave.

[0128] In this example embodiment, the power frequency synchronization bus, power frequency synchronization circuit, and power frequency synchronization controller implement the power frequency synchronization function of the parallel system. The logic master inverter in the parallel system sends phase information to the power frequency bus via the power frequency synchronization circuit. Both the master and slave inverters receive the power frequency synchronization signal on the power frequency bus. Each inverter converts the power frequency synchronization signal into phase information through the power frequency synchronization controller, and through a two-stage phase-locked loop algorithm, the phase synchronization of each inverter in the parallel system is achieved. The workflow is as follows: Figure 4 As shown, the description is as follows:

[0129] Judgment condition 201: If the local machine is the master, execute flow 201; if the local machine is the slave, execute flow 203.

[0130] Process 201: This inverter generates a power frequency signal based on the power frequency;

[0131] Process 202: This inverter sends the power frequency signal from Process 201 to the power frequency bus;

[0132] Process 203: This inverter generates a power frequency signal based on the phase information generated in process 208;

[0133] Process 204: This inverter is prohibited from sending the power frequency signal from Process 203 to the power frequency bus;

[0134] Procedure 205: This inverter receives the power frequency signal on the power frequency bus;

[0135] Process 206: This inverter converts the power frequency synchronization signal from Process 205 into phase information;

[0136] Process 207: The inverter performs a two-stage phase-locked loop;

[0137] Procedure 208: Phase is generated by phase locking according to procedure 207.

[0138] In this example embodiment, a PWM synchronization bus, a PWM synchronization circuit, and a PWM synchronization controller implement PWM synchronization in the parallel system. The logic master in the parallel system converts PWM synchronization information into a periodic carrier signal via the PWM controller. The master inverter's PWM synchronization circuit sends the carrier signal to the PWM synchronization bus. The slave inverters in the parallel system receive the carrier signal from the bus, process it through the PWM synchronization controller, convert the carrier signal into a time base signal, and synchronize the slave inverter's PWM time base with the master's, thus achieving PWM synchronization between the inverters. The workflow is as follows: Figure 5 As shown, the description is as follows:

[0139] Decision condition 301: If this machine is the master, execute flow 301; if this machine is the slave, execute flow 303.

[0140] Process 301: This inverter converts the PWM time base into a periodic carrier signal;

[0141] Process 302: This inverter sends the carrier signal from process 301 to the PWM bus;

[0142] Process 303: This inverter generates a carrier signal based on the time base signal generated in process 306;

[0143] Process 304: This inverter is prohibited from sending the carrier signal from Process 303 to the power frequency bus;

[0144] Process 305: This inverter receives the power frequency signal on the power frequency bus;

[0145] Process 306: This inverter converts the carrier signal from process 305 into a time base signal;

[0146] Process 307: Adjust the time base of this inverter;

[0147] In this example embodiment, compared to other existing technologies, the present invention achieves the following beneficial effects: The parallel system requires no host computer or other facilities and can automatically achieve high-precision, high-speed synchronization of inverters. The status information of each inverter in the parallel system is discretized and can be transmitted in real time. The parallel system can compete to become the master inverter within a quarter of a power frequency cycle and exit parallel operation after the master inverter fails. The parallel system can seamlessly switch master inverters and is unaffected by master inverter failures, avoiding the risk of single-point failure and achieving highly reliable parallel synchronization. Each inverter in the parallel system receives the power frequency synchronization signal indiscriminately from the master, and a two-stage phase-locked loop method is used to achieve high-precision phase synchronization. The PWM synchronization signal is carrier-based, and the carrier signal is converted into a PWM time base signal to achieve high-precision PWM synchronization.

[0148] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0149] Furthermore, in this example embodiment, an inverter parallel synchronization device is also provided. (Refer to...) Figure 6 As shown, the inverter parallel synchronization device 200 may include: a CAN bus module 210, a power frequency synchronization module 220, and a PWM synchronization module 230. Wherein:

[0150] The CAN bus module 210 is used to complete the configuration and update the master-slave status of the inverter within half a power frequency cycle based on the CAN parallel bus and according to the preset master-slave judgment logic.

[0151] The power frequency synchronization module 220 is used by the inverter master to send the power frequency signal to the power frequency bus, and the inverter slave to receive the power frequency signal on the power frequency bus and perform two-stage phase locking to achieve power frequency synchronization.

[0152] The PWM synchronization module 230 is used by the inverter master to send the periodic carrier signal to the PWM bus, and the inverter slave to receive the periodic carrier signal on the PWM bus and perform time base adjustment to achieve PWM synchronization.

[0153] The specific details of each of the inverter parallel synchronization device modules mentioned above have been described in detail in the corresponding inverter parallel synchronization method, so they will not be repeated here.

[0154] It should be noted that although several modules or units of the inverter parallel synchronization device 200 have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0155] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0156] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented as entirely hardware embodiments, entirely software embodiments (including firmware, microcode, etc.), or embodiments combining hardware and software aspects, collectively referred to herein as “circuit,” “module,” or “system.”

[0157] The following reference Figure 7 To describe an electronic device 300 according to such an embodiment of the present invention. Figure 7 The electronic device 300 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0158] like Figure 7 As shown, the electronic device 300 is presented in the form of a general-purpose computing device. The components of the electronic device 300 may include, but are not limited to: at least one processing unit 310, at least one storage unit 320, a bus 330 connecting different system components (including storage unit 320 and processing unit 310), and a display unit 340.

[0159] The storage unit stores program code that can be executed by the processing unit 310, causing the processing unit 310 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 310 can perform actions such as... Figure 1 Steps S110 to S130 are shown in the diagram.

[0160] Storage unit 320 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 3201 and / or a cache memory unit 3202, and may further include a read-only memory unit (ROM) 3203.

[0161] Storage unit 320 may also include a program / utility 3204 having a set (at least one) of program modules 3205, such program modules 3205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0162] Bus 330 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0163] Electronic device 300 can also communicate with one or more external devices 370 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 300, and / or with any device that enables electronic device 300 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 350. Furthermore, electronic device 300 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 360. As shown, network adapter 360 communicates with other modules of electronic device 300 via bus 330. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 300, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0164] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0165] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section above.

[0166] refer to Figure 8 As shown, a program product 400 for implementing the above-described method according to an embodiment of the present invention is described. This product may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0167] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0168] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0169] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0170] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0171] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0172] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0173] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for parallel synchronization of inverters, characterized in that, The method includes: Based on the CAN parallel bus, according to the preset master-slave judgment logic, the configuration and update of the inverter's master-slave status are completed within half a power frequency cycle; The inverter master sends the power frequency signal to the power frequency bus, and the inverter slave receives the power frequency signal on the power frequency bus and performs two-stage phase locking to achieve power frequency synchronization. The inverter master sends a periodic carrier signal to the PWM bus, and the inverter slave receives the periodic carrier signal on the PWM bus and performs time base adjustment to achieve PWM synchronization.

2. The method as described in claim 1, characterized in that, The master-slave determination method further includes: Step 101: Discretize the inverter address value; Process 102 discretizes the inverter's operating state; Judgment condition 101: When the inverter is working normally, judgment condition 102 is executed; when the inverter is faulty, execution process 103 is executed. Process 103: Inverter exits parallel system; If condition 102 is met, and the parallel system has two or more inverters operating in parallel, then proceed to condition 103. If the system has only one inverter, then proceed to process 104. If the parallel system already has a logical host, execute the process 105; otherwise, execute the condition 104. If the inverter's physical address is the smallest in the parallel system, then execute process 104; otherwise, execute process 105. Step 104: Set this inverter as the logic master; Step 105: Set this inverter as a logic slave.

3. The method as described in claim 2, characterized in that, The method further includes: The inverter's normal operation, fault, and shutdown states are discretized into a single byte and encoded to represent the inverter's operating state.

4. The method as described in claim 1, characterized in that, The power frequency synchronization method further includes: Judgment condition 201: If the local machine is the master, execute flow 201; if the local machine is the slave, execute flow 203. Process 201: This inverter generates a power frequency signal based on the power frequency; Process 202: This inverter sends the power frequency signal from Process 201 to the power frequency bus; Process 203: This inverter generates a power frequency signal based on the phase information generated in process 208; Process 204: This inverter is prohibited from sending the power frequency signal from Process 203 to the power frequency bus; Procedure 205: This inverter receives the power frequency signal on the power frequency bus; Process 206: This inverter converts the power frequency synchronization signal from Process 205 into phase information; Process 207: The inverter performs a two-stage phase-locked loop; Procedure 208: Phase is generated by phase locking according to procedure 207.

5. The method as described in claim 4, characterized in that, The method further includes: Each inverter converts the power frequency synchronization signal into phase information through the power frequency synchronization controller, and then uses a two-stage phase-locked loop algorithm to achieve phase synchronization of each inverter in the parallel system.

6. The method as described in claim 1, characterized in that, The PWM synchronization method further includes: Decision condition 301: If this machine is the master, execute flow 301; if this machine is the slave, execute flow 303. Process 301: This inverter converts the PWM time base into a periodic carrier signal; Process 302: This inverter sends the carrier signal from process 301 to the PWM bus; Process 303: This inverter generates a carrier signal based on the time base signal generated in process 306; Process 304: This inverter is prohibited from sending the carrier signal from Process 303 to the PWM bus; Process 305: This inverter receives the carrier signal on the PWM bus; Process 306: This inverter converts the carrier signal from process 305 into a time base signal; Process 307: Adjust the time base of this inverter.

7. The method as described in claim 1, characterized in that, The method further includes: After the inverter's master-slave status is updated, the master is adjusted according to the inverter's physical address, and then the power frequency synchronization and PWM synchronization are re-executed.

8. An inverter parallel synchronization device, characterized in that, The device includes: The CAN bus module is used to complete the configuration and update the master-slave status of the inverter within half a power frequency cycle based on the CAN parallel bus and according to the preset master-slave judgment logic. The power frequency synchronization module is used by the inverter master to send the power frequency signal to the power frequency bus, and the inverter slave receives the power frequency signal on the power frequency bus and performs two-stage phase locking to achieve power frequency synchronization. The PWM synchronization module is used by the inverter master to send the periodic carrier signal to the PWM bus, and the inverter slave to receive the periodic carrier signal on the PWM bus and perform time base adjustment to achieve PWM synchronization.

9. An electronic device, characterized in that, include Processor; and A memory storing computer-readable instructions that, when executed by the processor, implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 7.

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