Control method and control circuit of three-level switch circuit and three-level switch circuit

Abstract

The invention discloses a control method and control circuit of a three-level switch circuit and the three-level switch circuit, and the method comprises the steps: controlling the three-level switch circuit to alternately enter a first state and a second state, and enabling a third state and / or a fourth state to exist between the first state and the second state, the duration time of the first state and the duration time of the second state are both equal to the fixed conduction time; wherein in the first state, the first switch tube and the third switch tube are both switched on, and the second switch tube and the fourth switch tube are both switched off; in the second state, the second switch tube and the fourth switch tube are both switched on, and the first switch tube and the third switch tube are both switched off; in the third state, the third switch tube and the fourth switch tube are both switched on, and the first switch tube and the second switch tube are both switched off; and in the fourth state, the first switch tube and the second switch tube are both switched on, and the third switch tube and the fourth switch tube are both switched off. The control method is simple, and voltage sharing of the flying capacitor can be automatically realized.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a control method, control circuit, and three-level switching circuit for a three-level switching circuit. Background Technology

[0002] Three-level switching circuits, such as three-level buck circuits, offer several advantages over traditional switching circuits: 1) Lower device withstand voltage; ideally, the withstand voltage of power devices is half the input voltage; 2) With the same inductor ripple frequency, the switching frequency and voltage are halved, reducing switching losses; 3) Lower inductor ripple, further reducing inductor losses. Due to these advantages, three-level switching circuits have attracted widespread attention in next-generation mobile device charging applications. Existing control schemes for three-level switching circuits primarily rely on average current control. However, average current control requires an additional voltage equalization loop to achieve voltage equalization of the flying capacitor (i.e., to achieve a flying capacitor voltage equal to Vin / 2), and suffers from low bandwidth and complex loop design. Therefore, a new control scheme is needed to achieve self-voltage equalization of the flying capacitor, saving on additional voltage equalization loops, reducing control costs, improving transient response, and increasing bandwidth. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a control method, control circuit and three-level switching circuit for a three-level switching circuit, so as to solve the technical problem of the need for an additional voltage equalization ring in the prior art.

[0004] The technical solution of this invention is to provide a control method for a three-level switching circuit. The three-level switching circuit includes a first to a fourth switching transistor connected in series between the input terminal and a reference ground; a flying capacitor connected between the common terminal of the first and second switching transistors and the common terminal of the third and fourth switching transistors; and a first inductor connected between the common node of the second and third switching transistors and the output terminal of the three-level switching circuit. The input terminal of the three-level switching circuit is used to receive an input voltage, and the output terminal is used to output an output voltage. The control method includes:

[0005] The three-level switching circuit is controlled to alternately enter the first state and the second state, and there is a third state and / or a fourth state between the first state and the second state. The duration of the first state and the duration of the second state are both equal to a fixed on time.

[0006] In this context, the first state corresponds to both the first and third switches being turned on, and both the second and fourth switches being turned off; the second state corresponds to both the second and fourth switches being turned on, and both the first and third switches being turned off; the third state corresponds to both the third and fourth switches being turned on, and both the first and second switches being turned off; and the fourth state corresponds to both the first and second switches being turned on, and both the third and fourth switches being turned off.

[0007] Optionally, the control method further includes:

[0008] The termination of the third state and / or the fourth state is controlled based on the comparison results of the sampled signal and the compensation signal representing the current flowing through the first inductor.

[0009] The compensation signal represents the error between the output feedback signal and the reference signal of the three-level switching circuit.

[0010] Optionally, the three-level switching circuit can be controlled using a first control mode; or,

[0011] The system determines whether the duty cycle of the three-level switch circuit is within a first threshold range. When the duty cycle is determined to be within the first threshold range, a second control mode is used to control the three-level switch circuit. When the duty cycle is determined to be outside the first threshold range, a first control mode is used to control the three-level switch circuit. The first threshold range includes 0.5.

[0012] In the first control mode, the three-level switch circuit includes the first state, the second state, and the third state, or includes the first state, the second state, and the fourth state; in the second control mode, the three-level switch circuit includes the first state, the second state, the third state, and the fourth state.

[0013] Optionally, when the first control mode is adopted,

[0014] The first state and the second state alternate one after another. There is a third state or a fourth state between adjacent first states and second states. At the end of the first state and the end of the second state, it is determined whether to enter the third state or the fourth state based on the comparison result of the sampling signal and the compensation signal representing the current flowing through the first inductor. The compensation signal represents the error between the output feedback signal and the reference signal of the three-level switching circuit.

[0015] Optionally, when the first control mode is adopted,

[0016] At the end of the first state, if the sampled signal is greater than the compensation signal, then the system enters the third state; if the sampled signal is less than the compensation signal, then the system enters the fourth state.

[0017] At the end of the second state, if the sampled signal is greater than the compensation signal, the system enters the third state; if the sampled signal is less than the compensation signal, the system enters the fourth state.

[0018] Optionally, when the first control mode is adopted,

[0019] When the third state is included, during the third state, if the sampled signal is detected to be less than or equal to the compensation signal, the third state is controlled to end.

[0020] When the fourth state is included, during the fourth state, if the sampled signal is detected to be greater than or equal to the compensation signal, the fourth state is controlled to end.

[0021] Optionally, when the first control mode is adopted,

[0022] When the third state is included, the third state is controlled to end after the minimum conduction time after entering the third state, and when the sampled signal is detected to be less than or equal to the compensation signal.

[0023] When the fourth state is included, the fourth state is controlled to end after the minimum conduction time after entering the fourth state, and when the sampled signal is detected to be greater than or equal to the compensation signal.

[0024] Optionally, in the second control mode, the first state and the second state alternate one after another, and the third state and the fourth state alternate one after another, with a third state and a fourth state existing between adjacent first states and second states.

[0025] Optionally, when the second control mode is adopted, the third state is entered after the first state ends and the second state ends, the fourth state is entered after the third state ends, and the first state or the second state is entered after the fourth state ends.

[0026] Optionally, when the second control mode is adopted, the fourth state is entered after the first state ends and the second state ends, the third state is entered after the fourth state ends, and the first state or the second state is entered after the third state ends.

[0027] Optionally, when the second control mode is adopted, the first state and the second state alternate in pairs, the third state and the fourth state alternate one after another, and there is a first state or a second state between adjacent third states and fourth states.

[0028] Optionally, when the second control mode is adopted,

[0029] There is a third state between adjacent first states and second states, and there is a fourth state between adjacent first states and second states; or,

[0030] There is a fourth state between adjacent first states and second states, a third state between adjacent first states and second states, and a third state between adjacent second states.

[0031] Optionally, when the second control mode is adopted, the duration of the third state and the duration of the fourth state are both greater than or equal to the minimum conduction time.

[0032] Optionally, when employing the second control mode, the termination of the third and fourth states is controlled based on the comparison result of the sampled signal and the compensation signal representing the current flowing through the first inductor, and the minimum conduction time.

[0033] After the minimum conduction time following the entry into the third state, and when the sampled signal is detected to be less than or equal to the compensation signal, the third state is controlled to end.

[0034] After the minimum conduction time following the entry into the fourth state, and when the sampled signal is detected to be greater than or equal to the compensation signal, the fourth state is controlled to end.

[0035] The compensation signal represents the error between the output feedback signal and the reference signal of the three-level switching circuit.

[0036] Optionally, the method for controlling the three-level switching circuit to alternately enter the first state and the second state includes:

[0037] The number of times the first state and the second state are counted to generate a counting signal. When it is necessary to enter the first state or the second state, the counting signal is used to control whether to enter the first state or the second state.

[0038] Optionally, the fixed on-time is proportional to the smaller of the difference between the input voltage and the output voltage and the output voltage, and inversely proportional to the input voltage.

[0039] Optionally, methods for controlling the duration of both the first state and the duration of the second state to be equal to a fixed on-time include:

[0040] During the first state, a first ramp voltage with a slope proportional to the input voltage is generated, and the end of the first state is controlled based on a comparison between the first ramp voltage and the first voltage.

[0041] During the second state, a second ramp voltage with a slope proportional to the input voltage is generated, and the end of the second state is controlled based on the comparison result of the second ramp voltage and the first voltage.

[0042] The first voltage is proportional to the smaller of the difference between the input voltage and the output voltage and the output voltage.

[0043] Optionally, when determining whether the duty cycle of the three-level switching circuit is within the first threshold range, calculations and comparisons are performed based on the input voltage and the output voltage to determine whether the duty cycle of the three-level switching circuit is within the first threshold range.

[0044] Optionally, when determining whether the duty cycle of the three-level switching circuit is within the first threshold range, a hysteresis is provided.

[0045] Secondly, the present invention also provides a control circuit for a three-level switching circuit, the three-level switching circuit including a first to a fourth switching transistor connected in series between the input terminal of the three-level switching circuit and a reference ground, a flying capacitor connected between the common terminal of the first and second switching transistors and the common terminal of the third and fourth switching transistors, and a first inductor connected between the common node of the second and third switching transistors and the output terminal of the three-level switching circuit, the input terminal of the three-level switching circuit being used to receive an input voltage, the output terminal being used to output an output voltage, and the control circuit being used to control the switching states of the first to the fourth switching transistors;

[0046] The control circuit controls the three-level switch circuit to alternately enter the first state and the second state. There is a third state and / or a fourth state between the first state and the second state. The duration of the first state and the duration of the second state are both equal to a fixed on time.

[0047] In this context, the first state corresponds to both the first and third switches being turned on, and both the second and fourth switches being turned off; the second state corresponds to both the second and fourth switches being turned on, and both the first and third switches being turned off; the third state corresponds to both the third and fourth switches being turned on, and both the first and second switches being turned off; and the fourth state corresponds to both the first and second switches being turned on, and both the third and fourth switches being turned off.

[0048] Optionally, the control circuit uses a first control mode to control the three-level switching circuit; or,

[0049] The system determines whether the duty cycle of the three-level switch circuit is within a first threshold range. When the duty cycle is determined to be within the first threshold range, a second control mode is used to control the three-level switch circuit. When the duty cycle is determined to be outside the first threshold range, a first control mode is used to control the three-level switch circuit. The first threshold range includes 0.5.

[0050] In the first control mode, the three-level switch circuit includes the first state, the second state, and the third state, or includes the first state, the second state, and the fourth state; in the second control mode, the three-level switch circuit includes the first state, the second state, the third state, and the fourth state.

[0051] Thirdly, the present invention also provides a three-level switching circuit, wherein the three-level switching circuit includes the control circuit described above, or employs the control method described above.

[0052] Compared with the prior art, the control method, control circuit, or three-level switching circuit of the present invention has the following advantages: The present invention controls the three-level switching circuit to alternately enter the first state and the second state, and there is a third state and / or a fourth state between the first state and the second state. The duration of the first state and the duration of the second state are both set to be equal to a fixed conduction time, so as to automatically realize the voltage equalization of the flying capacitor. No additional voltage equalization ring is required. The control logic is simple, the control cost is low, and it can also improve transient response and bandwidth. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of the circuit structure of the three-level switch circuit according to the first embodiment of the present invention;

[0054] Figure 2(a) is a schematic diagram of the working waveform of a three-level switching circuit in the first control mode according to an embodiment of the present invention;

[0055] Figure 2(b) is a schematic diagram of another working waveform of the three-level switching circuit in the first control mode according to an embodiment of the present invention;

[0056] Figure 3 This is a schematic diagram of a state switching of a three-level switch circuit according to a first embodiment of the present invention;

[0057] Figure 4 According to Figure 1 A schematic diagram of the circuit structure of an embodiment of the control circuit of a three-level switching circuit;

[0058] Figure 5 According to Figure 4 A schematic diagram of the circuit structure of one embodiment of the conduction time generation circuit;

[0059] Figure 6 According to Figure 5 A waveform diagram of the conduction time generation circuit;

[0060] Figure 7 This is a schematic diagram of the circuit structure of the three-level switch circuit according to the second embodiment of the present invention;

[0061] Figure 8 According to Figure 7 A schematic diagram of a control mode switching;

[0062] Figure 9(a) is a schematic diagram of the working waveform of the three-level switching circuit according to the second embodiment of the present invention in the first second control mode;

[0063] Figure 9(b) is a schematic diagram of another working waveform of the three-level switching circuit according to the second embodiment of the present invention in the first second control mode;

[0064] Figure 10 This is a schematic diagram of a state switching of a three-level switching circuit according to a second embodiment of the present invention;

[0065] Figure 11(a) is a schematic diagram of the working waveform of the three-level switching circuit according to the second embodiment of the present invention in a second control mode;

[0066] Figure 11(b) is a schematic diagram of another working waveform of the three-level switching circuit in the second control mode according to the second embodiment of the present invention;

[0067] Figure 12(a) is a schematic diagram of the working waveform of the three-level switching circuit according to the second embodiment of the present invention in the third second control mode;

[0068] Figure 12(b) is a schematic diagram of another working waveform of the three-level switching circuit according to the second embodiment of the present invention in the third second control mode;

[0069] Figure 13 According to Figure 7 A schematic diagram of the circuit structure of an embodiment of the control circuit of a three-level switching circuit;

[0070] Figure 14 According to Figure 13 A schematic diagram of the circuit structure of one embodiment of the mode selection circuit. Detailed Implementation

[0071] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the present invention.

[0072] To provide the public with a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the invention, but those skilled in the art can fully understand the invention without these details.

[0073] The invention is described in more detail below by way of example with reference to the accompanying drawings. It should be noted that the drawings are in a simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0074] refer to Figure 1 and Figure 7 The three-level switching circuit 10 / 20 in this application embodiment is a three-level buck circuit. The input terminal of the three-level switching circuit is used to receive the input voltage Vin, and the output terminal is used to output the output voltage Vo. It includes a first switch Q1 to a fourth switch Q4 connected in series between the input terminal of the three-level switching circuit and the reference ground, a flying capacitor Cfly connected between the common terminal of the first switch Q1 and the second switch Q2 and the common terminal of the third switch Q3 and the fourth switch Q4, and a first inductor L1 connected between the common node of the second switch Q2 and the third switch Q3 and the output terminal of the three-level switching circuit. It also includes a control circuit 100 / 200 for outputting a first drive signal DR1 to a fourth drive signal DR4 to control the switching state of the first switch Q1 to the fourth switch Q4 respectively. In this application, the common node of the second switch Q2 and the third switch Q3 is referred to as the switching node SW. Figures 2(a), 2(b), 9(a), 9(b), 11(a), 11(b), 12(a), and 12(b) show schematic diagrams of the operating waveforms of a three-level switching circuit according to an embodiment of this application, wherein Vcs represents the current I flowing through the first inductor. LThe sampling signal, ton represents the fixed conduction time, and State represents the working state (where state (13) represents that the first switch Q1 and the third switch Q3 are both on, and the second switch Q2 and the fourth switch Q4 are both off; state (24) represents that the second switch Q2 and the fourth switch Q4 are both on, and the first switch Q1 and the third switch Q3 are both off; state (34) represents that the third switch Q3 and the fourth switch Q4 are both on, and the first switch Q1 and the second switch Q2 are both off; state (12) represents that the first switch Q1 and the second switch Q2 are both on. (When the circuit is turned on, both the third switch Q3 and the fourth switch Q4 are turned off), DR1 represents the first drive signal, DR2 represents the second drive signal, Vsw represents the switching node voltage, Vin represents the input voltage, Vcfly represents the voltage across the flying capacitor, Icfly represents the current across the flying capacitor, Qcg represents the charging charge, and Qdcg represents the charging charge. Specifically, the area of ​​the flying capacitor current Icfly waveform during state (13) represents the charging charge Qcg, and the area of ​​the flying capacitor current Icfly waveform during state (24) represents the discharging charge Qdcg. The control method of this application embodiment includes: controlling the three-level switching circuit to alternately enter the first state and the second state, with a third state and / or a fourth state between the first state and the second state, and the duration of the first state and the duration of the second state being equal to the fixed on time; wherein, the first state corresponds to state (13), the second state corresponds to state (24), the third state corresponds to state (34), and the fourth state corresponds to state (12). It is readily understood that in the embodiments of this application, the flying capacitor Cfly is charged during the first state, and the magnitude of the charging current of the flying capacitor is equal to the magnitude of the current of the first inductor. During this period, Icfly = I L The flying capacitor discharges during the second state, and the magnitude of the discharge current of the flying capacitor is equal to the magnitude of the current of the first inductor. During this period, Icfly = -I L The voltage across the flying capacitor remains constant during the third and fourth states, where Icfly represents the current across the flying capacitor, I... L This represents the current in the first inductor.

[0075] Further, the method of controlling the duration of the first state and the duration of the second state to both be equal to a fixed on-time includes: controlling the first state to end when the duration of the first state reaches the fixed on-time, and controlling the second state to end when the duration of the second state reaches the fixed on-time. In some embodiments, the fixed on-time can be set to be proportional to the smaller of the difference between the input voltage and the output voltage and the output voltage, and inversely proportional to the input voltage. Even further, the method of controlling the duration of the first state and the duration of the second state to both be equal to the fixed on-time includes: generating a first ramp voltage with a slope proportional to the input voltage during the first state, and controlling the end of the first state based on a comparison of the first ramp voltage and the first voltage; generating a second ramp voltage with a slope proportional to the input voltage during the second state, and controlling the end of the second state based on a comparison of the second ramp voltage and the first voltage; the first voltage is proportional to the smaller of the difference between the input voltage and the output voltage and the output voltage. The control method in this application embodiment further includes: controlling the end of the third state and / or the fourth state based on the comparison result of a sampling signal representing the current flowing through the first inductor and a compensation signal; wherein the compensation signal represents the error between the output feedback signal and the reference signal of the three-level switching circuit. For example, the compensation signal may be a signal obtained by amplifying and compensating the error between the output feedback signal and the reference signal, and the output feedback signal may represent the output voltage, output current, or output power of the three-level switching circuit, etc.

[0076] Using the control method of this application embodiment, the three-level switching circuit is controlled to alternately enter the first state and the second state, and the duration of the first state and the duration of the second state are both equal to a fixed on-time. When the flying capacitor voltage deviates from Vin / 2, the slope of the current flowing through the first inductor during the first state and / or during the second state will change. That is, the slope of the charging current and the slope of the discharging current of the flying capacitor will change. Since the duration of the first state and the duration of the second state are both equal to the fixed on-time, the charging charge and the discharge charge of the flying capacitor will be unequal. Specifically, if the flying capacitor voltage is greater than Vin / 2, the change in the slope of the first inductor current will cause the charging charge of the flying capacitor to be less than the discharging charge, and the flying capacitor voltage will decrease; if the flying capacitor voltage is less than Vin / 2, the change in the slope of the first inductor current will cause the charging charge of the flying capacitor to be greater than the discharging charge, and the flying capacitor voltage will increase. Ultimately, the voltage equalization of the flying capacitor can be automatically achieved without the need to add an additional voltage equalization ring. The self-equalization mechanism of the flying capacitor will be described in detail later based on specific waveforms.

[0077] Figure 1The diagram shows a schematic of the circuit structure of the three-level switch circuit 10 according to the first embodiment of this application. This embodiment adopts a first control method, which includes controlling the three-level switch circuit using a first control mode. Refer to Figures 2(a), 2(b) and 2(c). Figure 3 Figures 2(a) and 2(b) show schematic diagrams of two possible operating waveforms of the three-level switching circuit in the first control mode according to an embodiment of the present invention. Figure 3 A schematic diagram of a state switching of a three-level switching circuit according to a first embodiment of the present invention is shown. In the first control mode, the three-level switching circuit includes state (13), state (24), and state (34), as shown in FIG2(a); or, it includes state (13), state (24), and state (12), as shown in FIG2(b). Specifically, in the first control mode, state (13) and state (24) alternate one after another, and there is a state (34) or a state (12) between adjacent states (13) and state (24). At the end time of state (13) and the end time of state (24), it is determined whether to enter state (34) or state (12) based on the comparison result of the sampled signal Vcs and the compensation signal Vc. Further, in one embodiment, in the first control mode, the following steps are executed cyclically:

[0078] S101: When the duration of state (13) reaches the fixed conduction time ton, the control state (13) ends.

[0079] S102: At the end of state (13), the sampled signal Vcs and the compensation signal Vc are compared;

[0080] If Vcs > Vc, then enter state (34). During state (34), when Vcs ≤ Vc is detected, control state (34) ends and enters state (24).

[0081] If Vcs < Vc, then enter state (12). During state (12), when Vcs ≥ Vc is detected, control state (12) ends and enters state (24).

[0082] S103: When the duration of state (24) reaches the fixed conduction time ton, the control state (24) ends.

[0083] S104: At the end of state (24), the sampled signal Vcs and the compensation signal Vc are compared;

[0084] If Vcs > Vc, then enter state (34). During state (34), when Vcs ≤ Vc is detected, control state (34) ends and enters state (13).

[0085] If Vcs < Vc, then enter state (12). During state (12), when Vcs ≥ Vc is detected, control state (12) ends and enters state (13).

[0086] In another embodiment, under the first control mode, the duration of state (34) and the duration of state (12) can also be set to be greater than or equal to the minimum conduction time. In this embodiment, the following steps are executed cyclically:

[0087] S201: When the duration of state (13) reaches the fixed conduction time ton, the control state (13) ends.

[0088] S202: At the end of state (13), the sampled signal Vcs and the compensation signal Vc are compared;

[0089] If Vcs > Vc, then enter state (34). After the minimum conduction time of entering state (34) and when Vcs ≤ Vc is detected, control state (34) ends and enters state (24).

[0090] If Vcs < Vc, then enter state (12). After the minimum conduction time of entering state (12) and when Vcs ≥ Vc is detected, control state (12) ends and enters state (24).

[0091] S203: When the duration of state (24) reaches the fixed conduction time ton, the control state (24) ends.

[0092] S204: At the end of state (24), the sampled signal Vcs and the compensation signal Vc are compared;

[0093] If Vcs > Vc, then enter state (34). After the minimum conduction time of entering state (34) and when Vcs ≤ Vc is detected, the control state (34) ends and enters state (13).

[0094] If Vcs < Vc, then enter state (12). After the minimum conduction time of entering state (12), and when Vcs ≥ Vc is detected, control state (12) ends and enters state (13).

[0095] Figure 3 This diagram illustrates a state switching scenario under the first control mode according to a first embodiment of the present invention, where the duration of state (34) and the duration of state (12) are both greater than or equal to the minimum conduction time. It is readily understood that when the minimum conduction time is not set, only the state switching needs to be... Figure 3The conditions t12≥tmin and t34≥tmin can be deleted. Here, t12 represents the duration of state (12), t34 represents the duration of state (34), and tmin represents the minimum conduction time.

[0096] Furthermore, the method for controlling the three-level switch circuit to alternately enter state (13) and state (24) includes: counting the number of times state (13) and state (24) are entered to generate a counting signal, and controlling whether to enter state (13) or state (24) according to the counting signal when it is necessary to enter state (13) or state (24). Figure 3 The example circuit for generating the counting signal CNT in the first control mode is given, along with an example of how to control whether to enter state (13) or state (24) based on the counting signal CNT. Figure 3 As shown, in one embodiment, the circuit that generates the counting signal CNT includes: a first buffer U1, a second buffer U2, and an RS flip-flop U3. The input of the first buffer U1 receives a signal S representing the entry state (13). ST(13) The output terminal is connected to the set terminal S of RS flip-flop U3, and the input terminal of the first buffer U1 receives the signal S representing the entry state (24). ST(24) The output terminal is connected to the reset terminal R of RS flip-flop U3. The output terminal Q of RS flip-flop U3 outputs the counting signal CNT. This circuit can realize that the counting signal CNT is counted as 1 every time state (13) is entered, and counted as 0 every time state (13) is entered. Correspondingly, at the end time of state (34) and at the end time of state (12), if CNT = 0, then state (13) is entered; if CNT = 1, then state (24) is entered, so as to realize the alternation of state (13) and state (24). It is easy to understand that in another embodiment, it can also be set as another output terminal of RS flip-flop U3. Output a counting signal CNT. Accordingly, at the end time of state (13) and at the end time of state (24), if CNT = 1, then enter state (13); if CNT = 0, then enter state (24).

[0097] Using the first control method described above, it is possible to achieve the following cycle of state (13), state (34), state (24), and state (34) when the duty cycle D < 0.5 (i.e., Vin > 2Vo), as shown in Figure 2(a); and the following cycle of state (13), state (12), state (24), and state (12) when the duty cycle D > 0.5 (i.e., Vin < 2Vo), as shown in Figure 2(b).

[0098] Refer to FIGS. 2(a) and 2(b) below to analyze the mechanism by which the first control method or the first control mode can achieve the self-voltage balancing of the flying capacitor. The solid waveforms in FIGS. 2(a) and 2(b) illustrate the waveforms under ideal conditions (Vcfly = Vin / 2). Under ideal conditions, Vcfly = Vin - Vcfly = Vin / 2. Therefore, the slope of the current of the first inductor is equal during state (13) and during state (24) (which is manifested as the slope of the sampling signal Vcs being equal during state (13) and during state (24) in FIGS. 2(a) and 2(b)). Also, since the current of the first inductor at the start of state (13) is equal to the current of the first inductor at the start of state (24) (which is manifested as Vcs being equal to Vc at the start of state (13) and at the start of state (24) in FIGS. 2(a) and 2(b)), and the duration of state (13) is equal to the duration of state (24), therefore, under ideal conditions, the charging charge Qcg of the flying capacitor is equal to the discharging charge Qdcg. The dashed waveforms of Vcs, Vsw, and Icfly in FIGS. 2(a) and 2(b) illustrate the waveforms when Vcfly > Vin / 2. During state (13), when Vcfly > Vin / 2, Vsw = Vin - Vcfly < Vin / 2, which causes the slope of the current of the first inductor to decrease relative to the ideal state. Specifically, in the waveform diagram, it is manifested as the slope of the sampling signal Vcs decreasing relative to the ideal situation. During state (24), when Vcfly > Vin / 2, Vsw = Vcfly > Vin / 2, which causes the slope of the current of the first inductor to increase relative to the ideal state. Specifically, in the waveform diagram, it is manifested as the slope of the sampling signal Vcs increasing relative to the ideal situation. Since the current of the first inductor at the start of state (13) is equal to the current of the first inductor at the start of state (24) (manifested as Vcs being equal to Vc at the start of state (13) and at the start of state (24)), and the duration of state (13) is equal to the duration of state (24), therefore, when Vcfly > Vin / 2, the charging charge Qcg of the flying capacitor is less than the discharging charge Qdcg, and the voltage of the flying capacitor decreases, and finally, the voltage balance of the flying capacitor (Vcfly = Vin / 2) can be automatically achieved. Those skilled in the art can fully understand the situation when Vcfly < Vin / 2 based on the above content, and it will not be elaborated here.It is easy to understand that Figure 2(a) shows the control state (34) ending when Vcs = Vc is detected during state (34); Figure 2(b) shows the control state (12) ending when Vcs = Vc is detected during state (12); in another embodiment, it can also be set that the control state (34) ends when Vcs < Vc is detected during state (34); and the control state (12) ends when Vcs < Vc is detected during state (12). Similarly, when the duty cycle D < 0.5, the current of the first inductor at the beginning of state (13) and state (24) is equal; and when D > 0.5, the current of the first inductor at the beginning of state (13) and state (24) is equal, and finally, the flying capacitor voltage equalization can also be automatically achieved.

[0099] Figure 4 It shows according to Figure 1 A schematic diagram of the circuit structure of a control circuit 100 for a three-level switching circuit is shown below. The control circuit 100 uses the first control method described above to control the three-level switching circuit 10. The control circuit 100 includes an on-time generation circuit 101, an error amplification and compensation circuit 102, a first comparison circuit 103, a PWM signal generation circuit 104, and a drive circuit 105. The on-time generation circuit 101 is used to generate a turn-off control signal TON_RST at the end of control state (13) and state (24), such that the duration of control state (13) and the duration of state (24) are both equal to a fixed on-time. The error amplification and compensation circuit 102 is used to amplify and compensate the output feedback signal and reference signal Vref that characterize the three-level switching circuit to generate a compensation signal. For example, in this embodiment, the output voltage Vo is used as the output feedback signal. It is easily understood that in another embodiment, the output voltage Vo can also be divided to generate the output feedback signal. The first comparator circuit 103 receives the compensation signal Vc at its first input terminal and the sampled signal Vcs at its second input terminal, and compares the sampled signal Vcs with the compensation signal Vc to output a first comparison signal. The PWM signal generation circuit 104 generates first control signals PWM1 to fourth control signals PWM4 corresponding to the first switching transistors Q1 to Q4 respectively, based on the aforementioned turn-off control signal TON_RST and the first comparison signal. The drive circuit generates first drive signals DR1 to fourth drive signals DR4 with driving capability based on the first control signals PWM1 to fourth control signals PWM4. Specifically, the PWM signal generation circuit 104 can be configured to implement, for example... Figure 3 The state transitions shown are not described in detail here.

[0100] In some embodiments, the conduction time generation circuit 101 controls the fixed conduction time to be proportional to the smaller of the difference between the input voltage and the output voltage and the output voltage, and inversely proportional to the input voltage. Figure 5 A schematic diagram of the circuit structure of one embodiment of the conduction time generation circuit 101 is shown. Figure 6 It shows according to Figure 5 A waveform diagram of the conduction time generation circuit 101 is shown below. (Reference) Figure 5 and Figure 6 The conduction time generation circuit 101 includes a first current source 1011, a first capacitor C1, a first switch S1, and a second comparator circuit 1012. The first current source 1011 is used to generate a first current proportional to the input voltage. The first capacitor C1 and the first switch S1 are connected in parallel and connected to the first current source at the first node. By controlling the conduction and turn-off of the first switch S1, the first current charges the first capacitor C1 during state (13) to generate a first ramp voltage at the first node. The first current charges the first capacitor C1 during state (24) to generate a first ramp voltage. A second ramp voltage is generated at the first node; the first input terminal of the second comparator circuit 1012 is connected to the first node to receive the first node voltage vp, the second input terminal receives the first voltage V1, and the output terminal is used to output a turn-off control signal TON_RST, wherein the first voltage V1 is proportional to the smaller of the difference between the input voltage and the output voltage and the output voltage, and the end of the control state (13) is controlled according to the comparison result of the first ramp voltage and the first voltage; the end of the control state (24) is controlled according to the comparison result of the second ramp voltage and the first voltage. Further, the conduction time generation circuit 101 also includes a first voltage generation circuit 1013 for generating the first voltage V1. For example, in one embodiment, the first voltage V1 is equal to the smaller of the difference between the input voltage and the output voltage and the output voltage. Specifically, the conduction time generation circuit 101 includes a first diode D1 and a second diode D2. The cathode of the first diode D1 receives the output voltage, the cathode of the second diode D2 receives the difference between the input voltage and the output voltage, and the anodes of the first diode D1 and the second diode D2 are connected to output the first voltage V1. Combination Figure 6 It can be seen that, as Figure 5 The slopes of the first and second ramp voltages generated by the on-time generation circuit 101 shown are both proportional to the first current, that is, both proportional to the input voltage Vin. Since the first voltage V1 is equal to the smaller of the difference between the input voltage and the output voltage and the output voltage, the on-time generation circuit 101 can control the fixed on-time ton to be inversely proportional to the input voltage Vin and proportional to the smaller of the difference between the input voltage and the output voltage and the output voltage.

[0101] In summary, the first embodiment of the present invention uses the first control method described above, namely the first control mode, to control the three-level switching circuit. State (13) and state (24) alternate. The duration of state (13) and the duration of state (24) are both equal to a fixed conduction time. At the end of state (13) and the end of state (24), the system determines whether to enter state (34) or state (12) based on the comparison result of the sampled signal Vcs and the compensation signal Vc. When state (34) is included, the system determines whether to enter state (34) or state (12) based on the comparison result of the sampled signal and the compensation signal. As a result, when the control state (34) ends, if state (12) is included, the control state (12) ends based on the comparison result of the sampled signal Vcs and the compensation signal Vc. Without detecting the duty cycle information, the control state (12) can be rotated according to the rule of state (13), state (34), state (24), state (34) when the duty cycle D < 0.5; and rotated according to the rule of state (13), state (12), state (24), state (12) when the duty cycle D > 0.5. The control logic is simple and can realize the self-equalization of the flying capacitor without the need for an additional equalization loop.

[0102] However, using the first control method described above, when the duty cycle D is around 0.5 (i.e., Vin approaches 2Vo), the current ripple of the first inductor decreases. Due to factors such as comparison delay or comparison accuracy, the comparison results of the sampled signal Vcs and the compensation signal Vc may be inaccurate at the end of state (13) and the end of state (24), making it difficult to predict the current waveform of the first inductor and potentially causing a large voltage variation range for the flying capacitor. Therefore, this application also proposes a second control method, which includes determining whether the duty cycle of the three-level switching circuit is within a first threshold range. When the duty cycle is determined to be within the first threshold range, a second control mode is used to control the three-level switching circuit; when the duty cycle is determined to be outside the first threshold range, the first control mode described above is used to control the three-level switching circuit. The first threshold range includes 0.5. For example, the first threshold range can be set to, for example, 0.48~0.52, 0.45~0.55, 0.42~0.58, etc. For details, please refer to... Figure 8When the duty cycle D is determined to be within the first threshold range, the mode switching signal Smode = 1 is set; when the duty cycle D is determined to be outside the first threshold range, the mode switching signal Smode = 0 is set. The first control mode or the second control mode is then controlled according to the mode switching signal Smode. Specifically, the first control mode is used when Smode = 0, and the second control mode is used when Smode = 1. Furthermore, to avoid repeated switching between the first and second control modes, a hysteresis Δd can be set when determining whether the duty cycle of the three-level switching circuit is within the first threshold range. In the second control mode, the three-level switching circuit includes states (13), (24), (34), and (12), which can be referred to for details. Figure 9(a) , 9(b) , Figure 10 Figures 11(a), 11(b), 12(a), and 12(b). Furthermore, in the second control mode, the duration of the third state and the duration of the fourth state are both set to be greater than or equal to the minimum on-time, so that the three-level switching circuit can include all four states, from the first to the fourth.

[0103] Figure 7 A schematic diagram of the circuit structure of a three-level switch circuit 20 according to a second embodiment of this application is shown. This embodiment employs the second control method described above. For example, in the second control method, calculations and comparisons are performed based on the input voltage Vin and the output voltage Vo to determine whether the duty cycle of the three-level switch circuit 20 is within a first threshold range. Therefore, the comparison... Figure 7 and Figure 1 In contrast Figure 1 Control circuit 100 in the middle, Figure 7 The control circuit 200 also receives the input voltage Vin.

[0104] The second control method described above will be introduced in detail below. Since the first control mode has been explained in detail above, it will not be repeated here. The second control mode will be introduced in detail below.

[0105] Figures 9(a) and 9(b) show schematic diagrams of two possible operating waveforms under the first second control mode, and Figures 11(a) and 11(b) show schematic diagrams of two possible operating waveforms under the second second control mode. It can be seen that in both the first and second second control modes, control states (13) and (24) alternate one after another, and there is a state (34) and a state (12) between adjacent states (13) and (24). Specifically, in the first second control mode, as shown in Figure 9(a) or Figure 9(b), the states (13), (34), (12), and (24) alternate according to the pattern; in the second second control mode, as shown in Figure 11(a) or Figure 11(b), the states (13), (12), (34), and (24) alternate according to the pattern.

[0106] Figure 10 This diagram illustrates a state switching configuration including the first control mode and the first second control mode according to a second embodiment of the present invention. Figure 10 In this context, Smode represents the mode switching signal mentioned above, and CNT represents the counting signal. The mode switching signal Smode has been introduced earlier and will not be repeated here. Figure 10 The counting signal CNT and the example circuit for generating the counting signal CNT are shown in the figure. Figure 3 The similarities in [the figures] will not be repeated here. Refer to Figures 9(a), 9(b), and [other figures]. Figure 10 For example, in one embodiment, under the first type of second control mode, the following steps are executed cyclically:

[0107] S301: When the duration of state (13) reaches the fixed conduction time ton, the control state (13) ends and enters state (34).

[0108] S302: After the minimum conduction time tmin after entering state (34), and when Vcs≤Vc is detected, control state (34) ends and enters state (12).

[0109] S303: After the minimum conduction time tmin after entering state (12), and when Vcs≥Vc is detected, control state (12) ends and enters state (24).

[0110] S304: When the duration of state (24) reaches the fixed conduction time ton, the control state (24) ends and enters state (34).

[0111] S305: After the minimum conduction time tmin after entering state (34), and when Vcs≤Vc is detected, control state (34) ends and enters state (12).

[0112] S306: After the minimum conduction time tmin after entering state (12), and when Vcs≥Vc is detected, control state (12) ends and state (13) is entered.

[0113] Wherein, Vcs is a sampled signal representing the current flowing through the first inductor, and Vc is a compensation signal.

[0114] After repeatedly executing steps S301 to S306, one of the working waveforms shown in Figure 9(a) and Figure 9(b) can be obtained. Figure 9(a) shows a schematic diagram of the working waveform of an embodiment in the first type of second control mode, where Vcs = Vc at the beginning of state (12) and the duration of state (12) is equal to the minimum conduction time tmin. Since the current of the first inductor is equal at the beginning of each state (12) (meaning that Vcs is equal to Vc at the beginning of each state (12)) and the duration is the minimum conduction time tmin, the current of the first inductor is the same at the beginning of state (13) and state (24), and the duration of state (13) and state (24) are also the same. (All are fixed conduction time ton). Based on the above analysis of the mechanism by which the first control method can achieve self-equalization of voltage of the flying capacitor, and based on the dashed waveforms of Vcs, Vsw, and Icfly in Figure 9(a), it can be seen that in the first second control mode, when the working waveform is as shown in Figure 9(a), the deviation of the flying capacitor voltage Vcfly will cause the slope of the current of the first inductor to change. If Vcfly>Vin / 2, the slope of the current of the first inductor decreases during state (13), and the slope of the current of the first inductor increases during state (24). The charging charge Qcg of the flying capacitor is less than the discharging charge Qdcg, and the voltage of the flying capacitor decreases. Finally, the voltage equalization of the flying capacitor can be automatically achieved. It is easy to understand that if Vcfly < Vin / 2, the current slope of the first inductor increases during state (13), the current slope of the inductor decreases in state (24), the charging charge Qcg of the flying capacitor is greater than the discharging charge Qdcg, the voltage of the flying capacitor increases, and eventually the voltage equalization of the flying capacitor can be automatically achieved. Therefore, in the first type of second control mode, when the working waveform is as shown in Figure 9(a), the self-equalization of the flying capacitor can be achieved. Figure 9(b) shows a schematic diagram of the working waveform of an embodiment in the first type of second control mode, where Vcs < Vc at the beginning of state (12) and state (12) ends when Vcs = Vc. Figure 9(b) only briefly shows the schematic diagram of the sampling signal Vcs and the working state State. Those skilled in the art can fully understand the waveforms of the corresponding first driving signal DR1, second driving signal DR2, switching node voltage Vsw, flying capacitor voltage Vcfly, and flying capacitor current Icfly based on the above description. As shown in Figure 9(b), the current of the first inductor is equal at the beginning of state (13) and state (24) (meaning that Vcs is equal to Vc at the beginning of state (13) and state (24)). The duration of state (13) and state (24) is also the same. Therefore, referring to the above analysis, it can be seen that in the first type of second control mode, when the working waveform is as shown in Figure 9(b), the self-equalization of voltage of the flying capacitor can also be achieved.Therefore, in the first type of second control mode, self-equalization of voltage across the flying capacitor can be achieved.

[0115] Comparing Figures 9(a), 9(b), 11(a), and 11(b), it can be seen that the second type of second control mode is basically the same as the first type of second control mode. The difference is that the order of state (34) and state (12) is reversed. The specific control process and the mechanism of self-equalization of the flying capacitor are similar to the first type of second control mode mentioned above, and will not be repeated here.

[0116] When the first second control mode or the second second control mode is adopted, the waveform of the current of the first inductor can be made to have a preset pattern when the duty cycle D is within the first threshold range; and since the state (13) and state (24) are set to alternate one by one, and the duration of state (13) and the duration of state (24) are both equal to the fixed conduction time ton, the charging and discharging of the flying capacitor can be controlled to alternate one by one, and the duration of each charging and each discharging is equal to the fixed conduction time ton, so that the voltage of the flying capacitor has a very small variation range.

[0117] Figures 12(a) and 12(b) show schematic diagrams of two possible operating waveforms under the third second control mode. In Figure 12(b), only the sampling signal Vcs and the operating state State are briefly shown. Those skilled in the art can fully understand the waveforms of the corresponding first drive signal DR1, second drive signal DR2, switch node voltage Vsw, and flying capacitor voltage Vcfly based on the above description. Referring to Figures 12(a) and 12(b), in the third second control mode, control states (13) and (24) alternate in pairs, and states (34) and (12) alternate one after another. There is one state (13) or one state (24) between adjacent states (34) and states (12). Specifically, in one embodiment, under the third second control mode, the situation shown in FIG12(a) may occur, where there is a state (34) between adjacent states (13) and (24), a state (12) between adjacent states (13) and (24), and a state (12) between adjacent states (24). In another embodiment, under the third second control mode, the situation shown in FIG12(b) may also occur, where there is a state (12) between adjacent states (13) and (24), a state (34) between adjacent states (13) and (24), and a state (34) between adjacent states (24). Those skilled in the art, based on the foregoing description, are fully capable of understanding the specific control process under the third second control mode, and will not elaborate further here. It should be noted that although this application only shows two working waveforms in the third second control mode where the duration of state (12) is equal to the minimum conduction time tmin and the sampling signal Vcs is above the compensation signal Vc, referring to Figures 9(a), 9(b), 11(a), and 11(b), as well as the previous introduction to the first and second second control modes, it is easy to know that in the third second control mode, there may also be two other working waveforms in the third second control mode where the duration of state (34) is equal to the minimum conduction time tmin and the sampling signal Vcs is below the compensation signal Vc.As shown in Figure 12(a), the flying capacitor discharges with a smaller discharge current during the first state (24) of the two adjacent states (24), and discharges with a larger discharge current during the second state (24); it also charges with a smaller charging current during the first state (13) of the two adjacent states (13), and charges with a larger charging current during the second state (13). Referring to the previous description, the magnitude of the smaller discharge current at the beginning of the first state (24) is equal to the magnitude of the smaller discharge current at the beginning of the first state (13), and the magnitude of the larger discharge current at the beginning of the second state (24) is equal to the magnitude of the smaller discharge current. The magnitude of the current is equal to the magnitude of the larger charging current at the beginning of the second state (13), and the duration of both state (13) and state (24) is equal to the fixed on-time ton. Therefore, ideally, the total charging charge of the flying capacitor during the two adjacent states (13) is equal to the total discharging charge during the two adjacent states (24). Referring to the analysis of the mechanism by which the first control mode and the first second control mode can achieve self-equalization of voltage of the flying capacitor, it can be seen that in the third second control mode, when the working waveform is the waveform shown in Figure 12(a), self-equalization of voltage of the flying capacitor can be achieved. Comparing Figures 12(a) and 12(b), it can be seen that the sampling signal Vcs waveform shown in Figure 12(b) is similar to the sampling signal Vcs waveform in Figure 12(a). The difference lies in the relative positions of states (34) and (12). When the working waveform is as shown in Figure 12(b), the mechanism for achieving self-equalization of voltage across the flying capacitor is similar to that when the working waveform is as shown in Figure 12(a), and will not be elaborated further here. Therefore, in the third second control mode, self-equalization of voltage across the flying capacitor can be achieved.

[0118] When the third second control mode is adopted, the waveform of the current of the first inductor has a preset pattern when the duty cycle D is within the first threshold range. Furthermore, there is no direct switching process from state (34) to state (12), nor is there a direct switching process from state (12) to state (34). Therefore, there is no need to control the simultaneous switching of the first to fourth switching transistors. Compared to the first and second second control modes, the system switching losses are lower when the third second control mode is adopted.

[0119] In summary, when the three-level switching circuit is controlled by any of the first to third second control modes, the waveform of the current in the first inductor has a preset pattern when the duty cycle D is within the first threshold range, and self-equalization of the flying capacitor can be achieved. Furthermore, as previously mentioned, controlling the three-level switching circuit using the first control mode can achieve self-equalization of the flying capacitor. Therefore, the second embodiment of this invention, employing the second control method of this application, can achieve self-equalization of the flying capacitor when the duty cycle is any value, without the need for an additional voltage equalization ring.

[0120] Figure 13 It shows according to Figure 7 A schematic diagram of the circuit structure of a control circuit 200 for a three-level switching circuit is shown below. The control circuit 200 uses the second control method described above to control the three-level switching circuit 20. The control circuit 200 is basically the same as the control circuit 100, and will not be described again here. The difference is that the control circuit 200 also includes a mode selection circuit 206. The mode selection circuit 206 is used to generate the mode switching signal Smode described above. The PWM signal generation circuit 204 generates first control signals PWM1 to fourth control signals PWM4 corresponding to the first switching transistors Q1 to Q4, respectively, based on the mode switching signal Smode, the turn-off control signal TON_RST, and the first comparison signal. For example, in one embodiment, the PWM signal generation circuit 204 is used to implement the following... Figure 10 The state transition is shown.

[0121] Figure 14 A schematic diagram of the circuit structure of an embodiment of the mode selection circuit 206 is shown. The mode selection circuit 206 performs calculations and comparisons based on the input voltage Vin and the output voltage Vo to output a mode switching signal Smode. For example, in one embodiment, the mode selection circuit 206 includes a first proportional circuit 2061, a second proportional circuit 2062, a third comparison circuit 2063, a fourth comparison circuit 2064, and an AND gate 2065. The first proportional circuit 2061 receives the input voltage Vin and outputs a signal k proportional to the input voltage Vin in a first ratio. VH The upper limit voltage VH; the second proportional circuit 2062 receives the input voltage Vin and outputs a voltage k proportional to the input voltage Vin in a second ratio. VLThe lower limit voltage VL; the positive input terminal of the third comparator circuit 2064 receives the upper limit voltage VH, and the negative input terminal receives the output voltage Vo; the positive input terminal of the fourth comparator circuit 2064 receives the output voltage Vo, and the negative input terminal receives the lower limit voltage LV; the output terminals of the third comparator circuit 2063 and the fourth comparator circuit 2064 are respectively connected to the two input terminals of the AND gate 2065; the output terminal of the AND gate 2065 outputs the mode switching signal Smode. Wherein, the first proportional k... VH Second ratio k VL The settings are made according to the requirements of the first threshold range mentioned above. In one embodiment, at least one of the third comparison circuit 2063 and the fourth comparison circuit 2064 may be a hysteresis comparison circuit to provide hysteresis when determining whether the duty cycle of the three-level switching circuit is within the first threshold range.

[0122] It should be noted that although Figures 2(a), 2(b), 9(a), 9(b), 11(a), 11(b), 12(a), and 12(b) all show schematic diagrams of the operating waveforms of a three-level switching circuit in CCM (Continuous On-Mode), the control method and control circuit disclosed in this application are not limited to three-level switching circuits operating in CCM (Continuous On-Mode), but are also applicable to three-level switching circuits operating in DCM (Discontinuous On-Mode). It is readily understood that when a three-level switching circuit operates in DCM, it also includes other operating states where all four switching transistors from the first to the fourth are turned off and / or three of them are turned off. Those skilled in the art can fully deduce the control process and operating waveforms in DCM based on the above description, and will not be elaborated upon here.

[0123] In summary, the embodiments of the present invention control the three-level switching circuit to alternately enter the first state and the second state, with a third state and / or a fourth state between the first state and the second state. The duration of the first state and the duration of the second state are both set to be equal to the fixed on time, so as to achieve self-equalization of the flying capacitor. No additional voltage equalization ring is required, the control logic is simple, the control cost is low, and it can also improve transient response and bandwidth.

[0124] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A control method for a three-level switching circuit, the three-level switching circuit comprising a first to a fourth switching transistor connected in series between the input terminal and a reference ground, a flying capacitor connected between the common terminal of the first and second switching transistors and the common terminal of the third and fourth switching transistors, and a first inductor connected between the common node of the second and third switching transistors and the output terminal of the three-level switching circuit, wherein the input terminal of the three-level switching circuit is used to receive an input voltage and the output terminal is used to output an output voltage, characterized in that... The control method includes: The three-level switching circuit is controlled to alternately enter the first state and the second state, and there is a third state and / or a fourth state between the first state and the second state. The duration of the first state and the duration of the second state are both equal to a fixed on time. In this context, the first state corresponds to both the first and third switches being turned on, and both the second and fourth switches being turned off; the second state corresponds to both the second and fourth switches being turned on, and both the first and third switches being turned off; the third state corresponds to both the third and fourth switches being turned on, and both the first and second switches being turned off; and the fourth state corresponds to both the first and second switches being turned on, and both the third and fourth switches being turned off.

2. The control method according to claim 1, characterized in that, The control method further includes: The termination of the third state and / or the fourth state is controlled based on the comparison results of the sampled signal and the compensation signal representing the current flowing through the first inductor. The compensation signal represents the error between the output feedback signal and the reference signal of the three-level switching circuit.

3. The control method according to claim 1, characterized in that, The three-level switching circuit is controlled using the first control mode; or... Determine whether the duty cycle of the three-level switch circuit is within the first threshold range. When it is determined that the duty cycle is within the first threshold range, use the second control mode to control the three-level switch circuit. When it is determined that the duty cycle is outside the first threshold range, the three-level switch circuit is controlled by the first control mode, and the first threshold range includes 0.

5. In the first control mode, the three-level switch circuit includes the first state, the second state, and the third state, or includes the first state, the second state, and the fourth state; in the second control mode, the three-level switch circuit includes the first state, the second state, the third state, and the fourth state.

4. The control method according to claim 3, characterized in that, When the first control mode is used The first state and the second state alternate one after another. There is a third state or a fourth state between adjacent first states and second states. At the end of the first state and the end of the second state, it is determined whether to enter the third state or the fourth state based on the comparison result of the sampling signal and the compensation signal representing the current flowing through the first inductor. The compensation signal represents the error between the output feedback signal and the reference signal of the three-level switching circuit.

5. The control method according to claim 4, characterized in that, When the first control mode is used At the end of the first state, if the sampled signal is greater than the compensation signal, then the system enters the third state; if the sampled signal is less than the compensation signal, then the system enters the fourth state. At the end of the second state, if the sampled signal is greater than the compensation signal, the system enters the third state; if the sampled signal is less than the compensation signal, the system enters the fourth state.

6. The control method according to claim 4 or 5, characterized in that, When the first control mode is used When the third state is included, during the third state, if the sampled signal is detected to be less than or equal to the compensation signal, the third state is controlled to end. When the fourth state is included, during the fourth state, if the sampled signal is detected to be greater than or equal to the compensation signal, the fourth state is controlled to end.

7. The control method according to claim 4 or 5, characterized in that, When the first control mode is used When the third state is included, the third state is controlled to end after the minimum conduction time after entering the third state, and when the sampled signal is detected to be less than or equal to the compensation signal. When the fourth state is included, the fourth state is controlled to end after the minimum conduction time after entering the fourth state, and when the sampled signal is detected to be greater than or equal to the compensation signal.

8. The control method according to claim 3, characterized in that, In the second control mode, the first state and the second state alternate one after another, and the third state and the fourth state alternate one after another, with a third state and a fourth state existing between adjacent first states and second states.

9. The control method according to claim 8, characterized in that, When the second control mode is adopted, the system enters the third state after the first state ends and the second state ends, enters the fourth state after the third state ends, and enters the first state or the second state after the fourth state ends.

10. The control method according to claim 8, characterized in that, When the second control mode is adopted, the system enters the fourth state after the first state ends and the second state ends, enters the third state after the fourth state ends, and enters the first state or the second state after the third state ends.

11. The control method according to claim 3, characterized in that, When the second control mode is adopted, the first state and the second state alternate in pairs, the third state and the fourth state alternate one after another, and there is a first state or a second state between adjacent third states and fourth states.

12. The control method according to claim 11, characterized in that, When the second control mode is used There is a third state between adjacent first states and second states, and there is a fourth state between adjacent first states and second states; or, There is a fourth state between adjacent first states and second states, there is a third state between adjacent first states and first states, and there is a third state between adjacent second states and second states.

13. The control method according to any one of claims 3, 8-12, characterized in that, When the second control mode is used, the duration of the third state and the duration of the fourth state are both greater than or equal to the minimum conduction time.

14. The control method according to claim 13, characterized in that, When the second control mode is adopted, the termination of the third state and the fourth state is controlled based on the comparison result of the sampled signal and the compensation signal representing the current flowing through the first inductor and the minimum conduction time. After the minimum conduction time following the entry into the third state, and when the sampled signal is detected to be less than or equal to the compensation signal, the third state is controlled to end. After the minimum conduction time following the entry into the fourth state, and when the sampled signal is detected to be greater than or equal to the compensation signal, the fourth state is controlled to end. The compensation signal represents the error between the output feedback signal and the reference signal of the three-level switching circuit.

15. The control method according to claim 1, characterized in that, The method for controlling the three-level switching circuit to alternately enter the first state and the second state includes: The number of times the first state and the second state are counted to generate a counting signal. When it is necessary to enter the first state or the second state, the counting signal is used to control whether to enter the first state or the second state.

16. The control method according to claim 1, characterized in that, The fixed on-time is proportional to the smaller of the difference between the input voltage and the output voltage and the output voltage, and inversely proportional to the input voltage.

17. The control method according to claim 16, characterized in that, Methods for controlling the duration of both the first and second states to be equal to a fixed on-time include: During the first state, a first ramp voltage with a slope proportional to the input voltage is generated, and the end of the first state is controlled based on a comparison between the first ramp voltage and the first voltage. During the second state, a second ramp voltage with a slope proportional to the input voltage is generated, and the end of the second state is controlled based on the comparison result of the second ramp voltage and the first voltage. The first voltage is proportional to the smaller of the difference between the input voltage and the output voltage and the output voltage.

18. The control method according to claim 3, characterized in that, When determining whether the duty cycle of the three-level switching circuit is within the first threshold range, calculations and comparisons are performed based on the input voltage and the output voltage to determine whether the duty cycle of the three-level switching circuit is within the first threshold range.

19. The control method according to claim 3 or 18, characterized in that, Hysteresis is provided when determining whether the duty cycle of the three-level switching circuit is within the first threshold range.

20. A control circuit for a three-level switching circuit, the three-level switching circuit comprising a first to a fourth switching transistor connected in series between the input terminal and a reference ground, a flying capacitor connected between the common terminal of the first and second switching transistors and the common terminal of the third and fourth switching transistors, and a first inductor connected between the common node of the second and third switching transistors and the output terminal of the three-level switching circuit, the input terminal of the three-level switching circuit being used to receive an input voltage, the output terminal being used to output an output voltage, and the control circuit being used to control the switching states of the first to the fourth switching transistors, characterized in that... The control circuit controls the three-level switch circuit to alternately enter the first state and the second state. There is a third state and / or a fourth state between the first state and the second state. The duration of the first state and the duration of the second state are both equal to a fixed on time. In this context, the first state corresponds to both the first and third switches being turned on, and both the second and fourth switches being turned off; the second state corresponds to both the second and fourth switches being turned on, and both the first and third switches being turned off; the third state corresponds to both the third and fourth switches being turned on, and both the first and second switches being turned off; and the fourth state corresponds to both the first and second switches being turned on, and both the third and fourth switches being turned off.

21. The control circuit according to claim 20, characterized in that, The control circuit uses a first control mode to control the three-level switching circuit; or... Determine whether the duty cycle of the three-level switch circuit is within the first threshold range. When it is determined that the duty cycle is within the first threshold range, use the second control mode to control the three-level switch circuit. When it is determined that the duty cycle is outside the first threshold range, the three-level switch circuit is controlled by the first control mode, and the first threshold range includes 0.

5. In the first control mode, the three-level switch circuit includes the first state, the second state, and the third state, or includes the first state, the second state, and the fourth state; in the second control mode, the three-level switch circuit includes the first state, the second state, the third state, and the fourth state.

22. A three-level switching circuit, characterized in that, It includes the control circuit as described in claim 20 or 21, or employs the control method as described in any one of claims 1 to 19.

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