Multi-heterogeneous VRB network system architecture based on hybrid chip and communication method

Abstract

The embodiment of the invention provides a multi-heterogeneous VRB network system architecture and communication method based on a hybrid chip, the architecture comprises a first superior network architecture and a second superior network architecture, the first superior network architecture is in communication connection with the second superior network architecture, the first superior network architecture belongs to a first region, and the second superior network architecture belongs to a second region. The second superior network architecture belongs to a second region; the areas to which the first lower-level network architecture belongs are all located in the range of the first region, and the first lower-level network architecture is in communication connection with the first upper-level network architecture and the second upper-level network architecture; and at least one second subordinate network architecture, the areas to which the second subordinate network architectures belong are located in the range of the second area, and the second subordinate network architectures are in communication connection with the first superior network architectures and the second superior network architectures. Therefore, according to the embodiment of the invention, the problem that a traditional tree-like hierarchical network architecture cannot adapt to a cross-regional communication scene with high real-time performance can be solved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a multi-heterogeneous VRB network architecture and communication method based on hybrid chips. Background Technology

[0002] With the rapid development of communication technology, multi-level, cross-regional network architectures have become a key infrastructure supporting large-scale heterogeneous network collaboration. Traditional network architectures typically adopt a hierarchical topology, dividing the network into multiple geographical regions. Each region deploys an independent upper-level network architecture (such as a core routing node cluster) and sets up several lower-level network architectures (such as edge access nodes or subnet clusters) within its geographical scope, thus forming a regionally autonomous tree-like hierarchical system.

[0003] However, with the rapid development of cross-regional collaborative computing, wide-area IoT, and cloud-edge-device integrated applications, high real-time business scenarios are gradually increasing. The aforementioned tree-structured hierarchical network architecture often involves multi-hop transmission paths and significant transmission latency during cross-regional communication. Therefore, the traditional tree-structured hierarchical network architecture is unsuitable for high real-time cross-regional communication scenarios. Summary of the Invention

[0004] The embodiments of this application provide a multi-heterogeneous VRB network architecture and communication method based on hybrid chips to solve the problem that traditional tree-structured hierarchical network architectures cannot adapt to high real-time cross-regional communication scenarios.

[0005] In a first aspect, embodiments of this application provide a multi-heterogeneous VRB network architecture based on a hybrid chip, the multi-heterogeneous VRB network architecture based on a hybrid chip includes: A first superior network architecture and a second superior network architecture, wherein the first superior network architecture and the second superior network architecture are communicatively connected, the first superior network architecture belongs to a first region, and the second superior network architecture belongs to a second region; At least one first subordinate network architecture, different first subordinate network architectures belong to different regions, and the regions to which the first subordinate network architectures belong are all within the scope of the first region. The first subordinate network architecture is communicatively connected to both the first superior network architecture and the second superior network architecture. At least one second-level network architecture, different second-level network architectures belong to different regions, and the regions to which the second-level network architectures belong are all within the scope of the second region. The second-level network architectures are communicatively connected to both the first-level network architecture and the second-level network architecture.

[0006] Secondly, embodiments of this application provide a communication method applied to the above-described heterogeneous VRB network architecture based on a hybrid chip, the method comprising: When the destination address of the data packet to be sent by the first target lower-level network architecture corresponds to the second target lower-level network architecture, the first target lower-level network architecture sends the data packet to the target upper-level network architecture. Here, the first target lower-level network architecture is one of the first lower-level network architectures, the second target lower-level network architecture is one of the second lower-level network architectures, and the target upper-level network architecture is an upper-level network architecture that is communicatively connected to the first target lower-level network architecture and the second target lower-level network architecture. The data packet is sent to the second target lower-level network architecture through the target upper-level network architecture.

[0007] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program that causes a processor to execute the communication method described in the first aspect.

[0008] In some embodiments of this application, a multi-heterogeneous VRB network architecture based on a hybrid chip is provided. This architecture includes a first upper-level network architecture and a second upper-level network architecture, as well as at least one first lower-level network architecture and at least one second lower-level network architecture. The first upper-level network architecture is communicatively connected to the second upper-level network architecture, which belongs to a first region, while the second upper-level network architecture belongs to a second region. Different first lower-level network architectures belong to different regions, and all regions to which the first lower-level network architectures belong are within the first region. The first lower-level network architectures are communicatively connected to both the first and second upper-level network architectures. Similarly, different second lower-level network architectures belong to different regions, and all regions to which the second lower-level network architectures belong are within the second region. The second lower-level network architectures are communicatively connected to both the first and second upper-level network architectures.

[0009] As can be seen, in some embodiments of this application, the lower-level network architecture can communicate with other higher-level network architectures in addition to communicating with its parent higher-level network architecture. Thus, the multi-heterogeneous VRB network architecture based on hybrid chips provided in this application embodiment can support fewer hops in cross-regional communication scenarios, thereby supporting high real-time cross-regional communication scenarios. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a multi-heterogeneous VRB network architecture based on a hybrid chip according to this application; Figure 2 This is a schematic diagram of any lower-level or higher-level network architecture in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of any network unit in the embodiments of this application; Figure 4 This is a flowchart illustrating the communication method applied to the above-mentioned multi-heterogeneous VRB network architecture based on hybrid chips in the embodiments of this application; Figure 5 This is a schematic diagram of the transmission path of data packets within the network unit in an embodiment of this application. Detailed Implementation

[0011] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] In existing technologies, with the rapid development of cross-regional collaborative computing, wide-area IoT, and cloud-edge-device integrated applications, high real-time business scenarios are gradually increasing. However, traditional tree-structured hierarchical network architectures often involve multi-hop transmission paths and significant transmission latency when communicating across regions. Therefore, traditional tree-structured hierarchical network architectures are unsuitable for high real-time cross-regional communication scenarios.

[0013] In some embodiments of this application, in addition to communicating with its parent network architecture, the lower-level network architecture can also communicate with other parent network architectures. Thus, the hybrid chip-based multi-heterogeneous VRB network architecture provided in this application embodiment can support fewer hops in cross-regional communication scenarios, thereby supporting high real-time cross-regional communication scenarios.

[0014] The following provides a detailed description of the multi-heterogeneous VRB network architecture and communication method based on hybrid chips in the embodiments of this application.

[0015] See Figure 1 The embodiments of this application provide a multi-heterogeneous VRB network architecture based on a hybrid chip, which includes: A first superior network architecture and a second superior network architecture, wherein the first superior network architecture and the second superior network architecture are communicatively connected, the first superior network architecture belongs to a first region, and the second superior network architecture belongs to a second region; At least one first subordinate network architecture, different first subordinate network architectures belong to different regions, and the regions to which the first subordinate network architectures belong are all within the scope of the first region. The first subordinate network architecture is communicatively connected to both the first superior network architecture and the second superior network architecture. At least one second-level network architecture, different second-level network architectures belong to different regions, and the regions to which the second-level network architectures belong are all within the scope of the second region. The second-level network architectures are communicatively connected to both the first-level network architecture and the second-level network architecture.

[0016] Therefore, the first region can be divided into multiple regions, and a first-level network architecture can be deployed in each region. In this way, the first-level network architectures of multiple regions within the first region can communicate with the first-level network architecture of the first region, so that the first-level network architectures of different regions within the first region can communicate with each other through the first-level network architecture.

[0017] Similarly, the second region can be divided into multiple regions, and a second lower-level network architecture can be deployed in each region. In this way, the second lower-level network architectures of multiple regions within the second region can communicate with the second upper-level network architecture of the second region, thereby enabling the second lower-level network architectures of different regions within the second region to communicate with each other through the second upper-level network architecture.

[0018] Furthermore, the first lower-level network architecture belonging to the first region can also communicate with the second upper-level network architecture belonging to the second region, and the second lower-level network architecture belonging to the second region can also communicate with the first upper-level network architecture belonging to the first region. In this way, when any first lower-level network architecture communicates with any second lower-level network architecture, they can communicate through the transmission path formed by the first lower-level network architecture, the first upper-level network architecture, and the second lower-level network architecture, or they can communicate through the transmission path formed by the first lower-level network architecture, the second upper-level network architecture, and the second lower-level network architecture. Compared with the transmission path formed by the first lower-level network architecture, the first upper-level network architecture, the second upper-level network architecture, and the second lower-level network architecture, the transmission path is shortened, thereby reducing transmission latency. Thus, the multi-heterogeneous VRB network architecture based on hybrid chips provided in this application embodiment can support fewer hops in the transmission path, thereby supporting high real-time cross-regional communication scenarios.

[0019] Optionally, the hybrid chip-based multi-heterogeneous VRB network architecture may further include more upper-level and lower-level network architectures. For example, it may also include a third upper-level network architecture and at least one third lower-level network architecture. The third upper-level network architecture is communicatively connected to the first upper-level network architecture and the second upper-level network architecture, respectively. The third lower-level network architecture is communicatively connected to the third upper-level network architecture. The third upper-level network architecture belongs to a third region, and different third lower-level network architectures belong to different regions. The region to which the third lower-level network architecture belongs is within the scope of the third region.

[0020] As described above, in some embodiments of this application, a multi-heterogeneous VRB network architecture based on a hybrid chip is provided. This multi-heterogeneous VRB network architecture based on a hybrid chip includes a first upper-level network architecture and a second upper-level network architecture, as well as at least one first lower-level network architecture and at least one second lower-level network architecture. The first upper-level network architecture is communicatively connected to the second upper-level network architecture, the first upper-level network architecture belongs to a first region, and the second upper-level network architecture belongs to a second region. Different first lower-level network architectures belong to different regions, and the regions to which the first lower-level network architectures belong are all within the scope of the first region. The first lower-level network architecture is communicatively connected to both the first upper-level network architecture and the second upper-level network architecture. Different second lower-level network architectures belong to different regions, and the regions to which the second lower-level network architectures belong are all within the scope of the second region. The second lower-level network architecture is communicatively connected to both the first upper-level network architecture and the second upper-level network architecture.

[0021] As can be seen, in some embodiments of this application, the lower-level network architecture can communicate with other higher-level network architectures in addition to communicating with its parent higher-level network architecture. Thus, the multi-heterogeneous VRB network architecture based on hybrid chips provided in this application embodiment can support fewer hops in cross-regional communication scenarios, thereby supporting high real-time cross-regional communication scenarios.

[0022] Optionally, any higher-level network architecture or any lower-level network architecture includes multiple network units with communication connections (e.g., Figure 2 As shown), a network unit is formed by multiple computing nodes communicating and connecting to form a three-dimensional torus (3D-trous) structure. It can be seen that, in some embodiments of this application, within a network unit, a computing node acts as a vertex of a 3D mesh, communicating and connecting with its adjacent computing nodes, for example... Figure 3 As shown, a network unit is composed of multiple computing nodes interconnected through a three-dimensional toroidal topology.

[0023] Among them, computing nodes refer to hardware units with data processing capabilities, including central processing units (CPUs), graphics processing units (GPUs), and dedicated artificial intelligence accelerators (AIAs), and integrate memory controllers and network interfaces to perform computing tasks and communicate with neighboring nodes.

[0024] Network unit: refers to a logical cluster formed by N×M×K computing nodes arranged in a three-dimensional grid, where N, M, and K are all integers ≥2.

[0025] 3D-trous structure is a three-dimensional mesh topology in which each computing node is connected to its adjacent computing nodes in the three orthogonal dimensions of X, Y, and Z; and mesh boundary nodes are connected to opposite boundary nodes through wrap-around links to form a closed-loop structure, for example... Figure 3 As shown, the connection between the first and last nodes on the same straight line in the three-dimensional network architecture forms a loop. It should be noted that... Figure 3 Only one loop is shown in the diagram; examples of the other loops are similar.

[0026] The network unit adopts a 3D-Torus structure, so the maximum number of hops between any two computing nodes is (N / 2 + M / 2 + K / 2). Taking an 8×8×8 unit as an example, the maximum number of hops is only 12, which can significantly shorten the end-to-end latency. Furthermore, the loopback link can eliminate boundary bottlenecks and avoid data detours, which can further shorten data transmission latency. In addition, the 3D-Torus structure is easy to expand, thus supporting larger-scale network architectures.

[0027] Optionally, the multiple computing nodes within the network unit are connected via a crossbar switch.

[0028] Crossbar switches are primarily used to achieve efficient connections between multiple inputs and multiple outputs. Their core feature is that they allow any input and output to establish independent paths and support parallel transmission. In other words, crossbar switches can flexibly connect input ports and output ports to achieve efficient data transmission between multiple communication paths. Therefore, when computing nodes within a network unit communicate through crossbar switches, the data transmission latency within the network unit can be further reduced.

[0029] Optionally, the computing node includes a hybrid chip.

[0030] The hybrid chip adopts a multi-core heterogeneous integration design, and its core architecture may include the following modules: CPU: Responsible for executing control logic, task scheduling, and input / output management; GPU: Performs general-purpose parallel computing tasks; Neural Processing Unit (NPU): A tensor computation engine specifically designed for deep learning optimization; On-chip high-speed interconnect bus: It adopts a ring bus design based on the Network-on-Chip (NoC) architecture to realize data transmission between computing units; Hardware Task Scheduler (HTS): Based on a priority-based preemptive algorithm, it dynamically allocates computing resources and maintains task dependencies.

[0031] The aforementioned hybrid chip breaks the resource silo effect of traditional computing systems, achieving deep integration of multiple functional modules. Therefore, the hybrid chip in this embodiment can include modules with multiple functions. Thus, by using the hybrid chip as a computing node to build the aforementioned network unit, the network unit can possess more powerful functions and support more services.

[0032] Optionally, the computing node supports the VRB protocol.

[0033] VRB is a Remote Direct Memory Access (RDMA) technology system implemented using the V2V communication protocol; that is, the VRB protocol is a remote data reading protocol provided to support big data transmission in intelligent computing centers.

[0034] Therefore, in some embodiments of this application, when the computing nodes support the VRB protocol, remote direct memory access can be achieved between the computing nodes, thereby reducing the data transmission latency between the computing nodes.

[0035] In addition, the traditional hierarchical topology has the following shortcomings: (1) Insufficient system reliability and fault tolerance: If the upper-level node of a certain region fails (such as the core computer room being paralyzed due to natural disasters), all its subordinate nodes will completely lose cross-regional communication capabilities because they cannot switch to the upper-level node of other regions, resulting in the interruption of critical services.

[0036] (2) Rigid resource allocation: The computing and storage resources of lower-level nodes can only be scheduled through their respective upper-level nodes, making it difficult to achieve cross-regional resource pooling.

[0037] The embodiments of this application provide a communication method applied to the aforementioned multi-heterogeneous VRB network architecture based on hybrid chips. This method can break the regional binding restrictions between lower-level nodes and upper-level nodes, enabling cross-layer and cross-domain communication and resource collaboration, thereby improving the overall network performance and robustness. The communication method is described in detail below.

[0038] See Figure 4The communication method applied to the above-described heterogeneous VRB network architecture based on hybrid chips may include the following steps 401 to 402: Step 401: If the destination address of the data packet to be sent by the first target lower-level network architecture corresponds to the second target lower-level network architecture, the first target lower-level network architecture sends the data packet to the target upper-level network architecture.

[0039] Wherein, the first target lower-level network architecture is one of the first lower-level network architectures; the second target lower-level network architecture is one of the second lower-level network architectures; and the target upper-level network architecture is an upper-level network architecture that communicates with the first target lower-level network architecture and the second target lower-level network architecture.

[0040] In addition, the destination address corresponds to the lower-level network architecture of the second target, which can be understood as: the destination address includes the address of the lower-level network architecture of the second target.

[0041] Furthermore, the target upper-level network architecture is either the first upper-level network architecture or the second target upper-level network architecture.

[0042] Step 402: Send the data packet to the second target lower-level network architecture through the target upper-level network architecture.

[0043] As described above, in the multi-heterogeneous VRB network architecture based on hybrid chips, the first lower-level network architecture communicates not only with the first upper-level network architecture of its first region but also with the second upper-level network architecture of the second region. Similarly, the second lower-level network architecture communicates not only with the second upper-level network architecture of its second region but also with the first upper-level network architecture of the first region. Thus, when any first lower-level network architecture needs to send a data packet to any second lower-level network architecture, it can be forwarded through an upper-level network architecture (e.g., the first or second upper-level network architecture) that communicates with both the first and second lower-level network architectures. This shortens the transmission path between the first and second lower-level network architectures compared to existing technologies (i.e., the transmission path formed by first lower-level network architecture - first upper-level network architecture - second upper-level network architecture - second lower-level network architecture), thereby reducing data packet transmission latency. Furthermore, this communication method between the first and second lower-level network architectures breaks the regional binding restrictions between lower-level and upper-level nodes, enabling cross-layer and cross-domain communication and resource collaboration, thereby improving the overall network performance and robustness.

[0044] Optionally, any higher-level network architecture or any lower-level network architecture includes multiple network units with communication connections; The transmission process of the data packet in the first target lower-level network architecture, the second target lower-level network architecture, or the target upper-level network architecture includes: In the first target lower-level network architecture, the second target lower-level network architecture, or the target upper-level network architecture, the first network unit corresponding to the source address of the data packet sends the data packet to the second network unit corresponding to the destination address of the data packet.

[0045] As can be seen, in some embodiments, any upper-level network architecture or any lower-level network architecture may include multiple network units, and multiple network units within the same network architecture are communicatively connected. Therefore, data packets can be transmitted through the corresponding network units within any upper-level network architecture or any lower-level network architecture.

[0046] As described above, the process of transmitting data packets from any network unit in the first lower-level network architecture to any network unit in the second lower-level network architecture can be described as follows: When a data packet is transmitted in the first lower-level network architecture, the source address carried in the data packet includes the address of the network unit-1 that sent the data packet, and the destination address carried in the data packet includes the address of the network unit-2 in the second lower-level network architecture that received the data packet. When sending a data packet, network unit-1 can obtain the network unit-3 in the first lower-level network architecture that is connected to the target upper-level network architecture, and determine the transmission path from network unit-1 to network unit-3. The data packet is then sent to network unit-3 through this path, and then the data packet is transmitted to the target upper-level network architecture through network unit-3.

[0047] Next, the data packet is transmitted in the target upper-level network architecture. The specific process is as follows: After receiving the data packet, the network unit-4 in the target upper-level network architecture, which is connected to the network unit-3 mentioned above, can obtain the network unit-5 in the target upper-level network architecture, which is connected to the second lower-level network architecture used to receive the data packet, and determine the transmission path from the network unit-4 to the network unit-5. The data packet is then sent to the network unit-5 through this path, and then the data packet is transmitted to the second lower-level network architecture through the network unit-5.

[0048] Subsequently, the data packet is transmitted in the second lower-level network architecture. The specific process is as follows: After receiving the data packet, the network unit-6, which is connected to the network unit-5 in the second lower-level network architecture, can determine the transmission path from the network unit-6 to the network unit-2, and then send the data packet to the network unit-2 through the path.

[0049] The following describes the data packet transmission process within a network unit, as described in method one or two: Option 1: Optionally, a network unit is formed by multiple computing nodes communicating to form a 3D-trous structure; The transmission process of the data packet in the first network unit includes: The first computing node in the first network unit corresponding to the source address obtains the first network status information of the computing node adjacent to the first computing node in the first network unit, determines the second computing node that will receive the data packet next hop based on the first network status information and the destination address, and transmits the data packet to the second computing node. The second computing node obtains the second network status information of the computing nodes adjacent to the second computing node in the first network unit, determines the third computing node that will receive the data packet in the next hop according to the second network status information and the destination address, and transmits the data packet to the third computing node. The transmission of the data packet in the first network unit is completed when the data packet reaches the computing node corresponding to the destination address in the first network unit.

[0050] It should be noted that in the 3D-trous structure, the adjacent computing nodes of a computing node can be understood as computing nodes that are directly connected to that computing node.

[0051] The first computing node corresponding to the source address can be understood as the address of the computing node in the first network unit included in the source address, that is, the above data packet comes from the first computing node in the first network unit.

[0052] Furthermore, in a network unit formed by the 3D-trous structure, each computing node maintains local network state information. For example, each computing node can maintain the network state information of its neighboring computing nodes. Thus, when one computing node in the network unit sends a data packet to another computing node, the transmission path of the data packet can be determined step by step based on the local network state information of each node dimension. In this way, a computing node with a better network state can be found to transmit the data packet, thereby minimizing the transmission latency while ensuring that the data packet is successfully transmitted to the final computing node.

[0053] Optionally, the first network status information includes load information, latency information, and fault information; The first computing node determines the second computing node that will receive the data packet at the next hop based on the first network status information and the destination address, including: The first computing node selects a computing node that meets a first condition from among the nodes adjacent to it, based on the load information, the latency information, the fault information, and the destination address, as the second computing node. The first condition includes: the load is less than a first threshold, the latency is less than a second threshold, and the system is not in a fault state.

[0054] Therefore, each computing node within the same network unit can maintain load information, latency information, and fault information of multiple adjacent computing nodes. Load information indicates the load size of the computing node, latency information indicates the transmission latency between the computing node and its adjacent computing nodes, and fault information indicates whether the computing node has a fault. Thus, before sending a data packet, the first computing node can select a second computing node whose load is less than a first threshold, latency is less than a second threshold, and no fault has occurred, based on the load size, latency, and fault status of its adjacent computing nodes, and then send the data packet to the second computing node.

[0055] It should be noted that within the same network unit, each computing node that receives a data packet can determine the next-hop computing node to receive the data packet using the same method described above.

[0056] As can be seen from the above, when data packets are transmitted in network units, the transmission path of the data packets can be determined based on the load information, latency information, and fault information of the computing power nodes. This can ensure that the data packets can reach the final computing power node, minimize the transmission latency, and achieve load balancing among the computing power nodes, thereby further improving the overall network performance.

[0057] Understandably, the network status information of each computing node in the network unit can be updated periodically. In this way, during the transmission of data packets, a new transmission path can be determined at any time based on the updated network status information, thereby enabling the transmission of data packets in the network unit to adapt to the constantly changing network status and improving the flexibility and adaptability of the network.

[0058] Method 2: Optionally, a network unit is formed by multiple computing nodes communicating to form a 3D-trous structure; The transmission process of the data packet in the first network unit includes: The first computing node in the first network unit, corresponding to the source address, obtains the network status information of other computing nodes in the first network unit besides the first computing node. The first computing node determines the transmission path from the first computing node to the computing node corresponding to the destination address based on the destination address and the network status information of other computing nodes in the first network unit besides the first computing node. The first computing node sends the data packet to the computing node corresponding to the destination address through the transmission path from the first computing node to the computing node corresponding to the destination address.

[0059] Therefore, in some embodiments, each computing node in the first network unit can record the network status information of other computing nodes. In this way, before the first computing node sends a data packet, it can determine the entire transmission path of the data packet in the first network unit based on the destination address and the network status information of each computing node. Thus, the transmission path of the data packet determined based on the network status information of more computing nodes in the first network unit will be more in line with the overall network status of the first network unit, thereby further improving the overall network performance.

[0060] Optionally, the network status information includes load information, latency information, and fault information; the transmission path from the first computing node to the computing node corresponding to the destination address, based on the destination address and the network status information of other computing nodes in the first network unit besides the first computing node, includes: The first computing node determines multiple candidate transmission paths from the first computing node to the computing node corresponding to the destination address based on the fault information of the computing nodes other than the first computing node in the first network unit, wherein none of the computing nodes on the candidate transmission paths are faulty. The first computing node determines the sum of the loads of each computing node on the i-th candidate transmission path and the delay of the i-th transmission path, wherein the delay of the i-th transmission path is the sum of the delays between two adjacent computing nodes on the i-th transmission path, where i is an integer from 1 to N, and N represents the number of candidate transmission paths. The first computing node selects one path from the candidate transmission paths based on the sum of the load and the latency of the first to N candidate transmission paths, and uses it as the transmission path from the first computing node to the computing node corresponding to the destination address.

[0061] Among them, the transmission path with the minimum load and the minimum sum of delays can be selected from the N candidate transmission paths as the transmission path from the first computing power node to the computing power node corresponding to the destination address.

[0062] To facilitate understanding of Method Two, the following example is provided: Assume that the number of computing nodes in the first network unit is 3×3×3 (27 in total), and each computing node is dynamically connected through the video network; now it is necessary to transmit data packets from node A (coordinate (0,0,0)) to node B (coordinate (2,2,2)).

[0063] The network status is as follows: Link bandwidth: 50Gbps; Link (1,1,1)→(2,1,1): 80% load, 8 nanoseconds (ns) delay; Link (1,2,1)→(2,2,1): 90% load, 10ns delay; Other links have low load and a latency of 5ns.

[0064] In addition, computing node A initializes its local routing table to record the network status information of each computing node in the first network unit, such as load, latency, and whether it is faulty. If, based on the network status information of each node, computing node A finds that none of the computing nodes in the first network unit are fault-free, and the links (1,1,1)→(2,1,1) and (1,2,1)→(2,2,1) have high loads, then the transmission paths via (1,1,1)→(2,1,1) and (1,2,1)→(2,2,1) are not viable. In this case, computing node A can use a low-latency routing algorithm to calculate the optimal path from (0,0,0) to (2,2,2), avoiding the high-load links. For example... Figure 5 As shown, the following path can be selected: (0,0,0)→(1,0,0)→(2,0,0)→(2,1,0)→(2,2,0)→(2,2,1)→(2,2,2), and the total delay of this path is: 5ns×6 = 30ns; in this way, the data packet can be transmitted along the calculated path.

[0065] If, during transmission, the link (2,1,0)→(2,2,0) suddenly experiences a surge in load, the path can be recalculated. Figure 5 As shown: (0,0,0)→(1,0,0)→(1,1,0)→(1,2,0)→(2,2,0)→(2,2,1)→(2,2,2), the total delay of the new path is: 5ns×6=30ns, which avoids the impact of high-load links.

[0066] As can be seen, in some embodiments of this application, the network status (such as link load, latency, fault status, etc.) of each computing node in the network unit can be monitored in real time, and the optimal path can be dynamically selected based on this information. In this way, data traffic can be evenly distributed to multiple paths according to the real-time load of the links, avoiding the increase in latency caused by overload of some links. Moreover, when a computing node fault is detected, the path can be quickly recalculated to bypass the fault area and ensure the continuity of data transmission.

[0067] Alternatively, a priority queue can be introduced so that computing nodes can prioritize the transmission of high-priority data packets (such as real-time computing tasks).

[0068] It should also be noted that the above-mentioned heterogeneous VRB network architecture based on hybrid chips can be applied to video networks, and the communication method described above for the heterogeneous VRB network architecture based on hybrid chips can also be applied to video networks.

[0069] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of this application.

[0070] Embodiments of this application provide a computer-readable storage medium storing a computer program that causes a processor to execute the above-described communication method applied to a multi-heterogeneous VRB network architecture based on a hybrid chip.

[0071] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0072] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0073] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0074] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0075] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0076] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0077] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0078] The foregoing has provided a detailed description of the transmission testing method, apparatus, electronic device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A multi-heterogeneous VRB network architecture based on a hybrid chip, characterized in that, The hybrid chip-based heterogeneous VRB network architecture includes: A first superior network architecture and a second superior network architecture, wherein the first superior network architecture and the second superior network architecture are communicatively connected, the first superior network architecture belongs to a first region, and the second superior network architecture belongs to a second region; At least one first subordinate network architecture, different first subordinate network architectures belong to different regions, and the regions to which the first subordinate network architectures belong are all within the scope of the first region. The first subordinate network architecture is communicatively connected to both the first superior network architecture and the second superior network architecture. At least one second-level network architecture, different second-level network architectures belong to different regions, and the regions to which the second-level network architectures belong are all within the scope of the second region. The second-level network architectures are communicatively connected to both the first-level network architecture and the second-level network architecture.

2. The multi-heterogeneous VRB network architecture based on a hybrid chip according to claim 1, characterized in that, Any upper-level network architecture or any lower-level network architecture includes multiple network units with communication connections. A network unit is formed by multiple computing nodes with communication connections to form a three-dimensional torus structure.

3. The multi-heterogeneous VRB network architecture based on hybrid chips according to claim 2, characterized in that, The multiple computing nodes within the network unit are connected via crossbar switches.

4. The multi-heterogeneous VRB network architecture based on a hybrid chip according to claim 2 or 3, characterized in that, The computing nodes include hybrid chips.

5. The multi-heterogeneous VRB network architecture based on a hybrid chip according to claim 2 or 3, characterized in that, The computing nodes support the VRB protocol.

6. A communication method applied to the multi-heterogeneous VRB network architecture based on a hybrid chip as described in any one of claims 1 to 5, characterized in that, The method includes: When the destination address of the data packet to be sent by the first target lower-level network architecture corresponds to the second target lower-level network architecture, the first target lower-level network architecture sends the data packet to the target upper-level network architecture. Here, the first target lower-level network architecture is one of the first lower-level network architectures, the second target lower-level network architecture is one of the second lower-level network architectures, and the target upper-level network architecture is an upper-level network architecture that is communicatively connected to the first target lower-level network architecture and the second target lower-level network architecture. The data packet is sent to the second target lower-level network architecture through the target upper-level network architecture.

7. The method according to claim 6, characterized in that, Any higher-level network architecture or any lower-level network architecture includes multiple network units with communication connections. The transmission process of the data packet in the first target lower-level network architecture, the second target lower-level network architecture, or the target upper-level network architecture includes: In the first target lower-level network architecture, the second target lower-level network architecture, or the target upper-level network architecture, the first network unit corresponding to the source address of the data packet sends the data packet to the second network unit corresponding to the destination address of the data packet.

8. The method according to claim 7, characterized in that, A network unit consists of multiple computing nodes connected via communication to form a 3D-trous structure; The transmission process of the data packet in the first network unit includes: The first computing node in the first network unit corresponding to the source address obtains the first network status information of the computing node adjacent to the first computing node in the first network unit, determines the second computing node that will receive the data packet next hop based on the first network status information and the destination address, and transmits the data packet to the second computing node. The second computing node obtains the second network status information of the computing nodes adjacent to the second computing node in the first network unit, determines the third computing node that will receive the data packet in the next hop according to the second network status information and the destination address, and transmits the data packet to the third computing node. The transmission of the data packet in the first network unit is completed when the data packet reaches the computing node corresponding to the destination address in the first network unit.

9. The method according to claim 8, characterized in that, The first network status information includes load information, latency information, and fault information; The first computing node determines the second computing node that will receive the data packet at the next hop based on the first network status information and the destination address, including: The first computing node selects a computing node that meets a first condition from among the nodes adjacent to it, based on the load information, the latency information, the fault information, and the destination address, as the second computing node. The first condition includes: the load is less than a first threshold, the latency is less than a second threshold, and the system is not in a fault state.

10. A computer-readable storage medium, characterized in that, The computer program stored therein causes the processor to execute the communication method as described in any one of claims 6 to 9.

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