Manufacturing method of PCB and PCB

Abstract

This application relates to the field of printed circuit board (PCB) technology, and discloses a PCB manufacturing method and a PCB. The PCB manufacturing method includes: providing a substrate, the substrate including a first circuit layer, a second circuit layer, and an insulating layer; processing buried vias on the substrate, the buried vias including receiving holes and multiple routing holes, the inner wall of the routing holes being provided with conductive portions, the first circuit layer and / or the second circuit layer being connected to the conductive portions; placing electronic components within the buried vias, the first circuit layer, the second circuit layer, and the conductive portions being spaced apart from the electronic components; filling the space between the inner wall of the receiving holes and the electronic components with an insulating matrix, the insulating matrix supporting the electronic components. The PCB manufacturing method and PCB provided in this application are used to improve the problem of low wiring density around electronic components after they are embedded in the substrate of the PCB in related technologies.

Description

Technical Field

[0001] This application relates to the field of printed circuit board technology, and more particularly to a method for manufacturing a PCB and the PCB itself. Background Technology

[0002] With the rapid growth of computing power, chips are becoming more integrated and larger. Embedding electronic components such as capacitors into the PCB (Printed Circuit Board) substrate beneath the chip helps reduce leads, reduce parasitic inductance, and avoid failure at high frequencies. At the same time, it can reduce the space occupied by the chip's perimeter and provide space for large-scale fan-out routing, which is especially suitable for multi-chip interconnect layout.

[0003] In related technologies, after electronic components are embedded in the substrate of a PCB, the wiring density around the electronic components is relatively low. Summary of the Invention

[0004] This application provides a method for manufacturing a PCB and a PCB, which improves the problem of low wiring density around electronic components after they are embedded in the substrate of the PCB in the related art.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a PCB, comprising:

[0006] A substrate is provided, the substrate including a first circuit layer, a second circuit layer and an insulating layer located between the first circuit layer and the second circuit layer;

[0007] A buried via is fabricated on the substrate. The buried via penetrates the first circuit layer, the insulating layer, and the second circuit layer. The buried via includes a receiving hole and a plurality of routing holes. The plurality of routing holes are arranged at intervals around the receiving hole, and the receiving hole and the routing holes are connected. A conductive portion is provided on the inner wall of the routing hole, and the first circuit layer and / or the second circuit layer are connected to the conductive portion.

[0008] Electronic components are disposed within the embedded hole, and the first circuit layer, the second circuit layer, and the conductive part are all spaced apart from the electronic components.

[0009] An insulating matrix is ​​filled between the inner wall of the receiving hole and the electronic component, and the insulating matrix supports the electronic component.

[0010] In some embodiments, the process of forming embedded holes on the substrate includes:

[0011] Multiple process holes are processed on the substrate;

[0012] A conductive hole ring is provided on the inner wall of the process hole;

[0013] The receiving hole is processed on the substrate to remove part of the conductive hole ring, the remaining conductive hole ring forms the conductive part, and the remaining process hole forms the wiring hole.

[0014] In some embodiments, before placing electronic components within the embedded vias, the PCB fabrication method further includes:

[0015] The conductive portion that is in contact with the inner wall of the receiving hole is etched away, so that the remaining conductive portion is spaced apart from the inner wall of the receiving hole; when electronic components are placed in the embedded hole, some of the electronic components are located in the receiving hole and some of the electronic components are located in the trace hole.

[0016] In some embodiments, when the etching removes the conductive portion that is in contact with the inner wall of the receiving hole, the etching also removes the first circuit layer that is in contact with the inner wall of the receiving hole, such that the remaining first circuit layer is spaced apart from the inner wall of the receiving hole; and / or, when the etching removes the conductive portion that is in contact with the inner wall of the receiving hole, the etching also removes the second circuit layer that is in contact with the inner wall of the receiving hole, such that the remaining second circuit layer is spaced apart from the inner wall of the receiving hole.

[0017] In some embodiments, the conductive portion has an etched surface facing the receiving hole; before the receiving hole is machined on the substrate, an anti-etching material is used to cover the outer surface of the conductive hole ring; when the receiving hole is machined on the substrate, a portion of the anti-etching material is removed so that the conductive portion facing the receiving hole is exposed; the conductive portion in contact with the inner wall of the receiving hole is removed by etching the surface of the conductive portion facing the receiving hole; after the conductive portion in contact with the inner wall of the receiving hole is removed by etching the surface of the conductive portion facing the receiving hole, the anti-etching material is removed.

[0018] In some embodiments, filling the space between the inner wall of the accommodating hole and the electronic component with an insulating matrix includes:

[0019] An insulating resin is filled between the inner wall of the accommodating hole and the electronic component, and the insulating matrix includes the resin;

[0020] And / or, an adhesive layer is provided on at least one side of the substrate, and the adhesive layer and the substrate are pressed together such that a portion of the adhesive layer melts and fills the gap between the inner wall of the accommodating hole and the electronic component, wherein the insulating matrix includes at least a portion of the adhesive layer.

[0021] In some embodiments, the length direction of the electronic component is parallel to the arrangement direction of the first circuit layer, the insulating layer, and the second circuit layer.

[0022] Secondly, embodiments of this application provide a PCB, the PCB including a substrate, the substrate including a first circuit layer, a second circuit layer, and an insulating layer located between the first circuit layer and the second circuit layer; the substrate is provided with a buried via, the buried via penetrating the first circuit layer, the insulating layer, and the second circuit layer, the buried via including a receiving hole and a plurality of routing holes, the axis of the receiving hole being parallel to the axis of the routing holes, the plurality of routing holes being spaced around the receiving hole, and the receiving hole and the routing holes being connected, a conductive portion being provided on the inner wall of the routing hole, the first circuit layer and / or the second circuit layer being connected to the conductive portion; an electronic component is disposed in the buried via, the first circuit layer, the second circuit layer, and the conductive portion being spaced apart from the electronic component, and an insulating matrix is ​​filled between the inner wall of the receiving hole and the electronic component.

[0023] In some embodiments, some of the electronic components are located within the receiving hole, and some of the electronic components are located within the wiring hole.

[0024] In some embodiments, the PCB further includes a first connection layer and a third circuit layer, the first connection layer being located between the third circuit layer and the first circuit layer, the first connection layer having a first via, the interior of the first via being disposed of a first conductive material, and the third circuit layer being electrically connected to the electronic components through the first conductive material; and / or, the PCB further includes a second connection layer and a fourth circuit layer, the second connection layer being located between the fourth circuit layer and the second circuit layer, the second connection layer having a second via, the interior of the second via being disposed of a second conductive material, and the fourth circuit layer being electrically connected to the electronic components through the second conductive material.

[0025] In some embodiments, the PCB further includes a third circuit layer located on the side of the first circuit layer away from the insulating layer, the third circuit layer being connected to and electrically connected to the electronic components; and / or, the PCB further includes a fourth circuit layer located on the side of the second circuit layer away from the insulating layer, the fourth circuit layer being connected to and electrically connected to the electronic components.

[0026] Thirdly, embodiments of this application provide a PCB, which is manufactured by the PCB manufacturing method described in the first aspect.

[0027] The PCB manufacturing method provided in this application has the following advantages: First, embedded vias are processed on the substrate, penetrating the first circuit layer, the insulating layer, and the second circuit layer. Each embedded via includes a receiving hole and multiple routing holes, spaced apart around the receiving hole and connected to it. Conductive portions are provided on the inner walls of the routing holes, and the first and / or second circuit layers are connected to the conductive portions. Then, electronic components are placed within the embedded vias, with the first, second, and conductive portions spaced apart from the electronic components. Finally, an insulating matrix is ​​filled between the inner walls of the receiving hole and the electronic components, supporting the electronic components. Therefore, not only can the electronic components be confined within the embedded vias composed of the receiving hole and multiple routing holes, completing the embedding of the electronic components, but the space occupied by the embedded vias and electronic components is also small. The lines on the first and / or second circuit layers are electrically connected to the conductive portions, allowing for independent wiring around the electronic components, thus increasing the wiring density around them.

[0028] The advantages of the PCB provided in this application compared to the prior art can be found in the description of the advantages of the PCB manufacturing method provided in this application compared to the prior art, which will not be repeated here. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a flowchart of a PCB manufacturing method in one embodiment of this application;

[0031] Figure 2 This is a schematic diagram of the substrate structure in one embodiment of this application;

[0032] Figure 3 yes Figure 2 The substrate shown is a cross-sectional view along the LL direction;

[0033] Figure 4 Is Figure 3 The diagram shows a substrate with multiple trace holes fabricated on it.

[0034] Figure 5 Is Figure 4 A schematic diagram showing a conductive ring installed on the inner wall of a wiring hole.

[0035] Figure 6 Is Figure 5The diagram shows a substrate with accommodating holes machined to remove part of the conductive hole ring, and the remaining conductive hole ring forming a conductive part.

[0036] Figure 7 It is etching removal and Figure 6 The diagram shows a conductive portion connected to the inner wall of the receiving hole, such that the remaining conductive portion is spaced apart from the inner wall of the receiving hole.

[0037] Figure 8 Is Figure 7 A schematic diagram showing the placement of electronic components within an embedded hole composed of a receiving hole and a wiring hole.

[0038] Figure 9 Is Figure 8 The diagram shows an insulating matrix filling the space between the inner wall of the accommodating hole and the electronic component, with the insulating matrix supporting the electronic component. A third circuit layer is provided on the side of the first circuit layer away from the insulating layer, and a fourth circuit layer is provided on the side of the second circuit layer away from the insulating layer.

[0039] Figure 10 yes Figure 9 The cross-sectional view of the substrate, electronic components, insulating matrix, third circuit layer, and fourth circuit layer along the MM direction is shown.

[0040] Figure 11 yes Figure 9 The cross-sectional view of the substrate, electronic components, insulating matrix, third circuit layer, and fourth circuit layer along the NN direction is shown.

[0041] Figure 12 This is a cross-sectional view of the substrate, electronic components, insulating matrix, third circuit layer, and fourth circuit layer in another embodiment of this application.

[0042] The markings in the diagram mean:

[0043] 10. Substrate;

[0044] 11. First circuit layer; 12. Second circuit layer; 13. Insulation layer;

[0045] 20. Wiring holes;

[0046] 201. Process hole; 202. Conductive hole ring; 21. Conductive part;

[0047] 30. Receiving hole;

[0048] 40. Electronic components;

[0049] 50. Insulating matrix;

[0050] 60. Third line layer;

[0051] 61. First connection layer;

[0052] 70. Fourth line layer;

[0053] 71. Second connecting layer;

[0054] 80. First conductive material. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0056] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0058] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0059] With the rapid growth of computing power, chips are becoming more integrated and larger. Embedding electronic components such as capacitors into the PCB (Printed Circuit Board) substrate beneath the chip helps reduce leads, reduce parasitic inductance, and avoid failure at high frequencies. At the same time, it can reduce the space occupied by the chip's perimeter and provide space for large-scale fan-out routing, which is especially suitable for multi-chip interconnect layout.

[0060] In related technologies, after electronic components are embedded in the substrate of a PCB, the wiring density around the electronic components is low because the electronic components require a large amount of space.

[0061] In view of this, this application provides a PCB manufacturing method and a PCB. First, embedded vias are processed on the substrate, penetrating the first circuit layer, the insulating layer, and the second circuit layer. Each embedded via includes a receiving hole and multiple routing holes, spaced apart around the receiving hole and connected to it. Conductive portions are provided on the inner walls of the routing holes, and both the first and second circuit layers are connected to these conductive portions. Then, electronic components are placed within the embedded vias, with the first circuit layer, the second circuit layer, and the conductive portions spaced apart from the electronic components. Finally, an insulating matrix is ​​filled between the inner walls of the receiving hole and the electronic components, supporting the electronic components. Therefore, not only can the electronic components be confined within the embedded vias composed of the receiving hole and multiple routing holes through the insulating matrix, completing the embedding of the electronic components, but the space occupied by the embedded vias and electronic components is also small. The circuits on the first and second circuit layers are electrically connected through the conductive portions, allowing for independent wiring around the electronic components, thus increasing the wiring density around them.

[0062] To illustrate the technical solution of this application, the following description is provided in conjunction with specific accompanying drawings and embodiments.

[0063] Please refer to Figures 1 to 3 In a first aspect, embodiments of this application provide a method for manufacturing a PCB, comprising:

[0064] S100: A substrate 10 is provided, the substrate 10 including a first circuit layer 11, a second circuit layer 12 and an insulating layer 13 located between the first circuit layer 11 and the second circuit layer 12.

[0065] The materials of the first circuit layer 11 and the second circuit layer 12 can be copper, silver, or aluminum, etc. The material of the insulating layer 13 can include resin and glass fiber, etc.

[0066] Multiple first circuit layers 11, second circuit layers 12, and insulating layers 13 can be provided. One of the first circuit layers 11 and second circuit layers 12 can be an inner circuit layer of the substrate 10. For example, multiple core boards with completed inner circuit fabrication and copper surface treatment can be stacked as prepregs and laminated at least once to produce the substrate 10. The multilayer substrate 10 can be produced through core board cutting, inner circuit fabrication, etching and stripping, AOI (Automated Optical Inspection), browning, and lamination processes. The thickness of the substrate 10 can be 1.05 mm.

[0067] S200: Please refer to this as well. Figures 4 to 8 A buried via is fabricated on the substrate 10. The buried via penetrates the first circuit layer 11, the insulating layer 13, and the second circuit layer 12. The buried via includes a receiving hole 30 and a plurality of routing holes 20. The plurality of routing holes 20 are arranged at intervals around the receiving hole 30, and the receiving hole 30 and the routing holes 20 are connected. A conductive part 21 is provided on the inner wall of the routing hole 20. The first circuit layer 11 and / or the second circuit layer 12 are connected to the conductive part 21.

[0068] Buried vias can be fabricated on the substrate 10 using laser ablation or mechanical milling. One or more buried vias can be provided according to product design requirements. One receiving via 30 corresponds to two, three, or four routing vias 20, and the number of routing vias 20 depends on the routing requirements of a single buried via. For example, a first circuit layer 11 is connected to the conductive portion 21 within a portion of the routing vias 20, and a second circuit layer is connected to the conductive portion 21 within another portion of the routing vias 20. Alternatively, multiple first circuit layers 11, second circuit layers 12, and routing vias 20 can be provided, with multiple first circuit layers 11 corresponding one-to-one to a portion of the routing vias 20, and multiple second circuit layers 12 corresponding one-to-one to another portion of the routing vias 20.

[0069] The conductive part 21 can be made of copper, silver, or aluminum, etc. The first circuit layer 11 and / or the second circuit layer 12 are connected to the conductive part 21 in the following ways: all conductive parts 21 in the trace holes 20 are connected to the first circuit layer 11, and all conductive parts 21 in the trace holes 20 are connected to the second circuit layer 12, with the first circuit layer 11 and the second circuit layer 12 electrically connected; or, all conductive parts 21 in the trace holes 20 are connected to the first circuit layer 11, and the second circuit layer 12 is not connected to the conductive part 21; or, all conductive parts 21 in the trace holes 20 are connected to the second circuit layer 12, and the first circuit layer 11 is not connected to the conductive part 21; or, some conductive parts 21 in the trace holes 20 are connected to the first circuit layer 11, and other conductive parts 21 in the trace holes 20 are connected to the second circuit layer 12, with the first circuit layer 11 and the second circuit layer 12 not electrically connected.

[0070] It is understandable that, since the multiple trace holes 20 are independent, the corresponding conductive parts 21 within each trace hole 20 are also independent. Therefore, the corresponding conductive parts 21 within each trace hole 20 can each connect to different circuit layers. For example, when multiple first circuit layers 11 are provided, the corresponding conductive parts 21 within each trace hole 20 can each connect to different first circuit layers 11. Simultaneously, since the receiving hole 30 and the trace hole 20 are connected, the area occupied by the embedded hole can be reduced.

[0071] It should be noted that the trace holes 20 can be circular holes. Multiple trace holes 20 are spaced apart and evenly distributed around the receiving hole 30. When the receiving hole 30 intersects with the multiple trace holes 20, the overlapping areas are all equal. In this case, the center of the receiving hole 30 overlaps with the center of the line segment / graphic formed by connecting the centers of the multiple trace holes 20. For example, four trace holes 20 are provided, with a diameter of 0.25 mm. The diameter of the receiving hole 30 is 0.625 mm, and it is a non-metallized hole.

[0072] It is understandable that the wiring hole 20 and the receiving hole 30 can be round holes, square holes or other shapes of holes, and "hole" is not used as a limitation on their specific shape.

[0073] S300: Please refer to this as well. Figure 9 Electronic components 40 are disposed in embedded holes, and the first circuit layer 11, the second circuit layer 12 and the conductive part 21 are all disposed at intervals from the electronic components 40.

[0074] The electronic components 40 can be installed in the embedded holes by machine or manually. First, a high-temperature resistant protective film (such as a high-temperature resistant brown film) can be attached to one side of the substrate 10 to support the electronic components 40 and the uncured insulating matrix 50 during subsequent processing. Then, the electronic components 40 are placed into the embedded holes from the other side of the substrate 10, so that the lower end of the electronic components 40 is attached to the protective film, ensuring that the lower end of the electronic components 40 is exposed on the back side of the substrate 10 after embedding, and the upper end of the electronic components 40 is lower than the upper surface of the substrate 10.

[0075] Understandably, in order to facilitate the placement of electronic components 40, a gap is reserved between electronic components 40 and embedded holes, that is, the accommodating space of embedded holes can be larger than the volume of electronic components 40.

[0076] Electronic component 40 can be a capacitor or other components. Multiple electronic components 40 and embedded holes can be provided and arranged in a one-to-one correspondence. It is feasible to have the main body of electronic component 40 located in receiving hole 30 and the corners of electronic component 40 located in wiring hole 20.

[0077] It is understood that the first circuit layer 11, the second circuit layer 12 and the conductive part 21 are all insulated from the electronic component 40, thereby facilitating wiring of the first circuit layer 11 and the second circuit layer 12 around the electronic component 40, and the lines on the first circuit layer 11 and / or the lines on the second circuit layer 12 can be electrically connected to the conductive part 21 to transmit signals.

[0078] In the PCB manufacturing method provided in this application embodiment, the embedded hole is composed of a routing hole 20 and a receiving hole 30. When multiple first circuit layers 11 are provided, different first circuit layers 11 are connected to the conductive parts 21 inside different routing holes 20. When multiple second circuit layers 12 are provided, different second circuit layers 12 are connected to the conductive parts 21 inside different routing holes 20. That is, each routing hole 20 can be provided with an independent circuit, thereby increasing the wiring density.

[0079] S400: Please refer to this as well. Figure 10 and Figure 11 An insulating matrix 50 is filled between the inner wall of the receiving hole 30 and the electronic component 40, and the insulating matrix 50 supports the electronic component 40.

[0080] The insulating matrix 50 may include resin or the like. The insulating matrix 50 holds the electronic component 40, restricting the position of the electronic component 40 and preventing it from moving arbitrarily.

[0081] As can be seen from the above, the PCB manufacturing method provided in this application firstly involves processing buried vias on the substrate 10. These buried vias penetrate the first circuit layer 11, the insulating layer 13, and the second circuit layer 12. Each buried via includes a receiving hole 30 and multiple routing holes 20. The multiple routing holes 20 are spaced around the receiving hole 30 and are connected to it. A conductive portion 21 is provided on the inner wall of each routing hole 20. The first circuit layer 11 and / or the second circuit layer 12 are connected to the conductive portion 21. Then, electronic components 40 are placed within the buried vias. Some electronic components 40 are located within the receiving hole 30, and some are located within the routing holes 20. The first circuit layer 11, the second circuit layer 12, and the third circuit layer 12 are connected to each other. Both the circuit layer 12 and the conductive part 21 are spaced apart from the electronic component 40. Finally, an insulating matrix 50 is filled between the inner wall of the receiving hole 30 and the electronic component 40. The insulating matrix 50 supports the electronic component 40. Therefore, the electronic component 40 can be confined in the embedded hole composed of the receiving hole 30 and multiple wiring holes 20 by the insulating matrix 50, thus completing the embedding of the electronic component 40. Moreover, the space occupied by the embedded hole and the electronic component 40 is small. The lines on the first circuit layer 11 and / or the lines on the second circuit layer 12 can be electrically connected to the conductive part 21, thereby allowing independent wiring around the electronic component 40 and increasing the wiring density around the electronic component 40.

[0082] Please refer to Figures 4 to 6 In some embodiments, buried vias are formed on the substrate 10, including:

[0083] First, multiple process holes 201 are processed on the substrate 10.

[0084] Multiple process holes 201 can be processed on the substrate 10 by laser ablation or mechanical milling.

[0085] Secondly, a conductive hole ring 202 is provided on the inner wall of the process hole 201.

[0086] In this process, a conductive hole ring 202 can be formed on the inner wall of the process hole 201 by means of hole metallization (removal of adhesive, copper plating, and plate electroplating). The thickness of the conductive hole ring 202 can be 0.025mm.

[0087] Next, a receiving hole 30 is processed on the substrate 10 to remove part of the conductive hole ring 202, the remaining conductive hole ring 202 forms the conductive part 21, and the remaining process hole 201 forms the wiring hole 20.

[0088] The accommodating hole 30 can be processed on the substrate 10 by laser ablation or mechanical milling. The accommodating hole 30 coincides with part of the process hole 201, and part of the conductive hole ring 202 is cut off. At this time, the process hole 201 becomes a non-complete circular hole, namely the wiring hole 20, and the remaining conductive hole ring 202 forms the conductive part 21.

[0089] Understandably, the size of the receiving hole 30 needs to be adjusted according to the size of the electronic component 40 to be embedded. During processing, considering the processing accuracy and the convenience of placing the electronic component 40, it is also necessary to pre-enlarge it, such as by 0.025mm.

[0090] By adopting the above solution, it is relatively easy to process embedded holes on the substrate 10, and the area occupied by the embedded holes composed of the wiring holes 20 and the embedded holes is relatively small.

[0091] Please refer to this as well. Figures 7 to 9 Optionally, before placing the electronic components 40 in the embedded holes, the PCB fabrication method further includes:

[0092] The conductive portion 21 that is in contact with the inner wall of the receiving hole 30 is etched away, so that the remaining conductive portion 21 is spaced apart from the inner wall of the receiving hole 30.

[0093] When electronic components 40 are installed in embedded holes, some electronic components 40 are located in receiving holes 30 and some electronic components 40 are located in wiring holes 20.

[0094] This arrangement allows the conductive part 21 to be spaced apart from the inner wall of the receiving hole 30, preventing the conductive part 21 from conducting with the electronic component 40. It also restricts the position of the electronic component 40 at the junction of the inner wall of the receiving hole 30 and the inner wall of the wiring hole 20, while keeping the space occupied by the embedded hole and the electronic component 40 relatively small.

[0095] As an implementable method, the portion where the inner wall of the receiving hole 30 meets the inner wall of the wiring hole 20 abuts against the electronic component 40.

[0096] With this configuration, the position of the electronic component 40 can be restricted by the part where the inner wall of the receiving hole 30 meets the inner wall of the wiring hole 20. This can make the positional precision of the electronic component 40 higher and reduce the processing difficulty of the subsequent fabrication of the through hole for communicating with the electronic component 40.

[0097] Understandably, when the corner of electronic component 40 is located within the wiring hole 20, the portion where the inner wall of the receiving hole 30 intersects with the inner wall of different wiring holes 20 can respectively abut against the two adjacent sidewalls of the corner. When there are four wiring holes 20, they will provide a limiting effect on electronic component 40 from four directions; when there are three wiring holes 20, they will provide a limiting effect on electronic component 40 from three directions, and so on.

[0098] Optionally, when etching away the conductive portion 21 that is in contact with the inner wall of the receiving hole 30, the first circuit layer 11 that is in contact with the inner wall of the receiving hole 30 is also etched away, so that the remaining first circuit layer 11 is spaced apart from the inner wall of the receiving hole 30; and / or, when etching away the conductive portion 21 that is in contact with the inner wall of the receiving hole 30, the second circuit layer 12 that is in contact with the inner wall of the receiving hole 30 is also etched away, so that the remaining second circuit layer 12 is spaced apart from the inner wall of the receiving hole 30.

[0099] This arrangement allows the first circuit layer 11 and / or the second circuit layer 12 to be spaced apart from the inner wall of the receiving hole 30, thus preventing the first circuit layer 11 and / or the second circuit layer 12 from being connected to the electronic component 40.

[0100] It should be noted that the conductive portion 21, the first circuit layer 11, and the second circuit layer 12 that are in contact with the inner wall of the accommodating hole 30 can be removed by alkaline etching. The etching width can be greater than 50 μm, such as 50 μm-60 μm. The etching also removes the burrs generated when the accommodating hole 30 is machined on the substrate 10. When etching away the first circuit layer 11 and the second circuit layer 12 that are in contact with the inner wall of the accommodating hole 30, circuitry can be fabricated on the first circuit layer 11 and the second circuit layer 12 simultaneously.

[0101] As one possible implementation, the conductive portion 21 has an etched surface facing the receiving hole 30; before the receiving hole 30 is formed on the substrate 10, the outer surface of the conductive hole ring 202 is covered with an anti-etching material; when the receiving hole 30 is formed on the substrate 10, part of the anti-etching material is removed so that the surface of the conductive portion 21 facing the receiving hole 30 is exposed; the conductive portion 21 in contact with the inner wall of the receiving hole 30 is removed by etching the surface of the conductive portion 21 facing the receiving hole 30; after the conductive portion 21 in contact with the inner wall of the receiving hole 30 is removed by etching the surface of the conductive portion 21 facing the receiving hole 30, the anti-etching material is removed.

[0102] This configuration allows for the protection of other parts of the conductive part 21 when the conductive part 21 is etched away from the inner wall of the receiving hole 30 via the surface of the conductive part 21 facing the receiving hole 30, thus preventing the etching away of other parts of the conductive part 21 and affecting its conduction of the first circuit layer 11 and the second circuit layer 12.

[0103] It should be noted that the specific material of the etching-resistant material can be determined according to the specific process of etching away the conductive part 21 that is in contact with the inner wall of the accommodating hole 30. For example, when the conductive part 21 that is in contact with the inner wall of the accommodating hole 30 is etched away by alkaline etching, the material of the etching-resistant material can be tin, nickel, tin-nickel alloy, etc.

[0104] It is understandable that when using an anti-etching material to cover the outer surface of the conductive hole ring 202, the anti-etching material can be used to simultaneously cover part of the surface of the first circuit layer 11 and part of the surface of the second circuit layer 12, allowing for full-board tin plating of the substrate 10. When processing the receiving hole 30 on the substrate 10, part of the first circuit layer 11 and part of the second circuit layer 12 are removed, so that the remaining surfaces of the first circuit layer 11 and the second circuit layer 12 facing the receiving hole 30 are exposed. Subsequently, the first circuit layer 11 and the second circuit layer 12 that are in contact with the inner wall of the receiving hole 30 can be removed by etching the surfaces of the first circuit layer 11 and the second circuit layer 12 that are in contact with the inner wall of the receiving hole 30.

[0105] Please refer to Figures 8 to 11 In some embodiments, an insulating matrix 50 is filled between the inner wall of the receiving hole 30 and the electronic component 40, including:

[0106] An insulating resin is filled between the inner wall of the receiving hole 30 and the electronic component 40, and the insulating matrix 50 includes the insulating resin.

[0107] Insulating resin can be filled between the inner wall of the accommodating hole 30 and the electronic component 40 by means of vacuum resin plugging, baking plate curing, grinding plate and polishing.

[0108] By adopting the above scheme, it is relatively convenient to fill the space between the inner wall of the receiving hole 30 and the electronic component 40 with insulating matrix 50, so that the insulating matrix 50 limits the electronic component 40 and completes the embedding of the electronic component 40.

[0109] It should be noted that the insulating resin can be Low CTE (Low Coefficient of Thermal Expansion Resin) resin to improve the reliability of the embedded electronic components 40.

[0110] In another embodiment, an insulating matrix 50 is filled between the inner wall of the receiving hole 30 and the electronic component 40, including:

[0111] An adhesive layer is provided on at least one side of the substrate 10, and the adhesive layer and the substrate 10 are pressed together so that a portion of the adhesive layer melts and fills the gap between the inner wall of the receiving hole 30 and the electronic component 40. The insulating matrix 50 includes at least a portion of the adhesive layer.

[0112] The adhesive layer can be a prepreg, etc.

[0113] By adopting the above scheme, it is relatively easy to fill the space between the inner wall of the receiving hole 30 and the electronic component 40 with insulating matrix 50, so that the insulating matrix 50 limits the electronic component 40.

[0114] It is understood that an adhesive layer is provided on at least one side of the substrate 10, that is, on the side of the first circuit layer 11 opposite to the insulating layer 13 and / or on the side of the second circuit layer 12 opposite to the insulating layer 13.

[0115] In other embodiments, insulating resin can be filled between the inner wall of the accommodating hole 30 and the electronic component 40 first, and then an adhesive layer can be provided on the side of the first circuit layer 11 away from the insulating layer 13 and / or the side of the second circuit layer 12 away from the insulating layer 13. The adhesive layer and the substrate 10 are then pressed together so that a portion of the adhesive layer melts and fills the gap between the inner wall of the accommodating hole 30 and the electronic component 40. The insulating matrix 50 includes insulating resin and at least a portion of the adhesive layer.

[0116] This design ensures that the inner wall of the receiving hole 30 and the electronic component 40 are fully filled with the insulating matrix 50, preventing any depressions.

[0117] Optionally, the length direction of the electronic component 40 is parallel to the arrangement direction of the first circuit layer 11, the insulating layer 13, and the second circuit layer 12.

[0118] This configuration allows the electronic component 40 to occupy a smaller area on a plane perpendicular to the arrangement direction of the first circuit layer 11, the insulating layer 13, and the second circuit layer 12. This not only facilitates independent wiring around the electronic component 40 and increases the wiring density around the electronic component 40, but also ensures that the inner wall of the receiving hole 30 and the electronic component 40 are fully filled with less insulating matrix 50, and the surface of the substrate 10 will not be recessed.

[0119] It is understandable that the thickness of the substrate 10 can be greater than the length of the electronic device, so that the electronic device 40 will not protrude from the board surface after being placed in the embedded hole.

[0120] It should be noted that when the length direction of the electronic component 40 is parallel to the arrangement direction of the first circuit layer 11, the insulating layer 13, and the second circuit layer 12, the electronic component 40 can be a vertical embedded structure. Compared with the traditional horizontal embedded structure that occupies a large planar space and has a large embedding pitch, the PCB provided in this application embodiment has a small planar space occupied by the electronic component 40 and a small pitch, which increases the density of the electronic component 40 without increasing the number of embedded vias connected in series in the network and without increasing additional losses.

[0121] The PCB manufacturing method provided in this application embodiment can reduce the area occupied by embedded holes and electronic components 40, increase the embedding density of electronic components 40, and improve the flatness of the board surface.

[0122] Please refer to Figures 1 to 11 Secondly, embodiments of this application provide a PCB, the PCB including a substrate 10, the substrate 10 including a first circuit layer 11, a second circuit layer 12, and an insulating layer 13 located between the first circuit layer 11 and the second circuit layer 12; the substrate 10 is provided with buried vias, the buried vias penetrating the first circuit layer 11, the insulating layer 13 and the second circuit layer 12, the buried vias including receiving vias 30 and multiple trace vias 20, the axis of the receiving vias 30 being parallel to the axis of the trace vias 20, the multiple trace vias 20 being spaced around the receiving vias 30, and the receiving vias 30 and the trace vias 20 being connected, the inner wall of the trace vias 20 being provided with conductive portions 21, the first circuit layer 11 and / or the second circuit layer 12 being connected to the conductive portions 21; electronic components 40 are disposed in the buried vias, the first circuit layer 11, the second circuit layer 12 and the conductive portions 21 are all spaced apart from the electronic components 40, and the inner wall of the receiving vias 30 and the electronic components 40 are filled with an insulating matrix 50.

[0123] The PCB provided in this application embodiment first has buried vias processed on the substrate 10. These buried vias penetrate the first circuit layer 11, the insulating layer 13, and the second circuit layer 12. Each buried via includes a receiving hole 30 and multiple routing holes 20. The multiple routing holes 20 are spaced around the receiving hole 30 and are connected to it. A conductive portion 21 is provided on the inner wall of each routing hole 20. The first circuit layer 11 and / or the second circuit layer 12 are connected to the conductive portion 21. Then, electronic components 40 are placed within the buried vias. The first circuit layer 11, the second circuit layer 12, and the conductive portion 21 are all spaced apart from the electronic components 40. Finally, an insulating matrix 50 is filled between the inner wall of the receiving hole 30 and the electronic component 40. The insulating matrix 50 supports the electronic component 40. Therefore, the electronic component 40 can be confined in the embedded hole composed of the receiving hole 30 and multiple wiring holes 20 through the insulating matrix 50, thus completing the embedding of the electronic component 40. Moreover, the space occupied by the embedded hole and the electronic component 40 is small. The lines on the first circuit layer 11 and / or the lines on the second circuit layer 12 can be electrically connected to the conductive part 21, thereby allowing independent wiring around the electronic component 40 and increasing the wiring density around the electronic component 40.

[0124] Optionally, some electronic components 40 are located within the receiving hole 30, and some electronic components 40 are located within the wiring hole 20.

[0125] With this configuration, the position of the electronic component 40 can be restricted at the junction of the inner wall of the receiving hole 30 and the inner wall of the wiring hole 20, while the space occupied by the embedded hole and the electronic component 40 is relatively small.

[0126] In some embodiments, the PCB further includes a third circuit layer 60, which is located on the side of the first circuit layer 11 away from the insulating layer 13, and is connected to and electrically conductive with the electronic component 40; and / or, the PCB further includes a fourth circuit layer 70, which is located on the side of the second circuit layer 12 away from the insulating layer 13, and is connected to and electrically conductive with the electronic component 40.

[0127] This configuration facilitates the connection and electrical conduction between the third circuit layer 60 and the fourth circuit layer 70 and the electronic component 40.

[0128] It should be noted that the third circuit layer 60 and / or the fourth circuit layer 70 can be formed by electroplating.

[0129] Please refer to Figure 12In other embodiments, the PCB further includes a first connection layer 61 and a third circuit layer 60. The first connection layer 61 is located between the third circuit layer 60 and the first circuit layer 11. The first connection layer 61 is provided with a first via, and a first conductive material 80 is disposed inside the first via. The third circuit layer 60 and the electronic component 40 are electrically connected through the first conductive material 80. And / or, the PCB further includes a second connection layer 71 and a fourth circuit layer 70. The second connection layer 71 is located between the fourth circuit layer 70 and the second circuit layer 12. The second connection layer 71 is provided with a second via, and a second conductive material is disposed inside the second via. The fourth circuit layer 70 and the electronic component 40 are electrically connected through the second conductive material.

[0130] This configuration facilitates the connection and electrical conduction between the third circuit layer 60 and the electronic component 40 via the first conductive material 80 and / or the fourth circuit layer 70 via the second conductive material.

[0131] It should be noted that the materials of the third circuit layer 60, the fourth circuit layer 70, the first conductive material 80, and the second conductive material can all be copper, silver, or aluminum, etc. The third circuit layer 60 and / or the fourth circuit layer 70 can be copper foil or multilayer boards. The first connecting layer 61 and the second connecting layer 71 can be insulating dielectric layers or substrate layers obtained by laminating prepregs. The first connecting layer 61 and the third circuit layer 60 can be stacked on the substrate 10 and laminated to form an augmented PCB. Then, laser drilling is performed on the augmented PCB to form a first via on the upper surface of the capacitor. Then, the augmented PCB is metallized (plasma desmearing, copper plating, plate electroplating, and via filling electroplating). The first conductive material 80 fills the first via, making the electronic component 40 conductive with the third circuit layer 60. The second connecting layer 71 and the fourth circuit layer 70 can also be made in a similar way. The outer layer circuitry can be fabricated on the added-layer PCB, followed by routine post-processing such as solder masking, lettering, PCB routing, testing, surface treatment, and inspection to complete the PCB manufacturing.

[0132] In other embodiments, when the insulating matrix 50 is filled between the inner wall of the receiving hole 30 and the electronic component 40, the insulating matrix 50 is also provided on the electronic component 40 as the first connecting layer 61 and the second connecting layer 71.

[0133] For example, when the electronic component 40 is a capacitor, after the electronic component 40 is placed in the embedded hole, the lower copper cap of the capacitor is exposed and flush with the lower surface of the substrate 10, and the upper copper cap of the capacitor is covered by the insulating matrix 50 and buried in the substrate 10. Subsequently, the third circuit layer 60 and the fourth circuit layer 70 are formed by electroplating.

[0134] It should be noted that a prepreg (as the first connecting layer 61) and a metal layer (as the third circuit layer 60) can be stacked on only one side of the substrate 10 and then laminated to complete the layering, obtaining a layered PCB. The layered PCB is then drilled to obtain a first via with a diameter of 0.125 mm located on the upper side of the electronic component 40. In other embodiments, a prepreg (as the first connecting layer 61 and the second connecting layer 71) and a metal layer (as the third circuit layer 60 and the fourth circuit layer 70) can be stacked on both sides of the substrate 10, and then the first via and the second via can be processed on the upper and lower sides of the electronic component 40, respectively.

[0135] It is understood that the adhesive layer may include a prepreg, etc., for forming the first bonding layer 61 and / or the second bonding layer 71.

[0136] refer to Figures 1 to 11 Thirdly, embodiments of this application provide a PCB, which is manufactured using the PCB manufacturing method of the first aspect.

[0137] The PCB provided in this application embodiment first has buried vias processed on the substrate 10. These buried vias penetrate the first circuit layer 11, the insulating layer 13, and the second circuit layer 12. Each buried via includes a receiving hole 30 and multiple routing holes 20. The multiple routing holes 20 are spaced around the receiving hole 30 and are connected to it. A conductive portion 21 is provided on the inner wall of each routing hole 20. The first circuit layer 11 and / or the second circuit layer 12 are connected to the conductive portion 21. Then, electronic components 40 are placed within the buried vias. The first circuit layer 11, the second circuit layer 12, and the conductive portion 21 are all spaced apart from the electronic components 40. Finally, an insulating matrix 50 is filled between the inner wall of the receiving hole 30 and the electronic component 40. The insulating matrix 50 supports the electronic component 40. Therefore, the electronic component 40 can be confined in the embedded hole composed of the receiving hole 30 and multiple wiring holes 20 through the insulating matrix 50, thus completing the embedding of the electronic component 40. Moreover, the space occupied by the embedded hole and the electronic component 40 is small. The lines on the first circuit layer 11 and / or the lines on the second circuit layer 12 can be electrically connected to the conductive part 21, thereby allowing independent wiring around the electronic component 40 and increasing the wiring density around the electronic component 40.

[0138] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method of manufacturing a PCB, characterized by, include: A substrate is provided, the substrate including a first circuit layer, a second circuit layer and an insulating layer located between the first circuit layer and the second circuit layer; A buried via is fabricated on the substrate. The buried via penetrates the first circuit layer, the insulating layer, and the second circuit layer. The buried via includes a receiving hole and a plurality of routing holes. The plurality of routing holes are arranged at intervals around the receiving hole, and the receiving hole and the routing holes are connected. A conductive portion is provided on the inner wall of the routing hole, and the first circuit layer and / or the second circuit layer are connected to the conductive portion. Electronic components are disposed within the embedded hole, and the first circuit layer, the second circuit layer, and the conductive part are all spaced apart from the electronic components. An insulating matrix is ​​filled between the inner wall of the receiving hole and the electronic component, and the insulating matrix supports the electronic component.

2. The PCB manufacturing method according to claim 1, characterized in that, The process of fabricating embedded holes on the substrate includes: Multiple process holes are processed on the substrate; A conductive hole ring is provided on the inner wall of the process hole; The receiving hole is processed on the substrate to remove part of the conductive hole ring, the remaining conductive hole ring forms the conductive part, and the remaining process hole forms the wiring hole.

3. The PCB manufacturing method according to claim 2, characterized in that, Before placing electronic components in the embedded holes, the PCB manufacturing method further includes: The conductive portion that is in contact with the inner wall of the receiving hole is etched away, so that the remaining conductive portion is spaced apart from the inner wall of the receiving hole; when electronic components are placed in the embedded hole, some of the electronic components are located in the receiving hole and some of the electronic components are located in the trace hole.

4. The PCB manufacturing method according to claim 3, characterized in that, When etching away the conductive portion that is in contact with the inner wall of the receiving hole, the first circuit layer that is in contact with the inner wall of the receiving hole is also etched away, so that the remaining first circuit layer is spaced apart from the inner wall of the receiving hole; and / or, when etching away the conductive portion that is in contact with the inner wall of the receiving hole, the second circuit layer that is in contact with the inner wall of the receiving hole is also etched away, so that the remaining second circuit layer is spaced apart from the inner wall of the receiving hole.

5. The PCB manufacturing method according to claim 3, characterized in that, The conductive portion has an etched surface facing the receiving hole; before the receiving hole is machined on the substrate, an anti-etching material is used to cover the outer surface of the conductive hole ring; when the receiving hole is machined on the substrate, a portion of the anti-etching material is removed so that the conductive portion facing the receiving hole is exposed; the conductive portion in contact with the inner wall of the receiving hole is removed by etching the surface of the conductive portion facing the receiving hole; after the conductive portion in contact with the inner wall of the receiving hole is removed by etching the surface of the conductive portion facing the receiving hole, the anti-etching material is removed.

6. The method for manufacturing a PCB according to any one of claims 1 to 5, characterized in that, The process of filling the space between the inner wall of the accommodating hole and the electronic component with an insulating matrix includes: An insulating resin is filled between the inner wall of the accommodating hole and the electronic component, and the insulating matrix includes the resin; And / or, an adhesive layer is provided on at least one side of the substrate, and the adhesive layer and the substrate are pressed together such that a portion of the adhesive layer melts and fills the gap between the inner wall of the accommodating hole and the electronic component, wherein the insulating matrix includes at least a portion of the adhesive layer.

7. The method for manufacturing a PCB according to any one of claims 1 to 5, characterized in that, The length direction of the electronic component is parallel to the arrangement direction of the first circuit layer, the insulating layer, and the second circuit layer.

8. A PCB, characterized in that, The PCB includes a substrate, which includes a first circuit layer, a second circuit layer, and an insulating layer located between the first circuit layer and the second circuit layer. The substrate has embedded vias that penetrate the first circuit layer, the insulating layer, and the second circuit layer. Each embedded via includes a receiving hole and multiple routing holes. The axis of the receiving hole is parallel to the axis of the routing holes. The multiple routing holes are spaced apart around the receiving hole and are connected to it. A conductive portion is provided on the inner wall of each routing hole, and the first circuit layer and / or the second circuit layer are connected to the conductive portion. Electronic components are disposed within the embedded vias, with the first circuit layer, the second circuit layer, and the conductive portion spaced apart from the electronic components. An insulating matrix fills the space between the inner wall of the receiving hole and the electronic components.

9. The PCB according to claim 8, characterized in that, Some of the electronic components are located within the receiving hole, and some of the electronic components are located within the wiring hole.

10. The PCB according to claim 8, characterized in that, The PCB further includes a first connection layer and a third circuit layer. The first connection layer is located between the third circuit layer and the first circuit layer. The first connection layer is provided with a first via. A first conductive material is disposed inside the first via. The third circuit layer is electrically connected to the electronic component through the first conductive material. And / or, the PCB further includes a second connection layer and a fourth circuit layer. The second connection layer is located between the fourth circuit layer and the second circuit layer. The second connection layer is provided with a second via. A second conductive material is disposed inside the second via. The fourth circuit layer is electrically connected to the electronic component through the second conductive material.

11. The PCB according to claim 8, characterized in that, The PCB further includes a third circuit layer, which is located on the side of the first circuit layer away from the insulating layer and is connected to and electrically conductive with the electronic components; and / or, the PCB further includes a fourth circuit layer, which is located on the side of the second circuit layer away from the insulating layer and is connected to and electrically conductive with the electronic components.

12. A PCB, characterized in that, The PCB is manufactured by the PCB manufacturing method as described in any one of claims 1 to 7.

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