Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a grid electrode, an active layer and a first grid electrode insulating layer. The active layer is arranged on one side of the grid electrode; the first gate insulating layer is arranged between the gate and the active layer and is in contact with the active layer; wherein the nitrogen content of one side, close to the active layer, in the first gate insulating layer is smaller than that of one side, away from the active layer, in the first gate insulating layer; according to the thin film transistor, the electron transition potential barrier of the side, away from the active layer, of the first gate insulation layer can be improved, so that the off-state leakage current of the thin film transistor is reduced, the electron transition potential barrier of the side, close to the active layer, of the first gate insulation layer is reduced, the on-state current of the thin film transistor can be improved, and the device performance of the thin film transistor is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] An array substrate generally includes a substrate and an array of thin-film transistors formed on the substrate. Thin-film transistors include amorphous silicon (a-Si) thin-film transistors, low-temperature polysilicon (LTPS) thin-film transistors, and oxide semiconductor thin-film transistors. Among them, amorphous silicon (a-Si) thin-film transistors have been widely used due to their significant cost advantages and relatively simple and mature manufacturing process.

[0003] However, the on-state current of amorphous silicon thin-film transistors needs to be improved, and the off-state current needs to be reduced. Summary of the Invention

[0004] This application provides an array substrate and a display panel that can increase the on-state current of thin-film transistors in the array substrate and reduce the off-state leakage current of thin-film transistors.

[0005] This application provides an array substrate, which includes: Gate; An active layer is disposed on one side of the gate; A first gate insulating layer is disposed between the gate and the active layer and is in contact with the active layer; Wherein, the nitrogen content in the first gate insulating layer on the side closer to the active layer is less than the nitrogen content in the first gate insulating layer on the side farther from the active layer.

[0006] In one embodiment of this application, the first gate insulating layer includes a first sub-layer and a second sub-layer, the second sub-layer being located between the first sub-layer and the active layer, and the nitrogen content in the first sub-layer being greater than the nitrogen content in the second sub-layer.

[0007] In one embodiment of this application, the density of the second sublayer is greater than the density of the first sublayer.

[0008] In one embodiment of this application, both the first sublayer and the second sublayer contain nitrogen and silicon elements. The ratio of the number of nitrogen atoms to the number of silicon atoms in the first sublayer is greater than or equal to 8.2 and less than or equal to 8.6, and the ratio of the number of nitrogen atoms to the number of silicon atoms in the second sublayer is greater than or equal to 5.3 and less than or equal to 5.7. Alternatively, the ratio of nitrogen to silicon atoms in the first sublayer is greater than or equal to 8.2 and less than or equal to 8.6, and the ratio of nitrogen to silicon atoms in the second sublayer is greater than or equal to 4 and less than or equal to 4.4. Alternatively, the ratio of nitrogen to silicon atoms in the first sublayer is greater than or equal to 5.3 and less than or equal to 5.7, and the ratio of nitrogen to silicon atoms in the second sublayer is greater than or equal to 4 and less than or equal to 4.4.

[0009] In one embodiment of this application, the first gate insulating layer further includes a third sub-layer, the third sub-layer being located on the side of the first sub-layer away from the second sub-layer, and the nitrogen content in the third sub-layer being greater than or equal to the nitrogen content in the first sub-layer.

[0010] In one embodiment of this application, the density of the third sublayer is less than the density of the first sublayer.

[0011] In one embodiment of this application, the first sublayer, the second sublayer, and the third sublayer all contain nitrogen and silicon. The ratio of nitrogen to silicon atoms in the third sublayer is greater than or equal to 8.2 and less than or equal to 8.6. The ratio of nitrogen to silicon atoms in the first sublayer is greater than or equal to 5.3 and less than or equal to 5.7. The ratio of nitrogen to silicon atoms in the second sublayer is greater than or equal to 4 and less than or equal to 4.4.

[0012] In one embodiment of this application, the array substrate further includes a second gate insulating layer disposed between the first gate insulating layer and the gate, and the nitrogen content in the second gate insulating layer is greater than or equal to the nitrogen content in the first gate insulating layer on the side away from the active layer.

[0013] In one embodiment of this application, the density of the second gate insulating layer on the side closer to the gate is less than the density of the second gate insulating layer on the side farther from the gate.

[0014] In one embodiment of this application, the hydrogen content of the active layer on the side closer to the first gate insulating layer is greater than the hydrogen content of the active layer on the side farther away from the first gate insulating layer.

[0015] In one embodiment of this application, the active layer includes a first active layer and a second active layer stacked together, the first active layer being located between the first gate insulating layer and the second active layer, and the hydrogen content in the first active layer being greater than the hydrogen content in the second active layer.

[0016] In one embodiment of this application, the density of the second active layer is less than the density of the first active layer.

[0017] In one embodiment of this application, the first active layer contains silicon and hydrogen elements, and the ratio of the number of hydrogen atoms to the number of silicon atoms in the first active layer is greater than or equal to 42.2 and less than or equal to 43. And / or, the second active layer contains silicon and hydrogen, and the ratio of the number of hydrogen atoms to the number of silicon atoms in the second active layer is greater than or equal to 12.8 and less than or equal to 13.6.

[0018] In one embodiment of this application, the second active layer includes a third sub-layer and a fourth sub-layer stacked together, the third sub-layer being located between the first active layer and the fourth sub-layer, and the hydrogen content in the third sub-layer being greater than the hydrogen content in the fourth sub-layer; And / or, the ratio of the thickness of the third sublayer to the thickness of the second active layer is greater than or equal to one-quarter and less than or equal to one-third.

[0019] In one embodiment of this application, the array substrate further includes an ohmic contact layer disposed on the active layer, the ohmic contact layer containing phosphorus and silicon elements, wherein the ratio of the number of phosphorus and silicon atoms in the ohmic contact layer is greater than or equal to 4.4 and less than or equal to 4.8.

[0020] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a display panel, the display panel comprising the array substrate described above.

[0021] This application provides an array substrate and a display panel. A first gate insulating layer is disposed between the gate and the active layer and is in contact with the active layer. The nitrogen content on the side of the first gate insulating layer closer to the active layer is less than the nitrogen content on the side of the first gate insulating layer farther from the active layer. This can increase the electron transition barrier on the side of the first gate insulating layer farther from the active layer, thereby reducing the off-state leakage current of the thin-film transistor. Furthermore, reducing the electron transition barrier on the side of the first gate insulating layer closer to the active layer can increase the on-state current of the thin-film transistor and improve the device performance of the thin-film transistor.

[0022] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0024] Figure 1 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application; Figure 2 This is a schematic diagram of another structure of the array substrate provided in an embodiment of this application; Figure 3 A flowchart illustrating the fabrication method of the array substrate provided in this application embodiment; Figure 4 This is a schematic diagram of a display panel provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0026] Please refer to Figure 1 This application provides an array substrate, which includes a gate 10, an active layer 20, and a first gate insulating layer 30.

[0027] An active layer 20 is disposed on one side of a gate 10; a first gate insulating layer 30 is disposed between the gate 10 and the active layer 20 and is in contact with the active layer 20.

[0028] The nitrogen content in the first gate insulating layer 30 near the active layer 20 is less than the nitrogen content in the first gate insulating layer 30 away from the active layer 20.

[0029] In the implementation and application process, in the array substrate provided in this application embodiment, the first gate insulating layer 30 is disposed between the gate 10 and the active layer 20 and is in contact with the active layer 20. The nitrogen content on the side of the first gate insulating layer 30 near the active layer 20 is less than the nitrogen content on the side of the first gate insulating layer 30 away from the active layer 20. This can increase the electron transition barrier on the side of the first gate insulating layer 30 away from the active layer 20, thereby reducing the off-state leakage current of the thin film transistor. Furthermore, reducing the electron transition barrier on the side of the first gate insulating layer 30 near the active layer 20 can increase the on-state current of the thin film transistor and improve the device performance of the thin film transistor.

[0030] Specifically, please refer to Figure 1 The array substrate provided in this application embodiment includes a substrate 71 and a thin-film transistor array layer disposed on the substrate 71.

[0031] In some embodiments, substrate 71 may be a rigid substrate, such as a glass substrate; or substrate 71 may be a flexible substrate, such as a substrate formed of polyimide. When substrate 71 is a flexible substrate, substrate 71 may be formed of multiple sub-substrates of the same material, such as polyimide, and adjacent sub-substrates may be bonded together by adhesive sub-layers.

[0032] In some embodiments, the thin-film transistor array layer includes thin-film transistors disposed on a substrate 71 and an insulating layer spaced between the devices in the thin-film transistors.

[0033] In some embodiments, the thin-film transistor may include a gate 10, an active layer 20, a source 61, and a drain 62. The active layer 20 is located on one side of the gate 10, and the gate 10 may be disposed corresponding to the channel of the active layer 20. The source 61 and the drain 62 are respectively connected to opposite sides of the channel of the active layer 20. By controlling the voltage signal on the gate 10, a current path is formed in the channel of the active layer 20, turning on the source 61 and the drain 62, so that the thin-film transistor is in the on state. Alternatively, by controlling the voltage signal on the gate 10, the channel of the active layer 20 maintains semiconductor characteristics and no current path is formed, so that the source 61 and the drain 62 cannot be connected, so that the thin-film transistor is in the off state.

[0034] In this embodiment of the application, the array substrate further includes a first gate insulating layer 30 disposed between the gate 10 and the active layer 20, and the first gate insulating layer 30 is in contact with the active layer 20.

[0035] In this embodiment, the nitrogen content in the first gate insulating layer 30 near the active layer 20 is less than the nitrogen content in the first gate insulating layer 30 away from the active layer 20. In the array substrate provided in this application embodiment, the first gate insulating layer 30 is disposed between the gate 10 and the active layer 20 and is in contact with the active layer 20. The nitrogen content in the first gate insulating layer 30 near the active layer 20 is less than the nitrogen content in the first gate insulating layer 30 away from the active layer 20. That is to say, the first gate insulating layer 30 increases the nitrogen content on the side near the gate 10, forming a higher electron barrier, so that when the thin film transistor is in the off state, electrons can pass through the source or drain via thermal emission or tunneling. Electrons attempting to pass through the first gate insulating layer 30 are strongly blocked when they encounter this high barrier, thus significantly reducing the off-state leakage current. Furthermore, the nitrogen content of the first gate insulating layer 30 is reduced on the side near the active layer 20, forming a smoother interface and reducing interface defects. This results in a smaller conduction band difference between the first gate insulating layer 30 and the active layer 20, a smoother band transition, and reduced scattering and obstruction encountered by electrons at the interface. This allows electrons to flow more smoothly in the channel, improving carrier mobility and thus increasing the on-state current. Consequently, the thin-film transistors in the array substrate provided in this embodiment of the application simultaneously achieve a larger on-state current and a smaller off-state leakage current.

[0036] In some embodiments, the active layer 20 may be made of a semiconductor material, such as amorphous silicon.

[0037] In some embodiments, the material of the gate 10 may include Al, Ti, Mo, Cu, Ni, or an alloy of the above metals; the materials of the source 61 and the drain 62 may also include Al, Ti, Mo, Cu, Ni, or an alloy of the above metals.

[0038] Furthermore, the structure of the array substrate provided in this application will be described in detail below with reference to specific embodiments.

[0039] Please refer to Figure 1 In one specific embodiment of this application, the thin-film transistor has a bottom gate structure, and the array substrate includes a substrate 71, a gate 10 disposed on the substrate 71, a first gate insulating layer 30 disposed on the side of the gate 10 away from the substrate 71, and an active layer 20 disposed on the side of the first gate insulating layer 30 away from the gate 10.

[0040] The first gate insulating layer 30 is in contact with the active layer 20, and the first gate insulating layer 30 is in contact with or spaced apart from the gate 10.

[0041] The first gate insulating layer 30 includes a first sub-layer 31 and a second sub-layer 32. The second sub-layer 32 is located between the first sub-layer 31 and the active layer 20, and the nitrogen content in the first sub-layer 31 is greater than the nitrogen content in the second sub-layer 32. This makes it possible for the nitrogen content in the first gate insulating layer 30 on the side closer to the active layer 20 to be less than the nitrogen content in the first gate insulating layer 30 on the side farther from the active layer 20.

[0042] In some embodiments, the material of the first gate insulating layer 30 may be silicon nitride or silicon oxynitride, and the first gate insulating layer 30 contains nitrogen and silicon elements.

[0043] In some embodiments, the first gate insulating layer 30 can be obtained by deposition of NH3 and SiH4, for example by chemical vapor deposition. That is, both the first sublayer 31 and the second sublayer 32 can be obtained by deposition of NH3 and SiH4. Furthermore, by controlling the ratio of NH3 and SiH4, the nitrogen-silicon ratio in the first sublayer 31 and the second sublayer 32 can be different, thereby increasing the nitrogen-silicon ratio in the first sublayer 31 and making the nitrogen content in the first sublayer 31 greater than the nitrogen content in the second sublayer 32.

[0044] Furthermore, in some embodiments, both the first sublayer 31 and the second sublayer 32 contain nitrogen and silicon elements, and the ratio of the number of nitrogen atoms to the number of silicon atoms in the first sublayer 31 is greater than the ratio of the number of nitrogen atoms to the number of silicon atoms in the second sublayer 32.

[0045] In some embodiments, both the first sublayer 31 and the second sublayer 32 contain nitrogen and silicon. The ratio of the number of nitrogen atoms to the number of silicon atoms in the first sublayer 31 is greater than or equal to 8.2 and less than or equal to 8.6, for example, it can be 8.2, 8.3, 8.4, 8.5 or 8.6; the ratio of the number of nitrogen atoms to the number of silicon atoms in the second sublayer 32 is greater than or equal to 5.3 and less than or equal to 5.7, for example, it can be 5.3, 5.4, 5.5, 5.6 or 5.7.

[0046] In some embodiments, the ratio of nitrogen to silicon atoms in the first sublayer 31 is greater than or equal to 8.2 and less than or equal to 8.6, for example, it can be 8.2, 8.3, 8.4, 8.5 or 8.6; the ratio of nitrogen to silicon atoms in the second sublayer 32 is greater than or equal to 4 and less than or equal to 4.4, for example, it can be 4, 4.1, 4.2, 4.3 or 4.4.

[0047] In some embodiments, the ratio of nitrogen to silicon atoms in the first sublayer 31 is greater than or equal to 5.3 and less than or equal to 5.7, for example, it can be 5.3, 5.4, 5.5, 5.6 or 5.7; the ratio of nitrogen to silicon atoms in the second sublayer 32 is greater than or equal to 4 and less than or equal to 4.4, for example, it can be 4, 4.1, 4.2, 4.3 or 4.4.

[0048] Furthermore, the density of the second sub-layer 32 is greater than that of the first sub-layer 31. The first sub-layer 31 is located on the side of the first gate insulating layer 30 that is farther from the active layer 20, and is closer to the gate 10 than the second sub-layer 32. Therefore, when the density of the first sub-layer 31 is smaller, the electron mobility can be significantly improved, the subthreshold swing can be reduced, the on / off ratio can be increased, and the metal diffusion in the gate 10 can be suppressed to improve the interface stability.

[0049] Specifically, in this embodiment, a relatively loose and low-density first sub-layer 31 is first formed on the gate 10. The first sub-layer 31 can effectively capture or contain a small number of metal atoms escaping from the surface of the gate 10, "locking" them in the region near the gate 10. The second sub-layer 32 near the active layer 20 can serve as a high-density "blocking layer", forming a dense barrier to prevent the captured metal atoms from continuing to migrate upwards and to prevent any material in the subsequent process from penetrating downwards into the gate 10. The second sub-layer 32 has a dense and smooth surface with few dangling bonds and stable surface energy. The active layer 20 subsequently deposited on the second sub-layer 32 can be arranged more orderly on this flat and inert surface, forming an amorphous network with fewer defects.

[0050] Furthermore, in some embodiments, the first gate insulating layer 30 may further include a third sub-layer 33, which is located on the side of the first sub-layer 31 away from the second sub-layer 32, and the nitrogen content in the third sub-layer 33 is greater than or equal to the nitrogen content in the first sub-layer 31. In this embodiment, by forming a third sub-layer 33 with a higher nitrogen content on the side of the first sub-layer 31 away from the second sub-layer 32, the nitrogen content on the side of the first gate insulating layer 30 away from the active layer 20 can be further increased, forming a higher electron barrier. Thus, when the thin-film transistor is in the off state, electrons attempting to pass through the first gate insulating layer 30 from the source or drain through thermal emission or tunneling will be strongly blocked when they encounter this high barrier, thereby significantly reducing the off-state leakage current.

[0051] In some embodiments, the density of the third sublayer 33 is less than the density of the first sublayer 31; that is, in the embodiments of this application, the density of the first gate insulating layer 30 near the gate 10 can be further reduced to more effectively capture or contain a small number of metal atoms escaping from the surface of the gate 10 and "lock" them in the region near the gate 10.

[0052] In some embodiments, the first sublayer 31, the second sublayer 32, and the third sublayer 33 can all be obtained by deposition of NH3 and SiH4. Furthermore, by controlling the ratio of NH3 and SiH4, the nitrogen-silicon ratio in the first sublayer 31, the second sublayer 32, and the third sublayer 33 can be different, thereby increasing the nitrogen-silicon ratio in the first sublayer 31 and the third sublayer 33, so that the nitrogen content in the third sublayer 33 is greater than the nitrogen content in the first sublayer 31, and the nitrogen content in the first sublayer 31 is greater than the nitrogen content in the second sublayer 32.

[0053] Furthermore, in some embodiments, the first sublayer 31, the second sublayer 32, and the third sublayer 33 all contain nitrogen and silicon elements, the ratio of nitrogen to silicon atoms in the first sublayer 31 is greater than the ratio of nitrogen to silicon atoms in the second sublayer 32, and the ratio of nitrogen to silicon atoms in the third sublayer 33 is greater than the ratio of nitrogen to silicon atoms in the first sublayer 31.

[0054] In some embodiments, the first sublayer 31, the second sublayer 32, and the third sublayer 33 all contain nitrogen and silicon. The ratio of nitrogen to silicon atoms in the third sublayer 33 is greater than or equal to 8.2 and less than or equal to 8.6, for example, it can be 8.2, 8.3, 8.4, 8.5, or 8.6. The ratio of nitrogen to silicon atoms in the first sublayer 31 is greater than or equal to 5.3 and less than or equal to 5.7, for example, it can be 5.3, 5.4, 5.5, 5.6, or 5.7. The ratio of nitrogen to silicon atoms in the second sublayer 32 is greater than or equal to 4 and less than or equal to 4.4, for example, it can be 4, 4.1, 4.2, 4.3, or 4.4.

[0055] In some embodiments, the thickness of the first gate insulating layer 30 is greater than or equal to 1500 angstroms and less than or equal to 2000 angstroms, for example, it can be 1500 angstroms, 1600 angstroms, 1700 angstroms, 1800 angstroms, 1900 angstroms or 2000 angstroms.

[0056] Furthermore, in some embodiments, the array substrate further includes a second gate insulating layer 40 disposed between the first gate insulating layer 30 and the gate 10, wherein the second gate insulating layer 40 covers the gate 10, and the first gate insulating layer 30 is located on the side of the second gate insulating layer 40 away from the gate 10.

[0057] The nitrogen content in the second gate insulating layer 40 is greater than or equal to the nitrogen content in the first gate insulating layer 30 on the side away from the active layer 20. Therefore, by setting the second gate insulating layer 40, the nitrogen content on the side of the gate insulating layer away from the active layer 20 can be further increased, forming a higher electron barrier. As a result, when the thin-film transistor is in the off state, electrons that attempt to pass through the gate insulating layer from the source or drain through thermal emission or tunneling will be strongly blocked when they encounter this high barrier, thereby significantly reducing the off-state leakage current.

[0058] In some embodiments, the density of the second gate insulating layer 40 near the gate 10 is less than the density of the second gate insulating layer 40 away from the gate 10. The second gate insulating layer 40 may include multiple sub-layers. For example, the second gate insulating layer 40 includes a sixth sub-layer near the gate 10 and a seventh sub-layer away from the gate 10, and the density of the seventh sub-layer is greater than the density of the sixth sub-layer. Similarly, in this embodiment, by setting the second gate insulating layer 40, a relatively loose and low-density sixth sub-layer is first formed on the gate 10. The sixth sub-layer can effectively capture or contain a small number of metal atoms escaping from the surface of the gate 10, "locking" them in the area near the gate 10. The seventh sub-layer near the active layer 20 can serve as a high-density "blocking layer," forming a dense barrier that prevents the captured metal atoms from continuing to migrate upwards and also prevents any substances in subsequent processes from penetrating downwards into the gate 10.

[0059] Furthermore, in some embodiments, the hydrogen content on the side of the active layer 20 closer to the first gate insulating layer 30 is greater than the hydrogen content on the side of the active layer 20 farther from the first gate insulating layer 30; wherein, hydrogen binds to silicon single bonds to passivate dangling bonds, thereby reducing the defect state density in the semiconductor layer, which in turn can improve the on-state current of the thin-film transistor.

[0060] It should be noted that the active layer 20 can be made of amorphous silicon, and the active layer 20 can be obtained by deposition of H2 and SiH4, and can also be prepared by chemical vapor deposition. Furthermore, by controlling the ratio of H2 and SiH4 during the deposition of the active layer 20, the hydrogen-silicon ratio of the active layer 20 at different locations or regions can be made different, thereby increasing the hydrogen content of the active layer 20 on the side close to the first gate insulating layer 30.

[0061] In some embodiments, the active layer 20 includes a first active layer 21 and a second active layer 22 stacked together. The first active layer 21 is located between the first gate insulating layer 30 and the second active layer 22, and the hydrogen content in the first active layer 21 is greater than the hydrogen content in the second active layer 22. In this embodiment, by increasing the hydrogen content in the first active layer 21 near the first gate insulating layer 30, hydrogen can be combined with silicon single bonds to passivate dangling bonds and reduce the defect state density in the semiconductor layer, thereby increasing the on-state current of the thin film transistor.

[0062] Furthermore, the density of the second active layer 22 is less than that of the first active layer 21; this can increase the deposition rate of the second active layer 22 and reduce the preparation time of the active layer 20.

[0063] In some embodiments, both the first active layer 21 and the second active layer 22 can be obtained by deposition of H2 and SiH4, and can also be prepared by chemical vapor deposition. Furthermore, by controlling the ratio of H2 and SiH4 during the deposition of the active layer 20, the hydrogen content in the first active layer 21 can be made greater than the hydrogen content in the second active layer 22.

[0064] In some embodiments, the first active layer 21 contains silicon and hydrogen elements, and the ratio of the number of hydrogen atoms to the number of silicon atoms in the first active layer 21 is greater than or equal to 42.2 and less than or equal to 43, for example, it can be 42.2, 42.3, 42.4, 42.5, 42.6, 42.7, 42.8, 42.9 or 43.

[0065] In some embodiments, the second active layer 22 contains silicon and hydrogen elements, and the ratio of the number of hydrogen atoms to the number of silicon atoms in the second active layer 22 is greater than or equal to 12.8 and less than or equal to 13.6, for example, it can be 12.8, 12.9, 13, 13.1, 13.2, 13.3, 13.4, 13.5 or 13.6.

[0066] In some embodiments, the second active layer 22 includes a fourth sublayer 221 and a fifth sublayer 222 stacked together, the fourth sublayer 221 being located between the first active layer 21 and the fifth sublayer 222, and the hydrogen content in the fourth sublayer 221 being greater than the hydrogen content in the fifth sublayer 222.

[0067] It should be noted that when the fourth sublayer 221 is deposited on the side of the first active layer 21 away from the first gate insulating layer 30, hydrogen plasma can be used to treat the fourth sublayer 221 to increase the hydrogen content in the fourth sublayer 221, passivate the dangling bonds in the fourth sublayer 221, thereby reducing the defect state density in the fourth sublayer 221 and increasing the on-state current.

[0068] In some embodiments, the ratio of the thickness of the fourth sublayer 221 to the thickness of the second active layer 22 is greater than or equal to one-quarter and less than or equal to one-third.

[0069] In some embodiments, the density of the fourth sublayer 221 is greater than the density of the fifth sublayer 222; that is, in this embodiment, the thickness of the fourth sublayer 221 with a higher density is set to be smaller, while the thickness of the fifth sublayer 222 with a lower density is set to be larger, which is beneficial to improve the deposition rate of the second active layer 22 and reduce the preparation time of the active layer 20.

[0070] In some embodiments, the thickness of the first active layer 21 can be greater than or equal to 20 angstroms and less than or equal to 50 angstroms, for example, it can be 20 angstroms, 25 angstroms, 30 angstroms, 35 angstroms, 40 angstroms, 45 angstroms or 50 angstroms; the thickness of the second active layer 22 can be greater than or equal to 700 angstroms and less than or equal to 900 angstroms, for example, it can be 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms or 900 angstroms.

[0071] In some embodiments, the array substrate further includes an ohmic contact layer 50 disposed on the active layer 20, and the ohmic contact layer 50 is disposed on the side of the active layer 20 away from the first gate insulating layer 30, and may further be located on the side of the second active layer 22 away from the first active layer 21.

[0072] In some embodiments, the ohmic contact layer 50 includes a first contact portion 51 and a second contact portion 52 located on both sides of the channel of the active layer 20, wherein the first contact portion 51 is located on the side of the active layer 20 away from the second gate insulating layer 40, and the second contact portion 52 is located on the side of the active layer 20 away from the second gate insulating layer 40; the array substrate further includes a source electrode 61 and a drain electrode 62 disposed on the side of the active layer 20 away from the first gate insulating layer 30, wherein the source electrode 61 is located on the side of the first contact portion 51 away from the active layer 20 and is connected to the first contact portion 51, and the drain electrode 62 is located on the side of the second contact portion 52 away from the active layer 20 and is connected to the second contact portion 52.

[0073] It should be noted that, in the embodiments of this application, the ohmic contact layer 50 can be formed by depositing phosphorus (P) doped amorphous silicon material in the region on both sides of the channel on the active layer 20, so as to reduce the contact barrier between the source 61, drain 62 and the active layer 20, increase the tunneling probability, and improve the on-state current of the thin film transistor.

[0074] In some embodiments, the ohmic contact layer 50 contains phosphorus and silicon elements, and the ratio of the number of phosphorus and silicon atoms in the ohmic contact layer 50 is greater than or equal to 4.4 and less than or equal to 4.8, for example, 4.4, 4.5, 4.6, 4.7 or 4.8; that is, the embodiments of this application can further increase the phosphorus content in the ohmic contact layer 50, which can further reduce the contact barrier between the source 61, drain 62 and active layer 20, increase the tunneling probability, and thus increase the on-state current of the thin film transistor.

[0075] In some embodiments, a groove 201 is formed on the side of the active layer 20 away from the gate 10, and the groove 201 is located between the source 61 and the drain 62. The groove 201 is formed by removing the portion of the active layer 20 away from the gate 10. Since chlorine gas residue is generated during the etching process of the source 61 and the drain 62, in this embodiment, after the source 61 and the drain 62 are formed, the portion of the active layer 20 located in the channel is further patterned to form the groove 201. This can simultaneously remove the residual chlorine gas, thereby reducing or avoiding damage to the channel of the active layer 20 by the residual chlorine gas and reducing the off-state leakage current of the thin film transistor.

[0076] In some embodiments, the array substrate further includes a passivation layer 72 disposed on the side of the source 61 and drain 62 away from the active layer 20, and the passivation layer 72 covers the source 61, drain 62, the channel of the active layer 20 and the second gate insulating layer 40 not covered by the active layer 20.

[0077] Following on, Figure 1 In the illustrated embodiment, the thin-film transistor in the array substrate is a bottom-gate structure, while the thin-film transistor in the array substrate provided in this application embodiment can also be a top-gate structure. It should be noted that, regardless of whether it is a top-gate structure or a bottom-gate structure, the nitrogen content on the side of the first gate insulating layer 30 near the active layer 20 is less than the nitrogen content on the side of the first gate insulating layer 30 away from the active layer 20, and the hydrogen content on the side of the active layer 20 near the first gate insulating layer 30 is greater than the hydrogen content on the side of the active layer 20 away from the first gate insulating layer 30. The first gate insulating layer 30 is located between the active layer 20 and the gate 10, and the first gate insulating layer 30 is in contact with the active layer 20.

[0078] In another embodiment of this application, please refer to Figure 2 This implementation method is the same as Figure 1 The difference in the embodiment shown is that the thin-film transistor in this embodiment has a top-gate structure.

[0079] In this embodiment, the active layer 20 is disposed on the substrate 71, and the gate 10 is located on the side of the active layer 20 away from the substrate 71. The source 61 and the drain 62 are respectively connected to both sides of the channel of the active layer 20.

[0080] The array substrate includes a substrate 71, an active layer 20 disposed on the substrate 71, a first gate insulating layer 30 disposed on the substrate 71 and covering the active layer 20, a second gate insulating layer 40 disposed on the side of the first gate insulating layer 30 away from the substrate 71, a gate 10 disposed on the side of the second gate insulating layer 40 away from the first gate insulating layer 30, an interlayer dielectric layer 73 disposed on the side of the second gate insulating layer 40 away from the first gate insulating layer 30 and covering the gate 10, and a source 61 and a drain 62 disposed on the side of the interlayer dielectric layer 73 away from the second gate insulating layer 40.

[0081] In some embodiments, the active layer 20 includes a first active layer 21 and a second active layer 22 stacked together, with the second active layer 22 located between the first active layer 21 and the substrate 71. It should be noted that the element content, materials, and thicknesses of the first active layer 21 and the second active layer 22 can be related to... Figure 1 The same applies to the embodiments shown, and will not be repeated here.

[0082] In some embodiments, the second active layer 22 includes a fourth sublayer 221 and a fifth sublayer 222 stacked together, with the fourth sublayer 221 located between the first active layer 21 and the fifth sublayer 222. It should be noted that the element content, material, and thickness of the fourth sublayer 221 and the fifth sublayer 222 can be related to... Figure 1 The same applies to the embodiments shown, and will not be repeated here.

[0083] In some embodiments, the first gate insulating layer 30 is disposed on the side of the first active layer 21 away from the second active layer 22, and the nitrogen content of the first gate insulating layer 30 on the side closer to the active layer 20 is less than the nitrogen content of the first gate insulating layer 30 on the side away from the active layer 20, and the hydrogen content of the active layer 20 on the side closer to the first gate insulating layer 30 is greater than the hydrogen content of the active layer 20 on the side away from the first gate insulating layer 30.

[0084] In some embodiments, the first gate insulating layer 30 may include a second sub-layer 32, a first sub-layer 31, and a third sub-layer 33 stacked together, wherein the second sub-layer 32 is located on the side of the first active layer 21 away from the second active layer 22, the first sub-layer 31 is located on the side of the second sub-layer 32 away from the first active layer 21, and the third sub-layer 33 is located on the side of the first sub-layer 31 away from the second sub-layer 32; it should be noted that the element content, material, and thickness of the second sub-layer 32, the first sub-layer 31, and the third sub-layer 33 can all be related to... Figure 1 The same applies to the embodiments shown, and will not be repeated here.

[0085] In some embodiments, the second gate insulating layer 40 is disposed on the side of the third sub-layer 33 away from the first sub-layer 31. Similarly, the element content, material, and thickness of the second gate insulating layer 40 can be related to... Figure 1 The same applies to the embodiments shown, and will not be repeated here.

[0086] In some embodiments, the gate 10 is disposed on the side of the second gate insulating layer 40 away from the first gate insulating layer 30, and the interlayer dielectric layer 73 covers the gate 10, while the source 61 and drain 62 are disposed on the side of the interlayer dielectric layer 73 away from the second gate insulating layer 40.

[0087] In summary, in the array substrate provided in this application embodiment, the first gate insulating layer 30 is disposed between the gate 10 and the active layer 20 and is in contact with the active layer 20. The nitrogen content on the side of the first gate insulating layer 30 near the active layer 20 is less than the nitrogen content on the side of the first gate insulating layer 30 away from the active layer 20. This can increase the electron transition barrier on the side of the first gate insulating layer 30 away from the active layer 20, thereby reducing the off-state current. Furthermore, reducing the electron transition barrier on the side of the first gate insulating layer 30 near the active layer 20 can improve interface characteristics and thus increase the on-state current.

[0088] In addition, embodiments of this application also provide a method for fabricating an array substrate, and embodiments of this application use... Figure 1 For the purposes of this explanation, please refer to the following embodiments. Figure 1 and Figure 3 The methods for fabricating the array substrate include: S10, forming gate 10.

[0089] S20. A first gate insulating layer 30 is formed on one side of the gate 10. The nitrogen content in the first gate insulating layer 30 on the side away from the gate 10 is less than the nitrogen content in the first gate insulating layer 30 on the side closer to the gate 10.

[0090] S30, an active layer 20 is formed on the side of the first gate insulating layer 30 away from the gate 10, and the first gate insulating layer 30 is in contact with the active layer 20.

[0091] Specifically, in step S10, firstly, a substrate 71 is provided.

[0092] In some embodiments, substrate 71 may be a rigid substrate, such as a glass substrate; or substrate 71 may be a flexible substrate, such as a substrate formed of polyimide. When substrate 71 is a flexible substrate, substrate 71 may be formed of multiple sub-substrates of the same material, such as polyimide, and adjacent sub-substrates may be bonded together by adhesive sub-layers.

[0093] Next, a conductive material layer is formed on the substrate 71, and the conductive material layer is patterned to form a gate 10 on the substrate 71.

[0094] In some embodiments, the material of the gate 10 may include Al, Ti, Mo, Cu, Ni, or an alloy of the above metals.

[0095] In step S20, a second gate insulating layer 40 covering the gate 10 is formed on the substrate 71 using NH3 and SiH4.

[0096] It should be noted that the second gate insulating layer 40 can be deposited in two steps. For example, the sixth sublayer is deposited in the first step and the seventh sublayer is deposited in the second step, and the density of the sixth sublayer is less than that of the seventh sublayer. Similarly, in this embodiment, by setting the second gate insulating layer 40, a relatively loose and low-density sixth sublayer is first formed on the gate 10. The sixth sublayer can effectively capture or contain a small number of metal atoms escaping from the surface of the gate 10, "locking" them in the area close to the gate 10. The seventh sublayer close to the active layer 20 can serve as a high-density "blocking layer", forming a dense barrier to prevent the captured metal atoms from continuing to migrate upward and to prevent any substances in the subsequent process from penetrating downward into the gate 10.

[0097] Next, a third sublayer 33 is formed by depositing NH3 and SiH4 on the side of the second gate insulating layer 40 away from the substrate 71. The molar ratio of NH3 and SiH4 is greater than or equal to 8.2 and less than or equal to 8.6, for example, it can be 8.4. Then the element ratio Si:N:H in the third sublayer 33 is 1:8.4:29.2.

[0098] Next, NH3 and SiH4 are deposited on the side of the third sublayer 33 away from the gate 10 to form the first sublayer 31. The molar ratio of NH3 and SiH4 is greater than or equal to 5.3 and less than or equal to 5.7, for example, it can be 5.5. Then the element ratio Si:N:H in the second sublayer 32 is 1:5.1:20.5.

[0099] A second sublayer 32 is formed by depositing NH3 and SiH4 on the side of the first sublayer 31 away from the third sublayer 33. The molar ratio of NH3 and SiH4 is greater than or equal to 4 and less than or equal to 4.4, for example, it can be 4.2. Then the element ratio of Si:N:H in the second sublayer 32 is 1:4.2:16.6. The third sublayer 33, the first sublayer 31 and the second sublayer 32 are stacked to form the first gate insulating layer 30.

[0100] Among them, the density of the third sublayer 33 is less than the density of the first sublayer 31, and the density of the first sublayer 31 is less than the density of the second sublayer 32.

[0101] It is understood that in the embodiments of this application, a relatively loose and low-density third sub-layer 33 is first formed in the first gate insulating layer 30. The third sub-layer 33 can effectively capture or contain a small number of metal atoms escaping from the gate 10, "locking" them in the region near the gate 10. The second sub-layer 32 near the active layer 20 can serve as a high-density "blocking layer", forming a dense barrier to prevent the captured metal atoms from continuing to migrate upwards and to prevent any material in the subsequent process from penetrating downwards into the gate 10. Furthermore, the second sub-layer 32 has a dense and smooth surface with few dangling bonds and stable surface energy. The active layer 20 subsequently deposited on the second sub-layer 32 can be arranged more orderly on this flat and inert surface, forming an amorphous network with fewer defects.

[0102] In step S30, H2 and SiH4 are used to form a first active layer 21 on the side of the first gate insulating layer 30 away from the gate 10. The molar ratio of H2 and SiH4 is greater than or equal to 19.1 and less than or equal to 19.5, for example, it can be 19.3. Then the element ratio Si:H in the first active layer 21 is 1:42.6. A second active layer 22 is formed on the side of the first active layer 21 away from the first gate insulating layer 30 using H2 and SiH4. The molar ratio of H2 to SiH4 is greater than or equal to 4.4 and less than or equal to 4.8, for example, it can be 4.6. Then the element ratio Si:H in the second active layer 22 is 1:13.2. And the first active layer 21 and the second active layer 22 are stacked to form an active layer 20.

[0103] The hydrogen content on the side of the active layer 20 closer to the first gate insulating layer 30 is greater than the hydrogen content on the side of the active layer 20 farther from the first gate insulating layer 30. The hydrogen combines with silicon single bonds to passivate dangling bonds, thereby reducing the defect state density in the semiconductor layer and thus increasing the on-state current of the thin film transistor.

[0104] Furthermore, the density of the second active layer 22 is less than that of the first active layer 21; this can increase the deposition rate of the second active layer 22 and reduce the preparation time of the active layer 20.

[0105] Specifically, in the step of forming the second active layer 22, H2 and SiH4 can be used to deposit the fourth sub-layer 221 on the side of the first active layer 21 away from the first gate insulating layer 30.

[0106] Next, hydrogen plasma can be used to treat the fourth sublayer 221 to increase the hydrogen content in the fourth sublayer 221, passivate the dangling bonds in the fourth sublayer 221, thereby reducing the defect state density in the fourth sublayer 221 and increasing the on-state current.

[0107] Then, H2 and SiH4 are used in the fifth sublayer 222 on the side of the fourth sublayer 221 away from the first active layer 21, and the hydrogen content in the fourth sublayer 221 is greater than the hydrogen content in the fifth sublayer 222.

[0108] The fourth sublayer 221 and the fifth sublayer 222 are stacked to form the second active layer 22.

[0109] In some embodiments, the ratio of the thickness of the fourth sublayer 221 to the thickness of the second active layer 22 is greater than or equal to one-quarter and less than or equal to one-third.

[0110] In some embodiments, the density of the fourth sublayer 221 is greater than the density of the fifth sublayer 222; that is, in this embodiment, the thickness of the fourth sublayer 221 with a higher density is set to be smaller, while the thickness of the fifth sublayer 222 with a lower density is set to be larger, which is beneficial to improve the deposition rate of the second active layer 22 and reduce the preparation time of the active layer 20.

[0111] It should be noted that the first gate insulating layer 30 is disposed between the gate 10 and the active layer 20 and is in contact with the active layer 20. The nitrogen content in the first gate insulating layer 30 on the side closer to the active layer 20 is less than the nitrogen content on the side farther from the active layer 20. In other words, the first gate insulating layer 30 has a higher nitrogen content on the side closer to the gate 10, forming a higher electron barrier. Therefore, when the thin-film transistor is in the off state, electrons attempting to pass through the first gate insulating layer 30 from the source or drain via thermionic emission or tunneling will be strongly deflected when they encounter this high barrier. The blocking significantly reduces the off-state leakage current. Furthermore, the nitrogen content of the first gate insulating layer 30 is reduced on the side near the active layer 20 to form a smoother interface and reduce interface defects. This reduces the conduction band difference between the first gate insulating layer 30 and the active layer 20, resulting in a smoother band transition. This reduces the scattering and obstruction encountered by electrons at the interface, allowing electrons to flow more smoothly in the channel and improving carrier mobility, thereby increasing the on-state current. Consequently, the thin-film transistors in the array substrate provided in this application embodiment can simultaneously achieve a larger on-state current and a smaller off-state leakage current.

[0112] In some embodiments, the method of fabricating the array substrate includes: forming an ohmic contact layer 50 on the active layer 20 using PH3 and SiH4, specifically forming the ohmic contact layer 50 on the side of the active layer 20 away from the first gate insulating layer 30.

[0113] In some embodiments, the ohmic contact layer 50 includes a first contact portion 51 and a second contact portion 52 located on both sides of the channel of the active layer 20, wherein the first contact portion 51 is located on the side of the active layer 20 away from the second gate insulating layer 40, and the second contact portion 52 is located on the side of the active layer 20 away from the second gate insulating layer 40.

[0114] In some embodiments, the molar ratio of PH3 and SiH4 used to form the ohmic contact layer 50 is greater than or equal to 4.4 and less than or equal to 4.8, for example, it can be 4.6, then the element ratio P:Si:H in the formed ohmic contact layer 50 is 4.6:1:17.8.

[0115] Then, a source electrode 61 and a drain electrode 62 are formed on the side of the ohmic contact layer 50 away from the active layer 20. The source electrode 61 is located on the side of the first contact portion 51 away from the active layer 20 and is connected to the first contact portion 51. The drain electrode 62 is located on the side of the second contact portion 52 away from the active layer 20 and is connected to the second contact portion 52.

[0116] It should be noted that, in the embodiments of this application, the ohmic contact layer 50 can be formed by depositing phosphorus (P) doped amorphous silicon material in the region on both sides of the channel on the active layer 20, so as to reduce the contact barrier between the source 61, drain 62 and the active layer 20, increase the tunneling probability, and improve the on-state current of the thin film transistor.

[0117] Furthermore, the portion of the channel of the active layer 20 away from the gate 10 is removed to form a groove 201. Since chlorine gas residue is generated during the dry etching process of the source 61 and drain 62, in this embodiment, after the source 61 and drain 62 are formed, the portion of the active layer 20 located in the channel is further patterned to simultaneously remove the residual chlorine gas, thereby reducing or avoiding damage to the channel of the active layer 20 by the residual chlorine gas, which can reduce the off-state leakage current of the thin film transistor, and in this process, a groove 201 is formed at the channel of the active layer 20.

[0118] Next, a passivation layer 72 is formed on the source 61 and the drain 62. The passivation layer 72 covers the source 61, the drain 62, the channel of the active layer 20, and the first gate insulating layer 30 not covered by the active layer 20.

[0119] It should be noted that in the above-described method for fabricating the array substrate, the substrate 71, gate 10, second gate insulating layer 40, first gate insulating layer 30, active layer 20, ohmic contact layer 50, source 61, drain 62, and passivation layer 72 are described in the previous section. Figure 1 The specific implementation shown will be configured as described, and will not be repeated here.

[0120] Additionally, please refer to Figure 4This application also provides a display panel, which includes the array substrate 81 as described in the above embodiments.

[0121] The display panel also includes a display function device 82 disposed on one side of the array substrate 81, which cooperates with the array substrate 81 to realize the display function of the display panel.

[0122] In some embodiments, the display panel may be a liquid crystal display panel, and the display function device 82 may include a liquid crystal layer disposed on the array substrate 81 and a color filter substrate disposed on the side of the liquid crystal layer away from the array substrate.

[0123] In some embodiments, the display panel may also be an organic light-emitting diode display panel, and the display functional device 82 may include an organic light-emitting functional layer, an encapsulation layer, and a touch layer disposed on the array substrate 81.

[0124] In some embodiments, the display panel can be applied to mobile phones, computers, tablets, televisions, wearable devices, and virtual reality display devices, etc.

[0125] It is understood that since the display panel has the same array substrate as in the above embodiments, the display panel also has the same beneficial effects as the array substrate, which will not be repeated here.

[0126] In addition, this application embodiment also provides a display device, and the display device includes the display panel described in the above embodiments.

[0127] In some embodiments, the display device may be a mobile phone, computer, tablet, television, wearable device, or virtual reality display device, etc.

[0128] It is understood that since the display device has the same array substrate as in the above embodiments, the display device also has the same beneficial effects as the array substrate, which will not be repeated here.

[0129] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0130] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0131] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0132] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, characterized in that, include: Gate; An active layer is disposed on one side of the gate; A first gate insulating layer is disposed between the gate and the active layer and is in contact with the active layer; Wherein, the nitrogen content in the first gate insulating layer on the side closer to the active layer is less than the nitrogen content in the first gate insulating layer on the side farther from the active layer.

2. The array substrate according to claim 1, characterized in that, The first gate insulating layer includes a first sub-layer and a second sub-layer, the second sub-layer being located between the first sub-layer and the active layer, and the nitrogen content in the first sub-layer being greater than the nitrogen content in the second sub-layer.

3. The array substrate according to claim 2, characterized in that, The density of the second sublayer is greater than the density of the first sublayer.

4. The array substrate according to claim 2, characterized in that, Both the first sublayer and the second sublayer contain nitrogen and silicon. The ratio of nitrogen to silicon atoms in the first sublayer is greater than or equal to 8.2 and less than or equal to 8.6, and the ratio of nitrogen to silicon atoms in the second sublayer is greater than or equal to 5.3 and less than or equal to 5.

7. Alternatively, the ratio of nitrogen to silicon atoms in the first sublayer is greater than or equal to 8.2 and less than or equal to 8.6, and the ratio of nitrogen to silicon atoms in the second sublayer is greater than or equal to 4 and less than or equal to 4.

4. Alternatively, the ratio of nitrogen to silicon atoms in the first sublayer is greater than or equal to 5.3 and less than or equal to 5.7, and the ratio of nitrogen to silicon atoms in the second sublayer is greater than or equal to 4 and less than or equal to 4.

4.

5. The array substrate according to claim 2, characterized in that, The first gate insulating layer further includes a third sub-layer, which is located on the side of the first sub-layer away from the second sub-layer, and the nitrogen content in the third sub-layer is greater than or equal to the nitrogen content in the first sub-layer.

6. The array substrate according to claim 5, characterized in that, The density of the third sublayer is less than the density of the first sublayer.

7. The array substrate according to claim 2, characterized in that, The first sublayer, the second sublayer, and the third sublayer all contain nitrogen and silicon. The ratio of nitrogen to silicon atoms in the third sublayer is greater than or equal to 8.2 and less than or equal to 8.

6. The ratio of nitrogen to silicon atoms in the first sublayer is greater than or equal to 5.3 and less than or equal to 5.

7. The ratio of nitrogen to silicon atoms in the second sublayer is greater than or equal to 4 and less than or equal to 4.

4.

8. The array substrate according to claim 1, characterized in that, The array substrate further includes a second gate insulating layer disposed between the first gate insulating layer and the gate, wherein the nitrogen content in the second gate insulating layer is greater than or equal to the nitrogen content in the first gate insulating layer on the side away from the active layer.

9. The array substrate according to claim 8, characterized in that, The density of the second gate insulating layer on the side closer to the gate is less than the density of the second gate insulating layer on the side farther from the gate.

10. The array substrate according to any one of claims 1 to 9, characterized in that, The hydrogen content on the side of the active layer closer to the first gate insulating layer is greater than the hydrogen content on the side of the active layer farther from the first gate insulating layer.

11. The array substrate according to any one of claims 1 to 9, characterized in that, The active layer includes a first active layer and a second active layer stacked together. The first active layer is located between the first gate insulating layer and the second active layer, and the hydrogen content in the first active layer is greater than the hydrogen content in the second active layer.

12. The array substrate according to claim 11, characterized in that, The density of the second active layer is less than the density of the first active layer.

13. The array substrate according to claim 11, characterized in that, The first active layer contains silicon and hydrogen, and the ratio of the number of hydrogen atoms to the number of silicon atoms in the first active layer is greater than or equal to 42.2 and less than or equal to 43. And / or, the second active layer contains silicon and hydrogen, and the ratio of the number of hydrogen atoms to the number of silicon atoms in the second active layer is greater than or equal to 12.8 and less than or equal to 13.

6.

14. The array substrate according to claim 11, characterized in that, The second active layer includes a third sublayer and a fourth sublayer stacked together, wherein the third sublayer is located between the first active layer and the fourth sublayer, and the hydrogen content in the third sublayer is greater than the hydrogen content in the fourth sublayer; And / or, the ratio of the thickness of the third sublayer to the thickness of the second active layer is greater than or equal to one-quarter and less than or equal to one-third.

15. The array substrate according to any one of claims 1 to 9, characterized in that, The array substrate further includes an ohmic contact layer disposed on the active layer, the ohmic contact layer containing phosphorus and silicon elements, wherein the ratio of the number of phosphorus and silicon atoms in the ohmic contact layer is greater than or equal to 4.4 and less than or equal to 4.

8.

16. A display panel, characterized in that, The display panel includes an array substrate as described in any one of claims 1 to 15.

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