A power semiconductor wafer electrical parameter testing system and testing method

Abstract

The application relates to the technical field of power semiconductor wafer testing, and discloses a power semiconductor wafer electric parameter testing system and a testing method. The system comprises: a dynamic testing device and a wafer bearing device electrically connected, a static testing device and the wafer bearing device electrically connected, a wafer bearing device electrically connected switching device, the switching device electrically connected with the static testing device and the dynamic testing device respectively, a control device electrically connected with the switching device and used for controlling the switching device to turn on the wafer bearing device and the dynamic testing device or turn on the wafer bearing device and the static testing device. The application can complete two types of tests by using only one testing needle seat without replacing the testing system, can complete two types of tests by pressing a needle once, and reduces the damage of the wafer.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor wafer testing technology, and specifically to a power semiconductor wafer electrical parameter testing system and testing method. Background Technology

[0002] With the widespread application of third-generation wide-bandgap power semiconductors in new energy vehicles, higher reliability requirements have been placed on power semiconductor devices. These automotive-grade power semiconductor devices need to undergo rigorous standard testing. Dynamic parameter testing and static parameter testing have become important screening procedures. Third-generation wide-bandgap power semiconductors have faster turn-on and turn-off speeds and lower leakage current. Therefore, in order to accurately characterize the device characteristics during device screening testing, the parasitic stray inductance of the dynamic test circuit is required to be lower, and the static leakage current test needs to have higher testing accuracy and stability, reaching nanoampere or even picoampere accuracy.

[0003] In traditional technologies, due to the difficulty in suppressing stray inductance, dynamic parameter testing is usually performed after the wafer is cut into individual bare dies or after it is packaged into finished transistors. The problem with this is that the testing equipment for bare dies is very expensive, and performing dynamic testing after packaging further increases the cost of packaging.

[0004] In recent years, advancements in suppressing stray inductance during wafer testing have made dynamic testing of wafers possible. However, no solution exists for simultaneously performing dynamic and static parameter testing on power semiconductor wafers. This is because dynamic parameter testing requires extremely low parasitic parameters, while static parameter testing requires excellent leakage current shielding. Furthermore, the probe station only has one station, necessitating a test module that integrates both dynamic and static parameter testing functions, which are often difficult to reconcile.

[0005] Therefore, in related technologies, dynamic parameter testing and static parameter testing of wafers are performed at different workstations. However, testing at two workstations requires the wafer to be pressed twice, which will aggravate the damage to the wafer surface. Summary of the Invention

[0006] This invention provides a power semiconductor wafer electrical parameter testing system and method to solve the problem that dynamic and static testing require two indentation tests, which can cause increased wafer damage.

[0007] In a first aspect, the present invention provides a power semiconductor wafer electrical parameter testing system, the system comprising:

[0008] A dynamic testing device is electrically connected to a wafer carrier, and the dynamic testing device is used to measure dynamic parameters during dynamic testing;

[0009] A static testing device is electrically connected to the wafer carrier device, and the static testing device is used to acquire static parameters during static testing;

[0010] The wafer carrier device is electrically connected to the switching device, and the wafer carrier device is used to carry the wafer and is electrically connected to the wafer;

[0011] A switching device is electrically connected to the static test equipment and the dynamic test equipment respectively. The switching device is used to selectively connect the wafer carrier device and the dynamic test equipment, or the wafer carrier device and the static test equipment.

[0012] A control device electrically connected to the switching device, the control device being used to control the switching device to be in a first working state, connecting the wafer carrier and the dynamic testing device, or to control the switching device to be in a second working state, connecting the wafer carrier and the static testing device.

[0013] By selectively connecting dynamic and static test equipment to the wafer carrier under the control of the switching device, a static or dynamic test loop can be formed during wafer testing by switching the connected equipment of the wafer carrier. During dynamic testing, the wafer carrier and dynamic test equipment are combined to complete the dynamic test, and during static testing, the wafer carrier and static test equipment are combined to complete the static test. The two types of tests can be completed without changing the test system, and both types of tests can be completed with a single probe, reducing wafer damage.

[0014] In one optional embodiment, the wafer carrier includes a test socket, and the switching device includes a switching switch, a first switching relay, a second switching relay, a third switching relay, and a fourth switching relay.

[0015] One end of the switching switch is electrically connected to the test socket, and the other end is electrically connected to the dynamic testing equipment;

[0016] The common terminals of the first switching relay, the second switching relay, the third switching relay, and the fourth switching relay are all electrically connected to the test socket. The static terminals of the first switching relay, the second switching relay, the third switching relay, and the fourth switching relay are all electrically connected to the static test equipment. The dynamic terminals of the first switching relay, the second switching relay, the third switching relay, and the fourth switching relay are all electrically connected to the dynamic test equipment.

[0017] By controlling the switching on and off of the switching switch, the first switching relay, the second switching relay, the third switching relay, and the fourth switching relay, the test socket can be selectively connected to dynamic test equipment and static test equipment, so that the source and gate of the wafer can be selectively connected to dynamic test equipment and static test equipment, thereby enabling the switching of the equipment connected to the source and gate of the wafer.

[0018] In one optional embodiment, the dynamic testing equipment includes an oscilloscope, a switch testing device, and a gate driver, and the static testing equipment includes a static tester.

[0019] Specifically, one end of the switching switch that is electrically connected to the dynamic testing equipment is electrically connected to the gate driver. The dynamic terminal of the first switching relay is electrically connected to the current measurement port of the oscilloscope via the switch testing device. The dynamic terminal of the second switching relay is electrically connected to the drain voltage port and the gate voltage port of the oscilloscope, respectively. The dynamic terminal of the third switching relay is electrically connected to the gate driver. The dynamic terminal of the fourth switching relay is electrically connected to the gate voltage port of the oscilloscope.

[0020] The static terminal of the first switching relay is electrically connected to the source-to-source port of the static tester; the static terminal of the second switching relay is electrically connected to the source-to-measure port of the static tester; the static terminal of the third switching relay is electrically connected to the gate-to-source port of the static tester; and the static terminal of the fourth switching relay is electrically connected to the gate-to-measure port of the static tester.

[0021] During dynamic testing, when switched to the dynamic end, the switch test device and gate driver inject pulses into the wafer through a switching switch, a first switching relay, and a third switching relay. The gate voltage signal and source voltage signal of the wafer are read through the first switching relay, the second switching relay, and the fourth switching relay, and then the dynamic parameters of the wafer are analyzed. During static testing, the wafer is powered through the first switching relay and the third switching relay, and the wafer is measured through the second switching relay and the fourth switching relay, thereby reading the gate and source signals of the wafer and then analyzing the static parameters.

[0022] In one optional embodiment, the switch test device includes a DC bus capacitor, a test diode, an energy storage inductor, and a coaxial shunt.

[0023] The common terminal of the coaxial shunt is electrically connected to the current measurement port of the oscilloscope. The first shunt terminal of the coaxial shunt is electrically connected to the negative terminal of the DC bus capacitor. The positive terminal of the DC bus capacitor is electrically connected to one end of the energy storage inductor and the cathode of the accompanying diode. The other end of the energy storage inductor is electrically connected to the wafer carrier. The anode of the accompanying diode is electrically connected to the wafer carrier. The second shunt terminal of the coaxial shunt is electrically connected to the dynamic terminal of the first switching relay.

[0024] During dynamic testing, the DC bus capacitor is charged. Once the capacitor voltage reaches the set voltage, a double-pulse waveform test is performed. The wafer's on-state current is converted into a voltage signal by a coaxial shunt, which is then read by an oscilloscope.

[0025] In one optional embodiment, the wafer carrier includes a lower metal plate, a wafer holding disk, and a holding ring;

[0026] The wafer holding tray is used to place the wafer and electrically connect the wafer drain. The lower metal plate is electrically connected to the dynamic testing equipment. The fixing ring is in contact with the lower metal plate.

[0027] The switching device further includes a drain switching device, which is electrically connected to the wafer mounting disk, the fixing ring, and the static testing equipment. The drain switching device is used to selectively connect the wafer mounting disk and the fixing ring, or connect the wafer mounting disk and the static testing equipment.

[0028] During dynamic testing, the wafer holder and the dynamic testing equipment are connected to analyze and obtain the dynamic parameters of the wafer. During static testing, the wafer holder and the static testing equipment are connected to analyze and obtain the static parameters of the wafer.

[0029] In one optional embodiment, the drain switching device includes a dynamic test circuit, a first static test circuit, and a second static test circuit. The two ends of the dynamic test circuit are electrically connected to the wafer mounting disk and the fixing ring, respectively. One end of the first static test circuit is electrically connected to the wafer mounting disk, and the other end is electrically connected to the gate supply port of the static tester. One end of the second static test circuit is electrically connected to the wafer mounting disk, and the other end is electrically connected to the gate measurement port of the static tester.

[0030] The dynamic test circuit has a dynamic test circuit switch for controlling the on / off state of the circuit, and both the first static test circuit and the second static test circuit are provided with a static test circuit switch for controlling the on / off state of the circuit.

[0031] During dynamic testing, the dynamic test circuit switch is turned on while the static test circuit switch is turned off, enabling the reading of the wafer's gate voltage signal and source voltage signal, thereby analyzing the wafer's dynamic parameters. During static testing, the dynamic test circuit switch is turned off while the static test circuit switch is turned on, thereby reading the wafer's gate and source signals, and then analyzing the static parameters.

[0032] In one alternative embodiment, the wafer carrier is provided with a conductive cavity for accommodating the wafer.

[0033] The closed-cavity design of the conductive cavity enables the optimization and reduction of stray inductance in the test circuit.

[0034] In one alternative embodiment, the switching device includes a grounding switch, through which the conductive cavity is grounded.

[0035] During static testing, the grounding switch is turned on, and the lower metal plate is grounded, thereby converting the conductive space into an equipotential grounding layer, which serves as a shielding layer for the wafer. This provides excellent leakage current shielding protection required for dynamic parameter testing, improving the accuracy and stability of static parameter testing.

[0036] In one optional embodiment, the wafer carrier includes a lower metal plate, a wafer holding disk, and a holding ring, and the switching device includes a circuit board;

[0037] The circuit board is located on the wafer fixing disk away from the lower metal plate. The fixing ring surrounds the wafer fixing disk and is fixedly connected to the side of the circuit board facing the lower metal plate. The circuit board, the lower metal plate, and the fixing ring together constitute the conductive cavity.

[0038] This method of connecting the drain can effectively reduce the test circuit for dynamic measurements, reduce parasitic inductance in the circuit, and form a conductive cavity to further optimize and reduce stray inductance in the test circuit.

[0039] Secondly, the present invention provides a method for testing the electrical parameters of a power semiconductor wafer, applied to the power semiconductor wafer electrical parameter testing system described above, the method comprising:

[0040] During dynamic testing, the control switching device is in the first working state, connecting the wafer carrier and the dynamic testing equipment.

[0041] During static testing, the control switching device is in the second working state, connecting the wafer carrier and the static testing equipment.

[0042] By controlling the switching device, dynamic test equipment and static test equipment can be selectively connected. During wafer testing, the device can be switched to form a static test loop or a dynamic test loop. During dynamic testing, the wafer carrier device and dynamic test equipment are combined to complete the dynamic test. During static testing, the wafer carrier device and static test equipment are combined to complete the static test. There is no need to change the test system to complete the two types of tests separately. Both types of tests can be completed with a single probe, reducing wafer damage. Attached Figure Description

[0043] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of a power semiconductor wafer electrical parameter testing system according to an embodiment of the present invention;

[0045] Figure 2 This is another structural schematic diagram of a power semiconductor wafer electrical parameter testing system according to an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the cavity structure according to an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of the circuit board relay distribution according to an embodiment of the present invention;

[0048] Figure 5 This is a flowchart illustrating a method for testing the electrical parameters of a power semiconductor wafer according to an embodiment of the present invention.

[0049] 2. Test application module; 21. First switching relay; 22. Second switching relay; 23. Third switching relay; 24. Fourth switching relay; 31. Lower metal plate; 32. Test socket; 4. Probe station; 41. Wafer holder; 42. Fixing ring; 43. Circuit board; 431. Dynamic test circuit switch; 432. Static test circuit switch. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0052] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0053] As an optional application scenario of this invention, such as Figure 1 As shown, the present invention provides a power semiconductor wafer electrical parameter testing system for performing dynamic and static parameter testing on a wafer using a single probe. From a functional perspective, the power semiconductor wafer electrical parameter testing system of this embodiment includes a dynamic testing device, a static testing device, a wafer carrier device, a switching device, and a control device.

[0054] The dynamic testing equipment is electrically connected to the wafer carrier device and is used to measure dynamic parameters during dynamic testing. The static testing equipment is electrically connected to the wafer carrier device and is used to acquire static parameters during static testing. The wafer carrier device is electrically connected to a switching device for carrying the wafer and is electrically connected to the wafer. The switching device is electrically connected to the static testing equipment and the dynamic testing equipment respectively and is used to selectively conduct the wafer carrier device and the dynamic testing equipment, or the wafer carrier device and the static testing equipment.

[0055] The control equipment electrical connection switching device is used to control the switching device to be in a first working state, connecting the wafer carrier device and the dynamic test equipment, or to control the switching device to be in a second working state, connecting the wafer carrier device and the static test equipment.

[0056] Specifically, in this embodiment, the dynamic parameters include parameters such as switching time, and the static parameters include parameters such as leakage current and on-resistance.

[0057] In this embodiment, the dynamic testing equipment includes a dynamic tester, an oscilloscope, a switch testing device, and a gate driver. The wafer carrier includes a test socket 32, a lower metal plate 31, a circuit board 43, a wafer fixing disk 41, and a fixing ring 42. The switching device includes a grounding switch, a switching switch, a first switching relay 21, a second switching relay 22, a third switching relay 23, and a fourth switching relay 24, as well as a drain switching device located on the circuit board 43.

[0058] Please refer to Figure 2 and Figure 3 The power semiconductor wafer electrical parameter testing system of this embodiment includes, from a structural perspective, a test application module 2, a dynamic test device, a static test device, a lower metal plate 31, and a probe station 4.

[0059] In this embodiment, the test socket 32, the lower metal plate 31, the switch test device, the grounding switch, the switching switch, the first switching relay 21, the second switching relay 22, the third switching relay 23 and the fourth switching relay 24 are integrated in the test application module 2, and the drain switching device, the wafer fixing disk 41 and the fixing ring 42 are integrated in the probe station 4.

[0060] The oscilloscope is electrically connected to the wafer carrier to acquire dynamic test waveforms during dynamic testing. The dynamic tester is electrically connected to the oscilloscope so that it can read the waveforms acquired by the oscilloscope during dynamic parameter testing. Based on the oscilloscope's gate waveform, drain waveform, and current waveform, various dynamic parameters can be calculated. The static tester is electrically connected to the wafer carrier in the test application module 2 and the probe station 4 to control the voltage of the gate, source, and drain of each wafer during static testing. It tests the changes of each electrode of the wafer under relatively small voltage differences to obtain static parameters.

[0061] The lower metal plate 31, wafer holder 41, circuit board 43, and retaining ring 42 are used to cooperate with each other to achieve electrical connection with the drain of each die on the wafer. Drains are evenly distributed on one side of the wafer. During testing, the wafer is placed on the wafer holder 41 with the drain side facing the wafer holder 41, thus achieving electrical connection between the wafer holder 41 and the wafer drain. The retaining ring 42 is circular and surrounds the wafer holder 41. The circuit board 43 is located below the wafer holder 41 and is fixedly connected to the wafer holder 41 and retaining ring 42. The probe station 4 also has a lifting device that is driven by the wafer holder 41. The lifting device is used to drive the wafer holder 41, circuit board 43, and retaining ring 42 to move up and down as a whole. When the lifting device moves the wafer... When the circular fixing plate 41, circuit board 43, and fixing ring 42 rise as a whole, the whole assembly approaches and contacts the lower metal plate 31. The lower metal plate 31 achieves electrical connection with the drain on the back of the wafer, and the drain current data is read. This method of connecting the drain can effectively reduce the test circuit of dynamic measurement and reduce the parasitic inductance in the circuit. In addition, the lower metal plate 31 completely covers the movement range of the wafer fixing plate. At this time, the circuit board 43, fixing ring 42, and lower metal plate 31 form a closed conductive cavity. The design of the closed cavity space of the conductive cavity can optimize and reduce the stray inductance in the test circuit. Through the joint design of these two aspects, the parasitic inductance in the test circuit can be greatly reduced, making the measured dynamic parameters more accurate.

[0062] In this embodiment, the lower metal plate 31 is grounded via a grounding switch. During dynamic testing, the grounding switch is open, allowing connection to the wafer drain via the lower metal plate 31. During static testing, the grounding switch is closed, and the lower metal plate 31 is grounded, thereby converting the conductive space into an equipotential grounding layer, serving as a shielding layer for the wafer. This satisfies the excellent leakage current shielding protection required for static parameter testing, improving the accuracy and stability of static parameter testing. Specifically, the grounding switch in this embodiment is implemented using a relay.

[0063] In this embodiment, the switch testing device includes a DC bus capacitor, a test diode, an energy storage inductor, and a coaxial shunt. The common terminal of the coaxial shunt is electrically connected to the current measurement port of the oscilloscope. The first shunt terminal of the coaxial shunt is electrically connected to the negative terminal of the DC bus capacitor. The positive terminal of the DC bus capacitor is electrically connected to one end of the energy storage inductor and the cathode of the test diode. The other end of the energy storage inductor is electrically connected to the lower metal plate 31. The anode of the test diode is electrically connected to the lower metal plate 31.

[0064] Please refer to Figure 2 and Figure 4The switching device is used to switch the system between dynamic parameter test circuits and static parameter test circuits. When performing dynamic parameter testing, the switching device switches to the dynamic parameter test circuit for dynamic parameter testing; when performing static parameter testing, the switching device switches to the static parameter test circuit for static parameter testing. Specifically, one end of the switching switch is electrically connected to the test socket 32, and the other end is electrically connected to the gate driver of the dynamic tester. The common terminals of the first switching relay 21, the second switching relay 22, the third switching relay 23, and the fourth switching relay 24 are all electrically connected to the test socket 32 ​​to connect the gate and source of the wafer through the test socket 32 ​​during testing. The dynamic terminal of the first switching relay 21 is electrically connected to the second shunt terminal of the coaxial shunt. The static terminal of the first switching relay 21 is electrically connected to the source-to-source port of the static tester. The dynamic terminal of the second switching relay 22 is electrically connected to the drain voltage port and the gate voltage port of the oscilloscope, respectively. The static terminal of the second switching relay 22 is electrically connected to the source measurement port of the static tester. The dynamic terminal of the third switching relay 23 is electrically connected to the gate driver. The static terminal of the third switching relay 23 is electrically connected to the gate-to-source port of the static tester. The dynamic terminal of the fourth switching relay 24 is electrically connected to the gate voltage port of the oscilloscope. The static terminal of the fourth switching relay 24 is electrically connected to the gate measurement port of the static tester.

[0065] The switching mechanism is implemented using a relay.

[0066] In this embodiment, the switching switch and the grounding switch are in the normally open state, the static terminals of the first switching relay 21, the second switching relay 22, the third switching relay 23 and the fourth switching relay 24 are normally closed terminals, and the dynamic terminals of the first switching relay 21, the second switching relay 22, the third switching relay 23 and the fourth switching relay 24 are normally open terminals.

[0067] It is worth noting that, in optional embodiments, the gate driver can be a separate device in the test application module 2 or a device integrated into the dynamic tester.

[0068] Please refer to Figure 1-3The drain switching device includes a first static test circuit and a second static test circuit arranged on a circuit board 43, as well as multiple dynamic test circuits. The two ends of the dynamic test circuit are electrically connected to the wafer mounting plate 41 and the fixing ring 42, respectively. The dynamic test circuit has a dynamic test circuit switch 431 implemented by a relay, which is used to control the on / off state between the wafer mounting plate 41 and the fixing ring 42. One end of the first static test circuit is electrically connected to the wafer mounting plate 41, and the other end is electrically connected to the gate supply port of the static tester. One end of the second static test circuit is electrically connected to the wafer mounting plate 41, and the other end is electrically connected to the gate measurement port of the static tester. Both the first static test circuit and the second static test circuit are provided with static test circuit switches implemented by relays, which are used to realize the on / off state of the first static test circuit and the second static test circuit.

[0069] The controller is electrically connected to the control terminals of the dynamic test circuit switch 431, the static test circuit switch, the grounding switch, the switching switch, the first switching relay 21, the second switching relay 22, the third switching relay 23, and the fourth switching relay 24 to control the switching for dynamic and static testing.

[0070] It is worth noting that the controller in this embodiment is integrated into the dynamic tester. In other embodiments, a separate control system can also be used to control the operation of the switching device. This invention is not limited to this.

[0071] In this embodiment, during dynamic testing, the controller controls the dynamic test circuit switch 431, the static test circuit switch, the grounding switch, the switching switch, the first switching relay 21, the second switching relay 22, the third switching relay 23, and the fourth switching relay 24 to operate in the first working state. The dynamic test circuit switch 431 and the switching switch are turned on, while the static test circuit switch and the grounding switch are turned off. The first switching relay 21, the second switching relay 22, the third switching relay 23, and the fourth switching relay 24 are switched to the dynamic end, thereby switching to the dynamic parameter test circuit. The dynamic tester charges the DC bus capacitor. After the DC bus capacitor voltage is charged to the set voltage, the gate driver outputs a voltage pulse to realize the double pulse waveform test. The oscilloscope acquires the waveform, and the waveform data is read by the tester and displayed as the measured dynamic parameters.

[0072] During static testing, the controller controls the dynamic test circuit switch 431, the static test circuit switch, the grounding switch, the switching switch, the first switching relay 21, the second switching relay 22, the third switching relay 23, and the fourth switching relay 24 to operate in the second working state. The dynamic test circuit switch 431 and the switching switch are disconnected, while the static test circuit switch and the grounding switch are connected. The first switching relay 21, the second switching relay 22, the third switching relay 23, and the fourth switching relay 24 are switched to the static end, thus switching to the static parameter test circuit, fully connecting the static tester, and completing the static parameter test.

[0073] Please refer to Figure 5 According to an embodiment of the present invention, a method for testing the electrical parameters of a power semiconductor wafer is provided, which can be used in the above-described power semiconductor wafer electrical parameter testing system. The method includes:

[0074] During dynamic testing, the control switching device is in the first working state, connecting the wafer carrier and the dynamic testing equipment.

[0075] During static testing, the control switching device is in the second working state, connecting the wafer carrier and the static testing equipment.

[0076] Specifically, during dynamic testing, the dynamic test circuit switch 431, static test circuit switch, grounding switch, switching switch, first switching relay 21, second switching relay 22, third switching relay 23, and fourth switching relay 24 are operated in the first working state. The dynamic test circuit switch 431 and the switching switch are turned on, while the static test circuit switch and the grounding switch are turned off. The first switching relay 21, second switching relay 22, third switching relay 23, and fourth switching relay 24 are switched to the dynamic end, thus switching to the dynamic parameter test circuit. The dynamic tester charges the DC bus capacitor. After the DC bus capacitor voltage is charged to the set voltage, the gate driver outputs a voltage pulse to realize the double pulse waveform test. The oscilloscope acquires the waveform, and the waveform data is read by the tester and displayed as the measured dynamic parameters.

[0077] During static testing, the dynamic test circuit switch 431, the static test circuit switch, the grounding switch, the switching switch, the first switching relay 21, the second switching relay 22, the third switching relay 23, and the fourth switching relay 24 are operated in the second working state. The dynamic test circuit switch 431 and the switching switch are disconnected, while the static test circuit switch and the grounding switch are connected. The first switching relay 21, the second switching relay 22, the third switching relay 23, and the fourth switching relay 24 are switched to the static end, thereby switching to the static parameter test circuit, fully connecting the static tester, and completing the static parameter test.

[0078] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A power semiconductor wafer electrical parameter testing system, characterized in that, The system includes: A dynamic testing device is electrically connected to a wafer carrier, and the dynamic testing device is used to measure dynamic parameters during dynamic testing; A static testing device is electrically connected to the wafer carrier device, and the static testing device is used to acquire static parameters during static testing; The wafer carrier device is electrically connected to the switching device, and the wafer carrier device is used to carry the wafer and is electrically connected to the wafer; A switching device is electrically connected to the static test equipment and the dynamic test equipment respectively. The switching device is used to selectively connect the wafer carrier device and the dynamic test equipment, or the wafer carrier device and the static test equipment. A control device electrically connected to the switching device, the control device being used to control the switching device to be in a first working state, connecting the wafer carrier and the dynamic testing device, or to control the switching device to be in a second working state, connecting the wafer carrier and the static testing device; The wafer carrier is provided with a conductive cavity for accommodating the wafer. The switching device includes a grounding switch, through which the conductive cavity is grounded. The wafer carrier includes a lower metal plate, a wafer holding disk, and a fixing ring. The switching device includes a circuit board. The circuit board is located on the wafer holding disk away from the lower metal plate. The fixing ring surrounds the wafer holding disk and is fixedly connected to the side of the circuit board facing the lower metal plate. The circuit board, the lower metal plate, and the fixing ring together constitute the conductive cavity. During dynamic testing, the grounding switch is open; during static testing, the grounding switch is closed, grounding the lower metal plate.

2. The system according to claim 1, characterized in that, The wafer carrier includes a test socket, and the switching device includes a switching switch, a first switching relay, a second switching relay, a third switching relay, and a fourth switching relay; One end of the switching switch is electrically connected to the test socket, and the other end is electrically connected to the dynamic testing equipment; The common terminals of the first switching relay, the second switching relay, the third switching relay, and the fourth switching relay are all electrically connected to the test socket. The static terminals of the first switching relay, the second switching relay, the third switching relay, and the fourth switching relay are all electrically connected to the static test equipment. The dynamic terminals of the first switching relay, the second switching relay, the third switching relay, and the fourth switching relay are all electrically connected to the dynamic test equipment.

3. The system according to claim 2, characterized in that, The dynamic testing equipment includes an oscilloscope, a switch testing device, and a gate driver; the static testing equipment includes a static tester. Specifically, one end of the switching switch that is electrically connected to the dynamic testing equipment is electrically connected to the gate driver. The dynamic terminal of the first switching relay is electrically connected to the current measurement port of the oscilloscope via the switch testing device. The dynamic terminal of the second switching relay is electrically connected to the drain voltage port and the gate voltage port of the oscilloscope, respectively. The dynamic terminal of the third switching relay is electrically connected to the gate driver. The dynamic terminal of the fourth switching relay is electrically connected to the gate voltage port of the oscilloscope. The static terminal of the first switching relay is electrically connected to the source-to-source port of the static tester; the static terminal of the second switching relay is electrically connected to the source-to-measure port of the static tester; the static terminal of the third switching relay is electrically connected to the gate-to-source port of the static tester; and the static terminal of the fourth switching relay is electrically connected to the gate-to-measure port of the static tester.

4. The system according to claim 3, characterized in that, The switch test device includes a DC bus capacitor, a test diode, an energy storage inductor, and a coaxial shunt. The common terminal of the coaxial shunt is electrically connected to the current measurement port of the oscilloscope. The first shunt terminal of the coaxial shunt is electrically connected to the negative terminal of the DC bus capacitor. The positive terminal of the DC bus capacitor is electrically connected to one end of the energy storage inductor and the cathode of the accompanying diode. The other end of the energy storage inductor is electrically connected to the wafer carrier. The anode of the accompanying diode is electrically connected to the wafer carrier. The second shunt terminal of the coaxial shunt is electrically connected to the dynamic terminal of the first switching relay.

5. The system according to claim 3, characterized in that, The wafer carrier device includes a lower metal plate, a wafer holding disk, and a holding ring; The wafer holding tray is used to place the wafer and electrically connect the wafer drain. The lower metal plate is electrically connected to the dynamic testing equipment. The fixing ring is in contact with the lower metal plate. The switching device further includes a drain switching device, which is electrically connected to the wafer mounting disk, the fixing ring, and the static testing equipment. The drain switching device is used to selectively connect the wafer mounting disk and the fixing ring, or connect the wafer mounting disk and the static testing equipment.

6. The system according to claim 5, characterized in that, The drain switching device includes a dynamic test circuit, a first static test circuit, and a second static test circuit. The two ends of the dynamic test circuit are electrically connected to the wafer mounting disk and the fixing ring, respectively. One end of the first static test circuit is electrically connected to the wafer mounting disk, and the other end is electrically connected to the gate supply port of the static tester. One end of the second static test circuit is electrically connected to the wafer mounting disk, and the other end is electrically connected to the gate measurement port of the static tester. The dynamic test circuit has a dynamic test circuit switch for controlling the on / off state of the circuit, and both the first static test circuit and the second static test circuit are provided with a static test circuit switch for controlling the on / off state of the circuit.

7. A method for testing the electrical parameters of a power semiconductor wafer, characterized in that, The method, applied to the power semiconductor wafer electrical parameter testing system according to any one of claims 1 to 6, comprises: During dynamic testing, the control switching device is in the first working state, connecting the wafer carrier and the dynamic testing equipment. During static testing, the control switching device is in the second working state, connecting the wafer carrier and the static testing equipment.

Images