Modularized aging test device

Abstract

The invention discloses a modular aging test device, which comprises a high-frequency daughter board, a low-frequency mother board and a power division mother board which are stacked from top to bottom, a plurality of high-frequency daughter boards are arranged, and low-frequency signal connecting parts I connected with the low-frequency mother board are arranged on the high-frequency daughter boards; the low-frequency mother board is provided with a plurality of second low-frequency signal connecting parts matched with the first low-frequency signal connecting parts, and the first low-frequency signal connecting parts and the second low-frequency signal connecting parts are inserted in an opposite mode so as to be used for transmission of low-frequency signals. And the power division mother board is provided with a plurality of radio frequency signal connecting components II matched with the radio frequency signal connecting components I of the high-frequency daughter board. According to the invention, the design can be simplified to improve the design efficiency, so that the cost can be reduced, the use of coaxial cables can be reduced, the height between layers is small, but gaps are still reserved, and effective heat dissipation can still be realized under the condition that the overall structure is kept compact.

Description

A modular aging test device Technical Field

[0001] This invention belongs to the field of aging testing technology, specifically relating to a modular aging testing device. Background Technology

[0002] In the manufacturing process of radio frequency chips, aging testing is a key step to ensure product reliability and select qualified products. It involves long-term, multi-station parallel testing to comprehensively verify the performance stability of the chip under specific operating conditions.

[0003] In related technologies, conventional aging test solutions in the aging test field often adopt an integrated circuit board design with multiple test sockets. By integrating power supply lines, control lines, and various peripheral components on the circuit board, the power supply, control, and signal transmission functions of the chips under test at multiple stations are realized. However, for RF chip testing scenarios, since connector ports need to be reserved to input RF signals to the chip's main port or input port at each station, and the branch ports or output ports at each station need to be connected to onboard loads or lead out RF connectors before connecting the loads, and it is necessary to test the branch ports through connectors when necessary, the traditional integrated solution requires a high-frequency composite board composed of a high-frequency core board and a low-frequency core board as the transmission carrier board. The high-frequency core board is used to carry the load transmission lines led out from the chip, and a power divider is used to provide RF signal input to the main port or input port of each station. This power divider is generally a separate independent device from the high-frequency core board. The main ports or input ports of multiple stations need to be connected to the branch ports of the power divider through coaxial cables, and then connected to signal sources and other instruments and equipment.

[0004] Although it can meet basic testing needs, the circuit layout and interface definition of the integrated circuit board are strongly tied to the package form and pin distribution of the chip under test. For RF chips with different packages or pin definitions, the entire test device needs to be redesigned and manufactured, resulting in high development costs and long cycles. It cannot adapt to the testing needs of multiple types of chips, and the overall wiring is relatively messy. Summary of the Invention

[0005] The purpose of this invention is to propose a modular aging test device to solve the problem that in the prior art, the circuit layout, interface definition and the package form and pin distribution of the chip under test are strongly bound together. For RF chips with different packages or pin definitions, the entire test device needs to be redesigned and manufactured, resulting in high development costs, long development cycles and inability to adapt to the testing needs of multiple types of chips.

[0006] To address this, the present invention provides a modular aging test device, comprising: a high-frequency sub-board, a low-frequency motherboard, and a power divider motherboard stacked from top to bottom; multiple high-frequency sub-boards are provided, each high-frequency sub-board having a test socket configured with a chip under test, and a low-frequency signal connection component I connected to the low-frequency motherboard is provided on the high-frequency sub-board; multiple low-frequency signal connection components II adapted to the low-frequency signal connection components I are provided on the low-frequency motherboard, the low-frequency signal connection components I and the low-frequency signal connection components II being interlocked for low-frequency signal transmission; the power divider motherboard has radio frequency signal connection components II adapted to the radio frequency signal connection components I of the high-frequency sub-board, the radio frequency signal connection components I and the radio frequency signal connection components II being interlocked through an intermediate adapter to achieve signal conduction.

[0007] In some embodiments, the first low-frequency signal connection component is a low-frequency plug, and the second low-frequency signal connection component is a low-frequency socket adapted to the low-frequency plug; the first radio frequency signal connection component is a push-in radio frequency coaxial connector, the second radio frequency signal connection component is a push-in radio frequency coaxial connector, and the intermediate adapter is a KK connector.

[0008] In some embodiments, the low-frequency motherboard is provided with a plurality of low-frequency signal connection components 2, and the plurality of low-frequency signal connection components 2 are connected to low-frequency connectors via low-frequency traces provided on the low-frequency motherboard. The low-frequency connectors are used to lead out the converged low-frequency signals and power supply lines.

[0009] In some embodiments, the power divider busbar is further provided with an RF master input connector; a 1-to-multiple power divider network, wherein the 1-to-multiple power divider network employs multiple impedance transformation sections and thin-film isolation resistors. Preferably, the 1-to-multiple power divider structure is 1-to-4, 1-to-8, 1-to-16, etc. Considering the balance of size and quantity, 1-to-8 is preferred.

[0010] In some embodiments, each of the high-frequency subboards is provided with an RF connector for connecting a load or leading to a testing instrument.

[0011] In some embodiments, the bottom of the power distribution motherboard is bolted to a mounting base.

[0012] In some embodiments, the test socket is a flip-top test socket, with a metal pin holder on the base and a coaxial probe on the metal pin holder. The coaxial probe is electrically connected to the radio frequency signal connection component via a radio frequency (RF) trace. Preferably, the RF trace can be a microwave, coplanar waveguide, or stripline transmission line.

[0013] In some embodiments, multiple high-frequency sub-boards are provided, and the multiple high-frequency sub-boards are evenly distributed on the low-frequency motherboard. The number of high-frequency sub-boards corresponds one-to-one with the number of power divider ports.

[0014] Beneficial effects: 1. The power divider motherboard and low-frequency motherboard of this invention are both universal structures, and even different chips can share the same motherboard. Each time, a smaller test sub-board can be designed for different chips, which simplifies the design and improves design efficiency, thereby reducing costs. In addition, the entire application uses board-to-board connectors for interconnection, such as the pairing of low-frequency plugs and sockets, push-in coaxial connectors, and intermediate adapters, which reduces the use of coaxial cables. The height between layers is small, but gaps are still left. While maintaining a relatively compact overall structure, effective heat dissipation can still be achieved. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 is an exploded view of the modular aging test device of the present invention.

[0017] Figure 2 is a perspective view of the modular aging test device of the present invention.

[0018] Figure 3 is an exploded view of the high-frequency sub-board of the modular aging test device of the present invention.

[0019] Figure 4 is an exploded view of the low-frequency motherboard of the modular aging test device of the present invention.

[0020] Figure 5 is an exploded view of the power distribution motherboard of the modular aging test device of the present invention.

[0021] Figure 6 is a partial cross-sectional view of the modular aging test device of the present invention.

[0022] Figure 7 is a cross-sectional view of the connection between the RF coaxial connector and the KK connector of the modular aging test device of the present invention.

[0023] In the diagram: 1. High-frequency daughterboard; 2. Low-frequency motherboard; 3. Power divider motherboard; 4. Test socket; 5. RF connector; 6. Low-frequency connector; 7. RF coaxial connector; 8. Intermediate adapter; 9. Low-frequency plug; 10. Low-frequency socket; 11. Filter capacitor; 12. Surface mount resistor; 13. Low-frequency trace; 14. RF trace; 15. Coaxial probe; 16. Metal pin header; 17. Mounting base. Detailed Implementation

[0024] The invention will be more readily understood by referring to the following detailed description of preferred embodiments and included examples. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. In case of conflict, the definitions in this specification shall prevail.

[0025] This invention provides a modular aging test device, which solves the problems of high cost and long cycle time in the prior art, which requires the redesign and manufacture of the entire fixture for chips with different packages or pin definitions. It also solves the problem that when a single station is damaged or needs to be replaced, the entire fixture needs to be adjusted and disassembled accordingly, which is cumbersome and affects the test efficiency. Furthermore, it solves the problem that the RF ports of each station need to be connected to RF cables and then aggregated to the power divider, resulting in messy wiring and large footprint. Finally, it solves the problems of heat concentration and poor ventilation in the integrated circuit structure of the prior art, and the problem that the low frequency signal busbars are crowded and prone to crosstalk in high-density multi-station conditions.

[0026] The technical concept of this invention lies in the modular structure, specifically the separate architecture of a high-frequency daughterboard, a low-frequency motherboard, and a power divider motherboard. The high-frequency and low-frequency functional splitting is designed as a universal power divider network motherboard and a low-frequency network motherboard. At the same time, the test socket modules of each station can adopt a smaller high-frequency composite board daughterboard structure and customize different circuits and test sockets to adapt to different chips. The three are interconnected by RF connectors or low-frequency socket boards and according to different functional layers to achieve functional integrity and achieve efficient and flexible parallel testing. Furthermore, gaps are left between the high-frequency daughterboard and the low-frequency motherboard, as well as between the high-frequency motherboard and the high-frequency motherboard, to ensure heat dissipation efficiency.

[0027] As shown in Figures 1-7, a modular aging test device includes: a high-frequency sub-board 1, a low-frequency motherboard 2, and a power distribution motherboard 3 stacked from top to bottom. The power distribution motherboard 3 can also be referred to as the high-frequency motherboard. Gaps are left between the high-frequency sub-board 1 and the low-frequency motherboard 2, and between the low-frequency motherboard 2 and the power distribution motherboard 3, to facilitate airflow and heat dissipation.

[0028] Specifically, multiple high-frequency sub-boards 1 are provided, and each high-frequency sub-board 1 is provided with a test socket 4 configured with a chip under test, and a low-frequency signal connection component 1 connected to the low-frequency motherboard 2 is provided on the high-frequency sub-board 1; specifically, the low-frequency signal connection component 1 provided on the high-frequency sub-board 1 is a low-frequency plug 9 for low-frequency signal convergence, exemplarily a simple horn-shaped connector.

[0029] As shown in Figure 7, multiple low-frequency signal connection components 2, adapted to the first connection component, are provided on the low-frequency motherboard 2. The low-frequency signal connection components 1 and 2 are plugged into each other for the transmission of low-frequency signals. Among them, the low-frequency signal connection components 2 on the low-frequency motherboard 2 are low-frequency sockets 10 adapted to the low-frequency plugs 9, and their number corresponds to the low-frequency plugs 9 on the high-frequency daughterboard 1. In use, the two can be directly plugged into each other. Through the low-frequency motherboard 2, low-frequency signals such as power signals, control signals, and enable signals from multiple high-frequency daughterboards 1 can be combined and integrated, and then brought out to the outside through a single low-frequency connector 6, thereby realizing centralized control.

[0030] The power distribution motherboard 3 is equipped with a second RF signal connection component that is compatible with the first RF signal connection component of the high-frequency daughterboard 1. The first and second RF signal connection components are connected via an intermediate adapter to enable RF signal conduction. The power distribution motherboard 3 is located at the bottom layer and is the core RF signal distribution center of the test station on the high-frequency daughterboard 1. The second RF signal connection component integrated on it is a board-to-board push-in RF coaxial connector that is compatible with the RF coaxial connector 7 on the high-frequency daughterboard 1. It is connected via an intermediate adapter to enable quick-connection between the power distribution motherboard 3 and the high-frequency daughterboard 1. Preferably, the intermediate adapter 8 is a KK connector.

[0031] The power divider motherboard 3 and low-frequency motherboard 2 in the above technical solution are both universal structures, allowing different chips to share the same motherboard. Smaller test daughterboards can be designed for different chips each time, simplifying the design process, improving efficiency, and reducing costs. Furthermore, this application uses board-to-board connectors for interconnection, such as low-frequency plug 9 and low-frequency socket 10, board-to-board push-in coaxial connectors, and intermediate adapters. This reduces the use of coaxial cables, and while the height between layers is small, gaps are still maintained. This ensures effective heat dissipation while maintaining a compact overall structure. It is understood that airflow passing through the gaps between the high-frequency daughterboard 1 and the low-frequency motherboard 2, and between the low-frequency motherboard 2 and the power divider motherboard 3, carries away heat, thus achieving effective heat dissipation.

[0032] In some embodiments, the low-frequency motherboard 2 is provided with multiple low-frequency signal connection components 2, and the multiple low-frequency signal connection components 2 are connected to the low-frequency connector 6 via low-frequency traces 13 provided on the low-frequency motherboard 2. The low-frequency connector 6 is used to extract the converged low-frequency signal. Multiple high-frequency daughterboards 1 can be electrically connected to the total low-frequency connector 6 provided on the low-frequency motherboard 2 via the low-frequency traces 13, thereby realizing the extraction of the converged low-frequency signal.

[0033] As shown in Figure 5, in some embodiments, the power bus 3 is also provided with an RF main input connector, wherein the RF main input connector is preferably a vertical surface mount type RF connector 5.

[0034] This is a 1-to-multipoint power divider network that employs multiple impedance transformation sections and thin-film isolation resistors. It also utilizes a multi-stage Wilkinson power divider structure and thin-film isolation resistors to meet the requirements of a wide frequency range, from 2 to 18 GHz.

[0035] Preferably, the power divider structure is one of the following: 1 to 4, 1 to 8, or 1 to 16. Considering the balance of size and quantity, 1 to 8 is preferred.

[0036] Furthermore, a corresponding number of power divider output connectors are provided on the power divider motherboard 3, all of which adopt board-to-board push-in RF coaxial connectors 7, preferably board-to-board three-piece sets with standard connector interface structures such as SMP / SMPM.

[0037] In other embodiments, the one-to-many power divider network may also employ other numbers of power divider networks.

[0038] As shown in Figures 1-2, in one embodiment, the power distribution motherboard 3 is mechanically fixed and supported to the low-frequency motherboard 2 and the mounting base 17 via hexagonal studs, forming a stable whole. The radio frequency signals between the power distribution motherboard 3 and the high-frequency daughterboard 1 are vertically and quickly interconnected via a board-to-board three-piece connector assembly. The high-frequency daughterboard 1 and the low-frequency motherboard 2 are connected via a low-frequency plug-and-receptor assembly.

[0039] As shown in Figure 3, in one embodiment, each high-frequency sub-board 1 is provided with an RF connector 5, which is used to connect a load or lead to a testing instrument. Preferably, the RF connector 5 is a vertical surface-mount RF connector.

[0040] As shown in Figure 3, in one embodiment, the test socket 4 is a flip-top test socket. A metal pin holder 16 is mounted on the base of the test socket 4, and a coaxial probe 15 is mounted on the metal pin holder 16. The coaxial probe 15 is electrically connected to an RF signal connection component via an RF trace 14. In use, the test socket 4 is opened, the chip is placed onto the corresponding metal pin holder 16, and then the flip-top clamp is tightened. The power divider signal is transmitted and aggregated via the coaxial probe 15, the high-frequency trace 14, and the RF coaxial connector 7. Both the pressure block and the metal pin holder 16 in the test socket 4 can be made of brass, which is beneficial for heat conduction. The pressing height of the pressure block can be adjusted by rotating a knob, making it compatible with chips of different thicknesses and ensuring consistent probe contact pressure. The limiting frame on the metal pin holder 16, used to fix the position of the chip under test, can be made of PEEK material and can be quickly replaced according to the chip size.

[0041] The radio frequency trace 14 can use planar radio frequency transmission line structures such as microstrip, coplanar waveguide, and stripline. Preferably, a coplanar waveguide structure is used.

[0042] During installation, the supporting aluminum plate is fixed to the test bench, and then the power distribution motherboard 3 is installed. The low-frequency motherboard 2 is installed and supported by hexagonal studs. Then, each high-frequency daughterboard 1 is connected to the power distribution motherboard 3 through the intermediate adapter 8, and its low-frequency plug 9 is inserted into the low-frequency motherboard 2. Finally, the installation of the eight workstation modules is completed.

[0043] After installation, signal testing is performed. RF signals are input from the main port of the power divider motherboard 3, evenly distributed to each workstation via the power divider network, and then sent to the RF main port or input port of each chip via the board-to-board three-piece assembly. Low-frequency signals are input to the low-frequency motherboard 2 via low-frequency connector 6 and then transmitted to each workstation. RF monitoring signals from the chips are led out from the vertical surface-mount RF connector 5 on the daughterboard.

[0044] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A modular aging test device, characterized in that, include: The high-frequency sub-board, low-frequency motherboard, and power divider motherboard are stacked from top to bottom. The high-frequency sub-board is provided in multiple ways. Each high-frequency sub-board is provided with a test socket configured with a chip under test. The high-frequency sub-board is provided with a low-frequency signal connection component 1 that is connected to the low-frequency motherboard. The low-frequency motherboard is provided with multiple low-frequency signal connection components 2 that are adapted to the low-frequency signal connection component 1. The low-frequency signal connection components 1 and 2 are interlocked for low-frequency signal transmission. The power divider motherboard is provided with multiple radio frequency signal connection components 2 that are adapted to the radio frequency signal connection components 1 of the high-frequency sub-board. The radio frequency signal connection components 1 and 2 are interlocked through an intermediate adapter to achieve signal conduction.

2. The modular aging test device according to claim 1, characterized in that, The first low-frequency signal connection component is a low-frequency plug, and the second low-frequency signal connection component is a low-frequency socket adapted to the low-frequency plug; the first radio frequency signal connection component is a push-in radio frequency coaxial connector, the second radio frequency signal connection component is a push-in radio frequency coaxial connector, and the intermediate adapter is a KK connector.

3. The modular aging test device according to claim 1, characterized in that, The low-frequency motherboard is provided with multiple low-frequency signal connection components 2, and the multiple low-frequency signal connection components 2 are connected to low-frequency connectors via low-frequency traces provided on the low-frequency motherboard. The low-frequency connectors are used to lead out the converged low-frequency signals.

4. The modular aging test device according to claim 1, characterized in that, The power divider motherboard is also equipped with an RF master input connector and a one-to-many power divider network, which employs multiple impedance transformation sections and thin-film isolation resistors.

5. The modular aging test device according to claim 4, characterized in that, The 1-to-multi-channel power divider can be configured to split into four channels, eight channels, or sixteen channels.

6. The modular aging test device according to claim 1, characterized in that, Each of the high-frequency subboards is equipped with an RF connector, which is used to connect a load or lead out to a testing instrument.

7. The modular aging test device according to claim 1, characterized in that, Each of the high-frequency daughterboards is provided with radio frequency traces and surface mount resistors, which are used to form a low-cost onboard load.

8. The modular aging test device according to claim 7, characterized in that, The radio frequency traces can be any one of microstrip, coplanar waveguide, and stripline.

9. The modular aging test device according to claim 1, characterized in that, The test socket is a flip-top test socket. A metal pin holder is provided on the base of the test socket, and a coaxial probe is provided on the metal pin holder. The coaxial probe is electrically connected to the radio frequency signal connection component through a planar radio frequency trace such as a microwave, a coplanar waveguide, or a stripline.

10. The modular aging test device according to claim 1, characterized in that, Multiple high-frequency sub-boards are provided, and the multiple high-frequency sub-boards are evenly distributed on the low-frequency motherboard, and correspond one-to-one with the number of power divider ports.

Images