Display panel and driving circuit suitable for display panel

Abstract

A driving circuit suitable for a display panel includes a driving transistor connected between a first power supply voltage and a light emitting diode; and two capacitors controllably connected to the driving transistors and corresponding data lines providing image signals. One of the two capacitors is used as a driving capacitor which controllably drives the driving transistor by a current image signal, and the other capacitor is used as a preloading capacitor which controllably preloads a subsequent image signal.

Description

Display panel and driving circuit for display panel Technical Field

[0001] This invention relates to a display panel, and more particularly to a driving circuit suitable for a light-emitting diode display panel. Background Technology

[0002] A light-emitting diode (LED) display panel is a type of flat panel display that uses an array of light-emitting diodes to produce images and videos. Each pixel of an LED display panel consists of a small LED that emits light when an electric current passes through it. Unlike liquid crystal displays (LCDs), LED display panels are self-illuminating, and each LED emits light individually, thus providing better contrast and brightness.

[0003] Active-matrix organic light-emitting diodes (AMOLEDs) are commonly used in light-emitting diode display panels. AMOLED is a type of organic light-emitting diode (OLED) display technology that uses a thin-film transistor (TFT) matrix to control pixels, enabling faster response times and more precise display control. AMOLED display panels use organic compounds that emit light when an electric current passes through them.

[0004] MicroLEDs (mLEDs or μLEDs) are also commonly used in LED display panels, which use tiny LEDs as pixel components. MicroLEDs are extremely small, typically less than 100 micrometers in size. Therefore, microLED display panels can achieve very high pixel densities, making them suitable for high-resolution applications.

[0005] Hold-type displays are a type of display technology where each frame remains on the screen until the next frame is displayed. This contrasts with impulse-type displays, where each frame is displayed briefly before the screen dims until the next frame appears. Hold-type displays are commonly found in modern displays such as LED monitors. While hold-type displays offer good visual effects, they introduce motion blur, especially in rapidly changing scenes. Motion blur occurs because our eyes naturally follow moving objects; however, hold-type displays keep the image still until the next frame, resulting in a smearing effect.

[0006] In detail, pixels are driven column by column during the scanning selection period and remain displayed for a single frame after the line selection period ends. In other words, for each pixel, the pixel intensity remains a fixed value until the next image frame is updated. When multiple consecutive image frames are displayed, moving objects in the video remain stationary within one image frame, causing a motion blur effect in human vision. To reduce motion blur, a method is proposed to insert a black image between two frames.

[0007] Retention-type displays (such as those used in LED display panels) do indeed face challenges such as frame rate limitations, primarily due to the insertion of black / monochrome images or the smoothing of frames to improve motion image quality. Therefore, there is an urgent need to develop a novel mechanism to address the shortcomings of LED display panels, such as frame rate limitations, crosstalk interference, and motion blur. Summary of the Invention

[0008] In view of the above, one of the objectives of the embodiments of the present invention is to provide a driving circuit suitable for light-emitting diode display panels, which has improved frame rate, mitigated crosstalk interference, and reduced motion blur.

[0009] According to one embodiment of the present invention, a driving circuit suitable for a display panel includes a driving transistor and two capacitors. The driving transistor is connected between a first power supply voltage and a light-emitting diode. The two capacitors are controllably connected to the driving transistor and corresponding data lines providing image signals. One of the two capacitors serves as a driving capacitor, controllably driving the driving transistor with the current image signal, while the other capacitor serves as a preload capacitor, controllably preloading subsequent image signals.

[0010] According to one embodiment of the present invention, the two capacitors include a first capacitor and a second capacitor. During the display stage, the first capacitor acts as a driving capacitor, controllably driving the driving transistor with the current image signal, and the second capacitor acts as a preload capacitor, controllably preloading subsequent image signals. During the vertical obscuration zone, the subsequent image signals preloaded on the second capacitor are controllably transferred to the first capacitor.

[0011] According to one embodiment of the present invention, the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor.

[0012] According to one embodiment of the present invention, a first end of the first capacitor is connected to a first node and then to the gate of the driving transistor, and a second end of the first capacitor is connected to a reference point; a first end of the second capacitor is connected to a second node and then to a corresponding data line via a first switch, and a second end of the second capacitor is connected to the reference point; and a second switch is connected between the first node and the second node.

[0013] According to one embodiment of the present invention, during the display phase, the first switch is turned on and the second switch is turned off; and during the vertical obscuring zone, the first switch is turned off and the second switch is turned on.

[0014] According to one embodiment of the present invention, the two capacitors include a first capacitor and a second capacitor, which alternately serve as driving capacitors during successive display phases.

[0015] According to one embodiment of the present invention, a first end of the first capacitor is connected to a first node and a second end is connected to a reference point; a first end of the second capacitor is connected to a second node and a second end is connected to the reference point; the second node is connected to a corresponding data line via a first switch, the first node is connected to a corresponding data line via a second switch, the second node is also connected to the gate of the driving transistor via a third switch, and the first node is also connected to the gate of the driving transistor via a fourth switch.

[0016] According to one embodiment of the present invention, in the first display stage, the first switch and the fourth switch are turned on and the second switch and the third switch are turned off, thereby the first capacitor serves as a driving capacitor and the second capacitor serves as a preload capacitor; in the subsequent second display stage, the first switch and the fourth switch are turned off and the second switch and the third switch are turned on, thereby the second capacitor serves as a driving capacitor and the first capacitor serves as a preload capacitor.

[0017] According to one embodiment of the present invention, a display panel is also provided, comprising:

[0018] Multiple pixel units are used to display images;

[0019] The source driver provides image signals to the plurality of pixel units via data lines; and

[0020] The timing controller controls each column of pixel units sequentially through the control signals of the scan lines;

[0021] Each pixel unit contains:

[0022] Light-emitting diodes; and

[0023] The driving circuit includes:

[0024] The driving transistor is connected between the first power supply voltage and the light-emitting diode; and

[0025] Two capacitors are controllably connected to the driving transistor and the corresponding data lines that provide the image signal;

[0026] One of the two capacitors serves as a driving capacitor, which can controllably drive the driving transistor with the current image signal, while the other capacitor serves as a preload capacitor, which can controllably preload subsequent image signals.

[0027] According to one embodiment of the present invention, the two capacitors include a first capacitor and a second capacitor. During the display stage, the first capacitor acts as a driving capacitor, controllably driving the driving transistor with the current image signal, and the second capacitor acts as a preload capacitor, controllably preloading subsequent image signals. During the vertical obscuration zone, the subsequent image signals preloaded on the second capacitor are controllably transferred to the first capacitor.

[0028] According to one embodiment of the present invention, the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor.

[0029] According to one embodiment of the present invention, a first end of the first capacitor is connected to a first node and then to the gate of the driving transistor, and a second end of the first capacitor is connected to a reference point; a first end of the second capacitor is connected to a second node and then to a corresponding data line via a first switch, and a second end of the second capacitor is connected to the reference point; and a second switch is connected between the first node and the second node.

[0030] According to one embodiment of the present invention, during the display phase, the first switch is turned on and the second switch is turned off; and during the vertical obscuring zone, the first switch is turned off and the second switch is turned on.

[0031] According to one embodiment of the present invention, the two capacitors include a first capacitor and a second capacitor, which alternately serve as driving capacitors during successive display phases.

[0032] According to one embodiment of the present invention, a first end of the first capacitor is connected to a first node and a second end is connected to a reference point; a first end of the second capacitor is connected to a second node and a second end is connected to the reference point; the second node is connected to a corresponding data line via a first switch, the first node is connected to a corresponding data line via a second switch, the second node is also connected to the gate of the driving transistor via a third switch, and the first node is also connected to the gate of the driving transistor via a fourth switch.

[0033] According to one embodiment of the present invention, in the first display stage, the first switch and the fourth switch are turned on and the second switch and the third switch are turned off, thereby the first capacitor serves as a driving capacitor and the second capacitor serves as a preload capacitor; in the subsequent second display stage, the first switch and the fourth switch are turned off and the second switch and the third switch are turned on, thereby the second capacitor serves as a driving capacitor and the first capacitor serves as a preload capacitor.

[0034] According to one embodiment of the present invention, the light-emitting diode comprises an active-matrix organic light-emitting diode or a micro light-emitting diode.

[0035] According to one embodiment of the present invention, the display panel is an active matrix display panel, and each image frame is displayed globally. Attached Figure Description

[0036] Figure 1 shows a block diagram of the display panel according to an embodiment of the present invention;

[0037] Figure 2 shows a circuit diagram of the pixel unit of Figure 1 according to an embodiment of the present invention;

[0038] Figures 3A and 3B show the equivalent simplified circuit diagram of the drive circuit in operation diagram 2;

[0039] Figure 4 shows a circuit diagram of the pixel unit of Figure 1 according to another embodiment of the present invention;

[0040] Figures 5A and 5B show the equivalent simplified circuit diagrams of the drive circuit in Figure 4.

[0041] Figure label:

[0042] 100: Display panel

[0043] 11: Pixel unit

[0044] 111: Drive circuit

[0045] 112: Light Emitting Diode

[0046] 12: Source Driver

[0047] 13: Timing Controller

[0048] VDD: First power supply voltage

[0049] VSS: Second power supply voltage

[0050] REF: Reference point

[0051] M: Driving transistor

[0052] N1: First node

[0053] N2: Second node

[0054] C1: First capacitor

[0055] C2: Second capacitor

[0056] S1: First switch

[0057] S2: Second switch

[0058] S3: Third switch

[0059] S4: Fourth Switch

[0060] A: First control signal

[0061] B: Second control signal

[0062] C: Third control signal

[0063] D: Fourth control signal

[0064] V_t: Current image signal

[0065] V_t+1: Subsequent image signal / Current image signal

[0066] V_t+2: Subsequent image signal Detailed Implementation

[0067] Figure 1 shows a block diagram of a display panel 100 according to an embodiment of the present invention. The display panel 100 in this embodiment is preferably an active-matrix display panel, where each frame image is globally displayed / refreshed, meaning the entire frame image is displayed simultaneously and within the same period.

[0068] The display panel 100 of this embodiment may include a plurality of pixel units 11 for displaying images and is typically arranged in a row-column configuration. The display panel 100 may include a source driver 12 that provides image signals to the pixel units 11 via data lines. These image signals represent the image to be displayed by the pixel units 11. As shown in FIG1, each row of pixel units 11 receives the image signal via a corresponding data line. The display panel 100 may include a timing controller 13 that sequentially controls each column of pixel units 11 via control signals for the scan lines. As shown in FIG1, each column of pixel units 11 receives (at least two) control signals via a corresponding scan line.

[0069] Figure 2 shows a circuit diagram of the pixel unit 11 of Figure 1 according to an embodiment of the present invention. The pixel unit 11 may include a driving circuit 111 for driving the light-emitting diodes (LEDs) 112 of the pixel unit 11 of the display panel 100. In this embodiment, the light-emitting diodes 112 are preferably active-matrix organic light-emitting diodes (AMOLED) or micro LEDs (microLED, mLED, or μLED). In this embodiment, the driving circuit 111 and the light-emitting diode 112 of each pixel unit 11 are disposed on the same layer.

[0070] The driving circuit 111 may include a driving transistor M, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), connected between a first power supply voltage (e.g., VDD) and a light-emitting diode 112. In this embodiment, the driving transistor M is a P-type transistor, with its source connected to the first power supply voltage (e.g., VDD) and its drain connected to the anode of the light-emitting diode 112. The cathode of the light-emitting diode 112 is connected to a second power supply voltage (e.g., VSS or common-mode voltage Vcm), the potential of which is lower than that of the first power supply voltage.

[0071] According to one feature of this embodiment, the driving circuit 111 may include (at least) two capacitors, such as a first capacitor C1 and a second capacitor C2, controllably connected to the gate of the driving transistor M and the corresponding data line. During a display phase, when displaying an image on the pixel unit 11, one of the two capacitors (e.g., the first capacitor C1) acts as a driving capacitor, controllably driving the driving transistor M with the current image signal V_t (controlled by the scan line control signal), while the other capacitor (e.g., the second capacitor C2) acts as a pre-loading capacitor, controllably pre-loading the subsequent image signal V_t+1 (controlled by the scan line control signal). It is noteworthy that the image signal is pre-loaded column by column to the pixel unit 11 via the data line; however, each image frame is displayed globally.

[0072] As shown in the embodiment of Figure 2, the driving circuit 111 may include a first capacitor C1, whose first end is connected to a first node N1 and then to the gate of the driving transistor M. The second end of the first capacitor C1 is connected to a (fixed) reference point REF (which may be zero potential, VSS, or VDD). A second capacitor C2 has its first end connected to a second node N2 and then connected to a corresponding data line via a first switch S1. The second end of the second capacitor C2 is connected to the reference point REF. The second switch S2 is connected between the first node N1 and the second node N2. The second switch S2 and the first switch S1 are controlled by a first control signal A and a second control signal B, respectively. In this embodiment, the capacitance value of the second capacitor C2 is much larger than (e.g., 100 times) the capacitance value of the first capacitor C1.

[0073] Figures 3A and 3B show the equivalent simplified circuit diagram of the drive circuit 111 in operation Figure 2. During the display phase shown in Figure 3A, the first switch S1 is turned on and the second switch S2 is turned off. Here, the first capacitor C1 acts as a drive capacitor, controllably driving the drive transistor M with the current image signal V_t, and the second capacitor C2 acts as a preload capacitor, controllably preloading the subsequent image signal V_t+1. Next, during the vertical blanking interval shown in Figure 3B, as a transfer (or update) phase, the first switch S1 is turned off and the second switch S2 is turned on. Here, the subsequent image signal V_t+1 preloaded in the second capacitor C2 is controllably transferred to the first capacitor C1. The display phase of Figure 3A and the transfer phase of Figure 3B are repeated, controllably driving the drive transistor M with the current image signal (Figure 3A), and then controllably transferring the preloaded subsequent image signal V_t+1 to the first capacitor C1 (Figure 3B).

[0074] Figure 4 shows a circuit diagram of pixel unit 11 of Figure 1 according to another embodiment of the present invention. Pixel unit 11 of Figure 4 is similar to pixel unit 11 of Figure 2, and the differences are explained below.

[0075] As shown in the embodiment of Figure 4, the driving circuit 111 may include a first capacitor C1, whose first end is connected to a first node N1 and its second end is connected to a reference point REF; and a second capacitor C2, whose first end is connected to a second node N2 and its second end is connected to the reference point REF. The second node N2 is connected to a corresponding data line via a first switch S1, and the first node N1 is connected to a corresponding data line via a second switch S2. The second node N2 is also connected to the gate of the driving transistor M (via a third switch S3), and the first node N1 is also connected to the gate of the driving transistor M (via a fourth switch S4). The second switch S2, the first switch S1, the third switch S3, and the fourth switch S4 are controlled by a first control signal A, a second control signal B, a third control signal C, and a fourth control signal D, respectively. In this embodiment, the capacitance value of the second capacitor C2 does not need to be greater than the capacitance value of the first capacitor C1.

[0076] Figures 5A and 5B show equivalent simplified circuit diagrams of the drive circuit 111 in operation diagram 4. In the first display stage (starting at time t) as shown in Figure 5A, the first switch S1 and the fourth switch S4 are turned on, while the second switch S2 and the third switch S3 are turned off. Here, the first capacitor C1 acts as a drive capacitor, controllably driving the drive transistor M with the current image signal V_t, and the second capacitor C2 acts as a preload capacitor, controllably preloading the subsequent image signal V_t+1. Next, in the second display stage (starting at time t+1) as shown in Figure 5B, the first switch S1 and the fourth switch S4 are turned off, while the second switch S2 and the third switch S3 are turned on. Here, the second capacitor C2 acts as a drive capacitor, controllably driving the drive transistor M with the current image signal V_t+1, and the first capacitor C1 acts as a preload capacitor, controllably preloading the subsequent image signal V_t+2. The display stages of Figure 5A and Figure 5B are repeated. In each display stage, the driving transistor M is controllably driven by the current image signal, and the subsequent image signal is controllably preloaded. Since the first capacitor C1 and the second capacitor C2 alternately act as driving capacitors in consecutive display stages (while the other capacitor acts as a preload capacitor), the embodiment of Figure 4 does not require the transfer stage shown in Figure 3B. It is worth noting that the image signal is preloaded column by column to the pixel unit 11 via corresponding data lines; however, each image frame is globally displayed / updated. The embodiment using the preload capacitor described above can display the image globally, thus improving the frame rate, motion blur, and smearing effect. The global display method of this embodiment is applicable to high frame rate, crosstalk-free stereoscopic displays.

[0077] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed in the invention should be included in the scope of the patent application below.

Claims

1. A driving circuit suitable for a display panel, characterized in that, It includes: a driving transistor connected between a first power supply voltage and a light-emitting diode; and two capacitors controllably connected to the driving transistor and corresponding data lines providing image signals; wherein one of the two capacitors serves as a driving capacitor, controllably driving the driving transistor with the current image signal, and the other capacitor serves as a preload capacitor, controllably preloading subsequent image signals.

2. The driving circuit for a display panel as described in claim 1, characterized in that, The two capacitors include a first capacitor and a second capacitor. During the display phase, the first capacitor acts as a driving capacitor, controllably driving the driving transistor with the current image signal, and the second capacitor acts as a preload capacitor, controllably preloading subsequent image signals. During the vertical obscuration zone, the subsequent image signals preloaded on the second capacitor are controllably transferred to the first capacitor.

3. The driving circuit for a display panel as described in claim 2, characterized in that, The capacitance of the second capacitor is greater than that of the first capacitor.

4. The driving circuit for a display panel as described in claim 2, characterized in that, The first terminal of the first capacitor is connected to the first node and then to the gate of the driving transistor; the second terminal of the first capacitor is connected to the reference point. The first terminal of the second capacitor is connected to the second node and then to the corresponding data line through the first switch; the second terminal of the second capacitor is connected to the reference point. The second switch is connected between the first node and the second node.

5. The driving circuit for a display panel as described in claim 4, characterized in that, During the display phase, the first switch is turned on and the second switch is turned off; and during the vertical obscuring zone, the first switch is turned off and the second switch is turned on.

6. The driving circuit for a display panel as described in claim 1, characterized in that, The two capacitors include a first capacitor and a second capacitor, which alternately serve as driving capacitors during successive display phases.

7. The driving circuit for a display panel as described in claim 6, characterized in that, The first end of the first capacitor is connected to the first node, and the second end is connected to the reference point; the first end of the second capacitor is connected to the second node, and the second end is connected to the reference point; the second node is connected to the corresponding data line through the first switch, the first node is connected to the corresponding data line through the second switch, the second node is also connected to the gate of the driving transistor through the third switch, and the first node is also connected to the gate of the driving transistor through the fourth switch.

8. The driving circuit for a display panel as described in claim 7, characterized in that, During the first display phase, the first switch and the fourth switch are turned on and the second switch and the third switch are turned off, thereby the first capacitor acts as a driving capacitor and the second capacitor acts as a preload capacitor. In the subsequent second display phase, the first switch and the fourth switch are turned off and the second switch and the third switch are turned on, thereby the second capacitor acts as a driving capacitor and the first capacitor acts as a preload capacitor.

9. A display panel, characterized in that, It includes: a plurality of pixel units for displaying images; a source driver that provides image signals to the plurality of pixel units via data lines; and a timing controller that sequentially controls each column of pixel units via control signals of scan lines; wherein each pixel unit includes: a light-emitting diode; and a driving circuit including: a driving transistor connected between a first power supply voltage and the light-emitting diode; and two capacitors controllably connected to the driving transistor and the corresponding data lines providing the image signals; wherein one of the two capacitors serves as a driving capacitor, controllably driving the driving transistor with the current image signal, and the other capacitor serves as a preload capacitor, controllably preloading subsequent image signals.

10. The display panel as claimed in claim 9, characterized in that, The two capacitors include a first capacitor and a second capacitor. During the display phase, the first capacitor acts as a driving capacitor, controllably driving the driving transistor with the current image signal, and the second capacitor acts as a preload capacitor, controllably preloading subsequent image signals. During the vertical obscuration zone, the subsequent image signals preloaded on the second capacitor are controllably transferred to the first capacitor.

11. The display panel as claimed in claim 10, characterized in that, The capacitance of the second capacitor is greater than that of the first capacitor.

12. The display panel as claimed in claim 10, characterized in that, The first terminal of the first capacitor is connected to the first node and then to the gate of the driving transistor; the second terminal of the first capacitor is connected to the reference point. The first terminal of the second capacitor is connected to the second node and then to the corresponding data line through the first switch; the second terminal of the second capacitor is connected to the reference point. The second switch is connected between the first node and the second node.

13. The display panel as claimed in claim 12, characterized in that, During the display phase, the first switch is turned on and the second switch is turned off; and during the vertical obscuring zone, the first switch is turned off and the second switch is turned on.

14. The display panel as claimed in claim 9, characterized in that, The two capacitors include a first capacitor and a second capacitor, which alternately serve as driving capacitors during successive display phases.

15. The display panel as claimed in claim 14, characterized in that, The first end of the first capacitor is connected to the first node, and the second end is connected to the reference point; the first end of the second capacitor is connected to the second node, and the second end is connected to the reference point; the second node is connected to the corresponding data line through the first switch, the first node is connected to the corresponding data line through the second switch, the second node is also connected to the gate of the driving transistor through the third switch, and the first node is also connected to the gate of the driving transistor through the fourth switch.

16. The display panel as claimed in claim 15, characterized in that, During the first display phase, the first switch and the fourth switch are turned on and the second switch and the third switch are turned off, thereby the first capacitor acts as a driving capacitor and the second capacitor acts as a preload capacitor. In the subsequent second display phase, the first switch and the fourth switch are turned off and the second switch and the third switch are turned on, thereby the second capacitor acts as a driving capacitor and the first capacitor acts as a preload capacitor.

17. The display panel as claimed in claim 9, characterized in that, The light-emitting diode includes an active matrix organic light-emitting diode or a micro light-emitting diode.

18. The display panel as claimed in claim 9, characterized in that, The display panel is an active matrix display panel, and each image frame is displayed globally.

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