Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device, a pixel unit in the display panel is used for executing image display according to a received data signal, in the pixel unit, a driving module and a light emitting module are sequentially connected in series between a first power supply end and a second power supply end, and an adjusting module is electrically connected to the driving module. And the initialization reset module is electrically connected with the driving module and a second power supply end, and is used for transmitting a second power supply voltage provided by the second power supply end to the driving module according to the adjustment control signal in an initialization reset time period and a compensation time period so as to cooperatively execute reset and data compensation on the driving module. The adjusting module is used for adjusting the threshold voltage of at least one driving switch tube in the driving module to a preset range according to the adjusting control signal in cooperation with the second power supply voltage in the initialization reset time period and the compensation time period. The driving switch tube is used for providing a driving current to the light-emitting module according to the data signal in cooperation with a first power voltage provided by the first power end and driving light emitted by the light-emitting module to execute image display.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, and more particularly to display panels and display devices. Background Technology

[0002] Organic light-emitting diode (OLED) displays possess numerous advantages, including self-illumination, low driving current, high luminous efficiency, short response time, high clarity and contrast, near 180° viewing angle, wide operating temperature range, and the ability to achieve flexible displays and large-area full-color displays. They are considered by the industry to be the most promising display device. However, because OLED light-emitting materials are driven by current, as panel sizes increase, the current driving the OLED light-emitting material needs to be as small as possible to reduce heat generation in large OLED panels. This can easily lead to threshold voltage variations in the transistors controlling the driving current. Consequently, even with the same data voltage control, different driving currents flow through the transistors, resulting in varying OLED luminous intensity and poor display quality. Therefore, adjusting and compensating for threshold voltage variations in the driving transistors to improve display performance is a pressing issue that needs to be addressed. Summary of the Invention

[0003] In view of the shortcomings of the above-mentioned technical problems, this application provides a display panel and display device with better display effect.

[0004] In a first aspect, embodiments of this application disclose a display panel, including a display area, which displays a plurality of pixel units arranged in an array. Each pixel unit is used to perform image display based on received data signals. Each pixel unit includes a driving module, an adjustment module, an initialization / reset module, and a light-emitting module. The driving module and the light-emitting module are connected in series between a first power supply terminal and a second power supply terminal. The adjustment module is electrically connected to the driving module. The initialization / reset module is electrically connected to the driving module and the second power supply terminal, and is used to transmit a second power supply voltage provided by the second power supply terminal to the driving module according to an adjustment control signal during an initialization / reset period and a compensation period, to cooperate in resetting and data compensation of the driving module. The adjustment module is used to adjust the threshold voltage of at least one driving switch in the driving module to a preset range according to the adjustment control signal and the second power supply voltage during the initialization / reset period and the compensation period. The driving switch is used to provide a driving current to the light-emitting module according to the data signal and the first power supply voltage provided by the first power supply terminal during the light-emitting period, and drive the light-emitting module to emit corresponding light to perform image display. The initialization / reset period, the compensation period, the data loading period, and the light-emitting period are time periods arranged sequentially in time.

[0005] In one embodiment of this application, the pixel unit further includes a control module and a storage module. The control module is electrically connected between the first power supply terminal and the driving module, and is also electrically connected between the first power supply terminal and the adjustment module. The storage module is electrically connected to the adjustment module and the driving module. During the initialization and reset period, the control module controls the first voltage terminal to provide the first power supply voltage to the storage module through the adjustment module according to the light emission signal. During the compensation period, the adjustment module controls the storage module to discharge to the driving module to adjust the threshold voltage of the driving module to a preset range.

[0006] In one embodiment of this application, the pixel unit further includes a data loading module, which is electrically connected to the data line, the scan line, the driving module, and the second power supply terminal. The data loading module is used to receive the data signal from the data line and transmit it to the driving module under the control of the scan signal provided by the scan line during the data loading period, and at the same time transmit the second power supply voltage provided by the second power supply terminal to the driving module. The driving module provides the driving current to the light-emitting module under the control of the first power supply voltage, the second power supply voltage, and the data signal, wherein the first power supply voltage is greater than the second power supply voltage.

[0007] In one embodiment of this application, the data loading module includes a data loading switch and an auxiliary data loading switch. The data loading switch is used to transmit the data signal received from the data line to the first node of the driving module under the control of the scan signal. The auxiliary data loading switch is used to transmit the second power supply voltage to the third node of the driving module under the control of the scan signal. The voltage difference between the first node and the third node serves as a threshold voltage for controlling the driving module to turn on or off. The auxiliary data loading switch is connected to the second power supply terminal. The driving module is also connected to the control module through a second node and to the adjustment module and the storage module through a fourth node. The voltage difference between the fourth node and the third node is also used to control the driving module to turn on or off.

[0008] In one embodiment of this application, the initialization reset module includes a first reset switch and a second reset switch. The first reset switch is used to transmit the second power supply voltage provided by the second power supply terminal to the first node under the control of the adjustment control signal. The second reset switch is used to transmit the second power supply voltage provided by the second power supply terminal to the third node under the control of the adjustment control signal. The second reset switch is connected to the second power supply terminal.

[0009] In one embodiment of this application, the control module, the drive module, and the adjustment module include a plurality of low-temperature polycrystalline silicon thin-film transistors as switching transistors; the initialization reset module and the data loading module include a plurality of oxide thin-film transistors as switching transistors.

[0010] In one embodiment of this application, for any pixel unit, the display panel includes a substrate, a driving layer, a display layer, and a shielding structure stacked sequentially. The low-temperature polycrystalline silicon thin-film transistor and the oxide thin-film transistor are located within the driving layer. The low-temperature polycrystalline silicon thin-film transistor is spaced apart from the substrate by a first distance, and the oxide thin-film transistor is spaced apart from the substrate by a second distance. The first distance is less than the second distance. The display layer includes at least one light-emitting element. The shielding structure is disposed around the light-emitting element in the display layer. The shielding structure is electrically connected to the light-emitting element and at least one oxide thin-film transistor. The shielding structure is used to receive the second power supply voltage and transmit the second power supply voltage to the light-emitting element and at least one oxide thin-film transistor.

[0011] In one embodiment of this application, the shielding structure includes a stacked suspended conductive structure and a shielding structure. The suspended conductive structure is disposed on the surface of the display layer and electrically connected to the second power supply terminal, and electrically connected to the conductive terminal of the oxide thin film transistor through an opening in the display layer. The suspended conductive structure is used to receive the second power supply voltage from the outside and transmit it to the second power supply terminal and at least one of the oxide thin film transistors.

[0012] Secondly, this application provides a display device including a power module and a display panel as described above, wherein the power module is used to provide driving power to the display panel to drive the display panel to perform image display.

[0013] In one embodiment of this application, the display panel includes a first compensation mode and a second compensation mode. In the first compensation mode, corresponding to the pixel unit, each frame image display stage includes the initialization reset period, the compensation period, the data loading period, and the light emission period, which are arranged consecutively in time.

[0014] In the second compensation mode, corresponding to the pixel unit, the initialization reset period and the compensation period are performed during the non-image display phase, while the data loading period and the emission period are performed during the image display phase, wherein the non-image display phase is the power-on non-display period. Alternatively, in the first compensation mode, corresponding to the pixel unit, the initialization reset period and the compensation period are performed during the non-image display phase, while the data loading period and the emission period are performed during the image display phase, wherein the non-image display phase is the vertical blanking phase, and the vertical blanking phase is located between the image display phases of two adjacent frames.

[0015] The initialization reset period and the compensation period are located in each of the vertical blanking stages; or, the initialization reset period and the compensation period are located in the vertical blanking period of each frame a, where a is an integer greater than 1. Compared to existing technologies, this embodiment effectively eliminates the problem of different luminous intensities between adjacent pixel units due to threshold voltage differences by adjusting the threshold voltage of the driving switch in the pixel unit to a preset range before the data signal is written. Furthermore, by transmitting the second power supply voltage to the driving module during the initialization reset period and the compensation period for reset, the voltage stability of the driving switch is effectively maintained, avoiding the impact of voltage changes on the threshold voltage adjustment. Moreover, since this embodiment can compensate pixel units during non-image display stages, it reduces the occupation of display time and effectively avoids the problem of insufficient compensation time caused by compressing and reducing the compensation time to ensure the refresh rate of image display. This effectively increases the compensation time, making the compensation of the threshold voltage of the driving module more sufficient, ensuring the accuracy and uniformity of image display, and resulting in better image display effects.

[0016] Furthermore, in this embodiment, the switching transistors included in the data loading module and the initialization reset module are oxide thin-film transistors, which have relatively low leakage current, making it easier to achieve low-frequency driving. Due to the low leakage current, it is also more beneficial to maintain the voltage of the corresponding driving module at the corresponding node, thus preventing brightness decay during low-frequency driving. The switching transistors included in the driving module, control module, and adjustment module are low-temperature polycrystalline silicon thin-film transistors, which have high mobility, effectively increasing their driving current and ensuring that the display element can generate greater brightness. Simultaneously, they can reduce the voltage drop caused by their own resistance, allowing the voltage to reach the preset potential more quickly.

[0017] Furthermore, in this embodiment, in the layer structure of each pixel unit corresponding to the display panel, since the oxide thin-film transistor (OTFT) is farther from the substrate than the low-temperature polycrystalline silicon (LTPS) thin-film transistor (LTPS), the OTFT is closer to the shielding structure than the LTPS. Therefore, in the manufacturing process, it is easier for the OTFT to electrically connect to the second power supply terminal through the shielding structure and receive the second power supply voltage from the outside. Simultaneously, the OTFT and LTPS are staggered in the thickness direction of the display panel, which is more conducive to reducing the space occupied by the thin-film transistors within the plane of the display panel, reducing the area occupied by the pixel unit, and providing more space for improving the pixel resolution of the display panel.

[0018] In this embodiment, the suspended conductive structure in the shielding structure connects to the ground terminal and the second power terminal of the external power module. The suspended conductive structure transmits the ground voltage received from the outside as the second power voltage to the second power terminal, providing a low-voltage second power voltage for the pixel unit. This eliminates the need to adjust the control line separately, further simplifying the wiring structure of the pixel unit and the display panel.

[0019] In this embodiment, the shielding structure is a mesh structure, which makes the overall resistance of the traces in the display panel that connect to the second power supply terminal and provide ground voltage relatively small. This ensures that each pixel unit can accurately obtain the low voltage of the second power supply, so that the pixel unit can accurately obtain the compensation signal and data signal to execute the accurate display image. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 is a schematic diagram of a display device provided in an embodiment of this application;

[0022] Figure 2 is a schematic diagram of the planar layout of the display panel in Figure 1;

[0023] Figure 3 is a schematic diagram of the equivalent circuit of the pixel unit in Figure 2;

[0024] Figure 4 is a timing diagram of the signal output of the pixel unit in Figure 3;

[0025] Figure 5 is a schematic diagram of the conduction curve changes of the driving switch in Figure 3;

[0026] Figure 6 is a side view of some components in the corresponding pixel unit of the display panel shown in Figure 2;

[0027] Figure 7 is a top view of the display layer and masking structure in some pixel units of the display area of ​​the display panel;

[0028] Figures 8-10 are timing diagrams of the signal output during the compensation process of the display device shown in Figures 2-3.

[0029] Explanation of reference numerals in the attached figures:

[0030] Display device-1, display panel-10, power supply module-20, display area-10a, non-display area-10b, m data lines-S1~Sm, n scan lines-G1~Gn, n adjustment control lines-Com1~Comn, n light emission control lines-EM1~EMn, first direction-F1, second direction-F2, timing control circuit-11, data drive circuit-12, scan drive circuit-13, light emission drive circuit-14, scan clock signal-CK, light emission clock signal-ECK, pixel unit-15, drive module-151, control module-152, adjustment module-153, storage Storage module-154, Light-emitting module-155, Data loading module-156, Initialization and reset module-157, First node-N1, Second node-N2, Third node-N3, Fourth node-N4, Drive switch-T1, Second switch-T2, Third switch-T3, Fourth switch-T4, First data loading control terminal-T40, First data loading conductive terminal-T41, Second data loading conductive terminal-T42, Fifth switch-T5, Second data loading control terminal-T50, Third data loading conductive terminal-T53, Fourth data loading conductive terminal-T54, Sixth switch-T6, First Initialization control terminal - T60, first initialization conductive terminal - T61, second initialization conductive terminal - T62, seventh switch transistor - T7, first capacitor - C1, second capacitor - C2, light-emitting element - E, scan line - Si, data line - Sj, light-emitting line - EM, EMi, adjustment control line - Com, Comi, first power supply terminal - VDD, second voltage terminal - ELVSS, ground terminal - GND, initialization reset period - H1, compensation period - H2, data loading period - H3, light emission period - H4, data signal - Data, substrate - 100, driving layer - 200, first active layer - ACT1 First gate insulating layer - GI1, first gate - GT1, first buffer layer - BU1, second gate insulating layer - GI2, interlayer insulating layer - ILD, first source / drain layer - SD1, first planarization layer - PLN1, second source / drain layer - SD2, buffer layer - Buffer, second active layer - ACT2, second gate - GT2, first planarization layer - PLN1, display layer - 300, anode - AND, organic material layer - OLED, cathode - CAT, shielding structure - 400, suspended conductive structure - 401, shielding structure - 402, first distance - LL1, second distance - LL2. Detailed Implementation

[0031] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0032] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0033] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.

[0034] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0036] Please refer to Figure 1, which is a schematic diagram of the structure of a display device 1 provided in the first embodiment of this application. The display device 1 includes a display panel 10, a power module 20, and other functional modules. The power module 20 is disposed on the back of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used to provide driving power for the display panel 10 to display images. In this embodiment, the display device 1 can be an electronic display device such as a mobile phone or a tablet computer.

[0037] Please refer to Figure 2, which is a schematic diagram of the planar layout of the display panel in Figure 1.

[0038] As shown in Figure 2, the display area of ​​the display panel 10 includes multiple pixel units 15 arranged in a matrix, m data lines S1 to Sm, n scan lines G1 to Gn, n adjustment control lines Com1 to Comn, and n light emission control lines EM1 to EMn, where m and n are natural numbers greater than 1. The n scan lines S1 to Sn extend along a first direction F1 and are mutually insulated and parallel along a second direction F2. The m data lines D1 to Dm extend along the second direction F2 and are mutually insulated and parallel along the first direction F1. The first direction F1 and the second direction F2 are perpendicular to each other. The n adjustment control lines Com1 to Comn and the n light emission control lines EM1 to EMn also extend along the second direction F2 and are mutually insulated and parallel along the first direction F1. The n adjustment control lines Com1 to Comn can receive corresponding adjustment control signals KS from the self-scanning drive circuit 13. The light emission control lines EM1 to EMn are connected to the light emission drive circuit 14 and are used by the self-scanning drive circuit 14 to receive light emission signals.

[0039] The non-display area 10b of the display panel 10 includes a timing control circuit 11 for driving pixel units to display images, a data driving circuit 12, and a scanning driving circuit 13 and a light-emitting driving circuit 14 disposed on the array substrate 10c.

[0040] The timing control circuit 11 is electrically connected to the data driving circuit 12, the scan driving circuit 13, and the light-emitting driving circuit 14. It controls the operating timing of these circuits, specifically by outputting the corresponding scan clock signal CK and light-emitting clock signal ECK to the scan driving circuit 13 and the light-emitting driving circuit 14, thus controlling when to output the corresponding scan signal and data signal. In this embodiment, the timing control circuit 11 receives an image signal representing image information from an external signal source and outputs the synchronously operating scan clock signal CK, light-emitting clock signal ECK, horizontal synchronization signal, and vertical synchronization signal, thereby correspondingly controlling the scan driving circuit 13, the light-emitting driving circuit 14, and the data driving circuit 12 to output the corresponding scan signal, light-emitting signal, and data signal.

[0041] The data driving circuit 12 is electrically connected to the m data lines D1 to Dm, and is used to transmit the data signal (Data) to be displayed to the plurality of pixel units 15 in the form of data voltage through the m data lines D1 to Dm. The pixel units 15 are disposed in the display area 10a of the display panel 10. In this embodiment, the non-display area 10b is disposed in the peripheral area of ​​the display area 10a.

[0042] The scan driving circuit 13 is electrically connected to the n scan lines S1 to Sn, and outputs scan signals through the n scan lines S1 to Sn to control when the pixel unit 15 receives data signals. In some embodiments, the scan driving circuit 13 can output scan signals from the n scan lines S1 to Sn in sequence according to the scan cycle, and of course, it can also perform scanning in other orders according to specific needs, such as outputting scan signals in sequence from S1, S3, S5, etc. This application does not limit this.

[0043] The scan drive circuit 13 is also connected to the pixel unit via n adjustment control lines Com1 to Comn, and can output adjustment control signals KS to each pixel unit 15 via the n adjustment control lines Com1 to Comn. Of course, in other embodiments of this application, the n adjustment control lines Com1 to Comn can also be connected to other circuit modules that are independent of the scan drive circuit 13.

[0044] The light-emitting driving circuit 14 is used to output a corresponding light-emitting signal to the pixel unit 15 of the display area 10a according to the light-emitting clock signal ECK. The scanning driving circuit 13 and the light-emitting driving circuit 14 can be integrated into the same circuit module. Of course, the scanning driving circuit 13 and the light-emitting driving circuit 14 can also be independently set in the non-display area 10b of the display panel 10.

[0045] Please refer to Figure 3, which is a schematic diagram of the equivalent circuit of the pixel unit in Figure 2.

[0046] As shown in Figure 3, the pixel unit 15 includes a driving module 151, a control module 152, an adjustment module 153, a storage module 154, a light-emitting module 155, a data loading module 156, and an initialization and reset module 157.

[0047] The driving module 151 is connected to the data loading module 156 via the first node N1. Simultaneously, the control module 152, the driving module 151, and the light-emitting module 155 are connected in series between the first power supply terminal VDD and the second power supply terminal ELVSS. The control module 152 is adjacent to the first power supply terminal VDD, and the light-emitting module 155 is adjacent to the second power supply terminal ELVSS. Specifically, the data loading module 156 is also connected to data lines Dj and Si, and is electrically connected to the driving module 151 via the first node N1 to provide a data signal Data to the driving module 151. The driving module 151 generates a corresponding driving current Ids based on the data signal Data provided by the data loading module 156 from the first node N1, in conjunction with the first power supply voltage provided by the first power supply terminal VDD. It then transmits the driving current Ids to the light-emitting module 155 to drive the light emitted by the light-emitting module 155 to display an image corresponding to the data signal Data.

[0048] A second node N2 is provided between the control module 152 and the drive module 151, and a third node N3 is provided between the drive module 151 and the light-emitting module 155. The adjustment module 153 is electrically connected to the drive module 151 and the control module 152 through the second node N2, and is also electrically connected to the drive module 151 through the fourth node N4. The storage module 154 is connected to the drive module 151 through the fourth node N4 and the third node N3.

[0049] In this embodiment, the first power supply terminal VDD is used to provide a high-voltage first power supply voltage, and the second power supply terminal ELVSS is used to provide a low-voltage second power supply voltage. It can be understood that the first power supply voltage is greater than the second power supply voltage. In this embodiment, the second power supply terminal ELVSS is directly connected to the ground terminal GND, and the provided low-voltage second power supply voltage can be a 0V ground voltage.

[0050] The control module 152 is used to control the first voltage terminal VDD to charge the storage module 154 through the adjustment module 153. The storage module 154 is used to cooperate with the adjustment module 153 to adjust the threshold voltage Vth in the drive module 151 so as to adjust the threshold voltage of the drive module 151 within a preset range.

[0051] The initialization reset module 157 is connected to the adjustment control line Comi and electrically connected to the drive module 151 through the first node N1 and the third node N3. Under the adjustment control signal KS provided by the adjustment control line Comi, it provides an initialization reset voltage to the first node N1 and the third node N3 connected to the drive module 151 and the light-emitting module 155, enabling the drive module 151 and the light-emitting module 155 to perform an initialization reset. Simultaneously, it cooperates with the adjustment module 153 to provide a second power supply voltage to the drive module 151 to facilitate threshold voltage Vth adjustment. In this embodiment, the initialization reset voltage is the low-voltage second power supply voltage provided by the second power supply terminal ELVSS, for example, 0V.

[0052] The threshold voltage Vth of the driving module 151 in the pixel unit 15 can be directly adjusted to a preset range by adjusting module 153 and storage module 154. Therefore, the threshold voltage Vth of the driving module 151 in adjacent pixel units 15 can be adjusted to the same preset range, eliminating the difference in light intensity caused by the different threshold voltage Vth of the driving module 151 in adjacent pixel units, thereby avoiding brightness differences between adjacent pixel units 15 and effectively improving the display effect. In this embodiment, the adjustment control signal KS is also used to cooperate with the adjustment module 153 to adjust the threshold voltage Vth of the driving module 151.

[0053] For the pixel unit 15 including the first node N1, the second node N2, the third node N3, and the fourth node N4, the specific connection method is as follows: the data loading module 156 is electrically connected to the first control terminal of the driving module 151 through the first node N1; the fourth node N4 is electrically connected to the second control terminal of the driving module 151, the adjustment module 153, and the storage module 154, that is, the adjustment module 153 is electrically connected to the storage module 154 through the fourth node N4. The adjustment module 153 is also electrically connected to the second node N2 and is electrically connected to the driving module 151 and the control module 152 through the second node N2. The data loading module 156 is electrically connected to the third node N3 and is electrically connected to the storage module 154, the driving module 151, and the light-emitting module 155 through the third node N3. The data loading module 156 is used to provide a second power supply voltage to the driving module 151 through the third node N3.

[0054] It can be understood that any frame of image display stage includes m consecutive scan cycles, m temporally consecutive scan cycles, and m consecutive scan cycles corresponding sequentially to m scan lines S1 to Sm (m rows of pixel units P) in a one-to-one correspondence. Each scan cycle can perform the reset, data compensation, data writing, and emission processes and timing stages for a row of pixel units connected to the same scan line. For example, in any scan cycle, such as the i-th scan cycle, it includes a temporally consecutive initialization reset period H1, a compensation period H2, a data loading period H3, and an emission period H4.

[0055] During the initialization reset period H1, the initialization reset module 157 provides an initialization reset voltage to the drive module 151 and the light-emitting module 155 based on the adjustment control signal KS provided by the adjustment control line Comi, thereby enabling the drive module 151 and the light-emitting module 155 to perform an initialization reset. It can be understood that the initialization reset voltage is the second power supply voltage provided by the second power supply terminal ELVSS.

[0056] In this embodiment, during the initialization and reset period H1, the control module 152, under the control of the light emission signal provided by the light emission line EMi, provides the first power supply terminal VDD to the fourth node N4 through the adjustment module 153.

[0057] During the compensation period H2, the first power supply terminal VDD stops applying voltage to the fourth node through the control module 152. The storage module 154 is able to store the charge of the fourth node N4 and maintain the potential of the fourth node N4. At the same time, the fourth node N4 discharges to the drive module 151 and the third node N3 in sequence through the adjustment module 153 and the second node N2. The voltage of the fourth node N4 gradually decreases, and at the same time, the threshold voltage of the adjustment drive module 151 is reduced to the preset value.

[0058] During the data loading period H3, the data loading module 156 receives the data signal Data and transmits it to the first node N1, while the second power supply voltage is also applied to the third node N3.

[0059] During the light-emitting phase H4, the control module 152 controls the first power supply terminal VDD to output the first power supply voltage to the drive module 151 through the second node N2. The drive module 151 controls the first power supply voltage to drive the light-emitting module 155 to emit light during the light-emitting period H4 based on the received data signal Data.

[0060] More specifically, the driving module 151 includes a driving switch T1 and a first capacitor C1. The first control terminal of the driving switch T1 is electrically connected to a first node N1, the second control terminal of the driving switch T1 is electrically connected to a fourth node N4, the first conductive terminal of the driving switch T1 is electrically connected to a second node N2, and the second conductive terminal of the driving switch T1 is electrically connected to a third node N3 and then electrically connected to the light-emitting module 155 through the third node N3. That is, the driving switch T1 is a dual-gate transistor with a first control terminal and a second control terminal.

[0061] The first capacitor C1 is electrically connected between the first node N1 and the third node N3, that is, electrically connected between the first control terminal and the second conductive terminal of the driving switch T1. The driving switch T1 is used to turn on or off under the control of the first control terminal and / or the second control terminal, and when it is on, it receives the on-state voltage from the fourth node N4 through the adjustment module 153 and generates the corresponding current, or receives the driving current from the driving control module 152 and drives the light-emitting module 155 to emit light according to the driving current.

[0062] The control module 152 includes a second switch T2. The control terminal of the second switch T2 is electrically connected to the light-emitting signal line EMi. The first conductive terminal of the second switch T2 is electrically connected to the first power supply terminal VDD. The second conductive terminal of the second switch T2 is electrically connected to the second node N2, and through the second node N2, it is electrically connected to the adjustment module 153 and the first conductive terminal of the drive switch T1. The second switch T2 is used to turn on when it receives the light-emitting signal provided by the light-emitting signal line EMi, so as to control the first power supply voltage provided by the first power supply terminal VDD to be transmitted to the second node N2. It can be understood that when the second node N2 is connected to both the drive module 151 and the adjustment module 153, when the adjustment module 153 is turned on, the first power supply voltage provided by the first power supply terminal VDD will be transmitted to the fourth node N4 through the adjustment module 153. When the drive module 151 is turned on, it provides power supply voltage in conjunction with the data signal to transmit to the first conductive terminal of the drive switch T1 in the drive module 151.

[0063] The adjustment module 153 includes a third switch T3. The control terminal of the third switch T3 is electrically connected to the adjustment control line Com. The first conductive terminal of the third switch T3 is electrically connected to the fourth node N4. The second conductive terminal of the third switch T3 is electrically connected to the second node N2, and through the second node N2, it is electrically connected to the first conductive terminal of the drive switch T1. The third switch T3 is turned on under the control of the adjustment control signal KS output from the adjustment control line Com, thereby controlling the fourth node N4 to be electrically connected to the first conductive terminal of the drive switch T1. Since the fourth node N4 is also electrically connected to the second control terminal of the drive switch T1, when the potential of the fourth node N4 is the first power supply voltage provided by the first power supply terminal VDD, the drive switch T1 is turned on, forming a conductive path between the fourth node N4, the third switch T3, the second node N2, the drive switch T1, and the third node N3. The fourth node N4 can then discharge sequentially to the drive switch T1 and the third node N3 through the second node N2.

[0064] The storage module 154 includes a second capacitor C2. The first end of the second capacitor C2 is electrically connected to the fourth node N4, and the second end of the second capacitor C2 is electrically connected to the third node N3. The second capacitor C2 is used to store charge when the first power supply terminal VDD charges the fourth node N4 and to maintain the potential of the fourth node N4 at the first power supply voltage.

[0065] The light-emitting module 155 includes a light-emitting element E, which can be an organic light-emitting diode. The anode (AND) of the light-emitting element E is electrically connected to the third node N3, and the cathode (CAT) of the light-emitting element E is electrically connected to the second power supply terminal ELVSS. The light-emitting module 155 emits light according to the driving current Ids provided by the driving switch DT to perform image display.

[0066] The data loading module 156 is connected to the scan line Si, the data line Dj and the drive module 151, and is used to load the data signal Data to the first node N1 and the drive module 151 according to the scan signal during the data loading period H3.

[0067] In this embodiment, the data loading module 156 includes a fourth switch T4 and a fifth switch T5. The fourth switch T4 serves as a data loading switch, used to receive the data signal Data from the data line Dj under the control of the scan signal and transmit it to the first node N1. The fifth switch T5 serves as an auxiliary data loading switch, used to transmit the low voltage provided by the second power supply terminal ELVDD to the third node N3 under the control of the scan signal.

[0068] Specifically, the fourth switch T4 includes a first data loading control terminal T40, a first data loading conductive terminal T41, and a second data loading conductive terminal T42. The first data loading control terminal of the fourth switch T4 is electrically connected to the scan line Si, the first data loading conductive terminal T41 is electrically connected to the data line Dj, and the second data loading conductive terminal T42 is electrically connected to the first node N1. It is used to receive the data signal Data from the data line Dj and transmit it to the first node N1 under the control of the scan signal.

[0069] The fifth switch T5 includes a second data loading control terminal T50, a third data loading conductive terminal T53, and a fourth data loading conductive terminal T54. The second data loading control terminal T50 of the fifth switch T5 is electrically connected to the scan line Si. The third data loading conductive terminal T53 of the fifth switch T5 is electrically connected to the second voltage terminal ELVSS. The fourth data loading conductive terminal T54 of the fifth switch T5 is electrically connected to the third node N3. The fifth switch T5 is turned on under the control of the scan signal output from the scan line Si to control the second voltage terminal ELVSS to output a second power supply voltage to the third node N3. The voltage difference between the first node N1 and the third node N3 is the difference between the data voltage Vdata and the second power supply voltage (Vdata - V). GND That is, the gate-source voltage V between the gate G and source S of the driving switch T1. TG-S For Vdata-V GND , where V GND The grounding voltage is received by the ground terminal GND at the second voltage terminal ELVSS. In this embodiment, the grounding voltage is 0V, so the voltage of the first node N1 can be accurately maintained at the potential of the data voltage Vdata.

[0070] The initialization reset module 157 is connected to the adjustment control line Com, the second voltage terminal ELVSS, the first node N1 and the third node N3. During the initialization period H1, under the control of the initialization control signal provided by the adjustment control line Com, the module provides the second power supply voltage provided by the second voltage terminal ELVSS to the first node N1 and the third node N3, thereby initializing the first node N1 and the third node N3.

[0071] In this embodiment, the initialization reset module 157 includes a sixth switch T6 and a seventh switch T7. In this embodiment, the sixth switch T6 serves as the first reset switch, used to provide an initialization reset voltage to the first node N1, and the seventh switch T7 serves as the second reset switch, used to provide an initialization reset voltage to the third node N3.

[0072] Specifically, the sixth switch T6 includes a first initialization control terminal T60, a first initialization conductive terminal T61, and a second initialization conductive terminal T62. The first initialization control terminal T60 is electrically connected to the adjustment control line Com, the first initialization conductive terminal T61 is electrically connected to the second voltage terminal ELVSS, and the second initialization conductive terminal T62 is electrically connected to the first node N1. The sixth switch T6 is turned on or off under the control of the initialization control signal provided by the adjustment control line Com, and when turned on, it supplies the second power supply voltage provided by the second voltage terminal ELVSS to the first node N1.

[0073] Specifically, the sixth switch T6 is turned on under the control of the initialization control signal provided by the adjustment control line Com at the first initialization control terminal T60. The first initialization conductive terminal T61 and the second initialization conductive terminal T62 are electrically connected, thereby making the second voltage terminal ELVSS electrically connected to the first node N1. The second power supply voltage provided by the second voltage terminal ELVSS is applied to the first node N1 through the sixth switch T6, thereby initializing the first node N1.

[0074] It is understandable that when the first initialization control terminal T60 of the sixth switch T6 does not receive the initialization control signal provided by the adjustment control line Com, it is cut off, the first initialization conductive terminal T61 and the second initialization conductive terminal T62 are electrically disconnected, and the first node N1 stops receiving the second power supply voltage from the second voltage terminal ELVSS.

[0075] Correspondingly, the seventh switch T7 includes a second initialization control terminal T70, a third initialization conductive terminal T73, and a fourth initialization conductive terminal T74. The second initialization control terminal T70 is electrically connected to the adjustment control line Com, the third initialization conductive terminal T73 is electrically connected to the second voltage terminal ELVSS, and the fourth initialization conductive terminal T74 is electrically connected to the third node N3. The seventh switch T7 is turned on or off under the control of the initialization control signal provided by the adjustment control line Com, and when turned on, it supplies the second power supply voltage provided by the second voltage terminal ELVSS to the third node N3.

[0076] Specifically, the seventh switch T7 is turned on under the control of the adjustment control signal KS provided by the adjustment control line Com at the second initialization control terminal T70. The third initialization conductive terminal T73 and the fourth initialization conductive terminal T74 are electrically connected, thereby making the second voltage terminal ELVSS electrically connected to the third node N3. The second power supply voltage provided by the second voltage terminal ELVSS is applied to the third node N3 through the seventh switch T7, thereby initializing the third node N3.

[0077] It is understandable that when the second initialization control terminal T70 of the seventh switch T7 does not receive the initialization control signal provided by the adjustment control line Com, it is cut off, the third initialization conductive terminal T73 and the fourth initialization conductive terminal T74 are electrically disconnected, and the third node N3 stops receiving the second power supply voltage from the second voltage terminal ELVSS.

[0078] In this embodiment, the driving switch T1 is an N-type dual-gate thin-film transistor, whose first and second control terminals can be the gate, the first conductive terminal can be the drain, and the second conductive terminal can be the source. Meanwhile, the driving switch T1 to the third switch T3 are also low-temperature poly-silicon (LTPS) thin-film transistors; the fourth switch T4 to the seventh switch T7 are N-type oxide thin-film transistors. In this embodiment, the oxide thin-film transistor can be, for example, an indium gallium zinc oxide (IGZO) thin-film transistor.

[0079] It is understood that the control terminal of the driving switch transistors T1 to T7 can be the gate of the thin film transistor, and the conductive terminals can be the source and drain of the thin film transistor respectively. Of course, it can be adjusted according to specific needs, and this application does not limit it.

[0080] In this embodiment, the driving switches T1 through T7 are all N-type thin-film transistors, meaning they are in the on state under a high-level signal control, i.e., a high-level control signal is the effective signal to trigger their conduction; and they are in the off state under a low-level signal control. In other embodiments, the driving switches T1 through T7 can also be P-type thin-film transistors, meaning they are in the on state under a low-level signal control, i.e., a low-level control signal is the effective signal to trigger their conduction; and they are in the off state under a high-level signal control.

[0081] Please refer to Figures 3 and 4 together. Figure 4 is the signal output timing diagram in Figure 3, corresponding to the initialization reset period H1, compensation period H2, data loading period H3, and light emission period H4 within one scan cycle. The working state of pixel unit 15 is as follows:

[0082] During the initialization and reset period H1, the EM terminal outputs an emitting signal, and the Com line also outputs an adjustment control signal KS. Both the emitting signal and the adjustment control signal KS are high-level pulse signals.

[0083] The luminous signal controls the second switch T2 to conduct, and simultaneously, the control signal KS controls the third switch T3, the sixth switch T6, and the seventh switch T7 to conduct. The first power supply terminal VDD provides the first power supply voltage to the second node N2 and the fourth node N4 through the second switch T2 and the third switch T3. The second power supply terminal ELVSS outputs the second power supply voltage to the first node N1 and the third node N3 through the sixth switch T6 and the seventh switch T7. It can be understood that the second power supply voltage serves as the reset voltage for the first node N1 and the third node N3, or the reset voltage for the first node N1 and the third node N3 is the second power supply voltage provided by the corresponding second power supply terminal ELVSS. In this embodiment, the second power supply voltage is the low voltage provided by the ground terminal GND.

[0084] During the compensation period H2, the luminous signal terminal EM stops outputting the luminous signal, while the adjustment control line Com continuously outputs the adjustment control signal KS. The second switch T2 is turned off because it does not receive the first initialization control signal, and the drive switch T1 is turned on under the control of the fourth node N4. The fourth node N4, the third switch T3, the second node N2, and the drive switch T1 form a discharge path. The fourth node N4 discharges to the drive switch T1 and the third node N3 through the third switch T3 and the second node N2. The fourth node N4 gradually decreases from the first potential to the second potential until the drive switch T1 is turned off.

[0085] Figure 5 shows a schematic diagram of the conduction curve of the driving switch in Figure 3. Wherein, V... TG_S The voltage difference between the first control terminal and the second conductive terminal of the driving switch T1, i.e., the voltage difference between the first gate and the source, and also the voltage difference between the first node N1 and the third node N3; V MG_S This is the voltage difference between the second control terminal and the second conductive terminal of the driving switch T1, that is, the voltage difference between the second gate and the source, which is also the voltage difference between the fourth node N4 and the third node N3. DS The magnitude of the current flowing through the drive switch T1.

[0086] The following will be based on V MG S The discharge process is explained in detail using a curve of 2.5V. At the beginning of the compensation period H2, the discharge process is described using V... MG_S =2.5V (V N4 -V N3 =2.5V), V TG_S =0V(V N1 -V N4 Taking I = 0V as an example, at this time DS>0, the driving switch T1 is in the conducting state. During the compensation period H2, the fourth node N4 discharges to the driving switch T1 via the third switch T3 and the second node N2, causing the voltage difference (V) between the fourth node N4 and the third node N3 to... MG_S The discharge rate first decreases and then increases. In other words, the entire discharge process can be referenced by the arrows on the vertical axis, V. TG_S The voltage remains unchanged, while the voltage at the fourth node N4 continuously decreases. After the voltage at the fourth node N4 drops below the voltage at the third node N3, the voltage difference between the third node N3 and the fourth node N4 gradually increases again, that is, VMG_S gradually increases again. During this process, the driving current I... DS The voltage gradually decreases, and when the voltage at the fourth node N4 drops to the preset voltage, the drive current I... DS This can be ignored, and the driving switch T1 can be considered to be off. The critical voltage for the driving switch T1 to turn on and off is the threshold voltage Vth. In this embodiment, Vth = V TG_S =0. In other embodiments, the initialization reset period H1 can reduce V to 0. TG_S Set to other values, due to V in compensation period H2 TG_S While remaining unchanged, the threshold voltage Vth can also be other values. That is, the threshold voltage Vth can be set according to specific needs, and this application does not impose any restrictions on it.

[0087] During the data loading period H3, the scan line Si outputs a scan signal. The third switch T3, the sixth switch T6, and the seventh switch T7 are turned off, and the second capacitor C2 is used to maintain the voltage at the fourth node N4 at this time. Simultaneously, the scan signal controls the fourth switch T4 and the fifth switch T5 to turn on, and the data line Dj outputs the data signal Data corresponding to the data voltage V through the fourth switch T4. data (Data signal) is sent to the first node N1, and at the same time, the second power supply terminal ELVSS outputs the second power supply voltage V through the fifth switch T5. GND Up to the third node N3, at this point V TG_S =V N1 -V N4 =V data -V GND Because of V GND The voltage is 0V, meaning that the voltage difference between the first control terminal and the second conductive terminal of the driving switch T1 is equal to the data voltage V corresponding to the data signal. data .

[0088] By controlling the second power supply voltage V when the input data signal Data is received. GNDThe voltage at the third node N3, that is, accurately maintaining the voltage at the third node N3 at the second power supply voltage, effectively maintains the voltage difference V between the first control terminal and the second conductive terminal of the driving switch T1. TG_S To avoid voltage difference V TG_S Inaccuracy leads to a deterioration in image display.

[0089] During the light-emitting period H4, the scan line Si stops transmitting the scan signal, and the light-emitting signal line Emi outputs the light-emitting signal again. The fourth switch T4 is cut off because it does not receive the scan signal, and the data voltage V written to the data line Dj... data The signal is transmitted to the first node N1 and stored in the first capacitor C1, which maintains the voltage of the first node N1. Simultaneously, the light-emitting signal provided by the optical signal line Emi controls the second switch T2 to turn on, forming a path between the first power supply terminal VDD and the second power supply terminal ELVSS. This drives the voltage divider between the switch T1 and the light-emitting element E, causing the voltage of the third node N3 to rise to V. E +V GND To drive the light-emitting element E to emit light, V E This is the voltage used to drive the light-emitting element E to emit light.

[0090] As the voltage at the third node N3 increases, the voltage at the first node N1 also rises to V due to the coupling of the first capacitor C1. data +V E +V GND The fourth node N4 rises to V due to the coupling of the second capacitor C2. MG +V E +V GND At this time, the current through the light-emitting element is I = (k / 2)(V) TG_S -V th ) 2 =(k / 2)[(1-α)(V data -V GND -V th )] 2 Among them, due to V th =V TG_S =0, such that I = (k / 2)[(1-α)(V data -VSS)] 2 .

[0091] During the initialization and reset period H1, the control line Com controls the sixth switch T6 and the seventh switch T7 to write the same second power supply voltage to the first node N1 and the third node N3, respectively, which is to say, to write the ground voltage V. GND The threshold voltage V driving the switch transistor T1 th =V GND -V GND=0, meaning that by adjusting the voltage applied to the gate-source of the driving switch T1 during the initialization reset period H1 and the compensation period H2, its threshold voltage can be accurately limited to 0V. This facilitates uniform brightness compensation of the threshold voltage of the driving switch T1 in each pixel unit 15 in the display area, ensuring the uniformity of brightness compensation. Therefore, in this embodiment, by setting the adjustment module 153 and the storage module 154, the threshold voltage of the driving module 151 in the pixel unit 15 can be directly adjusted to a preset range. Thus, the threshold voltages of the driving modules 151 in adjacent pixel units 15 can be adjusted to the same preset range, eliminating the difference in luminous intensity caused by different threshold voltages of the driving modules 151 in adjacent pixel units, thereby avoiding brightness differences between adjacent pixel units 15 and effectively improving the display effect.

[0092] Please refer to Figure 6, which is a side view of some components in the corresponding pixel unit 15 of the display panel 10 shown in Figure 2.

[0093] As shown in Figure 6, corresponding to pixel unit 15, display panel 10 includes substrate 100, driving layer 200, display layer 300 and shielding structure 400.

[0094] A driving layer 200 is disposed on the substrate 100 and is used to drive the light-emitting element E in the display layer 300 to emit light. The driving layer 200 contains components including a first switch transistor T1 to a seventh switch transistor T7 (as shown in Figure 5), a first capacitor C1, a second capacitor C2, etc. The display layer 300 contains the light-emitting element E (as shown in Figure 5). A shielding structure 400 is disposed around the light-emitting element E to separate pixel units 15 of different colors, avoiding pixel crosstalk.

[0095] More specifically, the driving layer 200 includes first switch transistors T1 to third switch transistors T3 and fourth switch transistors T4 to seventh switch transistors T7. The first switch transistors T1 to third switch transistors T3 are LTPS (Low Temperature Polycrystalline Silicon) thin-film transistors (LTPS TFTs), and the fourth switch transistors T4 to seventh switch transistors T7 are oxide thin-film transistors, such as IGZO (Indium Zinc Oxide) thin-film transistors (IGZO TFTs). Figure 6 shows only one LTPS thin-film transistor from the first switch transistors T1 to third switch transistor T3 and one IGZO thin-film transistor from the fourth switch transistors T4 to seventh switch transistor T7.

[0096] Corresponding to the LTPS thin-film transistor, starting from the substrate 100, it sequentially includes a first active layer ACT1, a first gate insulating layer GI1, a first gate GT1, a first buffer layer BU1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a first source-drain layer SD1, and a first planarization layer PLN1. In this embodiment, the LTPS thin-film transistor shown in Figure 6 is the driving switch T1 of a dual-gate transistor, and the material of the first active layer ACT1 is low-temperature polycrystalline silicon. It can be obtained by first depositing amorphous silicon (a-Si) and then converting crystalline silicon to polycrystalline silicon (P-Si) and then patterning it. It can be understood that one or more buffer layers or other layer structures can also be provided between the first active layer ACT1 and the surface of the substrate 100.

[0097] Corresponding to the IGZO thin film transistor, the second active layer ACT2, the second gate insulating layer GI2, the second gate GT2, the interlayer insulating layer ILD, the first source-drain layer SD1, and the first planarization layer PLN1 are sequentially disposed starting from the surface of the first buffer layer BU1. The IGZO thin film transistor is not directly disposed on the surface of the substrate 100, but is spaced apart by a predetermined distance.

[0098] In this embodiment, the IGZO thin-film transistor shown in Figure 6 is any one of the fourth switch transistor T4 to the seventh switch transistor T7, and the material of the second active layer ACT2 is indium gallium zinc oxide or the like. In this embodiment, the IGZO thin-film transistor shown in Figure 6 can be either the sixth switch transistor T6 or the seventh switch transistor T7.

[0099] In this embodiment, the distance between the IGZO thin film transistor and the substrate 100 is larger than that between the LTPS thin film transistor and the substrate 100. In other words, the first distance LL1 between the LTPS thin film transistor and the substrate 100 is smaller than the second distance LL2 between the IGZO thin film transistor and the substrate 100. More specifically, the first distance LL1 between the first active layer ACT1 in the LTPS thin film transistor and the substrate 100 is smaller than the second distance LL2 between the second active layer ACT2 in the IGZO thin film transistor and the substrate 100.

[0100] Since the fourth to seventh switches T4 are IGZO thin-film transistors, their leakage current is relatively small, making it easier to achieve low-frequency driving. Furthermore, the smaller leakage current helps maintain the voltages of the corresponding first node N1 and third node N3, preventing brightness decay during low-frequency driving. The first to third switches T3 are LTPS thin-film transistors, which have high mobility, effectively increasing their driving current and ensuring that the display element E can generate a larger maximum brightness. They also reduce the voltage drop at the first power supply terminal VDD caused by their own resistance, allowing the voltage to reach the preset potential more quickly. Referring to Figure 6, the display layer 300 includes a second source-drain layer SD2 and a second planarization layer PLN2. The second source-drain layer SD2 is disposed on the surface of the first planarization layer PLN1, and the second planarization layer PLN2 is disposed on the surface of the second source-drain layer SD2.

[0101] In this embodiment, the portion of the second source-drain layer SD2 facing the LTPS thin film transistor is connected to and electrically connected to the first source-drain layer SD1 in the LTPS thin film transistor, and the portion of the second source-drain layer SD2 facing the IGZO thin film transistor is connected to and electrically connected to the first source-drain layer SD1 in the IGZO thin film transistor.

[0102] The display layer 300 further includes an anode AND, an organic material layer OLED, and a cathode CAT, which are sequentially stacked on the surface of the second planarization layer PLN2. The anode AND, OLED, and CAT constitute a light-emitting element E. The anode AND is electrically connected to the second source-drain layer SD2 of the LTPS thin-film transistor, which serves as the driving switch T1, through an opening in the second planarization layer PLN2.

[0103] In this embodiment, a pixel definition layer PDL is also included on the surface of the second planarization layer PLN2 and the anode AND. The pixel definition layer PDL also includes an opening (not shown) at the position corresponding to the anode AND. The anode AND is exposed from the opening position of the pixel definition layer PDL. In other words, a portion of the organic material layer OLED and the cathode CAT are sequentially stacked on the surface of the anode AND at the opening position of the pixel definition layer PDL. That is, the portion of the stacked organic material layer OLED and the cathode CAT are disposed on the same layer as the pixel definition layer PDL. Another portion of the stacked organic material layer OLED and the cathode CAT are disposed on the surface of the pixel definition layer PDL outside the opening. In this embodiment, the pixel definition layer PDL is disposed around the organic material layer OLED to block the light emitted from two adjacent light-emitting elements E from mixing interference.

[0104] The overhanging structure 400 includes a suspended conductive structure 401 and a blocking structure 402 disposed around the light-emitting element E. The suspended conductive structure 401 is disposed on the surface of the pixel definition layer, and the blocking structure 402 covers and blocks the suspended conductive structure 401. That is, the projected area of ​​the blocking structure 402 on the substrate 100 is larger than the projected area of ​​the suspended conductive structure 401 on the substrate 100. In this embodiment, the suspended conductive structure 401 is connected to the power module 20 to serve as the second power supply terminal ELVSS to receive the second power supply voltage. Since the second power supply terminal ELVSS is connected to the ground terminal GND in this embodiment, the entire suspended conductive structure 401 can serve as a ground trace or a ground signal line.

[0105] In this embodiment, the material of the suspended conductive structure 401 can be one or two conductive metals such as Mo, Al, Mg, Cu, and Cr, or conductive oxides such as ITO and IZO. The material of the shielding structure 402 can be an insulating material or a non-insulating material, used to protect the suspended conductive structure 401, and cooperate with the suspended conductive structure 401 to block the light emitted by the light-emitting element E from mixing with the light emitted by other adjacent pixel units 15. The material of the shielding structure 402 can be an inorganic insulating material such as SiNx and SiOx, or an inorganic conductive material such as Ti.

[0106] In this embodiment, the shielding structure 400 is formed using a maskless evaporation deposition combined with photolithography OLED process, namely the eLEAP OLED process technology. By forming a shielding structure 402 on the surface of the suspended conductive structure 401, the isolation effect of the suspended conductive structure is enhanced. This allows the suspended conductive structure 401 and the shielding structure 402 to better prevent the organic light-emitting material and cathode material from depositing in the light-emitting area of ​​the light-emitting element E in other color pixel units 15 during the evaporation deposition of the organic light-emitting material OLED and cathode CAT in the pixel unit 15, thus more effectively avoiding crosstalk between pixel units.

[0107] In this embodiment, the suspended conductive structure 401 can extend directly along the direction adjacent to the substrate 100 through the opening (not shown) of the pixel definition layer PDL as shown in FIG. 6, and be electrically connected to the second source-drain layer SD2 corresponding to the IGZO thin film transistor. Alternatively, in other embodiments of this application, the suspended conductive structure 401 can also be directly disposed on the surface of the pixel definition layer PDL, and then electrically connected to the second source-drain layer SD2 corresponding to the IGZO thin film transistor through other conductive structures. It can be understood that in this embodiment, it is only necessary for the suspended conductive structure 401 to be electrically connected to the second source-drain layer SD2 of the IGZO thin film transistor, and the connection method can be adjusted according to the specific structure of the shielding structure 400, and is not limited to the aforementioned structure and connection method.

[0108] The suspended conductive structure 401 is electrically connected to the second source-drain layer SD2 of the IGZO thin-film transistor, which serves as the sixth switch T6 or the seventh switch T7. Simultaneously, the suspended conductive structure 401 is also electrically connected to the cathode CAT. Therefore, the cathode CAT of the light-emitting element E can be directly connected to the conductive terminal of the sixth switch T6 or the seventh switch T7 via the suspended conductive structure 401. Furthermore, the suspended conductive structure 401 also directly serves as the second power supply terminal ELVSS, receiving the second power supply voltage, thereby directly providing the second power supply voltage to the cathode CAT of the light-emitting element E, the conductive terminals of the sixth switch T6, and the seventh switch T7.

[0109] In this embodiment, since the IGZO thin-film transistor is disposed on the surface of the first buffer layer BU1, it is closer to the suspended conductive structure 401 than the LTPS thin-film transistor, thus facilitating its electrical connection to the second power supply terminal ELVSS during the manufacturing process. Simultaneously, the IGZO and LTPS thin-film transistors are staggered in the thickness direction of the display panel 10, which further reduces the space occupied by the thin-film transistors within the plane of the display panel 10, and further reduces the area occupied by the pixel unit 15, providing more space for improving the pixel resolution of the display panel 10. In this embodiment, the suspended conductive structure 401 connects to the ground terminal GND of the external power module 20 and the second power supply terminal ELVSS. The suspended conductive structure 401 receives the ground voltage V, which serves as the second power supply voltage, from the outside. GND The voltage is transmitted to the second power supply terminal ELVSS, providing a low-voltage second power supply voltage to the pixel unit 15, thus eliminating the need to separately adjust the control line Com, further simplifying the structure of the pixel unit 15 and the display panel 10.

[0110] Please refer to Figure 7, which is a top view of the display layer 300 and the shielding structure 400 in a portion of the pixel unit 15 in the display area 10a of the display panel 10. As shown in Figure 7, the suspended conductive structures 401 are all arranged around the light-emitting element E and electrically connected to the cathode CAT in the light-emitting element E. Thus, the shielding structure 400 and the suspended conductive structure 401 form a mesh structure. In this embodiment, the suspended conductive structure 401 forms a mesh structure, so that the display panel 10 serves as a connection to the second power supply terminal ELVSS and provides a ground voltage V. GND The overall resistance of the traces is relatively small, thereby ensuring that each pixel unit 15 can accurately obtain the second power supply low voltage, which facilitates the pixel unit 15 to accurately obtain the compensation signal and data signal to execute accurate image display.

[0111] As shown in Figure 8, the display device 1 includes a first compensation mode and a second compensation mode. Please refer to Figures 8-10, which are signal output timing diagrams of the compensation process of the display device 1 shown in Figures 2-3.

[0112] As shown in Figures 8 and 9, when the first compensation mode is executed, for each pixel unit 15, during the image display stage of each frame image display process, n scan lines sequentially output scan signals. At the same time, the signal line Com and the light emission control line EM are adjusted to output signals according to a preset timing sequence to control the threshold voltage V of the driving switch transistor T1 in the pixel unit 15. th Adjustments are made, that is, during the compensation period, H2 coordinates with the threshold voltage V. th Compensation is performed, and then data signals are received for image display. That is, pixel unit 15 sequentially executes the initialization reset period H1 to the light emission period H4 during each frame image display process. In other words, in this embodiment, during each frame image display stage, pixel unit 15 sequentially executes the initialization reset period H1, the compensation period H2, the data loading period H3, and the light emission period H4. In this embodiment, the compensation period H2 lasts for 2 units of time.

[0113] In one embodiment of this application, as shown in FIG8, during the initialization reset period H1 and the compensation period H2, both the first node N1 and the third node N3 of the driving switch T1 are in a compensation state, which can last for two periods. As shown in FIG9, both nodes are in the compensation state during the compensation period H2. In this embodiment, the compensation period H2 lasts for one unit of time. It can be understood that the longer the compensation time for the driving switch T1, the better the compensation effect.

[0114] As shown in Figure 10, in the second compensation mode, for each pixel unit 15, during the non-image display phase, the pixel unit 15 adjusts the threshold voltage Vth of the driving switch transistor T1 during the initialization reset period H1 and the compensation period H2. During the image display phase, the pixel unit 15 executes the data loading period H3 and the light emission period H4 to receive data signals and display images. The non-image display phase can be the power-on non-image display phase of the display panel 10 or the vertical blanking period between any two adjacent image frames. That is, the initialization reset period H1 and the compensation period H2 correspond to the non-image display phase, while the data loading period H3 and the light emission period H4 correspond to the image display phase. In other words, each image display phase corresponds only to the data loading period H3 and the light emission period H4.

[0115] Before each frame of image display, i.e., during the vertical blanking phase of the non-image display phase or the power-on non-image display phase, compensation is simultaneously performed on all pixel units 15 of the display panel 10. During each frame of image display, pixel units 15 only receive data signals to perform image display, or compensation is not required for each frame, but is performed once during the vertical blanking phase after each consecutive a-frame image display period. In other words, the initialization reset period H1 and the compensation period H2 are located during the vertical blanking phase of each a-frame image display period, where a is an integer greater than or equal to 1. This means that the threshold voltage of the driving switch can be adjusted after multiple consecutive frame image display phases. In other words, during the non-image display phase, the initialization reset period H1 and the compensation period H2 in the first compensation mode can be executed to complete the setting process of the threshold voltage of the driving switch T1. Thus, during a single frame of image display, the aforementioned two periods are not required; only the data loading period H3 and the light emission period H4 are executed to complete the data writing and light emission process.

[0116] In this embodiment, the initialization reset period H1 and the compensation period H2 are both executed during the non-image display phase, while the data loading period H3 and the light emission period H4 are both during the image display phase. The non-image display phase is either the non-image display phase when the display device 1 is powered on or the vertical blanking period between any two adjacent frames, thereby effectively improving the time for the pixel unit 15 to perform image display and resulting in better image display effect.

[0117] The embodiments of this application also have the effect of increasing the threshold voltage compensation range. The specific principle is as follows: As can be seen from the aforementioned current formula, I=(k / 2)(V TG_S -Vth) 2 In this embodiment of the application, after the compensation period H2 and the data loading period H3, V TG_S =V data -0, meaning V TG_S Excluding Vth. For the traditional scheme where the driving switch is a single-gate transistor, after the compensation period H2 and the data loading period H3, the gate-source voltage V of the driving switch T1... TG_S =V data +Vth-Vt, where Vt can be understood as the reference voltage, and V... TG_S The voltage difference between the gate and the source includes the threshold voltage Vth. Because of the presence of the threshold voltage Vth, the overall range of the data voltage Vdata corresponding to the data signal Data is compressed, so the compensation range of the threshold voltage Vth is limited.

[0118] In this embodiment of the application, the gate-source voltage V driving the switch T1 is... TG_SExcluding the threshold voltage Vth, even if the range of the threshold voltage Vth is set very large, the overall range of the data voltage Vdata will not be compressed. Furthermore, since this embodiment can compensate for pixel units 15 during non-image display stages, it reduces the occupation of display time. It can also adjust and compensate the threshold voltage of the driving module 151 while displaying multiple frames of images at intervals, eliminating the need to compensate the driving switch T1 frame by frame. This effectively avoids the problem of insufficient compensation time for the driving switch T1 due to compressing and reducing the compensation time to ensure the refresh rate of the image display. This effectively increases the compensation time, making the compensation of the threshold voltage of the driving switch T1 more sufficient, ensuring the accuracy and uniformity of the image display, and resulting in a better image display effect.

[0119] In this embodiment, the initialization reset module 157 is used to perform initialization reset during the initialization reset period H1 and to assist in performing threshold voltage compensation for the drive switch T1 during the compensation period H2. The data loading module 156 performs data signal loading during the data loading period H3. It can be seen that the initialization reset period H1, the compensation period H2, and the data loading period H3 are performed by independent modules at different times. Therefore, the data loading period H3 is not occupied by the initialization reset period H1 or the compensation period H2, which effectively reduces the time occupied by the pixel unit 15 for image display and improves the image display effect.

[0120] In this embodiment, the initialization reset module 157 and the data loading module 156 employ IGZO thin-film transistors (TFTs). Because of their low leakage current, IGZO TFTs are easier to drive at low frequencies, ensuring low refresh rate image display. Furthermore, the low leakage current of IGZO TFTs is more conducive to maintaining the voltage and current load of the corresponding drive module 151 at the corresponding node when pixel units 15 simultaneously perform compensation.

[0121] In this embodiment, the suspended conductive structure 40 has an overall mesh structure. The IGZO thin-film transistor and the second power supply terminal ELVSS are simultaneously connected to the suspended conductive structure 40, thereby providing a ground voltage V within the display panel 10. GND If the overall resistance of the traces is low, the suspended conductive structure 40 of the multiplexed mesh structure can effectively withstand the large current load of the entire surface being compensated at the same time, ensuring that each pixel unit 15 can accurately obtain the second power supply low voltage, so that the pixel unit 15 can accurately obtain the compensation signal and data signal to execute accurate display image.

[0122] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A display panel, comprising a display area, wherein the display includes a plurality of pixel units arranged in an array, the pixel units being used to perform image display based on received data signals, characterized in that, The pixel unit includes a driving module, an adjustment module, an initialization / reset module, and a light-emitting module. The driving module and the light-emitting module are connected in series between a first power supply terminal and a second power supply terminal. The adjustment module is electrically connected to the driving module. The initialization / reset module is electrically connected to the driving module and the second power supply terminal. It is used to transmit the second power supply voltage provided by the second power supply terminal to the driving module according to the adjustment control signal during the initialization / reset period and the compensation period, so as to cooperate in resetting and data compensation of the driving module. The adjustment module is used to adjust the threshold voltage of at least one driving switch in the driving module to a preset range according to the adjustment control signal and the second power supply voltage during the initialization / reset period and the compensation period. The driving switch is used to provide driving current to the light-emitting module according to the data signal and the first power supply voltage provided by the first power supply terminal during the light-emitting period, and drive the light-emitting module to emit corresponding light to perform image display. The initialization / reset period, the compensation period, the data loading period, and the light-emitting period are time periods arranged sequentially in time.

2. The display panel as described in claim 1, characterized in that, The pixel unit further includes a control module and a storage module. The control module is electrically connected between the first power supply terminal and the driving module, and is also electrically connected between the first power supply terminal and the adjustment module. The storage module is electrically connected between the adjustment module and the driving module. During the initialization and reset period, the control module controls the first power supply terminal to provide the first power supply voltage to the storage module through the adjustment module according to the light emission signal. During the compensation period, the adjustment module controls the storage module to discharge to the driving module to adjust the threshold voltage of the driving module to a preset range.

3. The display panel as described in claim 2, characterized in that, The pixel unit further includes a data loading module, which is electrically connected to the data line, the scan line, the driving module, and the second power supply terminal. During the data loading period, the data loading module receives the data signal from the data line under the control of the scan signal provided by the scan line and transmits it to the driving module. At the same time, it transmits the second power supply voltage provided by the second power supply terminal to the driving module. The driving module provides the driving current to the light-emitting module under the control of the first power supply voltage, the second power supply voltage, and the data signal. The first power supply voltage is greater than the second power supply voltage.

4. The display panel as described in claim 3, characterized in that, The data loading module includes a data loading switch and an auxiliary data loading switch. The data loading switch is used to transmit the data signal received from the data line to the first node of the drive module under the control of the scan signal. The auxiliary data loading switch is used to transmit the second power supply voltage to the third node of the drive module under the control of the scan signal. The voltage difference between the first node and the third node serves as a threshold voltage for controlling the drive module to turn on or off. The auxiliary data loading switch is connected to the second power supply terminal. The drive module is also connected to the control module through a second node and to the adjustment module and the storage module through a fourth node. The voltage difference between the fourth node and the third node is also used to control the drive module to turn on or off.

5. The display panel as described in claim 4, characterized in that, The initialization reset module includes a first reset switch and a second reset switch. The first reset switch is used to transmit the second power supply voltage provided by the second power supply terminal to the first node under the control of the adjustment control signal. The second reset switch is used to transmit the second power supply voltage provided by the second power supply terminal to the third node under the control of the adjustment control signal. The second reset switch is connected to the second power supply terminal.

6. The display panel as described in claim 5, characterized in that, The control module, the drive module, and the adjustment module include multiple low-temperature polycrystalline silicon thin-film transistors as switching transistors; the initialization and reset module and the data loading module include multiple oxide thin-film transistors as switching transistors.

7. The display panel as described in claim 6, characterized in that, For any given pixel unit, the display panel includes a substrate, a driving layer, a display layer, and a shielding structure stacked sequentially. The low-temperature polycrystalline silicon thin-film transistor and the oxide thin-film transistor are located within the driving layer. The low-temperature polycrystalline silicon thin-film transistor is spaced apart from the substrate by a first distance, and the oxide thin-film transistor is spaced apart from the substrate by a second distance. The first distance is less than the second distance. The display layer includes at least one light-emitting element. The shielding structure is disposed around the light-emitting element in the display layer. The shielding structure is electrically connected to the light-emitting element and at least one oxide thin-film transistor. The shielding structure is used to receive the second power supply voltage and transmit the second power supply voltage to the light-emitting element and at least one oxide thin-film transistor.

8. The display panel as described in claim 7, characterized in that, The shielding structure includes a stacked suspended conductive structure and a shielding structure. The suspended conductive structure is disposed on the surface of the display layer and electrically connected to the second power supply terminal, and electrically connected to the conductive terminal of the oxide thin film transistor through the opening of the display layer. The suspended conductive structure is used to receive the second power supply voltage from the outside and transmit it to the second power supply terminal and at least one of the oxide thin film transistors.

9. A display device, characterized in that, It includes a power module and a display panel as described in any one of claims 1-8, wherein the power module is used to provide driving power to the display panel to drive the display panel to perform image display.

10. The display device as claimed in claim 9, characterized in that, The display device includes a first compensation mode and a second compensation mode. In the first compensation mode, each frame image display stage, corresponding to the pixel unit, includes the initialization reset period, the compensation period, the data loading period, and the light emission period, which are arranged consecutively in time. In the second compensation mode, corresponding to the pixel unit, the initialization reset period and the compensation period correspond to the non-image display stage, and the data loading period and the light emission period correspond to the image display stage, wherein the non-image display stage is the power-on non-display period; or, corresponding to the pixel unit, the initialization reset period and the compensation period are performed in the non-image display stage, and the data loading period and the light emission period are performed in the image display stage, wherein the non-image display stage is the vertical blanking stage, and the vertical blanking stage is located between the image display stages of two adjacent frames, wherein the initialization reset period and the compensation period are located in each of the vertical blanking stages; or, the initialization reset period and the compensation period are located in the vertical blanking period of each frame a, wherein a is an integer greater than 1.

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