Gate driver and display device including the same

Abstract

A gate driver according to an embodiment and a display device including the same are disclosed. The gate driver includes a plurality of signal transmission portions cascaded via carry lines configured to apply a respective carry signal as an input to the plurality of signal transmission portions, where each of the plurality of signal transmission portions includes: a first output circuit configured to output a first signal to the plurality of signal transmission portions, and a second output circuit configured to output a second signal to the plurality of signal transmission portions; a first signal transmission section configured to receive the first carry signal from the previous signal transmission section and output a second carry signal based on the first carry signal and a clock signal; a selection circuit configured to receive the second carry signal from the first output circuit and selectively output the second carry signal based on a voltage level of a selection data voltage; and a second output circuit configured to output a strobe signal based on the second carry signal selectively transmitted from the selection circuit and another clock signal.

Description

A gating driver and a display device including the gating driver Technical Field

[0001] This disclosure relates to gating drivers and display devices including thereto. Background Technology

[0002] Electroluminescent display devices are classified into inorganic light-emitting display devices and organic light-emitting display devices based on the material of the light-emitting layer. Active matrix organic light-emitting display devices include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), and have the advantages of fast response speed, high luminous efficiency, brightness, and wide viewing angle.

[0003] In organic light-emitting display devices, organic light-emitting diodes (called "OLEDs") are formed in each pixel. These OLED displays not only have a fast response and excellent luminous efficiency, brightness, and viewing angle, but also have excellent contrast and color reproduction because they can express black tones as perfect black.

[0004] Some display devices (e.g., liquid crystal display devices or organic light-emitting display devices) include a display panel having multiple sub-pixels, a driver that outputs drive signals for driving the display panel, a power supply that generates power to be supplied to the display panel or the driver, etc.

[0005] The descriptions provided in this Background section should not be assumed to be prior art simply because they are mentioned in or associated with this section. The Background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0006] Users can display two or more content images on a single screen of a display device, or run two or more applications to display different images of the application on the screen. In such a multitasking environment, the pixels on the display device are driven at a single frame rate.

[0007] Traditional display devices use gating drivers that output gating signals sequentially. Because the gating driver lacks a separate structure to block the output in the middle of a frame, it is impossible to drive different areas of the panel at different frequencies.

[0008] This disclosure relates to a gating driver and a display device including the same, which substantially eliminates one or more problems caused by the aforementioned limitations and disadvantages.

[0009] Therefore, the inventors of this disclosure recognized the limitations mentioned above and other limitations related to the related art, and conducted various experiments to realize a gating driver and a display device including the gating driver capable of driving different regions at different frequencies.

[0010] It should be noted that the aspects of this disclosure are not limited to those described above, and other aspects of this disclosure will be apparent to those skilled in the art from the following description.

[0011] To achieve these and other aspects of the inventive concept, as implemented and broadly described herein, a gating driver according to embodiments of the present disclosure may include a plurality of signal transmission units cascaded together via carry lines configured to apply a corresponding carry signal as input to the plurality of signal transmission units, wherein each of the plurality of signal transmission units includes: a first output circuit configured to receive a first carry signal from a preceding signal transmission unit and output a second carry signal based on the first carry signal and a clock signal; a selection circuit configured to receive the second carry signal from the first output circuit and selectively output the second carry signal based on a voltage level of a selection data voltage; and a second output circuit configured to output a gating signal based on the second carry signal selectively transmitted from the selection circuit and another clock signal.

[0012] A display device according to embodiments of the present disclosure may include a pixel array, wherein a plurality of data lines, a plurality of gating lines, and a plurality of pixel circuits are arranged; a data driver configured to output data voltages to the plurality of data lines; and a gating driver configured to output gating signals to the plurality of gating lines, wherein the gating driver includes a plurality of signal transmission units cascaded via carry lines, the carry lines being configured to apply corresponding carry signals as inputs to the plurality of signal transmission units, wherein each of the plurality of signal transmission units includes: a first output circuit configured to receive a first carry signal from a previous signal transmission unit and output a second carry signal based on the first carry signal and a clock signal; a selection circuit configured to receive the second carry signal from the first output circuit and selectively output the second carry signal based on the voltage level of a selected data voltage; and a second output circuit configured to output a gating signal based on the second carry signal selectively transmitted from the selection circuit and another clock signal.

[0013] Additional features and aspects of this disclosure are set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the inventive concept provided herein. Other features and aspects of the inventive concept may be realized and obtained by means of the structures pointed out in this disclosure, the contents derived therefrom, the appended claims, and the drawings.

[0014] According to this disclosure, the gating driver includes multiple signal transmission units, each including two output circuits and a selection circuit. One of the output circuits outputs a carry signal, the selection circuit selectively transmits the carry signal, and the other output circuit outputs a gating signal based on the selectively transmitted carry signal. Therefore, it is easy to change the drive frequency switching between high-speed and low-speed drive in each region, and to arbitrarily change the size of regions driven by different drive frequencies.

[0015] This disclosure can respond to overlapping outputs or changes in output timing of gating signals.

[0016] This disclosure enables low-speed operation based on the region, thus achieving low-power operation.

[0017] The effects of this specification are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims.

[0018] It should be understood that both the above general description and the following detailed description are illustrative and explanatory, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0019] The accompanying drawings may be included to provide a further understanding of the present disclosure and may be incorporated into and constitute a part of the present disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the various principles of the present disclosure.

[0020] The above and other aspects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0021] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 2 is a diagram illustrating a pixel circuit according to an exemplary embodiment of the present disclosure;

[0023] Figure 3 is a diagram illustrating an example of the driving timing of the pixel circuit shown in Figure 2;

[0024] Figure 4 is a diagram illustrating a shift register of a strobe driver according to an exemplary embodiment of the present disclosure;

[0025] Figure 5 is a diagram illustrating an example drive waveform of the strobe driver shown in Figure 4;

[0026] Figure 6 is a diagram illustrating the configuration of the output circuit according to an exemplary embodiment of the present disclosure shown in Figure 4;

[0027] Figure 7 is a diagram illustrating an example configuration of the selection circuit shown in Figure 4;

[0028] Figures 8A to 8D are illustrations of the operating principle of the selection circuit shown in Figure 7;

[0029] Figures 9A and 9B are diagrams illustrating a gating driver according to an exemplary embodiment of the present disclosure;

[0030] Figure 10 is a diagram illustrating the configuration of the output circuit according to another exemplary embodiment of the present disclosure, as shown in Figure 4;

[0031] Figure 11 is a diagram illustrating a strobe driver according to another exemplary embodiment of the present disclosure;

[0032] Figure 12 is a diagram illustrating the output result of a carry signal according to an exemplary embodiment of the present disclosure; and

[0033] Figure 13 is a diagram illustrating the output result of a gating signal according to an exemplary embodiment of the present disclosure.

[0034] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, and convenience, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0035] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted where it would unnecessarily obscure the essential points of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order. Similar reference numerals designate similar elements throughout. The names of corresponding elements used in the following description may be chosen solely for ease of writing and may therefore differ from the names used in actual products.

[0036] The advantages and features of this specification, as well as methods for implementing them, will become apparent from the exemplary embodiments described in detail with reference to the accompanying drawings. However, this specification is not limited to the embodiments described below, and may be implemented in various forms. These embodiments are provided only to fully disclose this disclosure and to fully convey the scope of this disclosure to those skilled in the art, and this specification is defined by the disclosed claims.

[0037] Since the shapes, dimensions, scales, angles, quantities, etc., disclosed in the accompanying drawings for describing embodiments of this disclosure are merely exemplary, this disclosure is not limited to what is shown. The same reference numerals indicate the same components throughout the specification. Furthermore, in describing this disclosure, detailed descriptions of related known technologies will be omitted where it is determined that such detailed descriptions might unnecessarily obscure the essential points of this disclosure. Any implementation described herein as an "example" is not necessarily to be construed as more preferred or advantageous than other implementations.

[0038] When terms such as “comprising,” “having,” or “including” are used in this specification, other components may be added unless more restrictive terms such as “only” are used. Unless otherwise expressly stated, components referred to in the singular include those in the plural.

[0039] When interpreting components, it should be understood that a component includes a range of errors or tolerances, even without a separate explicit description of the component.

[0040] When describing positional relationships, such as using terms like "on," "above," "below," "above," "under," "below," "near," "close to," "adjacent to," "beside," or "next to" to describe the positional relationship between two components, one or more other components may be placed between the two components unless more restrictive terms such as "immediately," "directly," or "closely" are used. For example, when a structure is described as being "above," "below," "on top," "below," "below," "near," "close to," "adjacent to," "beside," or "next to" another structure, this description should be interpreted to include situations where these structures are in contact with each other and situations where a third structure is placed or inserted between them. Furthermore, the terms "left," "right," "top," "bottom," "down," "up," "upper," "lower," etc., refer to any frame of reference.

[0041] When describing temporal relationships, such as when time sequence is described as "after," "following," "next," and "before," discontinuous situations may be included unless more restrictive terms such as "just," "immediately," or "directly" are used.

[0042] Although the terms "first," "second," "A," "B," "(a)," "(b)," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another, and the nature, order, sequence, or number of the corresponding elements should not be limited by these terms. Therefore, the first component mentioned below can also be a second component within the technical spirit of this disclosure. Furthermore, when an element or layer is described as "connected," "joined," or "adhered" to another element or layer, unless otherwise specified, the element or layer can not only be directly connected or adhered to the other element or layer, but also indirectly connected or adhered to the other element or layer through one or more intermediate elements or layers "disposed" between the elements or layers.

[0043] The term “at least one” should be understood to include any and all combinations of one or more of the related listed items. For example, “at least one of the first element, the second element, and the third element” means all combinations of the three listed elements, any two of the three elements, and each individual element, namely the first element, the second element, or the third element.

[0044] Features of the various embodiments of this disclosure may be linked or combined with each other in part or in whole, and may interoperate with each other and be technically driven in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant field, and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined herein. For example, the terms “component” or “unit” may be applied, for example, to a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the described functions as would be understood by one of ordinary skill in the art.

[0046] The transistors used in the display devices according to exemplary embodiments of this disclosure can be implemented as either n-channel transistors (NMOS) or p-channel transistors (PMOS). The transistor can be implemented as an oxide semiconductor transistor having an oxide semiconductor as the active layer or an LTPS transistor having a low-temperature polycrystalline silicon (LTPS) as the active layer. The transistor can include at least a gate electrode, a source electrode, and a drain electrode. The transistor can be implemented as a thin-film transistor (TFT) on a display panel. Charge carriers in the transistor flow from the source electrode to the drain electrode. In the case of an n-channel transistor (NMOS), since the charge carriers are electrons, the source voltage can be lower than the drain voltage, allowing electrons to flow from the source electrode to the drain electrode. In an n-channel transistor (NMOS), current can flow from the drain electrode to the source electrode, and the source electrode can be an output terminal. In the case of a p-channel transistor (PMOS), since the charge carriers are holes, the source voltage can be higher than the drain voltage, allowing holes to flow from the source electrode to the drain electrode. Because holes flow from the source electrode to the drain electrode in a p-channel transistor (PMOS), current can flow from the source electrode to the drain electrode, and the drain electrode can be the output terminal. Therefore, it should be noted that the source and drain of a transistor are not fixed, as the source and drain can change depending on the applied voltage. In this disclosure, the transistor is described by assuming it to be an n-channel transistor (NMOS), but this disclosure is not limited thereto; p-channel transistors can also be used, and consequently, the circuit configuration can be changed.

[0047] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0048] The following implementations may be combined or integrated with each other in whole or in part, and may be linked and operated in various technical ways. The implementations may be performed independently of each other, or may be performed in association with each other.

[0049] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, each gating driver according to all embodiments of the present disclosure and all components of each display device including it are operatively connected and configured. For ease of description, the scale of each element shown in the drawings differs from the actual scale, and therefore, the description is not limited to the scales shown in the drawings.

[0050] In the display device disclosed herein, the pixel circuit and the gating drive circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon (LTPS) TFTs including low-temperature polycrystalline silicon, etc.

[0051] The gating signal oscillates between a gating enable voltage and a gating disable voltage. The gating enable voltage is set to a voltage higher than the transistor's threshold voltage, and the gating disable voltage is set to a voltage lower than the transistor's threshold voltage.

[0052] A transistor turns on in response to a gating turn-on voltage and turns off in response to a gating turn-off voltage. In the case of an n-channel transistor, the gating turn-on voltage can be a high gating voltage, and the gating turn-off voltage can be a low gating voltage. In the case of a p-channel transistor, the gating turn-on voltage can be a low gating voltage, and the gating turn-off voltage can be a high gating voltage.

[0053] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0054] Referring to FIG1, a display device according to an embodiment of the present disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels 101 of the display panel 100. Additionally, the display device includes a power supply 150.

[0055] The display panel 100 may be, but is not limited to, a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be an irregularly shaped panel in which at least a portion is curved or elliptical.

[0056] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels 101. These power lines may be commonly connected to pixel circuitry to provide the voltage required to drive the pixels 101.

[0057] Each pixel 101 can be divided into red, green, and blue sub-pixels for color implementation. Each pixel 101 may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic light-emitting diode (LED). Each pixel circuitry is connected to a data line 102, a gate line 103, and a power line. In the following description, pixel 101 can be understood as a sub-pixel.

[0058] The display area AA comprises multiple pixel rows L1 to Ln. Each of the pixel rows L1 to Ln comprises a row of pixels 101 arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. Those pixels 101 arranged in a pixel row share a gate line 103. Subpixels arranged along the data line direction in the column direction (Y-axis direction) share the same data line 102. A horizontal time period is the time obtained by dividing a frame time period by the total number of pixel rows L1 to Ln.

[0059] The display panel 100 can be implemented using a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and real objects in the background are visible. The display panel 100 can be made of a flexible display panel.

[0060] Power supply 150 receives an input voltage applied from host system 300 and outputs the voltage required to drive pixels 101 of display panel 100 and display panel driving circuitry. For this purpose, power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, rectifier, buck converter, boost converter, etc. Power supply 150 can output a constant voltage (or DC voltage) such as a gating on voltage, gating off voltage, pixel drive voltage, cathode voltage, reference voltage, and IC drive voltage of display panel driving circuitry via the DC-DC converter. The gating on voltage and gating off voltage can be provided to level shifter 140 and gating driver 120. Voltages such as pixel drive voltage, cathode voltage, and reference voltage can be provided to pixel 101 via a power line commonly connected to pixel 101.

[0061] The power supply 150 may also include a gamma voltage generator. The gamma voltage generator receives a high-level reference voltage and a low-level reference voltage and outputs multiple gamma reference voltages divided at specific intervals on a preset gamma curve (e.g., a 2.2 gamma curve). The gamma reference voltages are provided to a data driver 110. In the data driver 110, the gamma reference voltages are further subdivided into grayscale voltages by a voltage divider circuit. The gamma voltage generator can be implemented using a programmable gamma circuit that can adjust the voltage of each gamma reference voltage according to digital data. A timing controller 130, a host system 300, or a separate external device can update the digital data stored in the registers of the programmable gamma circuit via a communication interface.

[0062] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image to the pixels 101 of the display panel 100. The display panel driving circuit includes a data driver 110 and a gating driver 120.

[0063] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. The touch sensor driver is not shown in Figure 1. The data driver 110 and the touch sensor driver may be integrated into a single source driver IC.

[0064] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 may receive a gamma reference voltage and generate a gamma compensation voltage for each grayscale using a voltage divider circuit. The gamma compensation voltage for each grayscale is provided to a digital-to-analog converter (hereinafter referred to as "DAC") disposed in each channel of the data driver 110.

[0065] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting a first mode and a second mode. The DAC converts the pixel data into a gamma-compensated voltage and outputs a data voltage for the pixel data.

[0066] The gating driver 120 may be formed on the display panel 100 together with the circuit elements and wiring of the display area AA. The gating driver 120 may be disposed in at least one of the non-display areas NA on the left and right sides outside the display area AA, or at least a portion thereof may be disposed within the display area AA.

[0067] Under the control of the timing controller 130, the gating driver 120 sequentially outputs the pulses of the gating signal to the gating line 103. The gating driver 120 can sequentially provide the gating signal to the gating line 103 by shifting the pulses of the gating signal using a shift register. When multiple gating signals are applied to each pixel 101, the gating driver 120 may include multiple shift registers. The gating signals may include scan signals and emission signals (or EM signals) input to the pixel circuit through multiple gating lines 103.

[0068] The timing controller 130 receives digital video data of the input image and timing signals synchronized with this data from the host system 300. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of one horizontal time period (1H).

[0069] The timing controller 130 can control the display panel driving circuit based on the timing signals Vsync, Hsync, and DE received from the host system 300. This is achieved by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gating timing control signal for controlling the operation timing of the gating driver 120. The timing controller 130 can synchronize the data driver 110 and the gating driver 120 by controlling the operation timing of the display panel driving circuit.

[0070] The gating timing control signal output from the timing controller 130 can be input to the shift register of the gating driver 120 via a level shifter 140. The level shifter 140 can convert the voltage of the gating timing control signal received from the timing controller 130 into a swing width between the gating on voltage and the gating off voltage, and provide it to the gating driver 120. In another example, the level shifter 140 can be formed or integrated into the gating driver 120.

[0071] The timing controller 130 can analyze the input image for each frame and generate a control signal for selectively outputting a gating signal based on the analysis results. The generated control signal can be provided to the shift register of the gating driver 120 via the level shifter 140.

[0072] The host system 300 may include a motherboard from one of a television system, set-top box, navigation system, personal computer (PC), vehicle system, mobile terminal, and wearable terminal. The host system 300 can scale the image signal from the video source according to the resolution of the display panel 100 and can send it along with a timing signal to the timing controller 130.

[0073] FIG2 is a diagram illustrating a pixel circuit according to an embodiment of the present disclosure, and FIG3 is a diagram illustrating the driving timing of the pixel circuit shown in FIG2.

[0074] Referring to Figures 2 and 3, the pixel circuit according to an embodiment of the present disclosure includes a light-emitting element EL, a driving element DT that provides current to the light-emitting element EL, a plurality of switching elements T1, T2, T3, T4, T5, T6, and T7 for switching the current path connected to the driving element DT, and a capacitor Cst for storing the gate-source voltage of the driving element DT. The driving element DT and the switching elements T2, T3, T4, T6, and T7 can be implemented as P-channel TFTs, and the switching elements T1 and T5 can be implemented as N-channel TFTs, but the present disclosure is not limited thereto.

[0075] The gating signals applied to this pixel circuit include a first scan signal SCAN1(n), a second scan signal SCAN2(n), a third scan signal SCAN3(n), a fourth scan signal SCAN4(n), and a light emission signal EM(n), but this disclosure is not limited thereto. Here, N is a natural number.

[0076] Capacitor Cst is connected between the first node n1 and the second node n2. The pixel driving voltage ELVDD is provided to the pixel circuit via ELVDD line 61. The first node n1 is connected to ELVDD line 61, the first electrode of the third switching element T3, and the first electrode of capacitor Cst. The second node n2 is connected to the second electrode of capacitor Cst, the gate electrode of driving element DT, the first electrode of the first switching element T1, and the first electrode of the fifth switching element T5.

[0077] The first switching element T1 is turned on according to the gate voltage VEH of the first scan signal SCAN1(n) to connect the gate electrode of the driving element DT to the second electrode. The first switching element T1 includes a gate electrode connected to the first scan line GL1, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The first scan signal SCAN1(n) is applied to the pixel via the first scan line GL1. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the first switching element T1, and the first electrode of the fourth switching element T4.

[0078] The second switching element T2 is turned on according to the strobe voltage VEL of the second scan signal SCAN2(n) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switching element T2 includes a gate electrode connected to the second scan line GL2, a first electrode connected to the fifth node n5, and a second electrode connected to the data line 60. The fifth node n5 is connected to the first electrode of the driving element DT, the first electrode of the second switching element T2, and the second electrode of the third switching element T3.

[0079] The third switching element T3 provides the pixel driving voltage ELVDD to the first electrode of the driving element DT in response to the emission signal EM(n). The third switching element T3 includes a gate electrode connected to the EM line GL5, a first electrode connected to the ELVDD line 61, and a second electrode connected to the fifth node n5. The emission signal EM(n) is fed to the pixel via the EM line GL5. Hereinafter, the EM line GL5 may also be referred to as the fifth scan line or the emission control line.

[0080] The fourth switching element T4 is turned on according to the gating voltage VEL of the light-emitting signal EM(n), so as to connect the second electrode of the driving element DT to the anode of the light-emitting element EL. The gate electrode of the fourth switching element T4 is connected to the EM line GL5. The first electrode of the fourth switching element T4 is connected to the third node n3, and the second electrode of the fourth switching element T4 is connected to the fourth node n4. The fourth node n4 is connected to the anode electrode of the light-emitting element EL, the second electrode of the fourth switching element T4, and the second electrode of the sixth switching element T6.

[0081] The fifth switching element T5 is turned on during the initialization phase (Tini) according to the gating voltage VEH of the fourth scan signal SCAN4(n), connecting the second node n2 to the Vini line 63, thereby initializing the gates of capacitor Cst and the driving element DT. The fifth switching element T5 includes a gate electrode connected to the fourth scan line GL4, a first electrode connected to the second node n2, and a second electrode connected to the Vini line 63. The fourth scan signal SCAN4(n) is fed to the pixel via the fourth scan line GL4. The initialization voltage Vini is provided to the pixel via the Vini line 63.

[0082] The sixth switching element T6 is turned on during the first OBS phase Tobs1 and the third OBS phase Tobs3 according to the gating voltage VEL of the third scan signal SCAN3(n), to connect the VAR line 64 to the anode electrode of the light-emitting element EL. During the first OBS phase Tobs1 and the third OBS phase Tobs3, the anode voltage of the light-emitting element EL is discharged to the reset voltage VAR through the sixth switching element T6. In this case, the light-emitting element EL does not emit light because the voltage between the anode and cathode is less than its threshold voltage. The sixth switching element T6 includes a gate electrode connected to the third scan line GL3, a first electrode connected to the VAR line 64, and a second electrode connected to the fourth node n4. In this disclosure, the expression "discharging the first voltage of a specific node to a second voltage" can refer to applying a second voltage to a specific node that previously carried a first voltage, or changing the first voltage of a specific node to a second voltage.

[0083] The seventh switching element T7 is turned on during the first OBS phase (Tobs1) and the third OBS phase (Tobs3) according to the gating voltage VEL of the third scan signal SCAN3(n), to apply a bias voltage Vobs by connecting the Vobs line 65 to the fifth node n5. During the first OBS phase (Tobs1) and the third OBS phase (Tobs3), the voltage on the first electrode of the drive element DT is discharged to the bias voltage Vobs via the seventh switching element T7. The seventh switching element T7 includes a gate electrode connected to the third scan line GL3, a first electrode connected to the fifth node n5, and a second electrode connected to the Vobs line 65.

[0084] The driving element DT drives the light-emitting element EL by adjusting the current flowing to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node n2, a first electrode connected to the fifth node n5, and a second electrode connected to the third node n3.

[0085] The light-emitting element EL is connected between the fourth node n4 and the ELVSS line 62. The light-emitting element EL can be implemented as an OLED, but this disclosure is not limited thereto. The OLED includes an organic compound layer formed between the anode and the cathode. The organic compound layer may include, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, an emissive layer EML, an electron transport layer ETL, and an electron injection layer EIL. When a voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emissive layer EML to form excitons, thereby causing visible light to be emitted from the emissive layer EML.

[0086] In the first OBS stage Tobs1, the seventh switching element T7 is turned on, discharging the voltage of the fifth node n5 to the bias voltage Vobs, and discharging the voltage of the fourth node n4 to the reset voltage VAR.

[0087] In the second OBS stage Tobs2, the fifth switching element T5 is turned on, discharging the voltage of the second node n2 to the initial voltage Vini.

[0088] During the initialization phase of Tini, the first switching element T1 and the fifth switching element T5 are turned on, discharging the voltages of the second node n2 and the third node n3 to the initialization voltage Vini.

[0089] During the data writing phase Tw, the second switching element T2 is turned on, causing the data voltage to be applied to the fifth node n5, and the voltage of the second node n2 becomes Vdata + Vth. The threshold voltage Vth of the driving element DT is sensed and charged to the capacitor Cst connected to the second node n2.

[0090] In the third OBS stage Tobs3, the seventh switching element T7 is turned on, discharging the voltage of the fifth node n5 to the bias voltage Vobs, and discharging the voltage of the fourth node n4 to the reset voltage VAR.

[0091] During the light-emitting stage Tem, the third switching element T3 and the fourth switching element T4 are turned on, so that current flows through the driving element DT to the light-emitting element EL, thereby causing the light-emitting element EL to emit light.

[0092] Although Figure 2 shows a pixel circuit including a light-emitting element EL, a driving element DT, first switching elements T1 to seventh switching elements T7, and a capacitor Cst, this disclosure is not limited thereto, and the pixel circuit of this disclosure may include more or fewer elements than shown. For example, structures such as 3T1C, 4T1C, 5T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T1C, 7T2C, and 8T2C are also feasible. Furthermore, it may include more or fewer transistors and capacitors.

[0093] Since frame skipping is achieved by not outputting the strobe signal, it can be achieved by not outputting the first and fourth scan signals out of the five signals (i.e., the first scan signal to the fourth scan signal and the light emission signal) to the pixel circuit of Figure 2. For example, during frame skipping, the first switching element T1 and the fifth switching element T5 can be turned off, so that the voltages of the second node n2 and the third node n3 are not initialized.

[0094] In embodiments of this disclosure, the gating driver includes multiple signal transmission units, each including two output circuits and a selection circuit. One output circuit outputs a carry signal, the selection circuit selectively transmits the carry signal, and the other output circuit outputs a gating signal based on the selectively transmitted carry signal.

[0095] Figure 4 is a diagram illustrating the shift register of the gating driver according to an embodiment of the present disclosure, and Figure 5 is a diagram illustrating the drive waveform of the gating driver shown in Figure 4.

[0096] Referring to Figures 4 and 5, the gating driver according to the embodiment includes multiple signal transmission units (STa(1), STb(1), STc(1)), (STa(2), STb(2), STc(2)), (STa(3), STb(3), STc(3)), (STa(4), STb(4), STc(4)), (STa(5), STb(5), STc(5)), ..., and these signal transmission units are cascaded together via carry lines that transmit carry signals.

[0097] In implementation, the pair of output circuits in each signal transmission unit can be implemented as the same circuit, but are not necessarily limited to this, and can also be implemented as different circuits.

[0098] Each of the first output circuits STa(1), STa(2), STa(3), STa(4), STa(5), ... in each signal transmission unit receives a start signal VST or a carry signal and a clock signal output from the previous signal transmission unit. The first output circuit STa(1) starts driving according to the start signal VST, and each of the other first output circuits STa(2), STa(3), STa(4), STa(5), ... starts driving by receiving carry signals COUT(1), COUT(2), COUT(3), COUT(4), COUT(5), ... from the previous signal transmission unit.

[0099] Each of the selection circuits STb(1), STb(2), STb(3), STb(4), STb(5), ... in each signal transmission section can transmit the carry signal output from the first output circuit STa(1), STa(2), STa(3), STa(4), STa(5), ... as is, or transmit a shutdown signal to replace the carry signal, depending on the selection signal.

[0100] Each of the other second output circuits STc(1), STc(2), STc(3), STc(4), STc(5), ... in each signal transmission section can shift the carry signals COUT(1)', COUT(2)', COUT(3)', COUT(4)', COUT(5)', ... output from the selection circuit according to the timing of the clock signal, and output the gating signals GOUT(1), GOUT(2), GOUT(3), GOUT(4), GOUT(5), ... in sequence.

[0101] In this case, as shown in Figure 5, even if the signal transmission unit at the start of the frame skip period blocks the transmission of the carry signal at the timing of the output strobe signal, and thus does not output the strobe signal, the carry signal still continues to be output. For example, when the outputs of the second output circuits STc(3) and STc(4) are blocked and the output of the second output circuit STc(5) is restored, even if the second output circuits STc(3) and STc(4) do not output the strobe signal, the carry signal is still continuously output from the first output circuits STa(3) and STa(4).

[0102] Therefore, based on the selection signal and the selection data voltage, the second output circuit STc(5) can receive the carry signal from the first output circuit STa(5), and thus can restore the output of the strobe signal.

[0103] Thus, in this embodiment, by applying only the high voltage level of the selection data voltage and the selection signal to the area desired by the user, the transmission of the carry signal can be blocked, thereby blocking the output of the gating signal to the area desired by the user; and by applying the low voltage level of the selection data voltage and the selection signal to the remaining areas, the carry signal can be transmitted, thereby restoring the output of the gating signal to the remaining areas. Therefore, different areas of the display device can be driven at different frequencies.

[0104] Figure 6 is a diagram illustrating the configuration of the output circuit according to an embodiment of the present disclosure shown in Figure 4.

[0105] Referring to FIG6, the output circuit according to an embodiment of the present disclosure may include an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor or pull-up transistor T16, a seventeenth transistor or pull-down transistor T17, an eleventh capacitor C1, a twelfth capacitor C2, and a thirteenth capacitor C3. The output circuit may include, but is not limited to, a first output circuit and a second output circuit that can be implemented with the same circuitry.

[0106] The eleventh transistor T11 is turned on according to the clock signal CLK(N) and connects the first node 81 to the second node 82. The eleventh transistor T11 includes a gate electrode connected to the fourth node 84 to which the clock signal CLK(N) is applied, a first electrode connected to the first node 81, and a second electrode connected to the second node 82.

[0107] The twelfth transistor T12 is turned on according to the start signal VST or the previous carry signal COUT(n-1), and connects the third node 83 to the first power line PL1, which is subjected to a high potential voltage VEH. The twelfth transistor T12 includes a gate electrode connected to the first node 81, a first electrode connected to the third node 83, and a second electrode connected to the first power line PL1.

[0108] The thirteenth transistor T13 is turned on by a voltage from the third node 83 and connects the fourth node 84 to the second control node Qb(n). The thirteenth transistor T13 includes a gate electrode connected to the third node 83, a first electrode connected to the fourth node 84, and a second electrode connected to the second control node Qb(n).

[0109] The fourteenth transistor T14 is turned on by a low potential voltage VEL and connects the second node 82 to the first control node Q(n). The fourteenth transistor T14 includes a gate electrode connected to a second power line PL2 to which a low potential voltage VEL is applied, a first electrode connected to the second node 82, and a second electrode connected to the first control node Q(n).

[0110] The fifteenth transistor T15 is turned on by a voltage from the second node 82 and connects the first power line PL1 to the second control node Qb(n). The fifteenth transistor T15 includes a gate electrode connected to the second node 82, a first electrode connected to the second control node Qb(n), and a second electrode connected to the first power line PL1.

[0111] The sixteenth transistor T16 is turned on by the voltage from the first control node Q(n) and outputs a low-potential voltage VEL as a gating signal GOUT to the output node OUT. The sixteenth transistor T16 includes a gate electrode connected to the first control node Q(n), a first electrode connected to the second power line PL2, and a second electrode connected to the output node OUT.

[0112] The seventeenth transistor T17 is turned on by the voltage from the second control node Qb(n) and outputs a high potential voltage VEH as a gating signal GOUT to the output node OUT. The seventeenth transistor T17 includes a gate electrode connected to the second control node Qb(n), a first electrode connected to the output node OUT, and a second electrode connected to the first power line PL1.

[0113] The eleventh capacitor C1 is connected between the third node 83 and the fourth node 84. The twelfth capacitor C2 is connected between the gate electrode and the second electrode of the sixteenth transistor T16. The thirteenth capacitor C3 is connected between the gate electrode and the second electrode of the seventeenth transistor T17.

[0114] Figure 7 is a diagram illustrating the configuration of the selection circuit shown in Figure 4, and Figures 8A to 8D are diagrams illustrating the operating principle of the selection circuit shown in Figure 7.

[0115] Referring to FIG7, the selection circuit according to an embodiment of the present disclosure may include a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor Cs.

[0116] The first transistor T1 is turned on by the selection signal RS(n) and provides the selection data voltage SDATA to the first node 71. The first transistor T1 includes a gate electrode to which the selection signal RS(n) is applied, a first electrode to which the selection data voltage SDATA is applied, and a second electrode connected to the first node 71.

[0117] The first transistor T1 can be implemented as a P-channel TFT, but is not limited to this. For example, if the first transistor T1 is implemented as a P-channel TFT, the selection signal RS(n) can be a signal generated from a timing controller or a signal generated from a separately configured circuit.

[0118] The second transistor T2 is turned on by the voltage at the first node 71, so that the carry signal COUT(n) from the first output circuit is output as the carry signal COUT(n)' to the output node OUT. The second transistor T2 includes a gate electrode connected to the first node 71, a first electrode connected to the carry line CL to which the carry signal COUT(n) is applied, and a second electrode connected to the output node OUT.

[0119] The third transistor T3 is turned on by the voltage at the first node 71, causing the low potential voltage VEL to be output as a carry signal COUT(n)' to the output node OUT. The third transistor T3 includes a gate electrode connected to the first node 71, a first electrode connected to the output node OUT, and a second electrode connected to the power line PL to which the low potential voltage VEL is applied.

[0120] In this case, the second transistor T2 can be implemented as a P-channel TFT, and the third transistor T3 can be implemented as an N-channel TFT, but is not limited thereto.

[0121] Capacitor Cs is connected between the first node 71 and ground. Capacitor Cs is capable of stably storing the selected data voltage applied to the first node 71.

[0122] Referring to Figure 8A, when the first transistor T1 is turned on by the selection signal RS(n), the selection data voltage SDATA can be stored in the first node 71. In this case, if the selection data voltage SDATA is a low level voltage, the second transistor T2 can be turned on and the third transistor T3 can be turned off, so that the carry signal COUT(n) from the first output circuit can be output as the carry signal COUT(n)' through the output node OUT.

[0123] Referring to Figure 8B, when the first transistor T1 is turned on by the selection signal RS(n), the selection data voltage SDATA can be stored in the first node 71. In this case, if the selection data voltage SDATA is a high-level voltage, the second transistor T2 can be turned off and the third transistor T3 can be turned on, so that the low-level voltage VEL can be output as a carry signal COUT(n)' through the output node OUT. Therefore, the carry signal COUT(n) from the first output circuit can be blocked, and the low-level voltage VEL can be output as a carry signal COUT(n)' from the selection circuit.

[0124] Thus, in the region where the frequency needs to be changed, by applying a high-voltage selection data voltage SDATA to the selection circuit in the signal transmission section connected to the pixel row in the region where the frequency needs to be changed, the carry signal COUT(n) from the first output circuit can be blocked.

[0125] Referring to Figure 8C, the high voltage level of the selection signal RS(n) and the selection data voltage SDATA is the same as the high potential voltage VEH, but the low voltage level can be formed differently. This is because, for example, in order to turn on the second transistor T2, which is a P-channel TFT, the low voltage level of the selection data voltage SDATA can be formed to be an amplitude that is -3V lower than the threshold voltage Vth of the carry signal COUT(n) (which can be as low as the low potential voltage VEL); and in order to turn on the first transistor T1, which is a P-channel TFT, the low voltage level of the selection signal RS(n) can be formed to be an amplitude that is -3V lower than the threshold voltage Vth of the low voltage level of the selection data voltage SDATA.

[0126] In other words, if the threshold voltage Vth of the P-channel TFT is -3V, the gating voltage can be lower than the low potential voltage VEL-|Vth|. However, since the low voltage level of the signal generated from the gating driver is the low potential voltage VEL, when the first transistor T1 is implemented as a P-channel TFT, the selection signal RS(n) can be generated from the timing controller instead of from the gating driver.

[0127] On the other hand, as shown in Figure 8D, when the first transistor T1 is implemented as an N-channel TFT, the gate enable voltage is a high-level voltage VEH, so the selection signal RS(n) can be generated from the gate driver or from the timing controller. In this case, the circuit for generating the selection signal RS in the gate driver can have the same configuration as the output circuit shown in Figure 10.

[0128] Therefore, as shown in Figure 8A, when the selected data voltage SDATA is at a low voltage level, the second transistor T2 is turned on, and when the selected data voltage SDATA is at a high voltage level, the second transistor T2 is turned off, because the selected data voltage SDATA is equal to the high potential voltage that serves as the turn-on voltage.

[0129] Figures 9A and 9B are diagrams illustrating a gating driver according to an embodiment of the present disclosure. Figure 9A shows the circuitry of the gating driver, and Figure 9B shows the panel layout of the gating driver.

[0130] Referring to Figures 9A and 9B, the gating driver according to an embodiment of the present disclosure may include a first output circuit STa, a selection circuit STb, and a second output circuit STc.

[0131] The first output circuit STa can output a high-voltage carry signal COUT(n) based on the start signal VST and clock signals CLK1 and CLK2. The first output circuit STa can apply the high-voltage carry signal COUT(n) to the selection circuit STb, and also to the first output circuit STa of the next signal transmission section.

[0132] For this purpose, the output node OUT1 of the first output circuit STa can be connected to the carry line CL of the selection circuit STb.

[0133] The selection circuit STb can transmit or block the carry signal COUT(n) from the first output circuit STa based on the selection signal RS and the selection data voltage SDATA. When the selection signal RS and the low-voltage selection data voltage SDATA are applied, the selection circuit STb can transmit the high-voltage carry signal COUT(n) from the first output circuit as the carry signal COUT(n)' to the second output circuit STc.

[0134] On the other hand, when the selection signal RS and the high-voltage selection data voltage SDATA are applied, the selection circuit STb can transmit the low-voltage carry signal COUT(n)' to the second output circuit STc instead of outputting the high-voltage carry signal COUT(n) from the first output circuit.

[0135] For this purpose, the output node OUT2 of the selection circuit STb can be connected to the first node 81 of the second output circuit STc.

[0136] The second output circuit STc can output a strobe signal GOUT(n) based on clock signals CLK1 and CLK2 and a high-voltage carry signal COUT(n)'. When the second output circuit STc receives the carry signal COUT(n)' from the selection circuit STb, it outputs the strobe signal GOUT(n), and when it does not receive the carry signal, it does not output the strobe signal.

[0137] As shown in Figure 9B, the first output circuit STa, the selection circuit STb, and the second output circuit STc can be arranged sequentially in the gating driver. The lines used to transmit clock signals CLK1 and CLK2 can be arranged in the first output circuit STa and the second output circuit STc, and the lines used to transmit the selection data voltage SDATA and the low potential voltage VEL can be arranged in the selection circuit STb.

[0138] Figure 10 is a diagram illustrating the configuration of the output circuit according to another embodiment of the present disclosure, as shown in Figure 4.

[0139] Referring to FIG10, the output circuit according to another embodiment of the present disclosure may include a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26, a twenty-seventh transistor or pull-up transistor T27, a twenty-eighth transistor or pull-down transistor T28, a twenty-first capacitor C21, and a twenty-second capacitor C22. The output circuit may include, but is not limited to, a first output circuit and a second output circuit that can be implemented with the same circuitry.

[0140] The 21st transistor T21 is turned on according to the previous clock signal CLK(N-1) and connects the first node 81 to the second node 82. The 21st transistor T21 includes a gate electrode to which the previous clock signal CLK(N-1) is applied, a first electrode connected to the first node 81, and a second electrode connected to the second node 82.

[0141] The 22nd transistor T22 is turned on by the voltage of the second control node Qb(n) and connects the second node 82 to the first power line PL1, which is subjected to a high potential voltage VEH. The 22nd transistor T22 includes a gate electrode connected to the second control node Qb(n), a first electrode connected to the second node 82, and a second electrode connected to the first power line PL1.

[0142] The 23rd transistor T23 is turned on by the next clock signal CLK(N+2) and connects the second control node Qb(n) to the second power line PL2, which is applied with a low potential voltage VEL. The 23rd transistor T23 includes a gate electrode to which the next clock signal CLK(N+2) is applied, a first electrode connected to the second power line PL2, and a second electrode connected to the second control node Qb(n).

[0143] The 24th transistor T24 is turned on by the voltage of the first node 81 and connects the first power line PL1 to the second control node Qb(n). The 24th transistor T24 includes a gate electrode connected to the first node 81, a first electrode connected to the second control node Qb(n), and a second electrode connected to the first power line PL1.

[0144] The 25th transistor T25 is turned on by a low potential voltage VEL and connects the second node 82 to the first control node Q(n). The 25th transistor T25 includes a gate electrode connected to the second power line PL2, a first electrode connected to the second node 82, and a second electrode connected to the first control node Q(n).

[0145] The 26th transistor T26 is turned on by the voltage of the second node 82 and connects the second control node Qb(n) to the first power line PL1. The 26th transistor T26 includes a gate electrode connected to the second node 82, a first electrode connected to the second control node Qb(n), and a second electrode connected to the first power line PL1.

[0146] The 27th transistor T27 is turned on by the voltage of the first control node Q(n) and outputs a low potential voltage VEL to the output node OUT. The 27th transistor T27 includes a gate electrode connected to the first control node Q(n), a first electrode connected to the clock line CKL to which the clock signal CLK(N) is applied, and a second electrode connected to the output node OUT.

[0147] The 28th transistor T28 is turned on by the voltage of the second control node Qb(n) and outputs a high potential voltage VEH to the output node OUT. The 28th transistor T28 includes a gate electrode connected to the second control node Qb(n), a first electrode connected to the output node OUT, and a second electrode connected to the first power line PL1.

[0148] The twenty-first capacitor C21 is connected between the gate electrode and the second electrode of the twenty-seventh transistor T27. The twenty-second capacitor C22 is connected between the gate electrode and the second electrode of the twenty-eighth transistor T28.

[0149] Figure 11 is a diagram illustrating a gating driver according to another embodiment of the present disclosure.

[0150] Referring to FIG11, a gating driver according to another embodiment of the present disclosure may include a first output circuit (STa), a selection circuit (STb), and a second output circuit (STc).

[0151] The first output circuit STa can output high-voltage clock signals CLK1 to CLK4 as high-voltage carry signals COUT(n) based on the start signal VST and clock signals CLK1 to CLK4. The first output circuit STa can apply the high-voltage carry signal COUT(n) to the selection circuit STb, and also to the first output circuit STa of the next signal transmission section.

[0152] For this purpose, the output node OUT1 of the first output circuit STa can be connected to the carry line CL of the selection circuit STb.

[0153] The selection circuit STb can transmit or block the carry signal COUT(n) from the first output circuit STa based on the selection signal RS and the selection data voltage SDATA. When the selection signal RS and the low-voltage selection data voltage SDATA are applied, the selection circuit STb can transmit the high-voltage carry signal COUT(n) from the first output circuit STa as the carry signal COUT(n)' to the second output circuit STc.

[0154] On the other hand, when the selection signal RS and the high-level selection data voltage SDATA are applied, the selection circuit STb may not output the high-level carry signal COUT(n) from the first output circuit STa, but instead transmit the low-level carry signal COUT(n)' to the second output circuit STc.

[0155] For this purpose, the output node OUT2 of the selection circuit STb can be connected to the first node 81c of the second output circuit STc.

[0156] The second output circuit STc can output high-voltage clock signals CLK1 to CLK4 as high-voltage strobe signals GOUT(n) based on clock signals CLK1 to CLK4 and a high-voltage carry signal COUT(n)'. When the second output circuit STc receives the carry signal COUT(n)' from the selection circuit STb, it outputs the strobe signal GOUT(n); when it does not receive the carry signal COUT(n)', it does not output the strobe signal GOUT(n).

[0157] It should be noted that although Figures 6 to 11 show different implementations of the structure of the output circuit, selection circuit, or gating driver, the structure of the output circuit, selection circuit, or gating driver is not limited to the specific structure mentioned above, and various other structures are also feasible as long as the gating signal can be selectively output from the gating driver based on the pixel row.

[0158] Figure 12 is a diagram illustrating the output result of the carry signal according to an embodiment of the present disclosure.

[0159] Referring to Figure 12, each of the eight signal transmission sections, the first output circuit STa, can output carry signals COUT(1), COUT(2), COUT(3), COUT(4), COUT(5), COUT(6), COUT(7), and COUT(8), respectively.

[0160] The selection circuit STb in the eight signal transmission sections can selectively transmit carry signals COUT(1), COUT(2), COUT(3), COUT(7), and COUT(8), which are partial carry signals output from the first output circuit STa, based on the selection signal RS and the selection data voltage SDATA. In other words, the selection circuit STb can receive the selection data voltage SDATA through the selection signal RS and selectively transmit the carry signal based on the voltage level of the received selection data voltage.

[0161] For example, when the select data voltage SDATA is at a low voltage level, the select circuit STb can output a carry signal, while when the select data voltage SDATA is at a high voltage level, it can not output a carry signal. Here, outputting a carry signal means outputting a carry signal at the strobe-on voltage, while not outputting a carry signal means outputting a carry signal at the strobe-off voltage.

[0162] Figure 13 is a diagram illustrating the output result of the gating signal according to an embodiment of the present disclosure.

[0163] Referring to Figure 13, during normal operation, each of the eight signal transmission units can output corresponding output strobe signals GOUT(1), GOUT(2), GOUT(3), GOUT(4), GOUT(5), GOUT(6), GOUT(7) and GOUT(8) according to the timing of the clock signal CLK.

[0164] During the frame skipping operation, among the eight signal transmission units that output their corresponding strobe signals according to the timing of the clock signal CLK, only the signal transmission unit that selectively receives the carry signal can output their corresponding strobe signals GOUT(1), GOUT(2), GOUT(3), GOUT(7), and GOUT(8).

[0165] In this way, in the implementation, the gating signal can be selectively output based on the pixel row.

[0166] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

[0167] Cross-reference to related applications

[0168] This application claims priority and benefit to Korean Patent Application No. 10-2024-0151664, filed in Korea on October 31, 2024, the entire disclosure of which is incorporated herein by reference for all purposes as if fully set forth herein.

Claims

1. A gating driver, the gating driver comprising: A plurality of signal transmission units are cascaded together via carry lines, the carry lines being configured to apply a corresponding carry signal as input to the plurality of signal transmission units. Each of the plurality of signal transmission units includes: a first output circuit configured to receive a first carry signal from a preceding signal transmission unit and output a second carry signal based on the first carry signal and a clock signal; a selection circuit configured to receive the second carry signal from the first output circuit and selectively output the second carry signal based on a voltage level of a selection data voltage; and a second output circuit configured to output a strobe signal based on the second carry signal selectively transmitted from the selection circuit and another clock signal.

2. The gating driver according to claim 1, wherein, The selection circuit is configured to output the second carry signal based on the voltage level of the selection data voltage applied as a strobe-on voltage level, and not output the second carry signal based on the voltage level of the selection data voltage applied as a strobe-off voltage level.

3. The gating driver according to claim 1, wherein, The selection circuit includes: a first transistor, the first transistor including a gate electrode to which a selection signal is applied, a first electrode to which the selection data voltage is applied, and a second electrode connected to a first node; a second transistor, the second transistor including a gate electrode connected to the first node, a first electrode to which a second carry signal is applied, and a second electrode connected to an output node; and a third transistor, the third transistor including a gate electrode connected to the first node, a first electrode connected to the output node, and a second electrode to which a low potential voltage is applied.

4. The gating driver according to claim 3, wherein, The second transistor and the third transistor are different transistors among P-channel transistors and N-channel transistors.

5. The gating driver according to claim 3, wherein the gating driver further comprises a capacitor connected between the first node and ground.

6. The strobe driver according to claim 5, wherein, The selection circuit is configured such that, based on the first transistor being turned on by the selection signal, the selection data voltage is stored in the capacitor, and based on the second transistor being turned on by the selection data voltage stored in the capacitor, the second carry signal is output through the output node.

7. The gating driver according to claim 6, wherein, The selection circuit is configured such that, based on the third transistor being turned on by the selection data voltage stored in the capacitor, the low potential voltage, instead of the second carry signal, is output through the output node.

8. The strobe driver according to claim 1, wherein, The first output circuit and the second output circuit each include a pull-up transistor and a pull-down transistor, wherein the pull-up transistor includes a gate electrode connected to the first control node, a first electrode connected to a low potential voltage, and a second electrode connected to the output node, and wherein the pull-down transistor includes a gate electrode connected to the second control node, a first electrode connected to the output node, and a second electrode connected to a high potential voltage.

9. The gating driver according to claim 1, wherein, The first output circuit and the second output circuit each include a pull-up transistor and a pull-down transistor. The pull-up transistor includes a gate electrode connected to the first control node, a first electrode to which the clock signal or the other clock signal is applied, and a second electrode connected to the output node. The pull-down transistor includes a gate electrode connected to the second control node, a first electrode connected to the output node, and a second electrode to which a high potential voltage is applied.

10. The strobe driver according to claim 1, wherein, The first output circuit and the second output circuit are implemented as the same circuit.

11. A display device, the display device comprising: A pixel array, wherein multiple data lines, multiple gate lines and multiple pixel circuits are arranged in the pixel array; A data driver configured to output a data voltage to the plurality of data lines; And the gating driver according to any one of claims 1 to 10.

12. The display device according to claim 11, further comprising a timing controller configured to control the operation timing of the data driver and the strobe driver, wherein, The selection signal is generated by the timing controller or by the strobe driver.

13. The display device according to claim 11, wherein, The pixel array comprises multiple pixel rows, and the gating signal is selectively output based on the pixel rows.

14. The display device according to claim 11, wherein, At least one of the plurality of pixel circuits includes: a driving element configured to provide current to a light-emitting element, and including a gate electrode connected to a second node, a first electrode connected to a fifth node, and a second electrode connected to a third node; a first switching element including a gate electrode connected to a first scan line, a first electrode connected to the second node, and a second electrode connected to the third node; a second switching element including a gate electrode connected to a second scan line, a first electrode connected to the fifth node, and a second electrode connected to one of the plurality of data lines; and a third switching element including a gate electrode connected to a light-emitting control line, a first electrode connected to a first node to which a pixel driving voltage is applied, and a second electrode connected to the fifth node. Two electrodes; a fourth switching element, the fourth switching element including a gate electrode connected to the light emission control line, a first electrode connected to the third node, and a second electrode connected to the fourth node; a fifth switching element, the fifth switching element including a gate electrode connected to the fourth scan line, a first electrode connected to the second node, and a second electrode connected to the initialization voltage; a sixth switching element, the sixth switching element including a gate electrode connected to the third scan line, a first electrode connected to the reset voltage, and a second electrode connected to the fourth node; a seventh switching element, the seventh switching element including a gate electrode connected to the third scan line, a first electrode connected to the fifth node, and a second electrode connected to the bias voltage; and a capacitor connected between the first node and the second node.

15. The display device according to claim 14, wherein, The strobe signal is sent through the third scan line or the fourth scan line.

16. A display device, the display device comprising: A pixel array, comprising multiple data lines, multiple gate lines, and multiple pixel circuits, wherein at least one of the multiple pixel circuits includes: a driving element configured to provide current to a light-emitting element, and including a gate electrode connected to a second node, a first electrode connected to a fifth node, and a second electrode connected to a third node; a first switching element including a gate electrode connected to a first scan line, a first electrode connected to the second node, and a second electrode connected to the third node; a second switching element including a gate electrode connected to a second scan line, a first electrode connected to the fifth node, and a second electrode connected to one of the multiple data lines; and a third switching element including a gate electrode connected to a light-emitting control line, a first electrode connected to a first node to which a pixel driving voltage is applied, and a second electrode connected to the fifth node. A second electrode; a fourth switching element, the fourth switching element including a gate electrode connected to the light emission control line, a first electrode connected to the third node, and a second electrode connected to the fourth node; a fifth switching element, the fifth switching element including a gate electrode connected to the fourth scan line, a first electrode connected to the second node, and a second electrode connected to an initialization voltage; a sixth switching element, the sixth switching element including a gate electrode connected to the third scan line, a first electrode connected to a reset voltage, and a second electrode connected to the fourth node; a seventh switching element, the seventh switching element including a gate electrode connected to the third scan line, a first electrode connected to the fifth node, and a second electrode connected to a bias voltage; and a capacitor connected between the first node and the second node, wherein a gating signal is selectively applied to the third scan line or the fourth scan line based on pixel rows.

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