Display device and control method of display device

Abstract

This display device is provided with: a display unit; a scan driver that drives the display unit; and a control unit that controls the scan driver, a plurality of clock signals having mutually different phases are input to the scan driver, and the control unit controls the scan driver when a first video and a second video having a lower frequency than the first video are displayed adjacent to each other. The refresh rate switching position is set according to the data of the first video, the data of the second video and the phases of the plurality of clock signals.

Description

Display device, control method of display device Technical Field

[0001] This disclosure relates to display devices, etc. Background Technology

[0002] Patent document 1 discloses a scan driver used in a display device for partial display. Existing technical documents Patent documents

[0003] Patent Document 1: Japanese Patent Publication No. 2011-209714 Summary of the Invention The problem the invention aims to solve

[0004] When displaying at different refresh rates, there is a problem that controlling the scan driver becomes complicated. Solution for solving the problem

[0005] One aspect of this disclosure relates to a driving circuit comprising: a display unit including multiple rows; a scan driver driving the display unit; and a control unit controlling the scan driver, wherein multiple clock signals with different phases are input to the scan driver, and the control unit sets the refresh rate switching position based on data of the first image, data of the second image, and the phases of the multiple clock signals when displaying a first image and a second image with a frequency lower than that of the first image adjacent to each other. Invention Effects

[0006] Controlling the scan driver becomes easy when displaying at different refresh rates. Attached Figure Description

[0007] Figure 1 is a block diagram showing an example of the configuration of the display device according to this embodiment. Figure 2 is a block diagram showing an example of the configuration of the display device according to this embodiment. Figure 3 is a block diagram showing an example of the configuration of the scan driver of this display device. Figure 4 is a timing diagram showing the control method of the scan driver of this display device. Figure 5 is a block diagram showing the driving method of this display device. Figure 6 is a block diagram showing the driving method of this display device. Figure 7 is a timing diagram showing the control method of the scan driver of this display device. Figure 8 is a timing diagram showing the control method of the scan driver of this display device. Figure 9 is a timing diagram showing the control method of the scan driver according to this embodiment and the comparison method. Figure 10 is a flowchart showing the operation of the control unit. Figure 11 is a timing diagram showing the control method of the scan driver of this display device. Figure 12 is a timing diagram showing the control method of the scan driver of this display device. Explanation of reference numerals in the attached figures9 Scan driver 10 Shift register 15 Control unit 16 Level shift IC 17 Timing controller 20 Display unit PF, PS Switching position Gj Scan line SP Sub-pixel HR High refresh rate area LR Low refresh rate area Detailed Implementation

[0008] Figures 1 and 2 are block diagrams showing an example of the configuration of the display device according to this embodiment. Figure 3 is a block diagram showing an example of the configuration of the scan driver of this display device. Figure 4 is a timing diagram showing the control method of the scan driver of this display device. Figures 5 and 6 are block diagrams showing the driving method of this display device. As shown in Figures 1 to 6, this display device 20 includes: a display unit 30, which includes a plurality of rows; a scan driver 9, which drives the display unit 30; and a control unit 15, which controls the scan driver 9. A plurality of clock signals K1 to K6 with different phases are input to the scan driver 9. When a first image and a second image with a frequency lower than that of the first image are displayed adjacent to each other, the control unit 15 sets the refresh rate (rewrite frequency) switching position PF according to the data DT of the first image and the second image and the phases of the plurality of clock signals K1 to K6.

[0009] Here, the pixel row of the display unit 30 is simply referred to as a "row". Switching position PF can mean switching rows. The display unit 30 contains multiple scan lines (Gj-1, Gj, Gj+1, etc.) arranged in the first direction (vertical direction), and each row of the display unit 30 contains scan lines. The first image and the second image are displayed adjacent to each other in the first direction (the column direction orthogonal to the row), and the second image is updated less frequently than the first image.

[0010] In this way, by setting the switching position PF based on the phases of multiple clock signals K1 to K6 in addition to the data DT of the first and second images, the control of the scan driver 9 becomes easy.

[0011] The control unit 15 includes an input unit 14 that receives data DT (hereinafter referred to as data DT) of the first image and the second image, a level shift IC (level shift circuit) 16, a timing controller 17, and a memory 18. The timing controller 17 generates a control signal containing reference signals E1 and E2 based on the data DT and outputs it to the level shift IC 16.

[0012] The level shifter IC16 generates multiple clock signals K1 to K6 and pulse signals Q1 and Q2 based on control signals (including reference signals E1 and E2) from the timing controller 17. The shift register 10 uses the clock signals K1 to K6 and pulse signals Q1 and Q2 from the level shifter IC16 to output the scan signal Vj to the scan line Gj of the display unit 30.

[0013] This display device 20 includes a data driver 8 that drives the display unit 30, and a control unit 15 that controls the data driver 8 and the scan driver 9. In each row (pixel row) of the display unit 30, multiple sub-pixels SP are arranged in the row direction (horizontal direction), and the sub-pixels SP are connected to the data line DL and the scan line Gj via transistors (not shown). The scan driver 9 may also be disposed on both sides of the display unit 30. The display unit 30 and the scan driver 9 may also be included in the liquid crystal panel 13.

[0014] As shown in Figure 3, the scan driver 9 has: a multi-stage shift register 10, which is input with multiple clock signals K1 to K6 with different phases; and a clock signal line group 11. The clock signal line group 11 includes a first clock signal line C1 to an m-th clock signal line C6 (m=6) that transmits multiple clock signals K1 to K6 respectively.

[0015] The first clock signal K1 to the m-th clock signal K6 (m=6) have the same period, and the phases of the first clock signal K1 and the m-th clock signal K6 are offset by 1 / m period (=1 / 6 period). 1 / m period (=1 / 6 period) can be equal to one horizontal scan period.

[0016] The unit circuit Zn of the nth stage of shift register 10 includes: a register circuit Hn, which includes a set terminal Sn, a reset terminal Rn, an input terminal IK for pulse signal Q1, and a control terminal Un; and an output circuit On, which includes clock terminals I1 and I2, a set terminal Sn, a reset terminal Rn, and output terminals Xn and Yn.

[0017] In the output circuit On of unit circuit Zn, the first clock signal K1 is input to clock terminal I1, and the second clock signal K2 is input to clock terminal I2. The pulse of the first clock signal K1 is output to scan line Gj (j=2n-1) via output terminal Xn, and the pulse of the second clock signal K2 is output to scan line Gj+1 via output terminal Yn. In the output circuit of unit circuit Zn-1, the fifth clock signal K5 is input to clock terminal I1, and the sixth clock signal K6 is input to clock terminal I2. The pulse of the sixth clock signal K6 is output to scan line Gj-1 via output terminal Yn-1. In the output circuit of unit circuit Zn+1, the third clock signal K3 is input to clock terminal I1, and the fourth clock signal K4 is input to clock terminal I2. The pulse of the third clock signal K3 is output to scan line Gj+2 via output terminal Xn+1.

[0018] As shown in Figures 4 to 6, the switching position PF is set to the row (including the scan line Gj) of the pulse of the first clock signal K1 (the clock of the first clock signal line C1). That is, the control unit 15 sets a portion of the second image (low-frequency image) to the same refresh rate as the first image (high-frequency image) (increasing the refresh rate) so that the switching position PF becomes the row (including the scan line Gj) of the pulse of the first clock signal K1. Specifically, as shown below.

[0019] When A is a natural number, T is an integer greater than or equal to 0, the end of the first image is row A, and the beginning of the second image (low-frequency image) is row (A+1), the control unit 15 sets rows A to (A+T) in the display unit 30 to the first refresh rate, and sets row (A+T+1), which serves as the switching position PF, to the second refresh rate, which is lower than the first refresh rate. Here, the number of phases of the clock signal is m, 0≤T≤m-1, the first refresh rate is, for example, 60 to 240 [Hz], and the second refresh rate is, for example, 1 to 48 [Hz].

[0020] In Figures 4 and 5, since m=6 and A=243, the switching position PF is set to the row containing the pulse of the first clock signal K1 (=243+3+1) by setting the adjustment row number T=3. That is, by increasing the refresh rate of these 3 rows containing scan lines G244 to G246, which are part of the low-frequency image (second image), to the same refresh rate as the high-frequency image (first image), the refresh rate switching position PF is set to the 247th row (containing scan line G247) containing the pulse of the first clock signal K1.

[0021] If B is a natural number greater than A, F is an integer greater than or equal to 0, and the end of the second image is line B, the control unit 15 sets lines (A+T+1) to (BF) in the display unit 30 to the second refresh rate. Here, the number of phases of the clock signal is set to m, and 0≤F≤m-1.

[0022] In Figures 4 and 5, since m=6, A=243 and B=480, T=3 and F=0 are set, and rows 247 (including scan line G247) to 480 (including scan line G480) in the display section 30 are set to the second refresh rate.

[0023] In Figures 4 and 5, in the display unit 30, rows 1 to 246 (including G246) are designated as the high refresh rate region HR, and rows 247 (including G247) to 480 (including G480) are designated as the low refresh rate region LR. In this case, the ending rows of the high refresh rate region HR (including scan line G246) and the ending rows of the low refresh rate region LR (including scan line G480) are respectively designated as rows where the pulse of the sixth clock signal K6 is output (corresponding to rows that are multiples of 6 of the phase number m of the clock signal).

[0024] As shown in Figures 1 to 6, when the control unit 15 displays a third image with a higher frequency than the second image adjacent to the second image, and the starting point of the third image is row (B+1), the control unit 15 sets row (B+1-F) in the display unit 30 to a third refresh rate different from the second refresh rate.

[0025] In Figures 4 and 6, since m=6 and B=480, the adjustment row number F=0 is set, and row 481 (including scan line G481) in the display unit 30 is set to the third refresh rate. That is, by setting F=0, the refresh rate switching position PS is set to the row containing the scan line G481 (=480+1-0) that is output with the pulse of the first clock signal K1. The third refresh rate is, for example, 60 to 240 [Hz].

[0026] In Figures 4 to 6, in the display unit 30, rows 0 to 246 (including scan line G246) are the high refresh rate region HR, rows 247 (including scan line G247) to 480 (including scan line G480) are the low refresh rate region LR, and rows 481 (including scan line G481) and thereafter are the high refresh rate region HR. In this case, the starting row of the low refresh rate region LR (row 247, which is the switching position PF) and the starting row of the high refresh rate region HR (row 481, which is the switching position PS) are respectively rows containing the scan lines of the output first clock signal K1 (equivalent to rows of numbers obtained by adding 1 to a multiple of 6, which is the phase number m of the clock signal).

[0027] In the display device 20, during the period when the second image is not updated, the pulse patterns of the first to m-th clock signals are blank (a flat state without pulses) in the (A+T+1) to (BF) rows of the display unit 30. That is, in the pulse patterns of the 6-phase clock signals K1 to K6 shown in FIG4, the portions corresponding to rows 247 (including scan line G247) to 480 (including scan line G480) are blank.

[0028] Figure 7 is a timing diagram illustrating the control method of the scan driver of this display device. Figure 4 shows the pulse pattern (the area corresponding to lines 247 to 480 is a blank space without pulses) for the period (frame) when the second image (low-frequency image) is not updated. However, during the period (frame) when the second image is updated, as shown in Figure 7, pulses are also formed for the areas corresponding to lines 247 to 480. For example, if the first image is 120 Hz and the second image is 24 Hz, then during the period when the first image is updated 5 times, the second image is updated once.

[0029] Figure 8 is a timing diagram illustrating the control method of the scan driver of this display device. In Figure 8, since m=6 (number of phases of the clock signal) and B (end row of the second image)=482, the number of adjustment rows F=2, and row 481 in the display unit 30, which is row (B+1-F), is set to the third refresh rate. Here, by setting F=2, the refresh rate switching position PS is set to the row containing the scan line G481 (=480+1-0) that is output with the pulse of the first clock signal K1. That is, by raising these two rows containing scan lines G481 to G482, which are part of the low-frequency image (second image), to the same refresh rate as the high-frequency image (first image), the refresh rate switching position PS is set to row 481 (containing scan line G481) that is output with the pulse of the first clock signal K1. The third refresh rate is, for example, 60 to 240 [Hz]. The first refresh rate and the third refresh rate can also be the same.

[0030] Figure 9 is a timing diagram illustrating the control method of the scan driver according to this embodiment and comparison method. As shown in Figure 9, the level shifting IC 16 of the display device 20 uses multiple reference signals E1 and E2 from the timing controller 17 to generate clock signals K1 to K6 with a number of phases greater than the number of phases of the multiple reference signals E1 and E2.

[0031] The frequencies of reference signals E1 and E2 are more than twice (e.g., six times) the frequencies of clock signals K1 to K6. Corresponding to the sequential increase of reference signal E1, clock signals K1 to K6 increase sequentially. Corresponding to the sequential decrease of reference signal E2, which has the opposite phase to reference signal E1, clock signals K1 to K6 decrease sequentially, thereby forming a pulse pattern of clock signals K1 to K6.

[0032] In one implementation, since the pulse is stopped at clock signal K6, pulse formation restarts from clock signal K1, and the start-end data D481 of the third image is correctly written to line 481 (including scan line G481). On the other hand, in the comparison mode, since the pulse is stopped at clock signal K3, pulse formation restarts from clock signal K4, and the start-end data D481 of the third image is written to line 478. This results in a display deviation of 3 lines. To eliminate this display deviation, the output timing of the start-end data needs to be adjusted according to the pulse's stopping position, or the control of the scan driver becomes more difficult.

[0033] Figure 10 is a flowchart showing the operation of the control unit. As shown in Figure 10, the control unit 15 receives data from the first image and the second image (step S50), determines the refresh rate region (step S60), sets the refresh rate switching position (step S70), generates a reference signal (step S80), and generates multiple clock signals (step S90).

[0034] The control unit 15 can receive position information (start position and end position) of the first image and the second image from the outside. For example, the position information of the first image and the second image can be included in the data DT input from the outside, and the refresh rate area can be determined based on the position information (step S60).

[0035] The control unit 15 can also determine the position information (start position and end position) of the first image and the second image from the time change of the input data DT. For example, the time change can also be determined by the data checksum of each unit area (e.g., line) across multiple frames, and the refresh rate area can be determined based on the determination result (step S60).

[0036] Figure 11 is a timing diagram illustrating the control method of the scan driver of this display device. In Figure 11, the number of phases of the clock signal is set to 8, and multiple clock signals K1 to K8 are used.

[0037] When A is a natural number, T is an integer greater than or equal to 0, the end of the first image is row A, and the beginning of the second image (low-frequency image) is row (A+1), the control unit 15 sets rows A to (A+T) in the display unit 30 to the first refresh rate, and sets row (A+T+1), which serves as the switching position PF, to the second refresh rate, which is lower than the first refresh rate. Here, the number of phases of the clock signal is set to m, 0≤T≤m-1, the first refresh rate is, for example, 60 to 240 [Hz], and the second refresh rate is, for example, 1 to 48 [Hz].

[0038] In Figure 11, since m=8 and A=236, the switching position PF is set to the row containing the pulse of the first clock signal K1 (=236+4+1) by setting T=4. That is, by increasing the refresh rate of these four rows containing scan lines G237 to G240, which are part of the low-frequency image (second image), to the same refresh rate as the high-frequency image (first image), the refresh rate switching position PF is set to the 241st row (containing scan line G241) containing the pulse of the first clock signal K1.

[0039] If B is a natural number greater than A, F is an integer greater than or equal to 0, and the end of the second image is line B, the control unit 15 sets lines (A+T+1) to (BF) in the display unit 30 to the second refresh rate. Here, the number of phases of the clock signal is set to m, and 0≤F≤m-1.

[0040] In Figure 11, since m=8, A=236 and B=408, the number of rows to be adjusted is set to T=4 and F=0, and rows 241 (including scan line G241) to 408 (including scan line G408) in the display section 30 are set to the second refresh rate.

[0041] In Figure 11, in the display unit 30, rows 0 to 240 (including G240) are high refresh rate areas, and rows 241 (including G241) to 408 (including G408) are low refresh rate areas. In this case, the end rows of the high refresh rate areas (including scan line G240) and the end rows of the low refresh rate areas (including scan line G408) are respectively the rows where the pulse of the 8th clock signal K8 is output (equivalent to rows that are multiples of 8 of the phase number m of the clock signal).

[0042] As shown in Figures 1 and 11, when the control unit 15 displays a third image with a higher frequency than the second image adjacent to the second image, and the starting point of the third image is row (B+1), the control unit 15 sets row (B+1-F) in the display unit 30 to a third refresh rate different from the second refresh rate.

[0043] In Figure 11, since m=8 and B=408, the adjustment row number F=0 is set, and row 409 (including scan line G409) in the display unit 30 is set to the third refresh rate. That is, by setting F=0, the refresh rate switching position PS is set to the row containing the scan line G409 (=408+1-0) that is output with the pulse of the first clock signal K1. The third refresh rate is, for example, 60 to 240 [Hz].

[0044] In Figure 11, in the display unit 30, rows 0 to 240 (including scan line G240) are high refresh rate regions, rows 241 (including scan line G241) to 408 (including scan line G408) are low refresh rate regions, and rows 409 (including scan line G409) and thereafter are high refresh rate regions. In this case, the starting row of the low refresh rate region (row 241, which is the switching position PF) and the starting row of the high refresh rate region (row 409, which is the switching position PS) are respectively rows containing the scan lines of the output first clock signal K1 (equivalent to rows of numbers obtained by adding 1 to a multiple of 8, which is the number of phases m of the clock signal).

[0045] Figure 12 is a timing diagram illustrating the control method of the scan driver of this display device. In Figure 12, since m=8 and B (the end of the second image)=411, the adjustment row number F=3 is set, and row 409, which is (B+1-F) rows in the display unit 30, is set to the third refresh rate. Here, by setting F=3, the refresh rate switching position PS is set to the row containing the scan line G409 (=411+1-3) that is output with the pulse of the first clock signal K1. That is, by raising these 3 rows containing scan lines G409 to G411, which are part of the low-frequency image (the second image), to the same refresh rate as the high-frequency image (the first image), the refresh rate switching position PS is set to row 409 (containing scan line G409) that is output with the pulse of the first clock signal K1. The third refresh rate is, for example, 60 to 240 [Hz]. The first refresh rate and the third refresh rate can also be the same.

[0046] The embodiments described above are for illustrative purposes only and are not intended to be limiting. Many modifications are possible based on these illustratives and descriptions, as will be apparent to those skilled in the art.

[0047] Disclosure 1: A display device comprising: a display unit including a plurality of rows; a scan driver driving the display unit; and a control unit controlling the scan driver, wherein a plurality of clock signals with different phases are input to the scan driver, and the control unit sets a refresh rate switching position based on data of the first image and data of the second image and the phases of the plurality of clock signals when displaying a first image and a second image with a frequency lower than that of the first image adjacent to each other.

[0048] Disclosure Item 2: In the display device according to Disclosure Item 1, m is an integer greater than or equal to 2, the plurality of clock signals are clock signals from the first clock signal to the m-th clock signal, and the switching position is the row of pulses of the first clock signal being output.

[0049] Disclosure 3: In the display device according to Disclosure 2, the control unit sets a portion of the second image to the same refresh rate as the first image, so that the switching position corresponds to the row of the pulse of the first clock signal being output.

[0050] Disclosure Item 4: According to the display device described in Disclosure Item 2, when A is a natural number, T is an integer greater than or equal to 0, the end of the first image is row A, and the beginning of the second image is row (A+1), the control unit sets row A to row (A+T) in the display unit to a first refresh rate, and sets row (A+T+1), which is the switching position, to a second refresh rate lower than the first refresh rate.

[0051] Disclosure Item 5: According to the display device described in Disclosure Item 4, when B is a natural number greater than A, F is an integer greater than or equal to 0, and the end of the second image is line B, the control unit sets lines (A+T+1) to (BF) in the display unit as the second refresh rate.

[0052] Disclosure Item 6: The display device according to Disclosure Item 4, wherein 0 ≤ T ≤ m-1.

[0053] Disclosure Item 7: The display device according to Disclosure Item 5, wherein 0 ≤ F ≤ m-1.

[0054] Disclosure Item 8: The display device according to Disclosure Item 5, wherein pulses of the first clock signal are output to the (A+T+1) row and the (B-F+1) row respectively.

[0055] Public Item 9: The display device according to Public Item 5, wherein the shift register outputs the pulse of the m-th clock signal to the (A+T) row and the (BF) row respectively.

[0056] Disclosure Item 10: According to the display device of Disclosure Item 5, when the control unit displays a third image with a frequency higher than that of the second image adjacent to the second image, and the starting point of the third image is row (B+1), the control unit sets row (B+1-F) in the display unit to a third refresh rate higher than the second refresh rate.

[0057] Disclosure Item 11: In the display device according to Disclosure Item 5, the portion corresponding to rows (A+T+1) to (BF) in the display section is set to blank in the pulse pattern of the first clock signal to the m-th clock signal.

[0058] Disclosure Item 12: A display device according to any one of Disclosure Items 2 to 11, wherein the first clock signal to the m-th clock signal have the same period, and the phases of the first clock signal and the m-th clock signal are offset by an amount of 1 / m period.

[0059] Disclosure Item 13: The display device according to Disclosure Item 12, wherein the 1 / m period is equal to one horizontal scan period.

[0060] Disclosure Item 14: A display device according to any one of Disclosure Items 1 to 13, wherein the display section includes a plurality of scan lines arranged in a first direction, and the first image and the second image are displayed adjacent to each other in the first direction.

[0061] Disclosure Item 15: A display device according to any one of Disclosure Items 1 to 14, wherein the control unit receives position information of the first image and the second image from the outside.

[0062] Disclosure Item 16: A display device according to any one of Disclosure Items 1 to 15, wherein the control unit determines the position information of the first image and the second image from the temporal changes of the image.

[0063] Disclosure Item 17: In the display device according to Disclosure Item 16, the control unit determines the time change by using a data checksum for each unit area.

[0064] Disclosure Item 18: The display device according to any one of Disclosure Items 1 to 17, wherein the control unit includes a timing controller and a level shifting circuit.

[0065] Disclosure Item 19: The display device according to Disclosure Item 18, wherein the level shifting circuit uses multiple reference signals from the timing controller to generate multiple clock signals with a number of phases greater than the number of phases of the multiple reference signals.

[0066] Disclosure 20: A control method for a display device, wherein the display device comprises: a display unit including a plurality of rows; a scan driver that drives the display unit; and a control unit that controls the scan driver, wherein a plurality of clock signals with different phases are input to the scan driver, and the control method for the display device sets a refresh rate switching position based on data of the first image, data of the second image, and the phases of the plurality of clock signals when displaying a first image and a second image with a frequency lower than that of the first image adjacent to each other.

Claims

1. A display device, characterized in that, The device includes: a display unit comprising multiple rows; a scan driver that drives the display unit; and a control unit that controls the scan driver, wherein multiple clock signals with different phases are input to the scan driver, and the control unit sets the refresh rate switching position based on the data of the first image and the data of the second image and the phases of the multiple clock signals when displaying a first image and a second image with a frequency lower than that of the first image adjacent to each other.

2. The display device according to claim 1, wherein, Let m be an integer greater than or equal to 2, the plurality of clock signals are clock signals from the first clock signal to the m-th clock signal, and the switching position is the row of pulses of the first clock signal being output.

3. The display device according to claim 2, wherein, The control unit sets a portion of the second image to the same refresh rate as the first image, so that the switching position corresponds to the row of the pulse of the first clock signal being output.

4. The display device according to claim 2, wherein, When A is a natural number, T is an integer greater than or equal to 0, the end of the first image is row A, and the beginning of the second image is row (A+1), the control unit sets row A to row (A+T) in the display unit to the first refresh rate, and sets row (A+T+1), which is the switching position, to the second refresh rate, which is lower than the first refresh rate.

5. The display device according to claim 4, wherein, If B is a natural number greater than A, F is an integer greater than or equal to 0, and the end of the second image is line B, the control unit sets lines (A+T+1) to (BF) in the display unit as the second refresh rate.

6. The display device according to claim 4, wherein, 0≤T≤m-1.

7. The display device according to claim 5, wherein, 0≤F≤m-1.

8. The display device according to claim 5, wherein, The pulses of the first clock signal are output to the (A+T+1) row and the (B-F+1) row respectively.

9. The display device according to claim 5, wherein, In the shift register, the pulses of the m-th clock signal are output to the (A+T) row and the (BF) row, respectively.

10. The display device according to claim 5, wherein, When the control unit displays a third image with a higher frequency than the second image adjacent to the second image, and the starting point of the third image is row (B+1), the control unit sets row (B+1-F) in the display unit to a third refresh rate that is higher than the second refresh rate.

11. The display device according to claim 5, wherein, In the pulse pattern of the first to the mth clock signals, the portions corresponding to rows (A+T+1) to (BF) in the display section are set to blank.

12. The display device according to any one of claims 2 to 9, wherein, The first clock signal to the m-th clock signal have the same period, and the phases of the first clock signal and the m-th clock signal are offset by 1 / m period.

13. The display device according to claim 12, wherein, The 1 / m period is equal to one horizontal scan period.

14. The display device according to any one of claims 1 to 9, wherein, The display unit includes a plurality of scan lines arranged in a first direction, and the first image and the second image are displayed adjacent to each other in the first direction.

15. The display device according to any one of claims 1 to 9, wherein, The control unit receives the position information of the first image and the second image from the outside.

16. The display device according to any one of claims 1 to 9, wherein, The control unit determines the position information of the first image and the second image based on the temporal changes of the images.

17. The display device according to claim 16, wherein, The control unit determines the time change by checking the data in each unit area.

18. The display device according to any one of claims 1 to 9, wherein, The control unit includes a timing controller and a level shifting circuit.

19. The display device according to claim 18, wherein, The level shifting circuit uses multiple reference signals from the timing controller to generate multiple clock signals with a greater number of phases than the multiple reference signals.

20. A control method for a display device, the display device comprising: a display unit including a plurality of rows; a scan driver driving the display unit; and a control unit controlling the scan driver, wherein a plurality of clock signals with different phases are input to the scan driver, the control method for the display device being characterized in that, when a first image and a second image with a frequency lower than the frequency of the first image are displayed adjacent to each other, a refresh rate switching position is set based on data of the first image and data of the second image and the phases of the plurality of clock signals.

Images