Method for realizing SDRAM function performance online detection based on JTAG tool
By designing an online testing method based on JTAG tools, a functional and performance test program for SDRAM was developed, which solves the problems of low testing efficiency and insufficient coverage in existing technologies, and achieves full coverage testing of SDRAM, thereby improving the quality and reliability of electronic devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-01
AI Technical Summary
In existing technologies, the boundary scan test efficiency of SDRAM is low and the internal bit test coverage is insufficient, which makes it impossible to effectively test performance when the CPU fails to access SDRAM, thus affecting the quality and reliability of electronic devices.
Using a JTAG-based approach, SDRAM functional and performance test programs were designed. By controlling the PC pointer logical address through a CPU emulator and utilizing the SRAM mode within the CPU for online testing, combined with an ELF test program, the functional and performance tests of the SDRAM were achieved.
This technology enables full-coverage functional and performance testing of SDRAM without altering the firmware of electronic devices, improving testing efficiency and coverage, and ensuring the quality and reliability of SDRAM.
Smart Images
Figure CN121963832A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic device design and manufacturing, specifically relating to a method for diagnosing and locating memory faults during the manufacturing and use of electronic devices. Background Technology
[0002] The electronic devices discussed in this article refer to embedded hardware systems that use a CPU as the central processing unit and SDRAM (Synchronous Dynamic Random Access Memory, hereinafter referred to as SDRAM) as the external storage unit. Commonly used SDRAM devices are divided into SDR SDRAM (Single Data Rate SDRAM), DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR2 SDRAM, DDR3 SDRAM, etc.
[0003] As the external storage unit of electronic devices, SDRAM plays a crucial role in the quality of electronic devices due to its correct functionality and stable performance. SDRAM functions include read / write capabilities and data retention; its performance includes read bandwidth, write bandwidth, copy bandwidth, latency, and high-temperature resistance.
[0004] During the manufacturing and use of electronic devices, the failure of CPU access to SDRAM often leads to the overall failure of the device's functionality. Common SDRAM testing methods include boundary scan testing and internal bit testing. Boundary scan testing inputs test vectors to SDRAM through the JTAG interface. The execution timing of the test vectors is limited by the timing of JTAG, making it impossible to perform SDRAM performance testing. Internal SDRAM bit testing requires the electronic device's SDRAM bit test program to execute normally. Most designers' SDRAM bit test programs need to be loaded into SDRAM for execution. When CPU access to SDRAM fails, internal SDRAM bit testing cannot be executed, resulting in SDRAM test failure. Summary of the Invention
[0005] The purpose of this invention is to provide a method for online functional performance testing of SDRAM based on JTAG tools. The test vectors can cover the entire physical address space of SDRAM, and the SDRAM read / write test frequency meets performance testing requirements. This method combines the advantages of CPU JTAG tools and ELF test programs to perform functional and stress tests on SDRAM devices to screen out products with abnormal SDRAM functions or unstable performance. It solves the problems of low testing efficiency in boundary scan testing and insufficient coverage in internal bit testing, thereby improving the quality and reliability of delivered products.
[0006] The objective of this invention is achieved through the following technical solution:
[0007] A method for online performance testing of SDRAM based on JTAG tools includes the following steps:
[0008] Step 1: Design SDRAM functional test program and performance test program; the target file size of the functional test program and performance test program shall not exceed the size of the CPU cache with SRAM mode; set the starting address information of code segment, static data segment, data segment and stack segment in the functional test program and performance test program;
[0009] Step 2: Use a CPU emulator to control the PC pointer to fetch logical addresses via the JTAG interface to complete the PC pointer jump function and switch the CPU cache in SRAM mode to SRAM mode.
[0010] Step 3: Load the functional test program and performance test program into the CPU's SRAM-mode cache to execute the test program.
[0011] Preferably, the target files of the SDRAM functional test program and performance test program are in ELF format and are compiled using the compilation environment provided by the CodeWarrior IDE integrated development environment.
[0012] The beneficial effects of this invention are as follows:
[0013] The present invention proposes a method for online testing of SDRAM functionality and performance based on JTAG tools. This method enables functional performance testing of CPU external storage SDRAM without altering the firmware (burned into FLASH) of the electronic device. The execution frequency of the test vectors is based on the CPU core speed, overcoming the limitation of emulator memory testing speed. Furthermore, compared to the memory testing methods included in debugging software, this invention supports the independent design of SDRAM functional performance ELF test programs. Users only need to develop ELF test programs according to the specific design of their own devices, gaining complete control over the ELF test program, testing process, and test results. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of SDRAM.
[0015] Figure 2 This is a schematic diagram of a DRAM cell.
[0016] Figure 3 This is a schematic diagram of a DRAM storage array.
[0017] Figure 4 This is a schematic diagram of the local memory map.
[0018] Figure 5 This is a schematic diagram of the P2020 (single-core mode).
[0019] Figure 6 This is a schematic diagram of the e500 Core.
[0020] Figure 7 This is a schematic diagram of the P2020 two-level cache.
[0021] Figure 8 This is a schematic diagram of the local memory map.
[0022] Figure 9 This is a schematic diagram of the Elf file execution process. Detailed Implementation
[0023] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.
[0024] SDRAM can be categorized into SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM. SDR SDRAM, literally translated as Synchronous Dynamic Random Access Memory, has a clock frequency and data transfer frequency synchronized with the CPU. DDR SDRAM, literally translated as Double Data Rate Synchronous Dynamic Random Access Memory, can transfer data twice per clock cycle compared to SDR SDRAM, which can only transfer data once per clock cycle, once on the rising edge and once on the falling edge of the clock. DDR2 SDRAM and DDR3 SDRAM have further improvements in frequency, bandwidth, and power consumption; see [link to documentation] for specific parameters. Figure 1 As shown.
[0025] The basic internal structural unit of SDRAM is the DRAM cell (memory cell), such as... Figure 2As shown, it consists of a capacitor and a CMOS transistor. By adding or removing the voltage to the gate of the transistor, the CMOS transistor can be controlled to turn on or off. When it is on, the amount of electricity stored in the capacitor can be read or written, corresponding to the logic "1" or "0" of the storage cell.
[0026] A memory array is composed of many DRAM cells, with rows corresponding to word lines and columns corresponding to bit lines, such as... Figure 3 As shown.
[0027] DRAM failure modes can be categorized as follows:
[0028] (1) Stack-at Fault (SAF)
[0029] The memory cell is either "0" or "1". "0" cannot be switched to "1" and "1" cannot be switched to "0".
[0030] (2)Translation Fault Model(TF)
[0031] The storage cell is either "0" or "1". "0" can switch to "1" but "1" cannot switch to "0", or "1" can switch to "0" but "0" cannot switch to "1".
[0032] (3) Coupling Fault (CF)
[0033] Take two cells as an example. The two cells are not independent and there is coupling interference.
[0034] (4)Neighborhood pattern sensitive Fault Model(NPSF)
[0035] It affects the values of adjacent cells.
[0036] (5) Decode Fault (DF)
[0037] The failure was caused by an address decoding error.
[0038] (6) Transition Delay Fault
[0039] Delay fault.
[0040] (7) Current-based fault model
[0041] Current fault.
[0042] The aforementioned faults are unavoidable during the manufacturing and repair of electronic devices. The focus of this invention is to find a way to perform functional performance tests on the CPU's external SDRAM without changing the firmware (burned into FLASH) of the electronic device, and to screen out products with abnormal SDRAM functions or unstable performance.
[0043] SDRAM functional testing is mainly achieved by the CPU executing test programs for SDRM storage array scanning, read / write functions, and data retention functions.
[0044] SDRAM performance testing is mainly achieved by configuring the CPU to meet different timing specifications such as speed grades, latency type, burst lengths, and burst type, and by having the CPU execute test programs for read bandwidth performance, write bandwidth performance, copy bandwidth performance, latency timing performance, and high temperature resistance performance.
[0045] This invention discloses a method for online performance testing of SDRAM based on the JTAG tool, comprising the following steps:
[0046] Step 1: Design SDRAM functional test program and performance test program
[0047] SDRAM functional and performance test programs need to reside on on-chip or off-chip memory resources accessible to the CPU. Off-chip memory resources are the test targets of this test program and cannot be used to reside on test programs. Considering that most CPUs have introduced multi-level cache architecture technology, the CPU has internal L1, L2, and even L3 level caches. L1 level cache is usually the CPU's instruction / data cache unit and cannot be used as SRAM. L2 or L3 level cache can be used as SRAM (the CPU must support this function).
[0048] Taking the P2020 processor as an example, the P2020's internal L1 I-Cache and L1 D-Cache are used to cache instructions and data. The L2 Cache has both cache and SRAM functions. The L2 Cache physical space is 512Kbytes. As long as the target file size of the designed SDRAM function test and performance test program does not exceed the size of the CPU's SRAM-mode cache, i.e., 512Kbytes, it is acceptable.
[0049] The target files for SDRAM functional and performance test programs are in ELF format and are generated by the CPU's corresponding compilation tools. The ELF file needs to set the starting address information for each segment, including the code segment, static data segment, data segment, and stack segment, such as... Figure 4 As shown.
[0050] Step 2: After the electronic device is powered on, the logical address of the PC pointer (instruction register) is determined by the hardware reset state and CPU function. It is necessary to use a CPU emulator to control the logical address of the PC pointer through the JTAG interface to complete the jump function of the PC pointer and switch the L2 Cache to SRAM mode.
[0051] Step 3: Use the load function of the debugging software to load the ELF file into the L2 Cache to enable the execution of the test program.
[0052] The following explanation uses the P2020 and DDR2 hardware platform design as an example.
[0053] like Figure 5 As shown, the P2020 integrates the e500 Core, e500 Coherency Module, and DDR2 / DDR3 controller. The e500 Core's instruction and data flows require control over DDR2 access via the Core Interface Unit, L2 Cache, e500 Coherency Module (ECM), and DDR2 / DDR3 controller. Figure 6 As shown. The P2020 internally includes two levels of cache: L1 cache and L2 cache, as... Figure 7 As shown.
[0054] After a hardware reset or power-on of the e500 Core, by default, L1CSR0[DCE] = 0, L1CSR1[ICE] = 0, and the instruction L1 cache and data L1 cache are not enabled. L2CTL[L2E] = 0, and the L2 SRAM is not enabled. Using a CPU emulator to control the PC pointer's logical address via the JTAG interface, the L2 cache / SRAM can be configured as an SRAM mode, serving as the memory environment for ELF programs. Figure 8 As shown.
[0055] The main functions of the CMM script are configuring the P2020 registers and controlling the TRACE32 function. P2020 register configuration includes configuring TLB0, TLB1, and TLB2 to map the physical addresses of CCSRBAR, DDR, and L2 cache; configuring the L2 cache / SRAM as SRAM; and configuring DDR2 controller parameters and the LAW controller. TRACE32 control includes booting the target board to load the ELF file, displaying the memory operation process, setting breakpoints, and commanding the PC to start the test.
[0056] The configuration function of the P2020 registers can be implemented in the CMM script or in the ELF program. Considering the portability of the CMM script + ELF file, the configuration function of the P2020 registers is implemented by the CMM script. Each type of CPU module reads back the BSP default register configuration information through the CMM script and configures the relevant registers before memory testing.
[0057] The CMM script implements hardware resource initialization functions before the ELF program loads, including CPU reset control, CPU internal register configuration, and SDRAM register configuration.
[0058] ELF files are compiled using the compilation environment provided by the CodeWarrior IDE integrated development environment. The compilation tools require configuration of the ELF program file's load address, stack address, and program entry point. The `memTest` function in the test case is the entry point function for memory testing. Common memory faults are categorized into configuration failures, connectivity failures, and read / write failures.
[0059] The following is an example of the test program execution. Figure 9 As shown.
[0060] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.
Claims
1. A method for online performance testing of SDRAM based on JTAG tools, characterized in that... Includes the following steps: Step 1: Design SDRAM functional test program and performance test program; The target file size of the functional test program and the performance test program shall not exceed the size of the CPU cache with SRAM mode; the starting address information of the code segment, static data segment, data segment and stack segment shall be set in the functional test program and the performance test program; Step 2: Use a CPU emulator to control the PC pointer to fetch logical addresses via the JTAG interface to complete the PC pointer jump function and switch the CPU cache in SRAM mode to SRAM mode. Step 3: Load the functional test program and performance test program into the CPU's SRAM-mode cache to execute the test program.
2. The method for online testing of SDRAM functional performance based on JTAG tools according to claim 1, characterized in that... The target files for the SDRAM functional test program and performance test program are in ELF format and are compiled using the compilation environment provided by the CodeWarrior IDE integrated development environment.