A high-speed differential clock switching circuit with no burr and low latency
By optimizing the circuit structure and replacing traditional flip-flops with synchronous modules and level flip-flops, the problem of excessive delay in high-speed differential clock switching was solved, achieving glitch-free and low-latency clock switching, and improving phase adjustment accuracy and circuit stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BRITE SEMICON SHANGHAI CORP
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-09
AI Technical Summary
Traditional glitch-free clock switching circuits suffer from excessive delays during high-speed differential signal switching, affecting phase adjustment accuracy and the normal operation of subsequent logic circuits.
The circuit structure consists of first and second synchronization modules, level triggering module and logic gates. By setting NOR gates and latches after the synchronization module, the clock switching process is optimized and the delay is reduced.
It achieves glitch-free high-speed differential clock switching, reduces the delay in the switching process, and improves the phase adjustment accuracy and circuit stability.
Smart Images
Figure CN121966522B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design technology, specifically to a glitch-free, low-latency high-speed differential clock switching circuit. Background Technology
[0002] In high-speed wired transmission systems, dynamic adjustment of the output clock phase is often required to achieve precise alignment between channels and overall timing convergence. This requirement is particularly critical in scenarios involving multi-channel SerDes, PCIe, and DDR interfaces. To achieve high-precision phase adjustment, systems typically employ a multi-phase clock generation architecture (such as 2-phase, 4-phase, or 8-phase clocks generated by DLLs or PLLs), selectively switching phase sources to achieve precise phase adjustment. This method must ensure that no glitches are generated during the switching process; otherwise, it will affect the normal operation of subsequent logic circuits. Furthermore, the smaller the phase switching delay, the higher the phase adjustment accuracy.
[0003] Traditional glitch-free clock switching circuits, such as Figure 1 As shown, input clocks CK0 and CK1 are synchronized with the switching signal SEL through two stages of DFF (D-FlipFlop). The synchronized selection signals DFF01_OUT and DFF11_OUT then perform the final clock switching between CK0 and CK1 through three NAND gates NAND0, NAND1, and NAND2. Because the selection signals are synchronized with their respective clocks, this ensures that no glitches occur during the switching process.
[0004] When CK0 and CK1 are differential clocks at the same frequency, their operation is as follows: Figure 2 As shown, when the SEL signal goes high from 0 to 1, the output of the NOR gate NOR0, which is the input DFF00_IN of DFF00, immediately goes low. When the next rising edge of CK0 arrives, the output DFF00_OUT of DFF00 changes from high to low. Then, the next falling edge of CK0 samples the low level to the output of DFF01. At this time, the output of the NAND gate NAND0 changes from CK0 to high. When DFF01_OUT changes from high to low, both inputs of the NOR gate NOR1 go low. At this time, the input DFF10_IN of DFF10 jumps from low to high. When the next falling edge of CK1 arrives, the high level is sampled to the output DFF10_OUT of DFF11. After receiving the high output of DFF11, the output of NAND1 switches to the clock of CK1, and then the output of NAND2 also switches to the clock of CK1. Thus, the output clock CKOUT changes from CK0 to CK1. Figure 2As can be seen, the time interval from the last falling edge of CK0 before the switch to the first rising edge of CK1 after the next switch is 2*Tclk (Tclk is the period of CK0 and CK1). Ideally, this time should be 1*Tclk, so... Figure 1 The circuit shown consumes an additional 1*Tclk delay during the switching process. Summary of the Invention
[0005] The purpose of this invention is to provide a glitch-free, low-latency high-speed differential clock switching circuit that can solve the problems mentioned in the background art.
[0006] To achieve the above objectives, the present invention provides the following technical solution: a glitch-free, low-latency high-speed differential clock switching circuit, comprising a first synchronization module, a second synchronization module, a first level trigger module, a second level trigger module, a first logic gate, a second logic gate, and an output module;
[0007] The first synchronization module receives an external selection signal at its data input terminal and a first clock signal at its clock input terminal, and is used to synchronize the external selection signal with the rising edge of the first clock domain to generate a first synchronization signal.
[0008] The second synchronization module receives the inverted signal of the external selection signal at its data input terminal and receives a second clock signal at its clock input terminal. It is used to synchronize the inverted external selection signal with the rising edge of the second clock domain to generate a second synchronization signal.
[0009] The first level-triggered module has its enable terminal connected to the output terminal of the first logic gate, and its clock input terminal receives a first clock signal. When the first clock signal is low, it is used to transparently transmit the output signal of the first logic gate to generate a first gating control signal.
[0010] The second level-triggered module has its enable terminal connected to the output terminal of the second logic gate, and its clock input terminal receives a second clock signal. When the second clock signal is low, it is used to transparently transmit the output signal of the second logic gate to generate a second gating control signal.
[0011] The first logic gate receives the first synchronization signal at its first input terminal and the second gating control signal at its second input terminal, and is used to perform logical operations on the two input signals and output them to the first level trigger module.
[0012] The second logic gate receives the second synchronization signal at its first input terminal and the first strobe control signal at its second input terminal, and is used to perform logical operations on the two input signals and output them to the second level trigger module.
[0013] The output module is connected to the first level trigger module and the second level trigger module respectively, receives the first gating control signal and the second gating control signal, and simultaneously receives the first clock signal and the second clock signal, and is used to select the first clock signal or the second clock signal as the output clock signal according to the first gating control signal and the second gating control signal.
[0014] Preferably, the first logic gate and the second logic gate are NOR gates.
[0015] Preferably, the first level-triggered module and the second level-triggered module are latches.
[0016] Preferably, the output module includes a first NAND gate, a second NAND gate, and a third NAND gate; the first input terminal of the first NAND gate receives the first clock signal, and the second input terminal receives the first gating control signal; the first input terminal of the second NAND gate receives the second clock signal, and the second input terminal receives the second gating control signal; the output terminals of the first NAND gate and the second NAND gate are respectively connected to the two input terminals of the third NAND gate, and the output terminal of the third NAND gate outputs the output clock signal.
[0017] Preferably, the first synchronization module and the second synchronization module are D flip-flops.
[0018] Compared with the prior art, the beneficial effects of the present invention are:
[0019] The present invention provides a high-speed differential clock switching circuit with no glitches and low latency. When the input clock is a differential signal, it can not only achieve a clock switching function without glitches, but also greatly reduce the latency consumed in the switching process. Attached Figure Description
[0020] Figure 1 This is a circuit diagram for a traditional glitch-free clock switching circuit.
[0021] Figure 2 This is a schematic diagram of a traditional glitch-free clock switching circuit when the input is a differential clock.
[0022] Figure 3 This is a circuit diagram of the glitch-free clock switching circuit proposed in this invention.
[0023] Figure 4 This is a schematic diagram of the glitch-free clock switching circuit proposed in this invention. Detailed Implementation
[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0025] The glitch-free clock switching circuit proposed in this invention is as follows: Figure 3 As shown. With Figure 1 The difference in the circuit is that the NOR gates NOR0 and NOR1 have been moved from the stage before the flip-flops DFF00 and DFF10 to the stage after the corresponding flip-flops, which can greatly reduce the delay caused by clock switching. Figure 1 The mid-edge flip-flops DFF01 and DFF11 are replaced with level flip-flops LATCH00 and LATCH11. This increases the timing window required for sampling of the second-stage flip-flops, which is more conducive to the structure working at high speeds.
[0026] The phase switching signal SEL is directly connected to the data input D terminal of DFF00. SEL, through the signal SELB of inverter INV0, is input to the D terminal of DFF10. After sampling on the rising edge of CK0, the outputs DFF00_OUT of DFF00 and LATCH10_OUT of LATCH10 are input to the two ends of NOR0. The output of NOR0 is connected to the input D terminal of LATCH00. After sampling at a low level of CK0, on one hand, the output LATCH00_OUT of LATCH00 and the clock signal CK0 are connected to the two input terminals of NAND0. On the other hand, LATCH00_OUT and DFF10_OUT are connected to the two output terminals of NOR1. The output of NOR1 is connected to the input D terminal of LATCH10. After sampling at a low level of CK1, the output LATCH10_OUT of LATCH10 and the clock signal CK1 are respectively connected to the two input terminals of NAND1. The outputs of NAND0 and NAND1 are respectively connected to the input terminals of NAND2, and the output terminal of NAND2 is the clock output signal CKOUT.
[0027] Figure 4The clock switching circuit proposed in this patent operates as follows when the input clock is a differential clock: When the selection signal SEL transitions from 0 to 1, the inputs DFF00_IN and DFF10_IN of DFF00 and DFF10 respectively transition from low to high and from high to low. When the next rising edge of CK0 arrives, the high level is sampled, and the output DFF00_OUT of DFF00 transitions from low to high. Similarly, when the next rising edge of CK1 arrives, the output DFF10_OUT of DFF10 transitions from high to low. After DFF00_OUT transitions high, the output of the NOR gate NOR0 and the input LATCH00_IN of LATCH00 transition from high to low. When the next low level of CK0 arrives, the output of LATCH00 transitions from high to low. At this time, the output of the NAND gate NAND0 changes from the clock of CK0 to a high level. After both DFF10_OUT and LATCH00_OUT go low, the NOR1 output LATCH10_IN will transition from low to high. When the next CK1 low level arrives, the high level is sampled onto the LATCH10 output LATCH10_OUT. At this point, the NAND1 output switches from high to the CK1 clock, completing the clock transition from CK0 to CK1. Figure 4 As can be seen, the time interval between the last falling edge of CK0 before the switch and the first rising edge of CK1 after the next switch is only one clock cycle Tclk, which is relatively... Figure 1 The circuit shown reduces the time by one clock cycle. The time consumed during the switching process is greatly reduced.
[0028] The following is an appendix to the instruction manual. Figures 1-4 Chinese explanations of English and Chinese terms:
[0029] SEL Select Signal
[0030] CK0 Clock 0
[0031] CK1 Clock 1
[0032] DFF D trigger
[0033] NOR gate
[0034] NAND gate
[0035] INV0 inverter
[0036] D (pin label) Data input terminal
[0037] Q (pin label) output terminal
[0038] CKOUT output clock
[0039] Tclk clock cycle
[0040] LATCH latch
[0041] This invention provides a high-speed differential clock switching circuit with zero glitches and low latency. When the input clock is a differential signal, it not only achieves glitch-free clock switching but also significantly reduces the latency consumed during the switching process. Furthermore, although this invention focuses on the case of differential clock input, if the logic speed is fast enough, this structure is also applicable to multi-phase clock (4-phase, 8-phase) switching.
[0042] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0043] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A glitch-free, low-delay high-speed differential clock switching circuit, characterized in that, It includes a first synchronization module, a second synchronization module, a first level-triggered module, a second level-triggered module, a first logic gate, a second logic gate, and an output module; The first synchronization module receives an external selection signal at its data input terminal and a first clock signal at its clock input terminal, and is used to synchronize the external selection signal with the rising edge of the first clock domain to generate a first synchronization signal. The second synchronization module receives the inverted signal of the external selection signal at its data input terminal and receives a second clock signal at its clock input terminal. It is used to synchronize the inverted external selection signal with the rising edge of the second clock domain to generate a second synchronization signal. The first level-triggered module has its enable terminal connected to the output terminal of the first logic gate, and its clock input terminal receives a first clock signal. When the first clock signal is low, it is used to transparently transmit the output signal of the first logic gate to generate a first gating control signal. The second level-triggered module has its enable terminal connected to the output terminal of the second logic gate, and its clock input terminal receives a second clock signal. When the second clock signal is low, it is used to transparently transmit the output signal of the second logic gate to generate a second gating control signal. The first logic gate receives the first synchronization signal at its first input terminal and the second gating control signal at its second input terminal, and is used to perform logical operations on the two input signals and output them to the first level trigger module. The second logic gate receives the second synchronization signal at its first input terminal and the first strobe control signal at its second input terminal, and is used to perform logical operations on the two input signals and output them to the second level trigger module. The output module is connected to the first level trigger module and the second level trigger module respectively, receives the first gating control signal and the second gating control signal, and simultaneously receives the first clock signal and the second clock signal, and is used to select the first clock signal or the second clock signal as the output clock signal according to the first gating control signal and the second gating control signal.
2. The glitch-free, low-latency high-speed differential clock switching circuit according to claim 1, characterized in that, The first logic gate and the second logic gate are NOR gates.
3. The glitch-free, low-delay high-speed differential clock switching circuit according to claim 1, characterized in that, The first level-triggered module and the second level-triggered module are latches.
4. The glitch-free, low-delay high-speed differential clock switching circuit according to claim 1, characterized in that, The output module includes a first NAND gate, a second NAND gate, and a third NAND gate; the first input terminal of the first NAND gate receives the first clock signal, and the second input terminal receives the first gating control signal; the first input terminal of the second NAND gate receives the second clock signal, and the second input terminal receives the second gating control signal; the output terminals of the first NAND gate and the second NAND gate are respectively connected to the two input terminals of the third NAND gate, and the output terminal of the third NAND gate outputs the output clock signal.
5. The glitch-free, low-latency high-speed differential clock switching circuit according to claim 1, characterized in that, The first synchronization module and the second synchronization module are D flip-flops.