Analog multiplexer interference rejection protection circuit for precision signal links

Abstract

The present application belongs to the field of analog integrated circuit design, and specifically relates to an analog multiplexer interference suppression protection circuit for a precision signal link, aiming to solve the problems of overvoltage impact on power supply, signal transmission interference, and damage to the subsequent circuit of the traditional structure I / O port. The circuit includes N input channel circuits arranged in parallel and an output end detection and discharge circuit. The input channel circuit integrates input end detection, input end discharge, transmission switch, and central discharge functions. All circuits are composed of resistors, NMOS tubes, and PMOS tubes. Single-channel signal gating transmission is realized by regulating the control end signal of the input channel circuit. The detection circuit monitors signal abnormalities in real time and triggers the discharge circuit to quickly discharge the overvoltage spike or injected current through the ground loop. At the same time, the voltage is clamped and the protection is shunted when the gating channel is abnormal. This scheme avoids the impact on the power supply rail, reduces signal interference between channels, realizes input power failure isolation, does not require strict external power-up timing, significantly improves the precision and reliability of precision signal transmission, enhances the stability of devices and systems, and is suitable for analog multiplexer, analog switch, and other integrated circuits, and is suitable for smart driving, industrial automation, and other multi-scenario requirements.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design, and in particular relates to an analog multiplexer interference suppression and protection circuit for precision signal links. Background Technology

[0002] With the rapid development of fields such as intelligent driving and industrial automation, the high integration of sensor technology has placed stringent demands on the accuracy and reliability of signal acquisition in the precision signal links within the system. Analog multiplexers, as core components for multi-sensor signal management, effectively simplify the signal transmission architecture of complex systems, reduce the number of components and PCB footprint, and are indispensable in scenarios such as driver assistance systems and IoT devices. The stability of their signal transmission directly determines the operational reliability of the entire system.

[0003] Traditional analog multiplexer architecture, such as Figure 3 As shown, each channel consists of diodes D1 and D2, inverter INV1, PMOS transistor, and NMOS transistor. The working principle is as follows: when the channel is selected, the control terminal is connected to a 0V potential, and the inverter controls the PMOS transistor and NMOS transistor to conduct. When the channel is not selected, the control terminal is connected to a VDD potential, which turns off the transmission switch. At the same time, diodes D1 and D2 are used to initially clamp and discharge the overvoltage spikes at the input port.

[0004] However, this traditional structure is difficult to meet the requirements of precision signal links and has obvious technical defects: First, overvoltage spikes are directly conducted to the power supply VDD through diode D1, which will cause overvoltage surges to the power supply. This may not only damage other devices on the same power rail, but also limit the power-down protection design of the system. Second, overvoltage will activate the PMOS transistor, causing the output voltage to deviate. When the analog input source impedance is large, it will further affect the stability of the input signal. Third, overvoltage spikes or injected currents from unselected channels will still interfere with the signal transmission accuracy of the selected channel through internal parasitic paths. Abnormal signals from the selected channel will be directly transmitted to the subsequent circuits, causing system judgment errors or permanent damage to devices, which seriously restricts the reliability of precision signal acquisition. Summary of the Invention

[0005] To address the problems existing in the background art, this invention provides an analog multiplexer interference suppression and protection circuit for precision signal links, comprising: N input channel circuits and an output detection and discharge circuit; the N input channel circuits are arranged in parallel to receive multiple input signals and realize the gating and transmission of a single signal, while monitoring abnormal states of the input signals and discharging abnormal input signals; the output detection and discharge circuit is used to monitor abnormal states of the output signals and discharge abnormal output signals; wherein, the output detection and discharge circuit includes: resistors R11~R16, NMOS transistors N6~N7, and PMOS transistor P6; one end of resistor R11 The source of P6 and one end of resistor R12 are connected to the output of the N input channel circuit; the other end of resistor R11 and the drain of N7 are connected to the output of the multiplexer; the other end of resistor R12 is connected to the substrate of P6; the gate of P6 is connected to one end of resistor R13; the other end of resistor R13 is connected to the power supply VDD; the drain of P6 is connected to one end of resistor R14; the other end of resistor R14, the drain of N6, the gate of N7, and one end of resistor R16 are connected; the substrate of N7, the source of N7, and the other end of resistor R16 are grounded; the substrate of N6 and the source of N6 are grounded; the gate of N6 is connected to one end of resistor R15; the other end of resistor R15 is connected to the enable signal terminal EN.

[0006] The present invention has at least the following beneficial effects

[0007] This invention, through the collaborative design of N parallel input channel circuits and output detection and bleedering circuits, can not only quickly discharge overvoltage spikes or injected currents from unselected channels through a ground bleedering loop, avoiding impact on the signal accuracy of selected channels and other devices on the power rail, but also clamp the voltage and shunt part of the current when abnormal overvoltage occurs in the selected channel, preventing abnormal signals from damaging subsequent circuits. At the same time, it supports power-down isolation protection when the power supply is not powered on, minimizing power transfer and voltage coupling between input and output during power failure, without the need for strict external power-on timing, significantly improving the accuracy and reliability of precision signal transmission, and enhancing the working stability and applicability of devices and systems. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the overall circuit structure of the present invention;

[0009] Figure 2 This is a diagram showing the operating state of the circuit of the present invention;

[0010] Figure 3 This is a circuit diagram of a traditional structure. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] Example 1, please refer to Figure 1 and Figure 2 The present invention provides an analog multiplexer interference suppression and protection circuit for precision signal links, comprising: N input channel circuits, resistors R11~R16, NMOS transistors N6~N7, and PMOS transistor P6, wherein each input channel circuit comprises: NMOS transistors N1~N5, NMOS transistors P1~P5, and resistors R1~R10.

[0013] One end of resistor R11, the source of P6, and one end of resistor R12 are connected to the output terminals of the N input channel circuits; the other end of resistor R11 and the drain of N7 are connected to the output terminal of the multiplexer; the other end of resistor R12 is connected to the substrate of P6; the gate of P6 is connected to one end of resistor R13; the other end of resistor R13 is connected to the power supply VDD terminal; the drain of P6 is connected to one end of resistor R14; the other end of resistor R14, the drain of N6, the gate of N7, and one end of resistor R16 are connected; the substrate of N7, the source of N7, and the other end of resistor R16 are grounded; the substrate of N6 and the source of N6 are grounded; the gate of N6 is connected to one end of resistor R15; the other end of resistor R15 is connected to the enable signal EN.

[0014] In each input channel circuit, one end of resistor R1 is connected to the power supply VDD; the other end of resistor R1 is connected to the gates of P3, P4, and P5; one end of resistor R4 and the drain of N3 are connected to the input signal Sn; Sn represents the input signal of the nth input channel circuit, where n is a positive integer from 1 to N; the other end of resistor R4, one end of resistor R5, the source of P1, the drain of P4, the source of P5, and the source of N1 are connected; the source of P4 and the drain of P3 are connected; the source of P3, the substrate of P3, and one end of resistor R2 are connected; the substrates of P4 and P5, one end of resistor R5, and the substrate of P1 are connected; the substrate of N3, the source of N3, and one end of resistor R7 are grounded; the gate of N3, the other end of resistor R7, one end of resistor R8, and the drain of N4 are connected; resistors The other end of R8 is connected to the drain of P5; the substrate and source of N4 are grounded; the gate of N4 is connected to one end of resistor R9; the other end of resistor R9, the gate of N1, one end of resistor R10, and the gate of N2 are connected; the other end of resistor R10 is connected to the second control terminal CNn of the input channel circuit; the other end of resistor R2, the gate of P1, the gate of N5, the gate of P2, and one end of resistor R3 are connected; the other end of resistor R3 is connected to the first control terminal CPn of the input channel circuit; the drains of P1, N1, N5, P2, and N2 are connected; the source and substrate of N5 are grounded; the substrates of N1 and N2 are grounded; the substrate of P2 is connected to one end of resistor R6; the source of P2, the other end of resistor R6, and the source of N2 are connected to the output terminal of the input channel circuit.

[0015] Example 2, please refer to Figure 1 and Figure 2This invention provides an analog multiplexer interference suppression and protection circuit for precision signal links, comprising: N input channel circuits and an output detection and discharge circuit; the N input channel circuits are arranged in parallel to receive multiple input signals and realize the selection and transmission of a single signal, while monitoring abnormal states of the input signals and discharging abnormal input signals; the output detection and discharge circuit is used to monitor abnormal states of the output signals and discharge abnormal output signals; wherein, the output detection and discharge circuit includes: resistors R11~R16, NMOS transistors N6~N7, and PMOS transistor P6; one end of resistor R11, the source of P6, and... One end of resistor R12 is connected to the output of the N input channel circuit; the other end of resistor R11 and the drain of N7 are connected to the output of the multiplexer; the other end of resistor R12 is connected to the substrate of P6; the gate of P6 is connected to one end of resistor R13; the other end of resistor R13 is connected to the power supply VDD; the drain of P6 is connected to one end of resistor R14; the other end of resistor R14, the drain of N6, the gate of N7, and one end of resistor R16 are connected; the substrate of N7, the source of N7, and the other end of resistor R16 are grounded; the substrate of N6 and the source of N6 are grounded; the gate of N6 is connected to one end of resistor R15; the other end of resistor R15 is connected to the enable signal terminal EN.

[0016] Preferably, each of the input channel circuits includes: an input terminal detection circuit, an input terminal bleeder circuit, a transmission switch circuit, and a central bleeder circuit;

[0017] The input detection circuit is used to monitor the abnormal state of the input signal of the corresponding input channel circuit in real time and output a trigger signal;

[0018] The input terminal discharge circuit is connected to the input terminal detection circuit and is used to discharge abnormal current at the input port in response to the first trigger signal.

[0019] The transmission switch circuit is connected to the input bleeder circuit, receives the input signal from the input channel circuit and the control signal from the decoder, and regulates the conduction and cutoff of the input channel circuit to realize signal transmission.

[0020] The central discharge circuit is connected to the transmission switch circuit to protect the selected transmission signal and discharge abnormal charges.

[0021] Please see Figure 2Preferably, each input channel circuit includes: NMOS transistors N1~N5, NMOS transistors P1~P5, and resistors R1~R10; in each input channel circuit, one end of resistor R1 is connected to the power supply VDD; the other end of resistor R1 is connected to the gate of P3, the gate of P4, and the gate of P5; one end of resistor R4 and the drain of N3 are connected to the input signal Sn; Sn represents the input signal of the nth input channel circuit, where n is a positive integer from 1 to N; the other end of resistor R4, one end of resistor R5, the source of P1, the drain of P4, the source of P5, and the source of N1 are connected; the source of P4 and the drain of P3 are connected; the source of P3, the substrate of P3, and one end of resistor R2 are connected; the substrate of P4, the substrate of P5, one end of resistor R5, and the substrate of P1 are connected; the substrate of N3, the source of N3, and one end of resistor R7 are grounded; the gate of N3 and resistor R10 are connected to the source of N3. The other end of resistor 7, one end of resistor R8, and the drain of N4 are connected; the other end of resistor R8 is connected to the drain of P5; the substrate and source of N4 are grounded; the gate of N4 is connected to one end of resistor R9; the other end of resistor R9, the gate of N1, one end of resistor R10, and the gate of N2 are connected; the other end of resistor R10 is connected to the second control terminal CNn of the input channel circuit; the other end of resistor R2, the gate of P1, the gate of N5, the gate of P2, and one end of resistor R3 are connected; the other end of resistor R3 is connected to the first control terminal CPn of the input channel circuit; the drains of P1, N1, N5, P2, and N2 are connected; the source and substrate of N5 are grounded; the substrates of N1 and N2 are grounded; the substrate of P2 is connected to one end of resistor R6; the source of P2, the other end of resistor R6, and the source of N2 are connected to the output terminal of the input channel circuit.

[0022] Preferably, the input channel circuit is controlled to turn on and off by regulating the input signals of the first control terminal CPn and the second control terminal CNn; CPn represents the first control terminal of the nth input channel circuit; CNn represents the second control terminal CNn of the nth input channel circuit; when the nth input channel circuit is selected, the first control terminal CPn of the nth input channel circuit is grounded, and the second control terminal CNn of the nth input channel circuit is connected to the VDD potential; when the nth input channel circuit is not selected, the first control terminal CPn of the nth input channel circuit is connected to the VDD potential, and the second control terminal CNn of the nth input channel circuit is grounded.

[0023] Preferably, at any given time, only one of the N input channel circuits can be in the selected state.

[0024] The working principle of the circuit in the embodiments of the present invention will be explained as follows:

[0025] In the overall circuit, N input channel circuits operate in parallel. Single-channel selection is achieved by regulating the signals of the first control terminal CPn and the second control terminal CNn (when selected, CPn is grounded and CNn is connected to VDD; when not selected, CPn is connected to VDD and CNn is grounded). At most one channel can be selected at any given time, and the enable signal terminal EN is connected to VDD when selected. The input channel circuit integrates input detection, bleeding, transmission switching, and central bleeding functions. It is responsible for transmitting input signals, monitoring abnormal states of input signals, and bleeding abnormal input signals. The output detection and bleeding circuit monitors abnormal states of output signals and bleeds abnormal output signals.

[0026] The PMOS transistor is turned on when the gate-source voltage V is 0. GS <threshold voltage V THP The NMOS transistor is turned on when the gate-source voltage V0 is 0. GS Threshold voltage V THN .

[0027] When the input channel circuit is not selected and an overvoltage spike / injected current occurs, the control terminal state of the unselected channel is CPn=VDD, CNn=GND. When the input signal Sn experiences positive / negative overvoltage, graded discharge is triggered.

[0028] Positive overvoltage interference

[0029] Triggering the detection circuit: In the input channel circuit, the gate of P5 is connected to VDD through R1, and the source is connected to Sn through R4; when Sn is large enough (satisfying VDD-Sn)... <V THP5 That is, Sn>VDD-V THP5 ), V THP5 This represents the threshold voltage of P5; the gate-source voltage V of P5. GS5 When (VDD-Sn) reaches the turn-on threshold, P5 turns on; Sn is transferred to the gate of N3 through the turned-on P5, and the source of N3 is grounded. At this time, the voltage difference between Sn and GND is much greater than VDD-Sn. THN3 (Threshold voltage of N3) (Sn>VDD>>V THN3 N3's V GS (Sn-GND) satisfies the conduction condition, N3 is fully turned on, and the overvoltage current is quickly discharged through "Sn→N3→GND", with most of the abnormal current being conducted away at this stage. P3 and P4, which share the same gate source as P5 (both connected to R1→VDD), also satisfy the VDD-Sn condition because their gate-source voltages are connected to R1→VDD. <V THP3 / V THP4 (Threshold voltages of P3 / P4) synchronously turn on. After P3 turns on, its source is connected to CPn (VDD) through R2 and R3, forming a path of "Sn→R4→P4→P3→R2→R3→CPn (VDD)", which clamps the gate potential of P1 at the intermediate value V between VDD and Sn.GP1 ; If Sn is too large, causing the V of P1 GS1 (V GP1 - Sn, the gate-source voltage of P1) is less than V THP1 (the threshold voltage of P1), at this time P1 is partially conducting, and the gate of N5 is homologous to the gate of P1 (the intermediate value V between VDD and Sn GP1 ), and the V of N5 GS5 (V GP1 - GND, the gate-source voltage of N5) is much greater than V THN5 (the threshold voltage of N5), N5 is fully conducting, and a small amount of leakage current through P1 is discharged through "P1 → N5 → GND", preventing current from flowing to the output terminal. At the same time, the gates of N1 and N2 are connected to CNn = GND, and the gate-source voltage is negative, so they are fully turned off; the gate of P2 is homologous to the gate of P1 (the intermediate value V between VDD and Sn GP1 ), and the gate-source voltage does not meet the conduction condition, so P2 is fully turned off, finally achieving complete isolation between input and output, and no interference is transmitted to the selected channel. When Sn drops to VDD - Sn > V THP5 , P5 is turned off, and Sn is clamped at VDD + |V THP5 |, and the discharge process terminates, and the channel returns to the standby state. <9000101>Negative overvoltage interference

[0031] When Sn < GND, the gate of N3 is grounded through R7, and the source is grounded. When Sn is a negative voltage, the gate-source voltage of N3 (GND - Sn) > the threshold voltage of N3 (the more negative Sn is, the larger GND - Sn is), and N3 conducts directly, and the negative overvoltage current is discharged through "Sn → N3 → GND"; the gate of N1 is connected to CNn = GND,; the gate-source voltage of N1 (GND - Sn) > the threshold voltage of N1 (Sn is negative, GND - Sn is positive and greater than the threshold voltage of N1), and N1 conducts; the gate of N5 is connected to CPn = VDD, and the gate-source voltage of N5 (VDD - GND) > the threshold voltage of N5, and N5 is fully conducting, and the leakage current through N1 is discharged through "N1 → N5 → GND". P2, P1, and N2 remain fully turned off because the gate potential does not meet the conduction condition, and the input and output are completely isolated, and the negative overvoltage is clamped at GND - V THN .

[0032] When the input channel circuit is activated and an overvoltage spike / injected current occurs, the control terminal state of the activated channel is CPn=GND, CNn=VDD. When the input signal Sn experiences an overvoltage, the circuit activates graded protection while ensuring signal transmission: When Sn is a positive overvoltage, the gate-source voltage (VDD-Sn) of P5 is less than the threshold voltage, and P5 is turned on; since CNn=VDD, the gate of N4 is connected to CNn=VDD through R9, and N4 is turned on. Most of the overvoltage current transmitted through P5 is discharged through "P5→N4→GND", with only a small residual voltage acting on the gate of N3. When Sn is large enough, N3 is partially turned on (VGS is not at full bias), shunting part of the overvoltage current to GND. P3 and P4 are turned on synchronously, clamping the gate potential of N5 at the intermediate value V between CPn (GND) and Sn. GN5 V GN5 -GND > N5's threshold voltage, so N5 is partially turned on, further shunting the small amount of abnormal current passing through the transfer switch. The gate of P2 in the unselected channel is connected to CPn = VDD, and the gate-source voltage (VDD - Sn) < the threshold voltage, so P2 is partially turned on; and the gate of N5 in the unselected channel is connected to VDD, making it fully turned on, forming a supplementary discharge path of "selected channel → output terminal → unselected channel P2 → unselected channel N5 → GND", further reducing the intensity of the abnormal current. Most of the abnormal current is shunted, clamping the overvoltage Sn at VDD + |V THP5 At this time, all MOSFETs of the transmission switch remain in the conducting state, and the remaining normal amplitude signal is transmitted to the output terminal through the conducting P1, P2, N1, and N2 to achieve "protection without interruption of transmission" and at the same time avoid transmitting overvoltage to the subsequent circuit and causing damage to the subsequent circuit.

[0033] When the system power supply is not on (VDD=0V) and voltage Sn is applied to the input terminal, the circuit achieves input and output isolation through passive discharge:

[0034] The gate of P5 is connected to VDD = 0V through R1, and the source is connected to Sn. When Sn is at a positive voltage, the gate-source voltage of P5 (0V - Sn) < the threshold voltage of P5, and P5 conducts. Sn is transmitted to the gate of N3 through P5. The gate-source voltage of N3 > the threshold voltage of N3, and N3 conducts fully, forming a passive discharge loop of "Sn → N3 → GND" to quickly conduct away the input current. The gates of P3 and P4 are connected to VDD = 0V. Since Sn is at a positive voltage, the gate-source voltages of P3 and P4 (0V - Sn) < the threshold voltages and they conduct. Sn is transmitted to the gates of P1 and P2 through P3 and P4, making the gate potentials of P1 and P2 equal to Sn. P1 and P2 are PMOS transistors, and the gate and source potentials are close (VGS ≈ 0V), not meeting the conduction condition, so P1 and P2 remain off. All transmission switches are in the off state. The input voltage Sn is only discharged to the ground through the discharge loop, and there is only a very low capacitive coupling voltage (negligible) with the output terminal, achieving input-output isolation in the power-off state, without the need to limit the external power-on timing sequence, and avoiding damage to the subsequent circuit due to input voltage interference.

[0035] This circuit accurately identifies signal abnormalities through MOS transistor threshold triggering detection, uses "multiple ground discharge paths (front-end N3 / P5, central N5, output N7)" to direct abnormal current to the ground, avoiding impact on the power supply VDD, achieving interference isolation for unselected channels, and ensuring normal signal transmission for selected channels; it supports the circuit to process input voltage when the power supply is not powered on, achieving power-off isolation. Overall, it achieves the four major goals of "interference suppression, signal fidelity, device protection, and mode controllability", perfectly adapting to the high reliability requirements of precision signal links.

[0036] In summary, through the collaborative design of N parallel input channel circuits and the output terminal detection and discharge circuit, the present invention can not only quickly export the overvoltage spikes or injected currents of unselected channels through the ground discharge loop, avoiding affecting the signal accuracy of selected channels and other devices on the power supply rail, but also clamp the voltage and shunt part of the current when abnormalities occur in selected channels, preventing abnormal signals from damaging the subsequent circuit. At the same time, it supports power-off isolation protection when the power supply is not powered on, minimizing the power transmission and voltage coupling between input and output, without strictly restricting the external power-on timing sequence, significantly improving the accuracy and reliability of precision signal transmission, and enhancing the working stability and application scenario adaptability of devices and systems.

[0037] Although the embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An analog multiplexer interference suppression and protection circuit for precision signal links, characterized in that, include: N input channel circuits, and output detection and discharge circuits; The N input channel circuits are arranged in parallel to receive multiple input signals and realize the gating and transmission of a single signal, while monitoring the abnormal state of the input signal and discharging the abnormal input signal. The output detection and discharge circuit is used to monitor abnormal states of the output signal and discharge abnormal output signals. The output detection and discharge circuit includes resistors R11-R16, NMOS transistors N6-N7, and PMOS transistor P6. One end of resistor R11, the source of P6, and one end of resistor R12 are connected to the outputs of the N input channel circuits. The other end of resistor R11 and the drain of N7 serve as the output of the multiplexer. The other end of resistor R12 is connected to the substrate of P6. The gate of P6 is connected to one end of resistor R13. The other end of resistor R13 is connected to the power supply VDD. The drain of P6 is connected to one end of resistor R14. The other end of resistor R14, the drain of N6, the gate of N7, and one end of resistor R16 are connected. The substrate, source, and the other end of resistor R16 of N7 are grounded. The substrate and source of N6 are grounded. The gate of N6 is connected to one end of resistor R15. The other end of resistor R15 is connected to the enable signal terminal EN.

2. The analog multiplexer interference suppression and protection circuit for precision signal links according to claim 1, characterized in that, Each of the input channel circuits includes: an input terminal detection circuit, an input terminal bleed circuit, a transmission switch circuit, and a central bleed circuit; The input detection circuit is used to monitor the abnormal state of the input signal of the corresponding input channel circuit in real time and output a trigger signal; The input discharge circuit is connected to the input detection circuit and is used to discharge abnormal current at the input port in response to the first trigger signal. The transmission switch circuit is connected to the input bleeder circuit, receives the input signal from the input channel circuit and the control signal from the decoder, and regulates the conduction and cutoff of the input channel circuit to realize signal transmission. The central discharge circuit is connected to the transmission switch circuit to protect the input signal and discharge abnormal charges.

3. The analog multiplexer interference suppression and protection circuit for precision signal links according to claim 2, characterized in that, Each input channel circuit includes: NMOS transistors N1~N5, NMOS transistors P1~P5, and resistors R1~R10. In each input channel circuit, one end of resistor R1 is connected to the power supply VDD; the other end of resistor R1 is connected to the gate of P3, the gate of P4, and the gate of P5; one end of resistor R4 and the drain of N3 are connected to the input signal Sn; Sn represents the input signal of the nth input channel circuit, where n is a positive integer from 1 to N; the other end of resistor R4, one end of resistor R5, the source of P1, the drain of P4, the source of P5, and the source of N1 are connected; the source of P4 and the drain of P3 are connected; the source of P3, the substrate of P3, and one end of resistor R2 are connected; the substrates of P4 and P5, one end of resistor R5, and the substrate of P1 are connected; the substrate of N3, the source of N3, and one end of resistor R7 are grounded; the gate of N3 and the other end of resistor R7 are connected to the ground. One end of resistor R8 is connected to the drain of N4; the other end of resistor R8 is connected to the drain of P5; the substrate and source of N4 are grounded; the gate of N4 is connected to one end of resistor R9; the other end of resistor R9, the gate of N1, one end of resistor R10, and the gate of N2 are connected; the other end of resistor R10 is connected to the second control terminal CNn of the input channel circuit; the other end of resistor R2, the gate of P1, the gate of N5, the gate of P2, and one end of resistor R3 are connected; the other end of resistor R3 is connected to the first control terminal CPn of the input channel circuit; the drains of P1, N1, N5, P2, and N2 are connected; the source and substrate of N5 are grounded; the substrates of N1 and N2 are grounded; the substrate of P2 is connected to one end of resistor R6; the source of P2, the other end of resistor R6, and the source of N2 are connected to the output terminal of the input channel circuit.

4. The analog multiplexer interference suppression and protection circuit for precision signal links according to claim 3, characterized in that, The on / off state of the input channel circuit is controlled by adjusting the input signals of the first control terminal CPn and the second control terminal CNn. CPn represents the first control terminal of the nth input channel circuit; CNn represents the second control terminal of the nth input channel circuit; when the nth input channel circuit is selected, the first control terminal CPn of the nth input channel circuit is grounded, and the second control terminal CNn of the nth input channel circuit is connected to the VDD potential; when the nth input channel circuit is not selected, the first control terminal CPn of the nth input channel circuit is connected to the VDD potential, and the second control terminal CNn of the nth input channel circuit is grounded.

5. The analog multiplexer interference suppression and protection circuit for precision signal links according to claim 3, characterized in that, At any given time, at most one of the N input channel circuits can be in the selected state.

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