Phase-locked loop circuit, phase locking method and frequency synthesizer

Abstract

The invention discloses a phase-locked loop circuit, a phase locking method and a frequency synthesizer, and the phase-locked loop circuit employs a phase rolling clock signal generation unit to carry out integer frequency division processing on a plurality of oscillation clock signals with uniformly-changed phases, obtains a plurality of feedback clock signals with uniformly-changed phases, and carries out frequency division processing on the feedback clock signals according to a preset clock period. The feedback clock signals with the corresponding phase sequence are selected from the multiple feedback clock signals with the uniformly-changed phases to be spliced, the phase rolling clock signal is generated, and the N-fractional frequency division phase-locked loop can be achieved, and compared with the mode that an SDM circuit is used for achieving the N-fractional frequency division phase-locked loop, the N-fractional frequency division phase-locked loop can be achieved more accurately. The occupied area and power consumption of the circuit are saved, and the performance of the phase-locked loop circuit is improved.

Description

Phase-locked loop circuits, phase-locked methods, and frequency synthesizers Technical Field

[0001] The embodiments of the present invention relate to the field of circuit technology, and in particular to a phase-locked loop circuit, a phase-locked method, and a frequency synthesizer. Background Technology

[0002] In the field of wireless communication, frequency synthesizers based on phase-locked loop (PLL) structures are widely used to generate oscillation signals. Among them, fractional-N PLL circuits are used in many clocks due to their flexibility in frequency planning.

[0003] The digital Σ-Δ modulator (SDM) is one of the main components of a fractional-N division multiplexing (PLL). The SDM circuit provides the PLL with the flexibility of a fractional multiplication factor and the advantage of noise shaping by jittering the PLL feedback divider value.

[0004] However, SDM circuits have the problems of large circuit area and high power consumption, which affect the area and power consumption of fractional N frequency divider PLL circuits. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a phase-locked loop circuit, a phase-locked method, and a frequency synthesizer, so as to save the area and power consumption of the phase-locked loop circuit while realizing a fractional N-fold frequency division phase-locked loop.

[0006] To address the above problems, embodiments of the present invention provide a phase-locked loop circuit, comprising:

[0007] The phase detection unit is adapted to receive an external reference clock signal and a phase rolling clock signal; when the phase of the phase rolling clock signal leads the external reference clock signal, it generates a fall control signal; when the phase of the phase rolling clock signal lags the external reference clock signal, it generates a rise control signal.

[0008] The loop filter unit is adapted to reduce the voltage value of the control voltage signal when receiving the decreasing control signal, and to increase the voltage value of the control voltage signal when receiving the increasing control signal.

[0009] The voltage-controlled oscillator unit is adapted to generate multiple oscillation clock signals with uniformly changing phases according to the voltage value of the control voltage signal;

[0010] The phase rolling clock signal generation unit is adapted to perform integer frequency division processing on the multiple oscillating clock signals with uniformly changing phases to obtain multiple feedback clock signals with uniformly changing phases; sort the multiple feedback clock signals with uniformly changing phases according to phase order to obtain the phase position order of the multiple feedback clock signals with uniformly changing phases; and select feedback clock signals with corresponding phase positions from the multiple feedback clock signals with uniformly changing phases according to a preset clock period and splice them to generate the phase rolling clock signal.

[0011] Optionally, the target frequency of the oscillation clock signal satisfies:

[0012]

[0013] Among them, f VCO_CLK f represents the target frequency of the oscillation clock signal. REF_CLK The frequency of the external reference clock signal is represented by M, the integer division coefficient related to the target frequency of the oscillation clock signal is represented by X, the fractional division coefficient related to the target frequency of the oscillation clock signal is represented by X, and X is a positive integer greater than zero and less than or equal to (N-1), and N represents the number of the plurality of feedback clock signals with uniformly changing phases.

[0014] Optionally, the phase rolling clock signal generation unit includes:

[0015] The frequency division processing module is adapted to receive a corresponding integer frequency division coefficient and N oscillating clock signals with uniformly changing phases; and to perform frequency division processing on the N oscillating clock signals with uniformly changing phases using the corresponding integer frequency division coefficients to obtain N feedback clock signals with uniformly changing phases.

[0016] The phase alignment module is suitable for sorting N feedback clock signals with uniformly changing phases according to their phase order to obtain the phase order of the N feedback clock signals with uniformly changing phases; it is also suitable for performing N OR-NOT operations on the N feedback clock signals with uniformly changing phases to generate a phase rolling control signal.

[0017] The logic control module is adapted to generate a phase selection control signal based on a preset correspondence between the clock periods of the phase rolling control signal and the phase rolling clock signal and the phase order of the N uniformly changing feedback clock signals; it is also adapted to generate a corresponding integer frequency division coefficient based on a preset condition satisfied by the clock periods of the phase rolling control signal and the phase rolling clock signal.

[0018] The phase rolling module is adapted to receive the phase rolling control signal and N feedback clock signals with uniformly changing phases; according to the phase selection control signal, it selects feedback clock signals with corresponding phase order from the N feedback clock signals with uniformly changing phases in each clock cycle of the phase rolling clock signal and splices them to generate the phase rolling clock signal.

[0019] Optionally, the frequency division processing module includes N frequency dividers, each corresponding to one of the N oscillating clock signals with uniformly changing phases.

[0020] The frequency divider is adapted to receive the corresponding integer frequency division coefficient and the corresponding oscillation clock signal from N oscillation clock signals with uniformly changing phases; and to perform frequency division processing on the corresponding oscillation clock signal from the N oscillation clock signals with uniformly changing phases using the corresponding integer frequency division coefficient to obtain the corresponding feedback clock signal.

[0021] Optionally, the phase alignment module includes:

[0022] The sampling processing submodule is adapted to use the feedback clock signal output by the frequency divider of the 0th bit sequence to sample the feedback clock signals output by the frequency dividers of the 1st to (N-1)th bit sequences respectively, and obtain the corresponding sampled signals.

[0023] The sorting processing submodule is adapted to obtain the phase order of N feedback clock signals with uniformly changing phases based on the sampled signal;

[0024] The logic operation submodule is adapted to perform N OR NOT logic operations on the N uniformly phased feedback clock signals to obtain the phase rolling control signal.

[0025] Optionally, the sorting submodule is adapted to obtain the phase order of N uniformly phase-changing feedback clock signals based on the sampled signal using the following formula:

[0026]

[0027] Among them, CLK_PHASE FB_CLK represents the feedback clock signal with phase order p when N uniformly phased feedback clock signals are arranged in ascending order according to their phase order.<p+Y> FB_CLK represents the feedback clock signal output by the frequency divider at the (p+Y)th bit position.<p+Y> The feedback clock signal output by the frequency divider at the (p+YN)th bit position is represented, where Y represents the number of second sample values ​​in the sampled signal, and Y is an integer greater than or equal to 0 and less than or equal to (N-1).

[0028] Optionally, the second sample value is 1.

[0029] Optionally, the logic control module includes:

[0030] The first control submodule is adapted to generate a phase selection control signal based on a preset correspondence between the clock period of the phase rolling control signal and the phase rolling clock signal and the phase order of the N uniformly changing feedback clock signals.

[0031] The second control submodule is adapted to generate corresponding modulation values ​​based on preset conditions satisfied by the clock periods of the phase rolling control signal and the phase rolling clock signal.

[0032] The adder operation submodule is adapted to calculate the sum of the corresponding modulation value and the integer frequency division coefficient related to the target frequency of the oscillation clock signal, and obtain the corresponding integer frequency division coefficient.

[0033] Optionally, the first control submodule is adapted to obtain the phase sequence of the feedback clock signal output by the phase rolling module for each clock period of the phase rolling clock signal according to a preset correspondence between the clock period of the phase rolling clock signal and the phase sequence of the N uniformly phase-changing feedback clock signals; and output the corresponding phase sequence of the feedback clock signal as the phase selection control signal when the phase rolling control signal has a first logic level according to a preset clock period.

[0034] The preset correspondence between the clock period of the phase rolling clock signal and the phase order of the N uniformly phase-changing feedback clock signals satisfies the following:

[0035]

[0036] and:

[0037]

[0038] Where k represents the phase sequence of the feedback clock signal output by the phase rolling module in the l-th clock cycle of the phase rolling clock signal, and j l represents the carry count value of the integer frequency division coefficient related to the target frequency of the oscillation clock signal in the l-th clock cycle of the phase rolling clock signal, and j l-1 represents the carry count value of the integer frequency division coefficient M related to the target frequency of the oscillation clock signal in the (l - 1)-th clock cycle of the phase rolling clock signal.

[0039] Optionally, the second control sub-module is adapted to generate a first modulation value when the phase rolling control signal has a first logic level and the preset condition satisfied by the clock cycle of the phase rolling clock signal is 0 ≤ l*X < N; when the phase rolling control signal has a first logic level and the preset condition satisfied by the clock cycle of the phase rolling clock signal is l*X - j l-1 *N ≥ N, generate a second modulation value;

[0040] The adder operation sub-module is adapted to, when receiving the first modulation value, obtain the sum of the integer frequency division coefficient related to the target frequency of the oscillation clock signal and the first modulation value as the corresponding integer frequency division coefficient; when receiving the second modulation value, obtain the sum of the integer frequency division coefficient related to the target frequency of the oscillation clock signal and the second modulation value as the corresponding integer frequency division coefficient.

[0041] Optionally, the first modulation value is 0 and the second modulation value is 1.

[0042] Optionally, the first logic level is a low level.

[0043] Correspondingly, an embodiment of the present invention further provides a phase-locked method, including:

[0044] Using a phase detection unit to receive an external reference clock signal and a phase rolling clock signal; generating a descending control signal when the phase of the phase rolling clock signal is ahead of the external reference clock signal; generating an ascending control signal when the phase of the phase rolling clock signal is behind the external reference clock signal;

[0045] Using a loop filter unit to reduce the voltage value of the control voltage signal when receiving the descending control signal; increasing the voltage value of the control voltage signal when receiving the ascending control signal;

[0046] Using a voltage-controlled oscillator unit to generate a plurality of oscillation clock signals with uniformly changing phases according to the voltage value of the control voltage signal;

[0047] A phase rolling clock signal generation unit performs integer frequency division processing on the multiple oscillating clock signals with uniformly changing phases to obtain multiple feedback clock signals with uniformly changing phases. The multiple feedback clock signals with uniformly changing phases are sorted according to phase order to obtain the phase position order of the multiple feedback clock signals with uniformly changing phases. According to the clock period of the feedback clock signals, the feedback clock signals with corresponding phase positions are selected from the multiple feedback clock signals with uniformly changing phases and spliced ​​together to generate the phase rolling clock signal.

[0048] Accordingly, embodiments of the present invention also provide a frequency synthesizer, including a phase-locked loop circuit as described in any of the preceding claims.

[0049] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0050] The phase-locked loop circuit provided in this embodiment of the invention includes: a phase detection unit, adapted to receive an external reference clock signal and a phase rolling clock signal; generating a falling control signal when the phase of the phase rolling clock signal leads the external reference clock signal; generating a boost control signal when the phase of the phase rolling clock signal lags the external reference clock signal; a loop filtering unit, adapted to reduce the voltage value of the control voltage signal when the falling control signal is received; and increasing the voltage value of the control voltage signal when the boost control signal is received; a voltage-controlled oscillator unit, adapted to generate multiple oscillating clock signals with uniformly changing phases according to the voltage value of the control voltage signal; and a phase rolling clock signal generation unit, adapted to perform integer frequency division processing on the multiple oscillating clock signals with uniformly changing phases respectively to obtain multiple feedback clock signals with uniformly changing phases; sorting the multiple feedback clock signals with uniformly changing phases according to phase order to obtain the phase position order of the multiple feedback clock signals with uniformly changing phases; and selecting feedback clock signals with corresponding phase positions from the multiple feedback clock signals with uniformly changing phases according to a preset clock period and splicing them together to generate the phase rolling clock signal.

[0051] In the phase-locked loop circuit provided in this embodiment of the invention, a phase rolling clock signal generation unit performs integer frequency division processing on multiple oscillating clock signals with uniformly changing phases to obtain multiple feedback clock signals with uniformly changing phases. Then, according to a preset clock period, feedback clock signals with corresponding phase order are selected from the multiple feedback clock signals with uniformly changing phases and spliced ​​together to generate the phase rolling clock signal. This can realize a fractional N-fold frequency division phase-locked loop. Compared with the method of using SDM circuit to realize fractional N-fold frequency division phase-locked loop, it is beneficial to improve the saving of circuit area and power consumption, and improve the performance of the phase-locked loop circuit. Attached Figure Description

[0052] Figure 1 is a schematic diagram of an embodiment of the phase-locked loop circuit provided by the technical solution of the present invention;

[0053] Figure 2 is a schematic diagram of an embodiment of the phase rolling clock signal generation unit in the technical solution of the present invention;

[0054] Figure 3 is a schematic diagram of the structure of an embodiment of the frequency division processing module in the technical solution of the present invention;

[0055] Figure 4 is a structural schematic diagram of an embodiment of the phase alignment module in the technical solution of the present invention;

[0056] Figure 5 is a structural schematic diagram of an embodiment of the logic control module in the technical solution of the present invention;

[0057] Figure 6 is a schematic diagram of the relevant signals when the target frequency of the oscillation clock signal output by the phase-locked loop circuit in the technical solution of the present invention is 5GHz;

[0058] Figure 7 is a schematic diagram of the relevant signals when the target frequency of the oscillation clock signal output by the phase-locked loop circuit in the technical solution of the present invention is 4GHz;

[0059] Figure 8 is a flowchart illustrating an embodiment of the phase-locked loop method provided by the technical solution of the present invention. Detailed Implementation

[0060] As can be seen from the background technology, the current fractional N-fold frequency-locked loop has the problems of large circuit area and high power consumption.

[0061] To address the aforementioned technical problem, the phase-locked loop circuit provided in this embodiment of the invention includes: a phase detection unit, adapted to receive an external reference clock signal and a phase rolling clock signal; generating a falling control signal when the phase of the phase rolling clock signal leads the external reference clock signal; generating a boost control signal when the phase of the phase rolling clock signal lags the external reference clock signal; a loop filtering unit, adapted to reduce the voltage value of the control voltage signal when the falling control signal is received; and increasing the voltage value of the control voltage signal when the boost control signal is received; a voltage-controlled oscillator unit, adapted to generate multiple oscillating clock signals with uniformly changing phases according to the voltage value of the control voltage signal; and a phase rolling clock signal generation unit, adapted to perform integer frequency division processing on the multiple oscillating clock signals with uniformly changing phases respectively to obtain multiple feedback clock signals with uniformly changing phases; sorting the multiple feedback clock signals with uniformly changing phases according to phase order to obtain the phase position order of the multiple feedback clock signals with uniformly changing phases; and selecting feedback clock signals with corresponding phase positions from the multiple feedback clock signals with uniformly changing phases according to a preset clock period and splicing them together to generate the phase rolling clock signal.

[0062] In the phase-locked loop circuit provided in this embodiment of the invention, a phase rolling clock signal generation unit performs integer frequency division processing on multiple oscillating clock signals with uniformly changing phases to obtain multiple feedback clock signals with uniformly changing phases. Then, according to a preset clock period, feedback clock signals with corresponding phase order are selected from the multiple feedback clock signals with uniformly changing phases and spliced ​​together to generate the phase rolling clock signal. This can realize a fractional N-fold frequency division phase-locked loop. Compared with the method of using SDM circuit to realize fractional N-fold frequency division phase-locked loop, it is beneficial to improve the saving of circuit area and power consumption, and improve the performance of the phase-locked loop circuit.

[0063] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0064] Figure 1 shows a schematic diagram of an embodiment of the phase-locked loop circuit provided by the present invention. Referring to Figure 1, a phase-locked loop circuit can be used to include a phase detection unit 10, a loop filter unit 30, a voltage-controlled oscillator unit 50, and a phase rolling clock signal generation unit 70. The phase detection unit 10 is coupled to both the loop filter unit 30 and the phase rolling clock signal generation unit 70, and the loop filter unit 30 is also coupled to the voltage-controlled oscillator unit 50.

[0065] In this embodiment, the phase detection unit 10 has a reference signal input terminal, a feedback signal input terminal, a fall control signal output terminal, and a rise control signal output terminal. Specifically, the reference signal input terminal of the phase detection unit 10 receives an external reference clock signal REF_CLK; the feedback signal input terminal receives a phase rolling clock signal PHASE_WHIRL_CLK; the fall control signal output terminal is coupled to the loop filter unit 30 and outputs a fall control signal DW; and the rise signal output terminal is coupled to the loop filter unit 30 and outputs a rise control signal UP. The phase detection unit 10 can be used to receive an external reference clock signal REF_CLK and a phase rolling clock signal PHASE_WHIRL_CLK; when the phase of the phase rolling clock signal PHASE_WHIRL_CLK leads the external reference clock signal REF_CLK, a fall control signal DW is generated; when the phase of the phase rolling clock signal PHASE_WHIRL_CLK lags the external reference clock signal REF_CLK, a boost control signal UP is generated.

[0066] In this embodiment, the phase detection unit 10 is a phase frequency detector (PFD) and a charge pump. In other embodiments, the phase detection unit can also be implemented using other structures with the same function, and no limitation is made here.

[0067] In this embodiment, the loop filter unit 30 has a falling control signal input terminal, a rising control signal input terminal, and a control voltage signal output terminal. The falling control signal input terminal of the loop filter unit 30 is coupled to the falling control signal output terminal of the phase detection unit 10 and is used to receive the falling control signal DW. The rising control signal input terminal of the loop filter unit 30 is coupled to the rising control signal output terminal of the phase detection unit 10 and is used to receive the rising control signal UP. The control voltage signal output terminal of the loop filter unit 30 is coupled to the voltage-controlled oscillator unit 50. The loop filter unit 30 can be used to reduce the voltage value of the control voltage signal when receiving the falling control signal DW, and to increase the voltage value of the control voltage signal when receiving the rising control signal UP.

[0068] In this embodiment, the loop filtering unit 30 is a low-pass loop filter. It can be understood that the loop filtering unit can also be implemented using other structures with the same function; those skilled in the art can select according to actual needs, and no limitations are imposed here.

[0069] In this embodiment, the voltage-controlled oscillator unit 50 has a control voltage input terminal and N oscillation clock signal output terminals. The control voltage input terminal of the voltage-controlled oscillator unit 50 is coupled to the control voltage output terminal of the loop filter unit 30 and is used to receive the control voltage signal. The multiple oscillation clock signal output terminals of the voltage-controlled oscillator unit 50 are respectively coupled to the phase rolling clock signal generation unit 70 and are used to output multiple oscillation clock signals VCO_CLK with uniformly changing phases. <0> ~VCO_CLK <n-1>The voltage-controlled oscillator unit 50 can be used to generate multiple oscillation clock signals VCO_CLK with uniformly changing phases based on the voltage value of the control voltage signal. <0> ~VCO_CLK <n-1>.

[0070] In this embodiment, multiple oscillating clock signals VCO_CLK with uniformly changing phases are used. <0> ~VCO_CLK <n-1>The quantity is N, where N is a positive integer greater than or equal to 2. Among them, multiple oscillating clock signals VCO_CLK with uniformly varying phases. <0> ~VCO_CLK <n-1>The periods are the same, denoted as T. Furthermore, multiple oscillating clock signals VCO_CLK with uniformly varying phases... <0> ~VCO_CLK <n-1>Mid-phase adjacent oscillation clock signals VCO_CLK< / n-1> VCO_CLK<P+1> The phase difference between them is Where P is an integer greater than or equal to 0 and less than or equal to N-2.

[0071] In this embodiment, the phase rolling clock signal generation unit 70 has N oscillation clock signal input terminals and feedback signal output terminals. The N oscillation clock signal input terminals of the phase rolling clock signal generation unit 70 are respectively coupled to the N oscillation clock signal output terminals of the voltage-controlled oscillator unit 50, and are used to receive the N oscillation clock signals VCO_CLK with uniformly changing phases. <0> ~VCO_CLK <n-1>The feedback signal output terminal of the phase rolling clock signal generation unit 70 is coupled to the feedback signal input terminal of the phase detection unit 10, and is used to output the phase rolling clock signal PHASE_WHIRL_CLK. The phase rolling clock signal generation unit 70 can be used to generate the N uniformly phased oscillation clock signals VCO_CLK. <0> ~VCO_CLK <n-1>Perform integer frequency division processing to obtain N feedback clock signals FB_CLK with uniform phase changes. <0> ~FB_CLK <n-1>The feedback clock signal FB_CLK with N phases uniformly varied. <0> ~FB_CLK <n-1>Sort the signals according to phase order to obtain N feedback clock signals FB_CLK with uniform phase changes. <0> ~FB_CLK <n-1>The phase sequence; according to a preset clock period, the N feedback clock signals FB_CLK with uniformly changing phases are respectively... <0> ~FB_CLK <n-1>Select the feedback clock signal CLK_PHASE with the corresponding phase position k. <k>The phase rolling clock signal PHASE_WHIRL_CLK is generated by splicing the signals together. Here, k is an integer greater than or equal to 0 and less than or equal to N-1.

[0072] In this embodiment, the N oscillating clock signals VCO_CLK with uniformly changing phases <0> ~VCO_CLK <n-1>The target frequency satisfies the following formula:

[0073]

[0074] Among them, f VCO_CLK VCO_CLK represents the N oscillating clock signals with uniformly changing phases. <0> ~VCO_CLK <n-1>Target frequency, f REF_CLK M represents the frequency of the external reference clock signal REF_CLK, and M represents the oscillation clock signal VCO_CLK that varies uniformly with the N phases. <0> ~VCO_CLK <n-1>The integer frequency division coefficient related to the target frequency, X represents the oscillation clock signal VCO_CLK that changes uniformly with the N phases. <0> ~VCO_CLK <n-1>The numerator of the fractional frequency division coefficient related to the target frequency is X, where X is a positive integer greater than zero and less than or equal to (N-1).

[0075] According to the above formula (1), when X is an integer greater than zero and less than or equal to (N-1), the N oscillating clock signals VCO_CLK with uniformly changing phases <0> ~VCO_CLK <n-1>Target frequency f VCO_CLK The frequency f of the external reference clock signal REF_CLK of In other words, when X is an integer greater than zero and less than or equal to (N-1), the phase-locked loop circuit provided in this embodiment of the invention is a fractional N frequency-division phase-locked loop circuit.

[0076] Referring to Figure 2, in this embodiment, the phase-locked loop circuit is a fractional-N frequency-division phase-locked loop circuit, that is, the N oscillation clock signals VCO_CLK with uniformly changing phases. <0> ~VCO_CLK <n-1>Target frequency f VCO_CLK The frequency f of the external reference clock signal REF_CLK of In the case of multiples, the phase rolling clock signal generation unit 70 may include a frequency division processing module 701, a phase alignment module 702, a logic control module 703, and a phase rolling module 704.

[0077] The frequency division processing module 701 has an integer frequency division coefficient input terminal, N oscillation clock signal input terminals, and N feedback clock signal output terminals. The integer frequency division coefficient input terminal of the frequency division processing module 701 is coupled to the logic control module 703, and the N oscillation clock signal input terminals of the frequency division processing module 701 are respectively coupled to the N oscillation clock signal output terminals of the voltage-controlled oscillator unit 50, and are used to receive the N oscillation clock signals VCO_CLK with uniformly changing phases. <0> ~VCO_CLK <n-1>The N feedback clock signal output terminals of the frequency division processing module 701 are coupled to the N feedback clock signal input terminals of the phase alignment module 702, and are used to output the N feedback clock signals FB_CLK with uniformly changing phases. <0> ~FB_CLK <n-1>The frequency division processing module 701 can be used to receive the corresponding integer frequency division coefficients and the N uniformly phased oscillation clock signals VCO_CLK. <0> ~VCO_CLK <n-1>The N oscillating clock signals VCO_CLK with uniformly varying phases are divided by corresponding integer frequency division coefficients. <0> ~VCO_CLK <n-1>Each signal is divided into N uniformly phased feedback clock signals FB_CLK. <0> ~FB_CLK <n-1>.

[0078] Referring to Figure 3, in this embodiment, the frequency division processing module 701 includes N oscillating clock signals VCO_CLK with uniformly changing phases. <0> ~VCO_CLK <n-1>N frequency dividers 701 configured in a one-to-one correspondence <0> ~701 <n-1>.

[0079] In other embodiments, the frequency division processing module can also be implemented using other structures with the same function, and no limitation is made here.

[0080] In this embodiment, the corresponding integer frequency division coefficient is (M+0) or (M+1), specifically determined by the logic control module 703 based on the bit order 1 of the period of the phase rolling clock signal PHASE_WHIRL_CLK and the feedback clock signal CLK_PHASE. <k>The correspondence between the phase position sequence k is generated, which will be explained in detail in the logic control module 703 later.

[0081] The phase alignment module 702 has N feedback clock signal input terminals, N phase sequence output terminals, and a phase rolling control signal output terminal. The N feedback clock signal input terminals of the phase alignment module 702 are coupled to the N feedback clock signal output terminals of the frequency division processing module 701, and are used to receive the N uniformly phase-changing feedback clock signals FB_CLK. <0> ~FB_CLK <n-1>The N phase sequence output terminals of the phase alignment module 702 are coupled to the phase rolling module 704 and are used to output the N phase-uniformly changing feedback clock signals FB_CLK. <0> ~FB_CLK <n-1>The phase alignment module 702, whose phase rolling control signal output is coupled to the logic operation module 703, is used to output the phase rolling control signal PW_CLK. The phase alignment module 702 can be used to convert N uniformly phased feedback clock signals FB_CLK... <0> ~FB_CLK <n-1>Sort the signals according to phase order to obtain N feedback clock signals FB_CLK with uniform phase changes. <0> ~FB_CLK <n-1>The phase sequence; it can also be used to generate N feedback clock signals FB_CLK with uniformly varying phases. <0> ~FB_CLK <n-1>Perform an OR operation to generate the phase rollover control signal PW_CLK. Wherein, CLK_PHASE... <0> CLK_PHASE represents the feedback clock signal with a phase sequence of 0. <1> This represents the feedback clock signal with a phase bit sequence of 1, ..., CLK_PHASE <n-1>This represents a feedback clock signal with a phase sequence of (N-1).

[0082] Referring to Figure 4, in this embodiment, the phase alignment module 702 includes a sampling processing submodule 7021, a sorting processing submodule 7022, and a logic operation submodule 7023.

[0083] The sampling processing submodule 7021 has N feedback clock signal input terminals and (N-1) sample value output terminals. Specifically, the N signal input terminals of the sampling processing submodule 7021 are used to receive N feedback clock signals FB_CLK with uniformly changing phases. <0> ~FB_CLK <n-1>The sampling processing submodule 7021 has (N-1) sample value output terminals used to output corresponding sampled signals. The sampling processing submodule 7021 can be used with a frequency divider 701 employing the 0th bit order. <0> The output feedback clock signal FB_CLK <0> Frequency divider 701 for bit sequence 1 to (N-1)th bit sequence <0> ~701 <n-1>The output feedback clock signal FB_CLK <1> ~FB_CLK <n-1>Sampling processing is performed separately to obtain the corresponding sampled signal CAL. <1> ~CAL <n-1>.

[0084] The sorting processing submodule 7022 has (N-1) sample value input terminals and N signal output terminals. The (N-1) sample value input terminals of the sorting processing submodule 7022 are coupled to the (N-1) sample value output terminals of the sampling processing submodule 7021, and are used to receive the corresponding sampled signals CAL. <1> ~CAL <n-1>The N signal output terminals of the sorting processing submodule 7022 are respectively used to output N feedback clock signals FB_CLK with uniform phase changes from the frequency divider output of the zeroth to (N-1)th position. <0> ~FB_CLK <n-1>The phase order. The sorting processing submodule 7022 can determine the phase order based on the sampled signal FB_CLK. <0> ~FB_CLK <n-1>Obtain N feedback clock signals FB_CLK with uniform phase changes. <0> ~FB_CLK <n-1>The phase order.

[0085] Specifically, the sorting processing submodule 7022 can be used to obtain the phase order of N uniformly phase-changing feedback clock signals according to the sampled signal using the following formula:

[0086]

[0087] Among them, CLK_PHASE < / k> < / k> FB_CLK represents the feedback clock signal with phase order p when N uniformly phased feedback clock signals are arranged in ascending order according to their phase order.<p+Y> FB_CLK represents the feedback clock signal output by the frequency divider at the (p+Y)th bit position.<p+Y> The feedback clock signal output by the frequency divider at the (p+YN)th bit position is represented, where Y represents the number of second sample values ​​in the sampled signal, and Y is an integer greater than or equal to 0 and less than or equal to (N-1).

[0088] In this embodiment, the second sample value is 1.

[0089] In this embodiment, the logic operation submodule 7023 has N feedback clock signal input terminals and a phase rolling control signal output terminal. The N feedback clock signal input terminals of the logic operation submodule 7023 are used to receive N feedback clock signals FB_CLK with uniformly changing phases. <0> ~FB_CLK <n-1>The phase rolling control signal output terminal of the logic operation submodule 7023 is coupled to the logic control module and is used to output the phase rolling control signal PW_CLK. The logic operation submodule 7023 can be used to process the N uniformly phased feedback clock signals FB_CLK. <0> ~FB_CLK <n-1>Perform NOR logic operations to obtain the phase rolling control signal PW_CLK.

[0090] In this embodiment, the logic operation submodule 7023 is a NOR gate. In other embodiments, the logic operation submodule can also be implemented using other structures with the same function, which are not limited here.

[0091] The logic control module 703 has a phase rolling control signal input terminal, a phase rolling control signal output terminal, and an integer frequency division coefficient output terminal. Specifically, the phase rolling control signal input terminal of the logic control module 703 is coupled to the phase rolling control signal output terminal of the phase alignment module 702 and is used to receive the phase rolling control signal PW_CLK. The phase rolling control signal output terminal of the logic control module 703 is coupled to the phase rolling module 704 and is used to output the phase rolling control signal PW_CLK. The integer frequency division coefficient output terminal of the logic control module 703 is coupled to the frequency division processing module 701 and is used to output the corresponding integer frequency division coefficient. The logic control module 703 can be used to adjust the clock period of the phase rolling control signal PW_CLK and the phase rolling clock signal PHASE_WHIRL_CLK according to the feedback clock signal FB_CLK, which has N phases that change uniformly. <0> ~FB_CLK <n-1>The preset correspondence between the phase positions generates a phase selection control signal; it can also be used to generate corresponding integer frequency division coefficients based on the preset conditions satisfied by the clock periods of the phase rolling control signal PW_CLK and the phase rolling clock signal PHASE_WHIRL_CLK.

[0092] Referring to Figure 5, in this embodiment, the logic control module 703 includes a first control submodule 7031, a second control submodule 7032, and an addition operation submodule 7033.

[0093] The first control submodule 7031 has a phase rolling control signal input terminal and a phase rolling control signal output terminal. Specifically, the phase rolling control signal input terminal of the first control submodule 7031 is used to receive the phase rolling control signal PW_CLK, and the phase selection control signal output terminal of the first control submodule 7031 is used to output the phase selection control signal. The first control submodule 7031 can be used to determine the phase rolling control signal PW_CLK and the clock period of the phase rolling clock signal PHASE_WHIRL_CLK based on the N uniformly changing phases FB_CLK. <0> ~FB_CLK <n-1>The preset correspondence between the phase positions generates a phase selection control signal.

[0094] Specifically, the first control submodule 7031 can be used to adjust the clock period of the phase rolling clock signal PHASE_WHIRL_CLK and the N phases uniformly changing FB_CLK. <0> ~FB_CLK <n-1>The preset correspondence between the phase positions is used to obtain each clock cycle of the phase rolling clock signal PHASE_WHIRL_CLK, and the feedback clock signal CLK_PHASE output by the phase rolling module 704 is obtained. <k>The phase sequence k; within each clock cycle l of the phase rolling clock signal PHASE_WHIRL_CLK, when the phase rolling control signal PW_CLK has the first logic level, the corresponding feedback clock signal CLK_PHASE is... <k>The phase position k is output as the phase selection control signal.

[0095] Wherein, the clock period l of the phase rolling clock signal PHASE_WHIRL_CLK is the same as that of the N phase-uniformly changing FB_CLK. <0> ~FB_CLK <n-1>The preset correspondence between the phase sequences satisfies:

[0096]

[0097] And:

[0098]

[0099] Where k represents the phase sequence of the feedback clock signal output by the phase rolling module in the l-th clock cycle of the phase rolling clock signal, and j l represents the carry count value of the integer division coefficient M related to the target frequency of the oscillation clock signal in the l-th clock cycle of the phase rolling clock signal, and j l-1 represents the carry count value of the integer division coefficient M related to the target frequency of the oscillation clock signal in the (l - 1)-th clock cycle of the phase rolling clock signal.

[0100] The second control sub-module 7032 has a phase rolling control signal input terminal and a modulation value output terminal. Among them, the phase rolling control signal input terminal of the second control sub-module 7032 is used to receive the phase rolling control signal PW_CLK, and the phase sequence output terminal of the second control sub-module 7032 is used to output the corresponding modulation value. The second control sub-module 7032 can be used to generate the corresponding modulation value according to the preset conditions satisfied by the phase rolling control signal and the clock cycle l of the phase rolling clock signal.

[0101] Specifically, the second control sub-module 7032 can be used to generate the first modulation value when the phase rolling control signal PW_CLK has the first logic level and the preset condition satisfied by the clock cycle l of the phase rolling clock signal PHASE_WHIRL_CLK is 0 ≤ l * X < N; when the phase rolling control signal PW_CLK has the second logic level and the preset condition satisfied by the clock cycle l of the phase rolling clock signal PHASE_WHIRL_CLK is l * X - j l-1 * N ≥ N, generate the second modulation value. In this embodiment, the first modulation value is 0 and the second modulation value is 1.

[0102] The addition submodule 7033 has a modulation value input terminal and an integer frequency division coefficient output terminal. The modulation value input terminal of the addition submodule 7033 is used to receive the corresponding modulation value, and the integer frequency division coefficient output terminal is used to output the corresponding integer frequency division coefficient. The addition submodule 7033 can be used to calculate the sum of the corresponding modulation value and the integer frequency division value M related to the target frequency of the oscillation clock signal, as the corresponding integer frequency division coefficient.

[0103] Specifically, the addition submodule 7033 can, upon receiving the first modulation value, calculate the sum of the first modulation value and the integer frequency division value M related to the target frequency of the oscillation clock signal as the corresponding integer frequency division coefficient; and upon receiving the second modulation value, calculate the sum of the second modulation value and the integer frequency division value M related to the target frequency of the oscillation clock signal as the corresponding integer frequency division coefficient.

[0104] In this embodiment, the first modulation value is 0, and the second modulation value is 1. Accordingly, the corresponding integer frequency division coefficient is (M+0) or (M+1).

[0105] It is understood that the logic control module can also be implemented using other structures with the same function, and those skilled in the art can select according to actual needs, without any restrictions.

[0106] The phase rolling module 704 has a phase rolling control signal input terminal and N feedback clock signal input terminals. The phase rolling control signal input terminal of the phase rolling module 704 is used to receive the phase rolling control signal, and the N feedback clock signal input terminals of the phase rolling module 704 are used to receive N feedback clock signals FB_CLK with uniformly changing phases. <0> ~FB_CLK <n-1>The phase rolling module 704 can be used to receive the phase rolling control signal and N feedback clock signals FB_CLK with uniform phase changes. <0> ~FB_CLK <n-1>According to the phase selection control signal, the feedback clock signal FB_CLK is generated from N uniformly varying phases within each clock period l of the feedback clock signal. <0> ~FB_CLK <n-1>Select the feedback clock signal CLK_PHASE with the corresponding phase position k. <k>The phase rolling clock signal PHASE_WHIRL_CLK is generated by splicing the signals together.

[0107] The working principle of the phase-locked loop circuit in the embodiments of the present invention will be described in detail below.

[0108] It should be noted that the working principles of the phase detection unit 10, loop filter unit 30, and voltage-controlled oscillation unit 50 in the phase-locked loop circuit of the present invention are the same as those of the corresponding modules in the existing phase-locked loop circuit, and will not be repeated here.

[0109] Unlike existing phase-locked loop (PLL) circuits, the PLL circuit in this embodiment employs a frequency division processing module 701, a phase alignment module 702, a logic control module 703, and a phase rolling module 704 within the phase rolling clock signal generation unit 70. It uses corresponding integer frequency division coefficients to divide the N oscillating clock signals VCO_CLK, whose phases change uniformly. <0> ~VCO_CLK <n-1>Each signal is divided by an integer to obtain multiple feedback clock signals FB_CLK with uniform phase changes. <0> ~FB_CLK <n-1>And the feedback clock signal FB_CLK with multiple phases changing uniformly. <0> ~FB_CLK <n-1>The feedback clock signals FB_CLK are sorted according to phase order to obtain multiple signals with uniformly changing phases. <0> ~FB_CLK <n-1>The phase sequence is determined, and finally, according to a preset clock period, the multiple uniformly phased feedback clock signals FB_CLK are used. <0> ~FB_CLK <n-1>Select the feedback clock signal CLK_PHASE with the corresponding phase sequence. <k>By splicing the signals together, the phase rolling clock signal PHASE_WHIRL_CLK is generated, which can realize a fractional N frequency division phase-locked loop.

[0110] Specifically, the frequency division processing module 701 receives N oscillating clock signals VCO_CLK with uniformly changing phases. <0> ~VCO_CLK <n-1>The clock signals VCO_CLK, which have uniformly changing phases, are divided by N frequency dividers using corresponding integer division coefficients (M+0) or (M+1). <0> ~VCO_CLK <n-1>Each signal is divided into N uniformly phased feedback clock signals FB_CLK. <0> ~FB_CLK <n-1>Among them, there are N feedback clock signals FB_CLK with uniformly changing phases. <0> ~FB_CLK <n-1>The frequencies are all the same, and the feedback clock signals CLK_PHASE with adjacent phase positions are also the same. <q>~CLK_PHASE<Q+1> The phase difference between them is also the same, that is Where Q is an integer greater than or equal to and less than or equal to N-2.

[0111] It should be noted that N frequency dividers 701 <0> ~701 <n-1>The output consists of N uniformly phased feedback clock signals FB_CLK. <0> ~FB_CLK <n-1>Each frequency divider is used in N frequency dividers 701. <0> ~701 <n-1>The bit sequence is used for identification. Specifically, the feedback clock signal FB_CLK <0> Composed of N frequency dividers 701 <0> ~701 <n-1>Frequency divider 701 with 0th bit sequence <0> Output, feedback clock signal FB_CLK <1> Composed of N frequency dividers 701 <0> ~701 <n-1>Frequency divider 701 with the first bit sequence <1> Output, ..., feedback clock signal FB_CLK <n-1>Composed of N frequency dividers 701 <0> ~701 <n-1>Frequency divider 701 with the (N-1)th bit sequence <n-1>Output.

[0112] Then, N frequency dividers 701 <0> ~701 <n-1>The output consists of N uniformly phased feedback clock signals FB_CLK. <0> ~FB_CLK <n-1>The input is fed into the phase alignment module 702, which then converts the N uniformly phased feedback clock signals FB_CLK into signals. <0> ~FB_CLK <n-1>Sort the signals according to phase order to obtain N feedback clock signals FB_CLK with uniform phase changes. <0> ~FB_CLK <n-1>The phase order.

[0113] Specifically, the sampling processing submodule 7021 employs a frequency divider 701 with the 0th bit sequence. <0> The output feedback clock signal INTIAL_PHASE_WHIRL_CLK <0> Frequency divider 701 for bit sequence 1 to (N-1)th bit sequence <1> ~701 <n-1>The output feedback clock signal FB_CLK <1> ~

[0114] FB_CLK <n-1>Sampling processing is performed separately to obtain the corresponding sampled signal CAL. <1> ~CAL <n-1>.

[0115] The sorting processing submodule 7022 receives the corresponding sampling signal CAL. <1> ~CAL <n-1>And according to the corresponding sampling signal CAL <1> ~CAL <n-1>Obtain N feedback clock signals FB_CLK with uniform phase changes. <0> ~FB_CLK <n-1>The phase order.

[0116] Specifically, as shown in formula (2), in the corresponding sampling signal CAL <1> ~CAL <n-1>When all values ​​are the first sampled values, the sorting processing submodule 7022 identifies N feedback clock signals FB_CLK with uniformly changing phases. <0> ~FB_CLK <n-1>The phase sequence and N frequency dividers 701 <0> ~701 <n-1>The positional order is the same. Among them, the first sampled value is 0.

[0117] As shown in formula (2), in the corresponding sampling signal CAL <1> ~CAL <n-1>When a unique second sample value exists, the first-order frequency divider 701 <1> The output feedback clock signal FB_CLK <1> The phase sequence is 0, and the feedback clock signal FB_CLK output by the frequency divider of the second sequence is 0. <2> The feedback clock signal FB_CLK output by the frequency divider with phase bit sequence 1, ..., N-2th bit sequence <n-2>The phase sequence is N-1, and the feedback clock signal FB_CLK output by the frequency divider of the (N-1)th phase sequence is... <n-1>The phase sequence is 0. The second sample value is 1.

[0118] In the corresponding sampling signal CAL <1> ~CAL <n-1>When there are two or more second sample values, the phase order of the feedback clock signal output by each frequency divider can be obtained by using the above formula (2).

[0119] It should be noted that when acquiring N feedback clock signals FB_CLK with uniform phase changes... <0> ~FB_CLK <n-1>After determining the phase order, CLK_PHASE is used. <0> ~CLK_PHASE <n-1>For each of the N uniformly phased feedback clock signals FB_CLK <0> ~FB_CLK <n-1>This is used for identification. Specifically, CLK_PHASE <0> CLK_PHASE is used to represent the feedback clock signal when the phase bit sequence is 0. <1> Used to represent the feedback clock signal with phase bit sequence 1, ..., CLK_PHASE <n-1>Used to represent a feedback clock signal with a phase sequence of N-1.

[0120] Simultaneously, the logic operation submodule 7023 will process the N feedback clock signals FB_CLK with uniformly changing phases. <0> ~FB_CLK <n-1>Perform NOR / NOT logical operations to obtain the phase rolling control signal PW_CLK. Specifically, when N feedback clock signals FB_CLK with uniformly changing phases... <0> ~FB_CLK <n-1>When all three phases have a first logic level, the phase rolling control signal PW_CLK has a second logic level; the feedback clock signal FB_CLK with N phases changing uniformly. <0> ~FB_CLK <n-1>When at least one of the components has a second logic level, the phase rolling control signal PW_CLK has a first logic level. The first logic level is low, and the second logic level is high.

[0121] The logic operation submodule 7023 processes the N uniformly phased feedback clock signals FB_CLK <0> ~FB_CLK <n-1>Perform NOR logic operations to obtain the phase rolling control signal PW_CLK, and obtain the feedback clock signal FB_CLK that changes uniformly across N phases. <0> ~FB_CLK <n-1>All are in a stable state, that is, avoiding the feedback clock signal FB_CLK with N uniformly changing phases. <0> ~FB_CLK <n-1>The rising and falling edges of the signal generate the N uniformly phased oscillation clock signals VCO_CLK produced by the frequency division processing module 701. <0> ~VCO_CLK <n-1>The corresponding integer division coefficients used for integer division processing are (M+0) or (M+1).

[0122] To obtain N feedback clock signals FB_CLK with uniform phase changes. <0> ~FB_CLK <n-1>After determining the phase sequence, the first control submodule 7031 in the logic control module 703 determines the phase rolling control signal PW_CLK and the phase rolling clock signal PHASE_WHIRL_CLK based on their clock periods and the feedback clock signal FB_CLK that uniformly changes the N phases. <0> ~FB_CLK <n-1>The preset correspondence between the phase positions generates a phase selection control signal.

[0123] Specifically, the first control submodule 7031 determines the clock period of the phase rolling clock signal PHASE_WHIRL_CLK and the N uniformly changing feedback clock signals FB_CLK. <0> ~FB_CLK <n-1>The preset correspondence between the phase positions is used to obtain the feedback clock signal CLK_PHASE output by the phase rolling module for each clock cycle of the phase rolling clock signal PHASE_WHIRL_CLK according to formulas (3) and (4). <k>The phase sequence k; according to the preset clock period, when the phase rolling control signal PW_CLK has the first logic level, the corresponding feedback clock signal CLK_PHASE is... <k>The phase sequence k is output as the phase selection control signal.

[0124] Meanwhile, the second control sub-module 7032 in the logic control module 703 generates a first modulation value when the phase roll control signal PW_CLK has a first logic level and the preset condition satisfied by the clock period of the phase roll clock signal PHASE_WHIRL_CLK is 0 ≤ l*X < N; and generates a second modulation value when the phase roll control signal PW_CLK has a first logic level and the preset condition satisfied by the clock period of the phase roll clock signal PHASE_WHIRL_CLK is l*X - j l-1 *N ≥ N, where l represents the clock period of the phase roll clock signal. For example, the first modulation value is 0 and the second modulation value is 1.

[0125] After that, when the addition operation sub-module 7033 receives the first modulation value, it calculates the sum of the first modulation value and the integer frequency division coefficient M related to the target frequency of the oscillation clock signal, and obtains the corresponding integer frequency division coefficient as (M + 0); when it receives the second modulation value, it calculates the sum of the second modulation value and the integer frequency division coefficient M related to the target frequency of the oscillation clock signal, and obtains the corresponding integer frequency division coefficient as (M + 1), so that the frequency division processing module 701 uses the corresponding integer frequency division coefficient to perform frequency division on the oscillation clock signals VCO_CLK<0> to VCO_CLK with N uniformly changing phases <n-1>Perform integer frequency division to obtain N feedback clock signals FB_CLK with uniform phase changes. <0> ~FB_CLK <n-1>.

[0126] Subsequently, the phase rolling module 704 in the phase rolling clock signal

[0127] Within each cycle of PHASE_WHIRL_CLK, the received feedback clock signal CLK_PHASE, which serves as the phase rolling control signal, is used. <k>The phase sequence k is derived from the N uniformly phased feedback clock signals FB_CLK. <0> ~FB_CLK <n-1>Select the feedback clock signal CLK_PHASE with the corresponding phase sequence k. <k>The output, thereby causing adjacent rising edges of the phase rolling clock signal PHASE_WHIRL_CLK output by the phase rolling module 704 to generate... The period of the oscillation clock signal VCO_CLK.

[0128] Referring to Figure 6, taking an external reference clock signal with a frequency of 24Hz, N=3 and X=1 as an example, the target frequency f of the oscillation clock signal output by the phase-locked loop circuit is... vco_clk_out When the frequency is 5GHz, the integer division factor M related to the target frequency of the oscillation clock signal can be calculated to be 208 according to formula (1). That is, when the phase-locked loop circuit is in the locked state, the phase rolling clock signal PHASE_WHIRL_CLK generated by the phase rolling clock signal generation unit 70 needs to generate a time interval between adjacent rising edges. The period of the oscillation clock signal VCO_CLK.

[0129] The values ​​of the relevant parameters in the 0th to 8th cycles of the phase rolling clock signal PHASE_WHIRL_CLK are shown in Table 1 below.

[0130] Table 1

[0131] ll*XNj l CLK_PHASE <k>M+0 / M+1003002081130120822302208333102094431120855312208663202097732120888322208 surface

[0132] Referring to Figure 6 and Table 1, during the 0th, 1st, and 2nd cycles of the phase-rolling clock signal PHASE_WHIRL_CLK, the frequency division processing module 701 uses a corresponding integer frequency division coefficient 208 to divide the three uniformly phase-changing oscillating clock signals VCO_CLK. <0> VCO_CLK <1> and VCO_CLK <2> Each signal is divided by an integer to obtain three feedback clock signals FB_CLK with uniform phase changes. <0> FB_CLK <1> and FB_CLK <2> At this time, the feedback clock signal FB_CLK <0> FB_CLK <1> and FB_CLK <2> Each adjacent rising edge generates 208 cycles of oscillation clock signals.

[0133] Simultaneously, during the 0th, 1st, and 2nd cycles of the phase rolling clock signal PHASE_WHIRL_CLK, the phase rolling module 704 selects the feedback clock signal CLK_PHASE with a phase sequence of 0, respectively. <0> The feedback clock signal CLK_PHASE with a phase sequence of 1 <1> And the feedback clock signal CLK_PHASE with a phase sequence of 2 <2> Output is performed, that is, from the feedback clock signal CLK_PHASE with a phase sequence of 0. <0> Jump to the feedback clock signal CLK_PHASE with phase bit sequence 1. <1> Then, from the feedback clock signal CLK_PHASE with phase sequence 1 <1> Jump to the feedback clock signal CLK_PHASE with phase bit sequence 2. <2> Due to the feedback clock signal CLK_PHASE with a phase sequence of 1. <1> Feedback clock signal CLK_PHASE with phase sequence of 0 <0> Delay The feedback clock signal CLK_PHASE has a period T of oscillation clock signal VCO_CLK and a phase sequence of 2. <2> The feedback clock signal CLK_PHASE with a phase bit sequence of 1 <1> Delay The period T of the oscillating clock signal VCO_CLK is such that a phase rolling clock signal PHASE_WHIRL_CLK is generated between the rising edges of the phase rolling clock signal PHASE_WHIRL_CLK in the 0th, 1st, and 2nd periods. The period T of the oscillation clock signal VCO_CLK.

[0134] In the third cycle of the phase-rolling clock signal PHASE_WHIRL_CLK, the frequency division processing module 701 uses a corresponding integer frequency division coefficient 209 to divide the phase-uniformly changing oscillating clock signal VCO_CLK. <0> VCO_CLK <1> and VCO_CLK <2> Each signal is divided by an integer to obtain three feedback clock signals FB_CLK with uniform phase changes. <0> FB_CLK <1> and FB_CLK <2> At this time, the feedback clock signal FB_CLK <0> FB_CLK <1> and FB_CLK <2> Each adjacent rising edge generates 209 cycles of oscillation clock signals.

[0135] Simultaneously, during the third cycle of the phase rolling clock signal, the phase rolling module 704 selects the feedback clock signal CLK_PHASE with a phase bit sequence of 0. <0> Output is performed, specifically from the feedback clock signal CLK_PHASE with phase sequence 2. <2> Jump to the feedback clock signal CLK_PHASE with phase bit sequence 0. <0> Due to the third cycle of the phase rolling clock signal, the feedback clock signal CLK_PHASE has a phase sequence of 0. <0> The feedback clock signal CLK_PHASE with a phase bit sequence of 2 <2> Advanced The period of the oscillating clock signal VCO_CLK is such that between the rising edges of the phase rolling clock signal in the third period, a... The period T of the oscillation clock signal VCO_CLK.

[0136] Similarly, during the 4th to 8th cycles of the phase rolling clock signal PHASE_WHIRL_CLK, a phase rolling clock signal is generated between the rising edges of the phase rolling clock signal. The period of the oscillation clock signal VCO_CLK is used to realize the fractional N division frequency lock loop.

[0137] Referring to Figure 7, taking an external reference clock signal with a frequency of 24Hz, N=3 and X=2 as an example, the target frequency f of the oscillation clock signal output by the phase-locked loop circuit is... vco_clk_out When the frequency is 4GHz, the integer frequency division coefficient M related to the target frequency of the oscillation clock signal can be calculated to be 166 according to formula (1). That is, when the phase-locked loop circuit is in the locked state, a phase rolling clock signal PHASE_WHIRL_CLK generated by the phase rolling clock signal generation unit 70 needs to generate a frequency between adjacent rising edges. The period of the oscillation clock signal VCO_CLK.

[0138] The values ​​of the relevant parameters in the 0th to 6th cycles of the phase rolling clock signal PHASE_WHIRL_CLK are shown in Table 2 below.

[0139] Table 2

[0140] ll*XNj l CLK_PHASE <k>M+0 / M+10030016612302166243211673632016748322166510331167612340167 surface

[0141] Referring to Figure 7 and Table 2, during the 0th and 1st cycles of the phase-rolling clock signal PHASE_WHIRL_CLK, the frequency division processing module 701 uses a corresponding integer frequency division coefficient of 166 to divide the three uniformly phase-changing oscillating clock signals VCO_CLK. <0> VCO_CLK <1> and VCO_CLK <2> Each signal is divided by an integer to obtain three feedback clock signals FB_CLK with uniform phase changes. <0> FB_CLK <1> and FB_CLK <2> At this time, the three feedback clock signals FB_CLK change phase uniformly. <0> FB_CLK <1> and FB_CLK <2> Each adjacent rising edge generates 166 cycles of oscillation clock signals.

[0142] Simultaneously, during the 0th and 1st cycles of the phase rolling clock signal PHASE_WHIRL_CLK, the phase rolling module 704 selects the feedback clock signal CLK_PHASE with a phase sequence of 0, respectively. <0> And the feedback clock signal CLK_PHASE with a phase sequence of 2 <2> Output is performed, that is, from the feedback clock signal CLK_PHASE with a phase sequence of 0. <0> Jump to the feedback clock signal CLK_PHASE with phase bit sequence 2. <2> Due to the feedback clock signal CLK_PHASE with a phase sequence of 2. <2> The feedback clock signal is compared to the feedback clock signal CLK_PHASE with a phase sequence of 0. <0> Delay The period T of the oscillating clock signal VCO_CLK is such that a phase rolling clock signal PHASE_WHIRL_CLK is generated between the rising edges of the phase rolling clock signal PHASE_WHIRL_CLK in the 0th and 1st periods. The period of the oscillation clock signal VCO_CLK.

[0143] During the second cycle of the phase-rolling clock signal PHASE_WHIRL_CLK, the frequency division processing module 701 uses a corresponding integer frequency division coefficient of 167 to divide the three uniformly phase-changing oscillation clock signals VCO_CLK. <0> VCO_CLK <1> and VCO_CLK <2> Each signal is divided by an integer to obtain three feedback clock signals FB_CLK with uniform phase changes. <0> FB_CLK <1> and FB_CLK <2> At this time, the three feedback clock signals FB_CLK change phase uniformly. <0> FB_CLK <1> and FB_CLK <2> Each adjacent rising edge generates 167 cycles of oscillation clock signals.

[0144] Simultaneously, during the second cycle of the phase rolling clock signal, the phase rolling module 704 selects the feedback clock signal CLK_PHASE with a phase bit sequence of 1. <1> Output is performed, specifically from the feedback clock signal CLK_PHASE with phase sequence 2. <2> Jump to the feedback clock signal CLK_PHASE with phase bit sequence 1. <1> Due to the second cycle of the phase rolling clock signal, the feedback clock signal CLK_PHASE with a phase bit sequence of 1. <1> The feedback clock signal CLK_PHASE with a phase bit sequence of 2 <2> Advanced The period of the oscillating clock signal VCO_CLK is such that a phase rolling clock signal is generated between the rising edges of the phase rolling clock signal in the third period. The period of the oscillation clock signal VCO_CLK.

[0145] Similarly, during the 3rd to 6th cycles of the phase rolling clock signal PHASE_WHIRL_CLK, a phase rolling clock signal is generated between the rising edges of the phase rolling clock signal. The period of the oscillation clock signal VCO_CLK is used to realize the fractional N division frequency lock loop.

[0146] In summary, the phase-locked loop circuit in this embodiment of the invention can realize a fractional N-fold frequency-division phase-locked loop by using an integer frequency division processing module. Compared with the method of using a digital Σ-Δ modulator to realize a fractional N-fold frequency-division phase-locked loop, it can save the area and power consumption of the phase-locked loop circuit, and thus help improve the performance of the phase-locked loop circuit.

[0147] Accordingly, embodiments of the present invention also provide a phase-locked loop method.

[0148] Figure 8 shows a schematic flowchart of an embodiment of the phase-locked loop (PLL) method provided by the present invention. Referring to Figure 8, a PLL method may specifically include the following steps:

[0149] Step S810: Receive an external reference clock signal and a phase rolling clock signal using a phase detection unit; generate a falling control signal when the phase of the phase rolling clock signal leads the external reference clock signal; generate a rising control signal when the phase of the phase rolling clock signal lags the external reference clock signal.

[0150] Step S820: When the drop control signal is received, the loop filter unit reduces the voltage value of the control voltage signal; when the boost control signal is received, it increases the voltage value of the control voltage signal.

[0151] Step S830: A voltage-controlled oscillator unit generates multiple oscillation clock signals with uniformly changing phases based on the voltage value of the control voltage signal;

[0152] Step S840: The phase rolling clock signal generation unit performs integer frequency division processing on the multiple oscillating clock signals with uniformly changing phases to obtain multiple feedback clock signals with uniformly changing phases; the multiple feedback clock signals with uniformly changing phases are sorted according to phase order to obtain the phase position order of the multiple feedback clock signals with uniformly changing phases; according to the clock period of the feedback clock signals, the feedback clock signals with corresponding phase positions are selected from the multiple feedback clock signals with uniformly changing phases and spliced ​​together to generate the phase rolling clock signal.

[0153] The phase-locked loop (PLL) method in this embodiment of the invention can be executed by the aforementioned PLL circuit, or it can be executed using other functional modules. For a detailed description of the PLL circuit, please refer to the foregoing section; it will not be repeated here.

[0154] Accordingly, embodiments of the present invention also provide a frequency synthesizer, including a phase-locked loop (PLL) circuit as provided in the embodiments of the present invention. For details regarding the PLL circuit, please refer to the foregoing description, which will not be repeated here.

[0155] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be used to implement other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0156] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.< / k> < / k> < / k> < / k> < / k> < / k> < / q> < / k> < / k> < / k> < / k>

Claims

1. A phase-locked loop circuit, characterized in that, include: The phase detection unit is suitable for receiving external reference clock signals and phase rolling clock signals; A fall control signal is generated when the phase of the phase rolling clock signal leads the external reference clock signal. When the phase of the phase rolling clock signal lags behind the external reference clock signal, a boost control signal is generated; the loop filtering unit is adapted to reduce the voltage value of the control voltage signal when the fall control signal is received. Upon receiving the boost control signal, the voltage value of the control voltage signal is increased; A voltage-controlled oscillator unit is adapted to generate multiple oscillating clock signals with uniformly changing phases based on the voltage value of the control voltage signal. A phase rolling clock signal generation unit is adapted to perform integer frequency division processing on the multiple oscillating clock signals with uniformly changing phases to obtain multiple feedback clock signals with uniformly changing phases; sort the multiple feedback clock signals with uniformly changing phases according to phase order to obtain the phase position order of the multiple feedback clock signals with uniformly changing phases; and select feedback clock signals with corresponding phase positions from the multiple feedback clock signals with uniformly changing phases according to a preset clock period and splice them together to generate the phase rolling clock signal.

2. The phase-locked loop circuit as described in claim 1, characterized in that, The target frequency of the oscillation clock signal satisfies: Among them, f VCO_CLK f represents the target frequency of the oscillation clock signal. REF_CLK The frequency of the external reference clock signal is represented by M, the integer division coefficient related to the target frequency of the oscillation clock signal is represented by X, the fractional division coefficient related to the target frequency of the oscillation clock signal is represented by X, and X is an integer greater than zero and less than or equal to (N-1), and N represents the number of the plurality of feedback clock signals with uniformly changing phases.

3. The phase-locked loop circuit as described in claim 2, characterized in that, The phase rolling clock signal generation unit includes: a frequency division processing module, adapted to receive a corresponding integer frequency division coefficient and N oscillating clock signals with uniformly changing phases; performing frequency division processing on the N oscillating clock signals with uniformly changing phases using the corresponding integer frequency division coefficients to obtain N feedback clock signals with uniformly changing phases; a phase alignment module, adapted to sort the N feedback clock signals with uniformly changing phases according to their phase order to obtain the phase position order of the N feedback clock signals with uniformly changing phases; and further adapted to perform N OR / NOT operations on the N feedback clock signals with uniformly changing phases to generate a phase rolling control signal; and a logic control module, adapted to generate a phase rolling control signal based on the phase rolling control signal and the... A phase selection control signal is generated based on a preset correspondence between the clock period of the phase rolling clock signal and the phase order of the N uniformly phase-changing feedback clock signals. It is also adapted to generate corresponding integer frequency division coefficients based on preset conditions satisfied by the phase rolling control signal and the clock period of the phase rolling clock signal. The phase rolling module is adapted to receive the phase rolling control signal and the N uniformly phase-changing feedback clock signals. Based on the phase selection control signal, it selects feedback clock signals with corresponding phase orders from the N uniformly phase-changing feedback clock signals in each clock period of the phase rolling clock signal and splices them together to generate the phase rolling clock signal.

4. The phase-locked loop circuit as described in claim 3, characterized in that, The frequency division processing module includes N frequency dividers, each corresponding to one of the N uniformly phased oscillating clock signals. Each frequency divider is adapted to receive a corresponding integer frequency division coefficient and a corresponding oscillating clock signal from the N uniformly phased oscillating clock signals. The corresponding integer frequency division coefficient is used to perform frequency division processing on the corresponding oscillating clock signal from the N uniformly phased oscillating clock signals to obtain a corresponding feedback clock signal.

5. The phase-locked loop circuit as described in claim 4, characterized in that, The phase alignment module includes: a sampling processing submodule, adapted to sample the feedback clock signals output by the frequency dividers from the 1st to the (N-1)th bit order using the feedback clock signal output by the frequency divider of the 0th bit order, and obtain the corresponding sampled signals; a sorting processing submodule, adapted to obtain the phase order of N uniformly phase-changing feedback clock signals according to the sampled signals; and a logic operation submodule, adapted to perform N uniformly phase-changing feedback clock signals with N OR and NOT logic operations to obtain the phase rolling control signal.

6. The phase-locked loop circuit as described in claim 5, characterized in that, The sorting submodule is adapted to obtain the phase order of N uniformly phase-changing feedback clock signals based on the sampled signals using the following formula: Among them, CLK_PHASE FB_CLK represents the feedback clock signal with phase order p when N uniformly phased feedback clock signals are arranged in ascending order according to their phase order.<p+Y> FB_CLK represents the feedback clock signal output by the frequency divider at the (p+Y)th bit position.<p+Y> The feedback clock signal output by the frequency divider at the (p+YN)th bit position is represented, where Y represents the number of second sample values ​​in the sampled signal, and Y is an integer greater than or equal to 0 and less than or equal to (N-1).

7. The phase-locked loop circuit as described in claim 6, characterized in that, The second sample value is 1.

8. The phase-locked loop circuit as described in claim 3, characterized in that, The logic control module includes: a first control submodule, adapted to generate a phase selection control signal based on a preset correspondence between the clock periods of the phase rolling control signal and the phase rolling clock signal and the phase order of the N uniformly phase-changing feedback clock signals; a second control submodule, adapted to generate a corresponding modulation value based on a preset condition satisfied by the clock periods of the phase rolling control signal and the phase rolling clock signal; and an addend operation submodule, adapted to calculate the sum of the corresponding modulation value and the integer frequency division coefficient related to the target frequency of the oscillation clock signal to obtain the corresponding integer frequency division coefficient.

9. The phase-locked loop circuit as described in claim 8, characterized in that, The first control submodule is adapted to obtain the phase sequence of the feedback clock signal output by the phase rolling module for each clock period of the phase rolling clock signal according to a preset correspondence between the clock period of the phase rolling clock signal and the phase sequence of the N uniformly phase-changing feedback clock signals; and to output the corresponding phase sequence of the feedback clock signal as the phase selection control signal when the phase rolling control signal has a first logic level, according to a preset clock period; wherein, the preset correspondence between the clock period of the phase rolling clock signal and the phase sequence of the N uniformly phase-changing feedback clock signals satisfies: and: Where k represents the phase position of the feedback clock signal output by the phase rolling module in the l-th clock cycle of the phase rolling clock signal, and j l j represents the carry count value of the integer frequency division coefficient related to the target frequency of the oscillating clock signal in the l-th clock cycle of the phase rolling clock signal. l-1 The integer frequency division coefficient M, which is related to the target frequency of the oscillating clock signal, represents the carry count value in the (l-1)th clock cycle of the phase rolling clock signal.

10. The phase-locked loop circuit as described in claim 8, characterized in that, The second control sub-module is adapted to generate a first modulation value when the phase roll control signal has a first logic level and the preset condition satisfied by the clock period of the phase roll clock signal is 0 ≤ l*X < N; when the phase roll control signal has a first logic level and the preset condition satisfied by the clock period of the phase roll clock signal is l*X - j l-1 *N ≥ N, generate a second modulation value; the adder operation sub-module is adapted to, when receiving the first modulation value, obtain the sum of the integer division coefficient M related to the target frequency of the oscillation clock signal and the first modulation value as the corresponding integer division coefficient; when receiving the second modulation value, obtain the sum of the integer division coefficient M related to the target frequency of the oscillation clock signal and the second modulation value as the corresponding integer division coefficient.

11. The phase-locked loop circuit as described in claim 10, characterized in that, The first modulation value is 0, and the second modulation value is 1.

12. The phase-locked loop circuit as described in claim 10, characterized in that, The first logic level is a low level.

13. A phase-locked loop method, characterized in that, include: A phase detection unit is used to receive an external reference clock signal and a phase rolling clock signal; A fall control signal is generated when the phase of the phase rolling clock signal leads the external reference clock signal. When the phase of the phase rolling clock signal lags behind the external reference clock signal, a boost control signal is generated; when the fall control signal is received, a loop filter unit reduces the voltage value of the control voltage signal. Upon receiving the boost control signal, the voltage value of the control voltage signal is increased; a voltage-controlled oscillator unit generates multiple oscillating clock signals with uniformly changing phases based on the voltage value of the control voltage signal; a phase rolling clock signal generation unit performs integer frequency division processing on each of the multiple oscillating clock signals with uniformly changing phases to obtain multiple feedback clock signals with uniformly changing phases; the multiple feedback clock signals with uniformly changing phases are sorted according to phase order to obtain the phase position order of the multiple feedback clock signals with uniformly changing phases; according to a preset clock period, feedback clock signals with corresponding phase positions are selected from the multiple feedback clock signals with uniformly changing phases and spliced ​​together to generate the phase rolling clock signal.

14. A frequency synthesizer, characterized in that, Includes the phase-locked loop circuit as described in any one of claims 1-12.

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