A master-slave single-disk time synchronization system for a communication device

Abstract

The application relates to a master-standby single-disk time synchronization system for a communication device, wherein the disk and the duplicate disk comprise a master control chip, a switching chip, a HUB chip, an SFP optical module, a CPLD module, a single-pole double-throw digital switch SPDT1 and a single-pole double-throw digital switch SPDT2; the switching chip and the HUB chip are respectively connected with the master control chip through electric signals; the SFP optical module is connected with the duplicate disk or the switching chip through the single-pole double-throw digital switch SPDT1 through electric signals; the HUB chip is connected with COM or the duplicate disk through the single-pole double-throw digital switch SPDT2 through electric signals; the CPLD module is used for detecting the existing state of the duplicate disk and dynamically switching the SPDT1 and the SPDT2. The application solves the problems of high algorithm power requirement and large error. The built-in single-pole double-throw digital switch can switch the control switch according to the in-place state of the duplicate disk, acquire the service information of the optical module of the duplicate disk, stamp the time through the HUB and the switching chip, cross through service fusion in the master control chip, issue the time information, and realize master-standby time synchronization.

Description

Technical Field

[0001] This invention relates to the field of network communication technology, and more specifically to a primary and backup single-disk time synchronization system for communication equipment. Background Technology

[0002] In communication network equipment, time synchronization is a key technology for ensuring data exchange, signal processing, and network collaborative operation. Most existing time synchronization devices rely on a single link to achieve primary and backup synchronization. Once the link is interrupted or the equipment fails, time drift can easily occur, reducing system stability.

[0003] Specifically, in existing communication technologies, the synchronization link between the primary control board and the backup board is fixed (e.g., a dedicated synchronization port or backplane channel); when the primary / backup roles are switched or a board is disconnected, this link needs to be re-established or manually switched; during the link switch, PTP synchronization messages are interrupted, causing system time drift.

[0004] Therefore, how to achieve highly reliable time synchronization between the primary and backup systems while ensuring normal communication between the devices has become an urgent technical problem to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a primary and backup single-disk time synchronization system for communication equipment, so as to overcome the shortcomings of the prior art.

[0006] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: a primary and backup single-disk time synchronization system for communication equipment.

[0007] It includes a main board and a dual board with the same structure. Both the main board and the dual board include a main control chip, a switching chip with a clock synchronization protocol, a HUB chip, an SFP optical module, a CPLD module, a single-pole double-throw digital switch SPDT1 and a single-pole double-throw digital switch SPDT2, respectively.

[0008] The switching chip and HUB chip of this board are electrically connected to the main control chip. The SFP optical module of this board is electrically connected to the switching chip of this board or the switching chip of the dual board through a single-pole double-throw digital switch SPDT1. The network management port COM of this board is electrically connected to the HUB chip of this board or the HUB chip of the dual board through a single-pole double-throw digital switch SPDT2.

[0009] The main control chip of the dual disk is connected to the main control chip of the local disk via a master-slave interconnection line electrical signal. The main control chips of both the local disk and the dual disk are externally connected to the service disk.

[0010] The CPLD module of the local or dual disk is used to detect the presence status of the dual disk or the local disk, and dynamically switch the respective single-pole double-throw digital switch SPDT1 and single-pole double-throw digital switch SPDT2 according to the master-slave synchronization requirements.

[0011] The beneficial effects of this invention are: This invention eliminates the need for complex algorithms on primary and backup disks, and avoids repeated time synchronization to eliminate errors, thus solving the problems of high computational requirements and large errors associated with traditional methods. This invention features a built-in single-pole double-throw digital switch on each disk, which can switch the control switch according to the status of the paired disk, obtain the optical module service information of the paired disk, timestamp it through the HUB and switching chip, and distribute the time synchronization information in the main control chip through service fusion and cross-connection, achieving primary and backup time synchronization in one step.

[0012] Through the control of the CPLD module, the system can dynamically switch to the dual-disk link to obtain time information while ensuring normal link communication, achieving highly reliable primary and backup time synchronization. The single-pole double-throw digital switch can obtain the status of the dual-disk optical module and COM port according to the service scenario, achieving 500G cross-connect capacity locally on the primary disk. This is suitable for light-load situations, reducing the service processing requirements of the backup disk.

[0013] To ensure normal communication: the system maintains the connection between the switching chip and the local SFP optical module by default, ensuring normal data transmission and reception of network devices.

[0014] Flexible synchronization: The CPLD module switches briefly only when the dual disk exists and time synchronization is required, avoiding interference with business communication.

[0015] High reliability: The dual-disk hardware structure is symmetrical, supporting either side as the primary disk and the other as the backup disk, achieving seamless interconnection. Business data is uniformly timestamped, with time fusion and cross-correction completed in the main control chip. This realizes "business as time carrier," reducing hardware costs and improving system reliability.

[0016] Redundant links: The HUB chip can provide backup communication paths, improving the system's fault tolerance and link redundancy.

[0017] Easy to expand: Through the configuration logic of the CPLD module, it can be expanded to multi-channel synchronization or time synchronization application scenarios with different protocols.

[0018] Based on the above technical solution, the present invention can be further improved as follows.

[0019] Furthermore, both the main disk and the dual disk are equipped with at least two SFP optical modules, each including optical module SFP1 and optical module SFP2.

[0020] The optical modules SFP1 and SFP2 of this board are electrically connected to the switching chip of this board or the switching chip of the dual board via single-pole double-throw digital switches SPDT1 and SPDT3, respectively.

[0021] Furthermore, the single-pole double-throw digital switches SPDT1, SPDT2, and SPDT3 are all model TS3A5018RSVR, and the enable pins of SPDT1, SPDT2, and SPDT3 are all controlled by the CPLD module.

[0022] Furthermore, the switching chip is model VSC7436, and its clock synchronization protocol is IEEE1588.

[0023] Furthermore, the switching chip and the HUB chip are electrically connected to the main control chip via SGMII serial ports.

[0024] Furthermore, the main control chip is model 98DX3258. Attached Figure Description

[0025] Figure 1 This is a system structure block diagram of the present invention. Detailed Implementation

[0026] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0027] like Figure 1 As shown in Embodiment 1, a primary and backup single-disk time synchronization system for communication equipment includes a primary disk and a dual disk with the same structure. Both the primary disk and the dual disk include a main control chip, a switching chip with a clock synchronization protocol, a HUB chip, an SFP optical module, a CPLD module, a single-pole double-throw digital switch SPDT1, and a single-pole double-throw digital switch SPDT2.

[0028] The switching chip and HUB chip of this board are electrically connected to the main control chip. The SFP optical module of this board is electrically connected to the switching chip of this board or the switching chip of the dual board through a single-pole double-throw digital switch SPDT1. The network management port COM of this board is electrically connected to the HUB chip of this board or the HUB chip of the dual board through a single-pole double-throw digital switch SPDT2.

[0029] The main control chip of the dual disk is connected to the main control chip of the local disk via a master-slave interconnection line electrical signal. The main control chips of both the local disk and the dual disk are externally connected to the service disk.

[0030] The CPLD module of the local or dual disk is used to detect the presence status of the dual disk or the local disk, and dynamically switch the respective single-pole double-throw digital switch SPDT1 and single-pole double-throw digital switch SPDT2 according to the master-slave synchronization requirements.

[0031] This invention eliminates the need for complex algorithms on primary and backup disks and repeated time synchronization to eliminate errors, thus solving the problems of high computational requirements and large errors associated with traditional methods. This invention features a single-pole double-throw digital switch built into each disk, which can switch the control switch according to the presence status of the paired disk, obtain the optical module service information of the paired disk, and timestamp it through a hub and switching chip. The main control chip then uses service fusion and cross-validation to send out time synchronization information, achieving primary and backup time synchronization in one step.

[0032] Through the control of the CPLD module, the system can dynamically switch to the dual-disk link to obtain time information while ensuring normal link communication, achieving highly reliable primary and backup time synchronization. The single-pole double-throw digital switch can obtain the status of the dual-disk optical module and COM port according to the service scenario, achieving 500G cross-connect capacity locally on the primary disk. This is suitable for light-load situations, reducing the service processing requirements of the backup disk.

[0033] Flexible synchronization: The CPLD module switches briefly only when the dual disk exists and time synchronization is required, avoiding interference with business communication.

[0034] High reliability: The dual-disk hardware structure is symmetrical, supporting either side as the primary disk and the other as the backup disk, achieving seamless interconnection. Business data is uniformly timestamped, with time fusion and cross-correction completed in the main control chip. This realizes "business as time carrier," reducing hardware costs and improving system reliability.

[0035] Redundant links: The HUB chip can provide backup communication paths, improving the system's fault tolerance and link redundancy.

[0036] Easy to expand: Through the configuration logic of the CPLD module, it can be expanded to multi-channel synchronization or time synchronization application scenarios with different protocols.

[0037] Example 2 is a further improvement based on Example 1, and its details are as follows:

[0038] The main board and the dual board are each equipped with at least two SFP optical modules, each including optical module SFP1 and optical module SFP2.

[0039] The optical modules SFP1 and SFP2 of this board are electrically connected to the switching chip of this board or the switching chip of the dual board via single-pole double-throw digital switches SPDT1 and SPDT3, respectively.

[0040] The SFP port in the device can realize link multiplexing, and can still maintain the continuity of synchronous link in scenarios such as primary and backup disconnection, failure or redundant link.

[0041] Example 3 is a further improvement based on Example 2, and its details are as follows:

[0042] The single-pole double-throw digital switches SPDT1, SPDT2, and SPDT3 are all model TS3A5018RSVR, and their enable pins are controlled by a CPLD module. In practice, the single-pole double-throw digital switches SPDT1, SPDT2, and SPDT3 are connected to the CPLD module via digital switch control lines.

[0043] Achieving low latency in 4G communication: Compared to using software instructions to control link switching (e.g., MCU driving multiplexers via GPIO), this solution uses CPLD hardware detection + logic judgment, with a response time in the microsecond range, without CPU involvement, achieving seamless time synchronization during automatic master / slave switching and avoiding 1588 message interruptions.

[0044] Example 4 is a further improvement based on Example 1, and its details are as follows:

[0045] The switching chip is model VSC7436, and its clock synchronization protocol is IEEE1588.

[0046] Hardware and software collaboration for 1588 time synchronization: The VSC7436 features hardware 1588 synchronization, working in conjunction with switchable links to achieve stable IEEE 1588 time synchronization at the physical layer.

[0047] Example 5 is a further improvement based on Example 1, and its details are as follows:

[0048] The switching chip and the HUB chip are electrically connected to the main control chip via SGMII serial ports.

[0049] The SGMII interface has an embedded clock recovery mechanism, which can reduce the impact of clock deviation on data transmission. It plays a positive role in achieving accurate synchronization between the main control board and the daughter board (such as 1588 time synchronization). The interface is compatible with various switching chips and HUB chip models, which facilitates system upgrades and interconnection with devices from different manufacturers.

[0050] Example 6 is a further improvement based on Example 1, and its details are as follows:

[0051] The main control chip is model 98DX3258.

[0052] The main control chip uses the 98DX3258 high-performance Ethernet switching and processing chip. The main control chip integrates multiple high-speed Ethernet interfaces to enable multi-channel communication between the main control board and individual service boards, thereby improving the system's data forwarding capability and overall throughput without adding additional processors or programmable logic devices.

[0053] The main control chip natively supports the IEEE 1588v2 Precision Time Protocol (PTP) and a hardware-based data packet timestamp mechanism, enabling the acquisition of timestamps related to time synchronization to be completed at the hardware level. This achieves nanosecond-level time synchronization accuracy between the main control board and the service single board, significantly improving the clock consistency between various functional units of the system.

[0054] In addition, the main control chip integrates switching functions and network protocol processing capabilities to uniformly complete business data forwarding and time synchronization message processing, reducing reliance on external auxiliary logic or field-programmable gate arrays, making the system structure more compact, and helping to reduce system power consumption and improve overall reliability.

[0055] This invention uses the high-performance Ethernet switching and processing chip 98DX3258 as the main control chip. It utilizes its integrated multi-channel high-speed Ethernet interface to realize multi-channel communication between the main control board and the service single board. Without adding additional processors or programmable logic devices, it improves the system's data forwarding capability and overall throughput, and is suitable for communication scenarios with multiple services running concurrently.

[0056] This invention fully utilizes the native support of the 98DX3258 for the IEEE 1588 precision time protocol, and pushes the timestamp acquisition process of the time synchronization message down to the hardware layer. This avoids the uncertainty and error accumulation problems caused by the software timestamp method, thereby achieving nanosecond-level time synchronization accuracy between the main control board and the service single board, and significantly improving the clock consistency between various functional units of the system.

[0057] This invention reduces reliance on external auxiliary logic or field-programmable gate arrays by unifying the processing of service data forwarding and time synchronization messages on the main control chip, making the system structure more compact, which helps to reduce system power consumption and improve the overall reliability and stability of the system.

[0058] By combining the dynamic sensing of the dual disk's in-place status with the primary / backup control mechanism, this invention can automatically switch the time synchronization role between the primary and backup disks and smooth the time adjustment during the switching process, avoiding sudden time changes caused by disk switching or communication path changes, thereby further improving the continuity and reliability of system time synchronization.

[0059] Specific implementation process:

[0060] (1) After the two main control boards are inserted into the main control slots and powered on, the first main board to start transmits main and backup information through the CPLD main / backup interconnection line. The main control board in the other slot is set as the dual board. The hardware framework of the dual board is the same as that of the main board, both containing two optical modules and three single-pole double-throw switches. When the equipment does not receive the main / backup 1588 time synchronization request:

[0061] (2) Optical modules SFP1 and SFP2 send service flow information to the switching chip VSC7436 through the high-speed SERDES port. The switching chip VSC7436 timestamps the service flow information for time synchronization.

[0062] (3) The network management port com is connected to the main control chip 98DX3258 (the service cross-connect chip of this board) through the HUB chip. The main control chip 98DX3258 realizes service fusion and cross-connection, transmits timestamps, and transmits synchronization information to the other end dual board in a timely manner.

[0063] After the network administrator sends the time synchronization command from primary and backup 1588:

[0064] (4) The CPLD module first checks the status of the dual disk. If it is in place, the CPLD module checks whether the heartbeat signal of the dual disk is normal.

[0065] (5) If the CPLD module detects that the heartbeat signal of the dual disk is normal, it executes the switching command to switch the single-pole double-throw digital switches SPDT1, SPDT2 and SPDT3. At this time, the optical modules SFP1, SFP2 and COM port are switched to the dual disk. The master and backup transmission line transmits the time information of this disk to the dual disk in a timely manner. The dual disk completes the 1588 master and backup time synchronization according to the reported information. At this time, the dual disk is upgraded to the master disk.

[0066] Table 1. Truth Table for Switching

[0067] Line sequence SPDT1 control line SPDT2 control line SPDT3 control line Take this disk 0 0 0 Connecting to the dual disk 1 1 1

[0068] (6) When this disk needs to receive information from optical module SFP1 and optical module SFP2, that is, when it needs to be upgraded to the master disk, the original dual disk re-executes steps (3) and (4), this disk is upgraded to the master disk, and the original dual disk is downgraded to the backup disk, which can reliably realize the 1588 time synchronization of the master and backup single disks.

[0069] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A master-backup single-disk time synchronization system for a communication device, characterized in that, It includes a main board and a dual board with the same structure. Each of the main board and the dual board includes a main control chip, a switching chip with a clock synchronization protocol, a HUB chip, an SFP optical module, a CPLD module, a single-pole double-throw digital switch SPDT1, and a single-pole double-throw digital switch SPDT2. The switching chip and the HUB chip of this board are both electrically connected to the main control chip. The SFP optical module of this board is electrically connected to the switching chip of this board or the switching chip of the dual board through the single-pole double-throw digital switch SPDT1. The network management port COM of this board is electrically connected to the HUB chip of this board or the HUB chip of the dual board through the single-pole double-throw digital switch SPDT2. The main control chip of the dual disk and the main control chip of the local disk are connected via a master-slave interconnection line electrical signal. The main control chips of both the local disk and the dual disk are externally connected to service disks. The CPLD module of the local disk or the dual disk is used to detect the existence status of the dual disk or the local disk, and dynamically switch the respective single-pole double-throw digital switch SPDT1 and single-pole double-throw digital switch SPDT2 according to the master-slave synchronization requirements.

2. The active-standby single-disk time synchronization system for a communication device according to claim 1, wherein, The main disk and the dual disk are each provided with at least two SFP optical modules, each including optical module SFP1 and optical module SFP2; The optical modules SFP1 and SFP2 of the main disk are electrically connected to the switching chip of the main disk or the switching chip of the dual disk through the single-pole double-throw digital switch SPDT1 and the single-pole double-throw digital switch SPDT3, respectively.

3. A primary / backup single-disk time synchronization system for communication equipment according to claim 2, characterized in that, The single-pole double-throw digital switches SPDT1, SPDT2, and SPDT3 are all model TS3A5018RSVR, and the enable pins of SPDT1, SPDT2, and SPDT3 are all controlled by the CPLD module.

4. A primary / backup single-disk time synchronization system for communication equipment according to claim 1, characterized in that, The switching chip is model VSC7436, and the clock synchronization protocol of the switching chip is IEEE1588.

5. A primary / backup single-disk time synchronization system for communication equipment according to claim 1, characterized in that, The switching chip and the HUB chip are respectively connected to the main control chip via SGMII serial ports.

6. A primary / backup single-disk time synchronization system for communication equipment according to claim 1, characterized in that, The main control chip is model 98DX3258.

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