Distributed converged communication domain applied to converged architecture

Abstract

The embodiment of the invention discloses a distributed converged communication domain applied to a converged architecture. The distributed converged communication domain comprises a first communication domain and a second communication domain, wherein the first communication domain is a communication domain corresponding to a classic computer in a converged system architecture; the second communication domain is a communication domain corresponding to a quantum computer in the fusion system architecture, the second communication domain comprises a quantum process group, the quantum process comprises a quantum device network address and a measurement and control board card number, the quantum device network address characterization is taken as a network address corresponding to the measurement and control board card of the quantum device, and the quantum device network address characterization is taken as a network address corresponding to the measurement and control board card of the quantum device; the number representation of the measurement and control board card is taken as a board card physical number corresponding to the measurement and control board card of the quantum device, and the number of the measurement and control board card included in the quantum process is distributed by the measurement and control board card driver. According to the implementation mode, basic environment support is provided for distributed computing of a'classic computer + quantum computer 'fusion system structure.

Description

Distributed converged communication domain applied to converged architecture Technical Field

[0001] The embodiments disclosed herein relate to the field of superconducting quantum computer communication protocols, and more specifically to a distributed converged communication domain applied to a converged architecture. Background Technology

[0002] As quantum computer architectures develop towards large-scale and distributed architectures, cross-node communication between classical computer control systems and quantum computers faces challenges such as high latency, complex processes, and low performance.

[0003] The communication domain is an important concept in the field of communication protocols. Taking the communication domain of a classic computer as an example, it is usually defined as a group of processes that can send messages to each other to describe the communication relationship between processes. Each process is assigned a unique identifier (called "rank") in the communication domain. The communication domain is often composed of communication context, process groups and virtual processor topology, etc., which are used to manage and schedule communication objects and related resources.

[0004] As is well known, the number of cores in a single computer is limited. When computing power reaches its limit, multi-machine parallelism is the optimal route to enhance computing power and improve scalability. In the field of distributed parallel computing, MPI (Message Passing Interface) is an important communication mechanism. In parallel computing, a communication domain defines an independent and closed communication environment, which clearly defines the processes that can communicate with each other, as well as the communication tasks corresponding to the control and maintenance of these processes. Specifically, communication domains are often divided into intra-group communication domains and component communication domains to realize communication between processes within the same process group, as well as communication between different process groups. For example, a communication domain can provide a secure "sandbox" environment to ensure that communication only occurs within a specified process group, thereby avoiding communication interference between different communication domains; another example is that a communication domain can independently manage process groups corresponding to different tasks in large-scale parallel computing tasks; yet another example is that a communication domain can give processes additional logical topology structures (such as Cartesian topology, graph topology), so that processes can be logically arranged into arbitrary graphs such as grids, thereby facilitating the perception of process positions.

[0005] With the exponential growth of data volume and the ever-increasing computational demands, the processing power of traditional classical computers is gradually approaching their corresponding physical and theoretical limits. To overcome this bottleneck, scientists are seeking new computational paradigms, making quantum computing a hot research topic. However, the physical realization of quantum computers is extremely complex, facing numerous challenges such as the creation and maintenance of qubits, precise control of quantum gates, accurate measurement of quantum states, and the stability and scalability of quantum systems. Therefore, the performance of current quantum computers is still insufficient to meet the needs of solving large-scale application problems.

[0006] The proposed hybrid architecture of "classical computer + quantum computer" offers a new path for the practical application of quantum computing. This architecture combines the powerful computing capabilities of quantum computers with the stability and ease of use of classical computers, helping to address some of the challenges faced by quantum computers when used independently. However, realizing the hybrid architecture also faces many challenges, and distributed quantum computing is currently one of the most promising approaches to achieving this hybrid architecture.

[0007] Distributed computing is a common computing power model in classical computing, and many mature distributed computing protocols exist, such as MPI. However, classical distributed computing protocols are not suitable for quantum computer-based distributed computing. For example, MPI supports multi-GPU distributed computing, where the mapping between processes and GPUs depends on the specific framework design, task type, and hardware resource configuration, resulting in various mapping methods such as "one-to-one," "one-to-many," and "many-to-one." The core goal is to achieve efficient utilization of GPU resources and parallel execution of tasks. In multi-GPU distributed computing, the mapping between processes and GPUs is not fixed but dynamically determined by runtime configuration, environment variables, or resource scheduling logic. Taking the "one-to-one" mapping as an example, process 0 of the same program might be mapped to GPU 0 the first time it runs, but could be mapped to GPU 1 the second time it runs. The mapping between process IDs and GPU physical IDs is not fixed and depends entirely on runtime environment configuration, resource status, or framework logic. Therefore, the same program's process could be mapped to any other GPU with an arbitrary physical ID the second time it runs. Quantum computer-based distributed computing cannot accept this non-fixed mapping between processes and physical quantum resources. Taking a superconducting quantum computer as an example, each quantum control board physically corresponds to a set of qubits. Because each qubit is unique, meaning its waveform control parameters are different, the configuration file for each qubit set corresponding to a quantum control board is different. To access a quantum control board, the correct waveform must be generated using the correct configuration file to actually access the qubit resources. For example, if quantum process 0 wants to use qubit resources, it will read the configuration file for the 0th qubit set. In this case, it must call the driver for the 0th quantum control board to run correctly. Therefore, in distributed quantum computing, each quantum process must physically correspond to a quantum control board, a problem that classical MPI communication cannot solve. Summary of the Invention

[0008] The summary portion of this disclosure is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description portion. This summary portion is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0009] Some embodiments of this disclosure propose a distributed converged communication domain for converged architectures to address the technical problems mentioned in the background section above.

[0010] In a first aspect, some embodiments of this disclosure provide a distributed converged communication domain applied to a converged architecture, wherein the distributed converged communication domain includes: a first communication domain and a second communication domain, wherein the first communication domain is a communication domain within the converged architecture corresponding to a classical computer; the second communication domain is a communication domain within the converged architecture corresponding to a quantum computer, wherein the second communication domain includes a quantum process group, wherein the quantum process includes: a quantum device network address and a measurement and control board number, wherein the quantum device network address represents the network address corresponding to the measurement and control board of the quantum device, and the measurement and control board number represents the physical number of the board corresponding to the measurement and control board of the quantum device, and the measurement and control board number included in the quantum process is allocated by the measurement and control board driver.

[0011] Secondly, some embodiments of this disclosure provide an electronic device, including: one or more processors; and a storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the distributed converged communication domain described in any implementation of the first aspect above.

[0012] Thirdly, some embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the distributed converged communication domain described in any of the implementations of the first aspect above.

[0013] The embodiments disclosed above have the following beneficial effects: they solve the problems of high latency, complex processes, and low performance in cross-node communication between classical and quantum computers in practical scenarios where quantum computer architectures are developing towards large-scale, distributed architectures. They provide a basic environmental support for distributed computing using a fusion architecture of "classical computer + quantum computer". Attached Figure Description

[0014] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0015] Figure 1 is a schematic diagram of the architecture between multiple measurement and control boards and quantum chips; Figure 2 is a schematic diagram of the communication process between processes under different circumstances; Figure 3 is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of this disclosure. Detailed Implementation

[0016] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0017] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0018] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0019] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0020] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0021] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] The distributed converged communication domain disclosed herein includes: a first communication domain and a second communication domain. The first communication domain is the communication domain corresponding to a classical computer within the converged architecture. The second communication domain is the communication domain corresponding to a quantum computer within the converged architecture. The second communication domain includes a quantum process group, where each quantum process includes: a quantum device network address and a measurement and control board number. The quantum device network address represents the network address corresponding to the measurement and control board of the quantum device. The measurement and control board number represents the physical board number corresponding to the measurement and control board of the quantum device. The measurement and control board number included in the quantum process is assigned by the measurement and control board driver.

[0023] In practice, the communication domain is crucial in distributed computing of classical computers. Similarly, a communication domain is needed in distributed computing of quantum computers for communication management between different processes. Based on the current state of quantum computer development, all physical quantum computer systems require independently arranged core components according to their physical characteristics. That is, the core components of a quantum computer must be independently placed in dedicated hardware devices, thus preventing high integration with traditional computers. For example, quantum computers in ion trap systems rely on vacuum and laser modules. Similarly, quantum computers in optical quantum systems rely on optical platforms. Furthermore, quantum computers in topological quantum systems rely on extreme environments. Likewise, quantum computers in superconducting systems rely on dilution refrigerators. This "physical isolation" is a fundamental premise of the current quantum computer architecture. Since the "physical isolation" of quantum computers is similar to the relationship between physical devices in distributed parallel scenarios of classical computers, this disclosure uses the communication domain design in MPI multi-machine parallelism as a reference to design the quantum communication domain (second communication domain). The core structure of the quantum communication domain is the quantum process group. In the quantum communication domain, a quantum process is essentially a classical process (non-quantum process) used to manage quantum resources, which can be quantum devices or sets of qubits.

[0024] In some optional implementations of some embodiments, the quantum processes in the above-mentioned quantum process group independently call the corresponding measurement and control board driver, the quantum device corresponding to the quantum process in the quantum process group controls the fixed-connected set of qubits, and the measurement and control board driver of the quantum device corresponding to the quantum process in the quantum process group independently controls the corresponding set of qubits.

[0025] In practice, taking a superconducting computer as an example, refer to Figure 1, which shows a schematic diagram of the architecture between multiple control boards and a quantum chip. Figure 1 shows control board A and control board B. Each control board can be considered a quantum device, connected to a fixed set of qubits. The configuration file for each control board is pre-set by the control personnel, and the control board driver is also present. Taking Figure 1 as an example, control board A corresponds to quantum processes "R0", "R1", and "R2". Control board B corresponds to quantum processes "R3", "R4", and "R5". Quantum processes "R0", "R1", "R2", "R3", "R4", and "R5" respectively control the fixed set of qubits in the quantum chip. Each quantum process in this disclosure corresponds to one control board. Each control board corresponds to a unique quantum device network address (IP, Internet Protocol) and control board number (Card_id). Therefore, the mapping relationship between each quantum process and its corresponding control board can be described as "rank = function(IP, Card_id)", where "function" is the mapping function. In this way, there is a physical correspondence between the quantum process and the control board, between the control board and the set of qubits, and between the quantum process and the set of qubits. That is, the quantum process can only call the control board driver corresponding to a fixed control board to control a fixed set of qubits.

[0026] Specifically, unlike the communication domain of classical computers, a key problem that the quantum communication domain (the second communication domain) needs to solve is how to fix the scheduling of quantum processes to corresponding quantum resources. On the hardware side, the control board driver assigns a unique physical number to the control board (e.g., 0, 1, 3…, which mainly corresponds to the hardware slot order of the control board). On the software side, the quantum communication domain records the physical information of the control board, namely the quantum device network address (IP, Internet Protocol) and the control board number (Card_id). When a quantum process starts, the process number corresponding to the quantum process is no longer randomly assigned like that of a classical process (non-quantum process). Instead, the quantum communication domain assigns the quantum device network address (IP, Internet Protocol) and the control board number (Card_id) to the quantum process. A mapping relationship is generated using "rank = function(IP, Card_id)", and the quantum process is bound to the control board corresponding to the control board number using the binding function "SetDevice(Card_id)".

[0027] Specifically, this disclosure defines the quantum process as a process responsible for calling the measurement and control board. The structure corresponding to the quantum process can be represented by the following code: typedef struct {const char* ip;int card_id;} MPIQ_Rank; where "ip" represents the network address of the quantum device, "card_id" represents the measurement and control board number, and "MPIQ_Rank" represents the quantum process.

[0028] Specifically, the quantum communication domain (second communication domain) is a process group composed of multiple quantum processes. Therefore, the structure corresponding to the quantum communication domain can be represented by the following code: `MPIQ_Rank *MPIQ_COMM_WORLD = {{ip_0, card_id_0}, / / Quantum process 0 {ip_1, card_id_1}, / / Quantum process 1 {ip_2, card_id_2}, / / Quantum process 2 {ip_3, card_id_3} / / Quantum process 3…….};` Where, "{ip_0, card_id_0}" is the network address and control board number of the quantum device corresponding to quantum process 0. "{ip_1, card_id_1}" is the network address and control board number of the quantum device corresponding to quantum process 1. "{ip_2, card_id_2}" is the network address and control board number of the quantum device corresponding to quantum process 0. "{ip_3, card_id_3}" is the network address and control board number of the quantum device corresponding to quantum process 0.

[0029] In some alternative implementations of some embodiments, the above-mentioned distributed converged communication domain is configured as follows: Step S1: Start the first communication domain included in the distributed converged communication domain by a start command.

[0030] The startup command can be either the mpirum command or the mpiexec command in MPI.

[0031] Step S2: In response to the startup of the first communication domain, read the quantum configuration file through the non-quantum process corresponding to the first communication domain.

[0032] The quantum configuration file stores the network address of the quantum device and the control board number corresponding to the accessible control board.

[0033] Step S3: According to the quantum configuration file, perform connectivity verification on the accessible measurement and control board.

[0034] Step S4: In response to the successful connectivity verification, the network address of the quantum device and the number of the control board corresponding to the accessible control board stored in the quantum configuration file are written into the second communication domain as a quantum process group.

[0035] In some optional implementations of certain embodiments, the first communication domain includes a non-quantum process group, wherein non-quantum processes in the non-quantum process group communicate with each other via MPI communication instructions, and quantum processes in the quantum process group communicate with each other via quantum communication instructions. The MPI communication instructions can be instructions such as MPI_Send / Recv. The quantum communication instructions can be instructions such as MPIQ_Send / Recv. MPIQ_Send / Recv are user-defined functions designed for data communication between quantum processes, suitable for both single-host and multi-host applications. This is implemented through a socket communication mechanism. For example, the MPIQ_Send function converts quantum waveform data into a double-type array, then encapsulates it into a data packet, and sends it via a network protocol (such as TCP) to a specific IP address and its network port (i.e., the IP address and board number corresponding to the target quantum process). In some optional implementations of certain embodiments, when the non-quantum processes in the first communication domain and the quantum processes in the second communication domain are located on the same computing node, the non-quantum processes and quantum processes achieve zero-copy data transfer through shared memory.

[0036] In some alternative implementations of certain embodiments, when the non-quantum process in the first communication domain and the quantum process in the second communication domain are not located on the same computing node, the non-quantum process and the quantum process communicate with each other through a socket communication mechanism.

[0037] In some alternative implementations of some embodiments, the non-quantum processes in the non-quantum process group included in the first communication domain synchronize their process clocks via the MPI_Brrier function.

[0038] In some alternative implementations of some embodiments, the quantum processes in the quantum process group included in the second communication domain synchronize their process clocks via a quantum clock.

[0039] In practice, the structure corresponding to the distributed converged communication domain can be represented by the following code: `typedef struct {MPI_Comm MPI_COMM_WORLD; MPIQ_Rank *MPIQ_COMM_WORLD;} MPI-Q_COMM_WORLD;` where "MPI-Q_COMM_WORLD" represents the distributed converged communication domain. "MPI_COMM_WORLD" represents the first communication domain (classical MPI communication domain). "*MPIQ_COMM_WORLD" represents the second communication domain (quantum communication domain). Specifically, the structure "MPI-Q_COMM_WORLD" simultaneously contains pointers to both the structure "MPI_Comm" and the structure "MPIQ_Rank," thus encapsulating the classical process (non-quantum process) and the quantum process together. When the distributed converged communication domain starts, the classical process (the non-quantum process corresponding to the first communication domain) is launched via the `mpirum` command or the `mpiexec` command (startup command). Classical processes (non-quantum processes) read the quantum configuration file (hostfile) corresponding to the quantum process through the MPIQ_Init function. This allows them to write the network address of the quantum device and the control board number corresponding to the accessible control board into the distributed converged communication domain. At the same time, the MPIQ_Init function also verifies the connectivity between all computing nodes (quantum processes) in the distributed converged communication domain to ensure the correctness of the distributed converged communication domain.

[0040] Specifically, in the distributed converged communication domain, communication between processes can be divided into the following three categories: (1) communication between non-quantum processes and non-quantum processes; (2) communication between quantum processes and quantum processes; and (3) communication between non-quantum processes and quantum processes. As an example, see the schematic diagram of the communication process between processes under different situations shown in Figure 2, where: for (1), functions such as MPI_Send / Recv are still used to maintain compatibility with traditional MPI programs.

[0041] For (2), functions such as MPIQ_Send / Recv (implemented at the underlying level through TCP control messages) are used to support the transmission of quantum waveform arrays corresponding to quantum processes.

[0042] For (3), classical processes (non-quantum processes) and quantum processes within the same computing node achieve zero-copy data transfer through shared memory, thereby improving communication efficiency; classical processes and quantum processes on different computing nodes exchange data through the SOCEKT communication mechanism.

[0043] Furthermore, the MPIQ_Barrier function is introduced in the distributed converged communication domain. This function simultaneously implements the functionality of the classical MPI_Barrier function and the quantum clock synchronization function. When classical processes (non-quantum processes) in the distributed converged communication domain need to synchronize, MPIQ_Barrier calls the MPI_Barrier function; when quantum processes in the distributed converged communication domain need to synchronize, MPIQ_Barrier calls the driver that controls the clock triggering of the quantum devices, ensuring synchronization between the quantum gate level and the process level.

[0044] Referring now to FIG3, a schematic diagram of the structure of an electronic device (e.g., a computing device) 300 suitable for implementing some embodiments of the present disclosure is shown. The electronic device shown in FIG3 is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of the present disclosure.

[0045] As shown in Figure 3, the electronic device 300 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory 302 or a program loaded from a storage device 308 into a random access memory 303. The random access memory 303 also stores various programs and data required for the operation of the electronic device 300. The processing unit 301, the read-only memory 302, and the random access memory 303 are interconnected via a bus 304. An input / output interface 305 is also connected to the bus 304.

[0046] Typically, the following devices can be connected to the input / output interface 305: input devices 306 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 307 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 308 including, for example, magnetic tape, hard disk, etc.; and communication devices 309. Communication devices 309 allow the electronic device 300 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 3 shows an electronic device 300 with various devices, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Each box shown in Figure 3 may represent one device, or multiple devices may be represented as needed.

[0047] In particular, according to some embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 309, or installed from a storage device 308, or installed from a read-only memory 302. When the computer program is executed by the processing device 301, it performs the functions defined in the methods of some embodiments of this disclosure.

[0048] It should be noted that, in some embodiments of this disclosure, the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In some embodiments of this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0049] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol), and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0050] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable medium carries one or more programs.

[0051] Computer program code for performing operations of some embodiments of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0052] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0053] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0054] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. A distributed converged communication domain applied to a converged architecture, characterized in that, The distributed converged communication domain includes: a first communication domain and a second communication domain, wherein: the first communication domain is the communication domain corresponding to the classical computer within the converged architecture; the second communication domain is the communication domain corresponding to the quantum computer within the converged architecture, wherein the second communication domain includes a quantum process group, and the quantum process includes: the quantum device network address and the measurement and control board number, wherein the quantum device network address represents the network address corresponding to the measurement and control board of the quantum device, and the measurement and control board number represents the physical number of the board corresponding to the measurement and control board of the quantum device, and the measurement and control board number included in the quantum process is allocated by the measurement and control board driver.

2. The distributed converged communication domain applied to a converged architecture according to claim 1, characterized in that, The quantum processes in the quantum process group independently call the corresponding measurement and control board drivers. The quantum devices corresponding to the quantum processes in the quantum process group control the fixed set of qubits. The measurement and control board drivers of the quantum devices corresponding to the quantum processes in the quantum process group independently control the corresponding set of qubits.

3. The distributed converged communication domain applied to a converged architecture according to claim 2, characterized in that, The distributed converged communication domain is configured to: initiate a first communication domain included in the distributed converged communication domain via a start command; in response to the initiation of the first communication domain, read the quantum configuration file through the non-quantum process corresponding to the first communication domain, wherein the quantum configuration file stores the quantum device network address and the measurement and control board number corresponding to the accessible measurement and control board; perform connectivity verification on the accessible measurement and control board according to the quantum configuration file; in response to the connectivity verification passing, write the quantum device network address and the measurement and control board number corresponding to the accessible measurement and control board stored in the quantum configuration file as a quantum process group into the second communication domain.

4. The distributed converged communication domain applied to a converged architecture according to claim 3, characterized in that, The first communication domain includes: a non-quantum process group, wherein non-quantum processes in the non-quantum process group communicate with each other via MPI communication instructions, and quantum processes in the quantum process group communicate with each other via quantum communication instructions.

5. The distributed converged communication domain applied to a converged architecture according to claim 4, characterized in that, When the non-quantum process in the first communication domain and the quantum process in the second communication domain are located on the same computing node, the non-quantum process and the quantum process achieve zero-copy data transfer by sharing memory.

6. The distributed converged communication domain applied to a converged architecture according to claim 5, characterized in that, When the non-quantum process in the first communication domain and the quantum process in the second communication domain are not located on the same computing node, the non-quantum process and the quantum process communicate with each other through a socket communication mechanism.

7. The distributed converged communication domain applied to a converged architecture according to claim 6, characterized in that, The non-quantum processes in the non-quantum process group included in the first communication domain synchronize their process clocks using the MPI_Brrier function.

8. The distributed converged communication domain applied to a converged architecture according to claim 7, characterized in that, The quantum processes in the quantum process group included in the second communication domain synchronize their process clocks via a quantum clock.

9. An electronic device, characterized in that, include: One or more processors; A storage device having one or more programs stored thereon; when the one or more programs are executed by the one or more processors, the one or more processors implement the distributed converged communication domain as described in any one of claims 1 to 7.

10. A computer-readable medium, characterized in that, It stores a computer program, wherein the computer program, when executed by a processor, implements the distributed converged communication domain as described in any one of claims 1 to 7.

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