Video signal processing method and device, and storage medium

Abstract

The invention provides a video signal processing method and device, and a storage medium. The method comprises the following steps: acquiring a video source signal at a video interface of a video input channel; monitoring a corresponding source clock frequency, a DDR clock polarity, an enable signal polarity and a synchronization signal polarity according to the video source signal; after the polarity of the synchronization signal is monitored, monitoring a frame header, a time sequence control parameter and odd-even field information of the synchronization signal; when any one of the source clock frequency, the frame header of the synchronous signal and the time sequence control parameter is monitored to be abnormal, generating corresponding abnormal interruption and recording the abnormal interruption in a register; and playing the video source signal based on the obtained time sequence parameter. On the basis, the time sequence parameters of the video signals including the unknown video source can be automatically detected, the time sequence parameters are automatically reported and recorded when the video signals are abnormal, manual intervention is not needed, and problems can be found in the design stage.

Description

Video signal processing methods, equipment, and storage media Technical Field

[0001] This application relates to the fields of video processing, timing monitoring, and timing analysis, specifically to a video signal processing method, device, and storage medium. Background Technology

[0002] In video interface technology, timing refers to the arrangement and transmission order of video signals over time, directly affecting whether the image can be displayed correctly. Therefore, timing detection of video interfaces is crucial in video system design, production, and maintenance, as it directly impacts video signal quality and system stability. Currently, playback systems primarily obtain standard timing parameters from manufacturers beforehand or pre-configure them during production, then configure the necessary playback parameters based on these standard timing parameters. However, the transmission and display of video signals involves multiple technologies and standards, and different video standards have different requirements for video signal timing. When the input video signal is from an unknown video source, if the original standard timing parameters are still used, the playback system will find it difficult to configure the parameters correctly, potentially leading to display failure. This significantly limits the application scenarios, restricting its use to environments with known video sources.

[0003] Furthermore, when abnormalities occur during playback of unknown video sources, manual intervention is required to locate and resolve the issues, resulting in high costs and technical complexity, while also affecting the stability and reliability of the playback system. In addition, existing technologies can only verify whether the monitoring performance of timing parameters meets expectations based on the playback results, making it difficult to achieve verification during the design phase. If problems are not detected in the early stages of design, it may lead to rework in the subsequent production process, wasting both costs and time. Summary of the Invention

[0004] In view of this, this application provides a video signal processing method, device, and storage medium that can automatically detect the timing parameters of unknown video sources, facilitate the automatic configuration of playback parameters to ensure the normal display of video images, and automatically report and record when abnormal timing parameters are detected, without manual intervention. It also allows problems to be discovered in the design stage, avoiding rework in the subsequent production process and saving costs and time.

[0005] This application provides a video signal processing method, comprising: acquiring a video source signal at a video interface of a video input path; monitoring and obtaining the source clock frequency, DDR clock polarity, enable signal polarity, and synchronization signal polarity corresponding to the video source signal based on the video source signal; after monitoring and obtaining the polarity of the synchronization signal, monitoring and obtaining the frame header, timing control parameters, and parity field information of the synchronization signal based on the video source signal; when any one of the source clock frequency, the frame header, and timing control parameters of the synchronization signal is detected to be abnormal, generating a corresponding abnormal interrupt and reporting and recording it in a register; and playing the video source signal based on the source clock frequency, DDR clock polarity, enable signal polarity, and the polarity, frame header, timing control parameters, and parity field information of the synchronization signal.

[0006] Optionally, the method for monitoring the source clock frequency corresponding to the video source signal includes: obtaining the IO register clock and using it as a reference clock f. IO Set the counting period N; start counting under the IO register clock and the source clock; when the count value under the IO register clock reaches N-1, generate a pulse signal; synchronize the pulse signal to the clock domain corresponding to the source clock, obtain the current count value Sclk_cnt under the source clock, and calculate the count value according to the formula f = (Sclk_cnt / N)*f IO The source clock frequency f is calculated.

[0007] Optionally, the method for monitoring the DDR clock polarity corresponding to the video source signal includes: identifying a preset mode from the video source signal, wherein the preset mode includes any one of SAV / EAV mode, VSYNC mode, HSYNC mode, and enable mode; determining the DDR clock polarity based on the clock sampling value in the preset mode, including any one of the following: in the SAV / EAV mode, if the sampling value of the rising edge of the clock is the expected code, then the DDR clock polarity is determined to be 0, and if the sampling value of the falling edge of the clock is the expected code, then the DDR clock polarity is determined to be 1; in the VSYNC mode, HSYNC mode, or enable mode, if the sampling values ​​of the rising edge and falling edge of the same clock are different, then the DDR clock polarity is determined to be 1, and if the sampling value of the falling edge of the previous clock is different from the sampling value of the rising edge of the current clock, then the DDR clock polarity is determined to be 0.

[0008] Optionally, the method for monitoring the polarity of the enable signal corresponding to the video source signal includes: taking two adjacent rising edges of the enable signal as a monitoring cycle; counting the high and low levels of the enable signal in two monitoring cycles; comparing the count values ​​of the high and low levels in the second monitoring cycle; if the count value of the high level in the second monitoring cycle is less than the count value of the low level, then determining that the polarity of the enable signal is negative; if the count value of the high level in the second monitoring cycle is greater than the count value of the low level, then determining that the polarity of the enable signal is positive.

[0009] Optionally, the method for detecting the polarity of the synchronization signal corresponding to the video source signal includes: counting the high level, low level, and rising edge of the horizontal synchronization signal respectively; when the second rising edge of the horizontal synchronization signal is detected, comparing the count values ​​of the high level and the low level; if the count value of the high level is greater than the count value of the low level, then the polarity of the horizontal synchronization signal is determined to be negative; if the count value of the high level is less than the count value of the low level, then the polarity of the horizontal synchronization signal is determined to be positive; counting the high level, low level, and rising edge of the vertical synchronization signal respectively; when the second rising edge of the vertical synchronization signal is detected, comparing the count values ​​of the high level and the low level; if the count value of the high level is greater than the count value of the low level, then the polarity of the vertical synchronization signal is determined to be negative; if the count value of the high level is less than the count value of the low level, then the polarity of the vertical synchronization signal is determined to be positive.

[0010] Optionally, the method of obtaining the frame header of the synchronization signal based on the video source signal monitoring includes: detecting a field synchronization signal; and detecting that the V value of the SAV signal is 1 and the V value of the EAV signal is 0.

[0011] Optionally, the method of obtaining the timing control parameters of the synchronization signal based on the video source signal monitoring includes: monitoring the length of the field synchronization signal; monitoring the length of the line synchronization signal; monitoring the length of the field display leading edge; monitoring the length of the field display trailing edge; monitoring the length of the line display leading edge; monitoring the length of the line display trailing edge; monitoring the image width and height; and monitoring the position of the pixels of the video source signal in the image.

[0012] Optionally, the method of obtaining the odd / even field information of the synchronization signal based on the video source signal monitoring includes: when the time interval between the transition edges of the field synchronization signal and the line synchronization signal is detected to be within a first time interval, the synchronization signal is determined to be in an odd field state; when the time interval between the transition edges of the field synchronization signal and the line synchronization signal is detected to be within a second time interval, the synchronization signal is determined to be in an even field state.

[0013] Optionally, the methods for monitoring abnormalities in the source clock frequency include: determining that the source clock frequency is abnormal if the difference between the count values ​​Sclk_cnt of the source clock in two adjacent counting cycles reaches a preset value; the methods for monitoring abnormalities in the frame header of the synchronization signal include: generating a preset interrupt after determining that a frame header of the synchronization signal has appeared, and determining that the frame header monitoring of the synchronization signal is abnormal if no frame header is detected within a preset time after the preset interrupt; and the methods for monitoring abnormalities in the timing control parameters include: determining that the timing control parameters are abnormal if the detection value of the field synchronization signal is different in each field or the detection value of the line synchronization signal is different in each line.

[0014] This application provides a video signal processing device, including a processor and a memory. The memory stores a processing program, which, when executed by the processor, implements the steps of the video signal processing method described in any of the above claims.

[0015] This application provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-described video signal processing methods.

[0016] As described above, this application acquires video source signals at the video interface of the video input path and automatically monitors and obtains corresponding timing parameters in real time, including source clock frequency, DDR clock polarity, enable signal polarity, synchronization signal polarity, frame header, timing control parameters, and odd / even field information. Even for unknown video sources, the corresponding timing parameters can be automatically monitored and obtained, which is beneficial for automatically configuring playback parameters to ensure normal display of video images. Furthermore, when any abnormality is detected in the source clock frequency, the frame header of the synchronization signal, or the timing control parameters, a corresponding abnormal interrupt is generated and reported and recorded in the register, thus realizing automatic monitoring and reporting of abnormalities without manual intervention. This allows problems to be discovered during the design phase, avoiding rework in the subsequent production process and saving costs and time. Attached Figure Description

[0017] Figure 1 is a flowchart illustrating a video signal processing method according to an embodiment of this application; Figure 2 is a structural diagram illustrating a video signal processing device according to an embodiment of this application. In order to solve the above-mentioned problems in the prior art, this application provides a video signal processing method, device, and storage medium. These protection subjects are based on the same concept, and the principles for solving the problems are basically the same or similar. The implementation methods of each protection subject can be referred to mutually, and the repeated parts will not be described in detail.

[0018] In the solution of this application, the video source signal is acquired at the video interface of the video input path, and the corresponding timing parameters are automatically monitored in real time, including the source clock frequency, DDR clock polarity, enable signal polarity, synchronization signal polarity, frame header, timing control parameters, and parity field information. Even for unknown video sources, the corresponding timing parameters can be automatically monitored, which is conducive to automatically configuring playback parameters to ensure the normal display of video images. Furthermore, when any abnormality is detected in the source clock frequency, the frame header of the synchronization signal, or the timing control parameters, a corresponding abnormal interrupt is generated and reported and recorded in the register. This achieves automatic monitoring and reporting of abnormalities without manual intervention, and allows problems to be discovered during the design phase, avoiding rework in the subsequent production process and saving costs and time.

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only a part of the embodiments of this application, and not all of them. Unless otherwise specified, the following embodiments and their technical features can be combined with each other, and also belong to the technical solutions of this application.

[0020] Figure 1 is a schematic flowchart of a video signal processing method provided in an embodiment of this application. The video signal processing method may also be referred to as a "method" or "processing method," and the executing entity of each step may be a suitable video signal processing device, a device for performing video playback, or a storage medium, processor, controller, etc. with video signal analysis function.

[0021] Referring to Figure 1, the method includes at least the following steps S1 to S5.

[0022] S1. Acquire video source signals at the video interface of the video input path.

[0023] S2. Based on the video source signal, monitor and obtain the source clock frequency, DDR clock polarity, enable signal polarity, and synchronization signal polarity corresponding to the video source signal.

[0024] In one example, methods for monitoring the source clock frequency include: obtaining the I / O register clock and using it as a reference clock f. IO The counting period N is set, and counting begins under the clock of the IO register and the source clock. When the count value under the clock of the IO register reaches N-1, a pulse signal is generated. The pulse signal is then synchronized to the clock domain corresponding to the source clock to obtain the current count value Sclk_cnt under the source clock, and the result is calculated according to the formula f = (Sclk_cnt / N)*f. IO The source clock frequency f is calculated.

[0025] For example, using the I / O register clock as the reference clock, and 1000 clock monitoring cycles as one counting cycle, with N set to 1000, counting is performed under both the I / O register clock and the source clock. When the counter under the I / O register clock reaches 999, an end pulse is generated as the pulse signal, and the counter is cleared. This pulse signal is synchronized to the source clock domain, and the count value Sclk_cnt of the counter under the source clock domain is cleared. The source clock frequency f is then calculated. In practical scenarios, the clock may be unstable when the playback system is first powered on, so the monitoring value of the first clock monitoring cycle can be discarded.

[0026] In one example, the method for monitoring the DDR (Double Data Rate SDRAM) clock polarity includes: firstly, identifying a preset mode from the video source signal, the preset mode including any one of SAV (Start of Active Video) / EAV (End of Active Video) mode, VSYNC (vertical sync signal) mode, HSYNC (horizontal sync signal) mode, and enable mode; then, determining the DDR clock polarity based on the clock sampling value in the preset mode, including any one of the following: in the SAV / EAV mode, if the sampling value of the rising edge of the clock is the expected code, the DDR clock polarity is determined to be 0, and if the sampling value of the falling edge of the clock is the expected code, the DDR clock polarity is determined to be 1; in the VSYNC mode, HSYNC mode, or enable mode, if the sampling values ​​of the rising edge and falling edge of the same clock are different, the DDR clock polarity is determined to be 1, and if the sampling value of the falling edge of the previous clock is different from the sampling value of the rising edge of the current clock, the DDR clock polarity is determined to be 0.

[0027] Taking the expected code 3FF as an example, specifically, in SAV / EAV mode, if the sample value of the rising edge of the clock is 3FF (i.e., the expected code), then the DDR clock polarity (i.e., ddr_clkp) is 0; if the sample value of the falling edge of the clock is 3FF, then the DDR clock polarity is 1. It should be noted that the code value of the expected code can be determined according to the actual scenario and requirements.

[0028] In the vertical sync signal mode (i.e., VSYNC mode), the sampled signal is the vertical sync signal; in the horizontal sync signal mode (i.e., HSYNC mode), the sampled signal is the horizontal sync signal; in the enable mode, the sampled signal is the enable signal (de signal). In these three modes, the sampled signal is sampled twice, once on the rising edge of the clock and once on the falling edge of the clock. If the sampled value on the rising edge of the same clock is different from the sampled value on the falling edge, the DDR clock polarity is 1. If the sampled value on the falling edge of the previous clock is different from the sampled value on the rising edge of the current clock, the DDR clock polarity is 0.

[0029] In one example, the method for monitoring the polarity of the enable signal includes: using two adjacent rising edges of the enable signal as a monitoring cycle; counting the high and low levels of the enable signal separately within two monitoring cycles; comparing the count values ​​of the high and low levels within the second monitoring cycle; if the count value of the high level is less than the count value of the low level within the second monitoring cycle, then determining that the polarity of the enable signal is negative; if the count value of the high level is greater than the count value of the low level within the second monitoring cycle, then determining that the polarity of the enable signal is positive.

[0030] The synchronization signal includes a horizontal synchronization signal and a vertical synchronization signal. Therefore, monitoring the polarity of the synchronization signal includes: monitoring the polarity of the horizontal synchronization signal and monitoring the polarity of the vertical synchronization signal. The method for monitoring the polarity of the synchronization signal includes: counting the high level, low level, and rising edge of the horizontal synchronization signal respectively; when the second rising edge of the horizontal synchronization signal is detected, comparing the count values ​​of the high level and the low level; if the count value of the high level is greater than the count value of the low level, then the polarity of the horizontal synchronization signal is determined to be negative; if the count value of the high level is less than the count value of the low level, then the polarity of the horizontal synchronization signal is determined to be positive. Similarly, counting the high level, low level, and rising edge of the vertical synchronization signal respectively; when the second rising edge of the vertical synchronization signal is detected, comparing the count values ​​of the high level and the low level; if the count value of the high level is greater than the count value of the low level, then the polarity of the vertical synchronization signal is determined to be negative; if the count value of the high level is less than the count value of the low level, then the polarity of the vertical synchronization signal is determined to be positive.

[0031] S3. After monitoring the polarity of the synchronization signal, the frame header, timing control parameters and odd / even field information of the synchronization signal are obtained based on the video source signal.

[0032] The frame header of the synchronization signal can be considered as the start signal of the detected field synchronization signal. This application can use one of the following two conditions to detect the frame header of the synchronization signal.

[0033] Condition 1: Field synchronization signal is detected; Condition 2: The V value of the SAV signal is 1 and the V value of the EAV signal is 0.

[0034] In the SAV / EAV mode, the SAV and EAV signals are identified by a specific 4-byte code sequence, where the V value (i.e., the control bit) indicates the signal type and state. When the V value of SAV is 1, it indicates the start of video; when the V value of EAV is 0, it indicates the end of video. Therefore, when the V value of SAV is 1 and the V value of EAV is 0, it indicates that complete frame header information has been detected. This detection mechanism is used to accurately identify the start and end positions of video frames, ensuring the correct parsing and display of video data.

[0035] The timing control parameters of the synchronization signal include: the length of the field synchronization signal, the length of the line synchronization signal, the length of the field display leading edge, the length of the field display trailing edge, the length of the line display leading edge, the length of the line display trailing edge, the image width, the image height, and the starting positions of the field synchronization signal and the line synchronization signal.

[0036] Hereinafter, the timing control parameters are monitored in the following eight ways: (1) Monitoring the length of the field synchronization signal: the field synchronization signal is counted according to its polarity to obtain the length of the field synchronization signal; (2) Monitoring the length of the line synchronization signal: the line synchronization signal is counted according to its polarity to obtain the length of the line synchronization signal; (3) Monitoring the length of the leading edge of the field display: if the enable mode is not turned on, even if the enable signal is continuously in a low level state, it indicates that the system has not detected valid video data, and the length of the leading edge of the field display is determined to be 0; if the enable mode is turned on, the line synchronization signal is counted before the field synchronization signal arrives, and the count value is used as the length of the leading edge of the field display. (4) Detect the length of the field display trailing edge: If only the sync signal (sync) mode is turned on, the length of the field display trailing edge (vback), the length of the field active data (vact), and the length of the field display leading edge (vfront) are detected, and the sum of the three is taken as the length of the field display trailing edge; if only the enable mode or SAV / EAV mode is turned on, the field blanking (vblank) length is detected and taken as the length of the field display trailing edge, wherein, in the enable mode, the detection of the field blanking length is based on the known line blanking (hblank) length and line active data (hact) length; if the sync mode and the enable mode are turned on at the same time, when the enable signal and the field sync signal are both 0 , and after the field synchronization signal arrives, the line synchronization signal is counted, and the count value is used as the length of the field display trailing edge; (5) The length of the line display leading edge is monitored: if the enable mode is not turned on, the length of the line display leading edge is determined to be 0; if the enable mode is turned on, the field synchronization signal is counted before the enable signal and the line synchronization signal are both 0 and the line synchronization signal arrives, and the count value is used as the length of the line display leading edge; (6) The length of the line display trailing edge is monitored: if only the sync mode is turned on, the length of the line display trailing edge (hback), the length of the line valid data (hact), and the length of the line display leading edge (hfront) are detected, and the sum of the three is used as the length of the line display trailing edge; if only the enable mode or SAV / In EAV mode, the length of the horizontal blanking (hblank) is monitored and used as the length of the horizontal display trailing edge; if sync mode and enable mode are turned on at the same time, the field sync signal is counted after the horizontal sync signal arrives when both the enable signal and the horizontal sync signal are 0, and the count value is used as the length of the horizontal display trailing edge; (7) Monitor the image width: in enable mode, the enable signal is counted and the count value is used as the image width; in SAV / EAV mode, the interval from the start point of the effective video to the end point of the effective video is counted and the count value is used as the image width; in other modes, the image width is 0; Monitor the image height: in enable mode, the rising edge of the enable signal is counted and the count value is used as the image height;In SAV / EAV mode, the starting point of the valid video is counted, and the count value is used as the image height; in other modes, the image height is 0; (8) Monitor the position of the pixel of the current input source (i.e., the video source signal) in the image: By starting the count from the frame start signal (Frame Sync) or field start signal (Field Sync), the system can accurately identify the position of the current pixel, thereby better understanding the current state of the input source.

[0037] In one example, the method for monitoring the odd / even field information includes: when the time interval between the transition edges of the field synchronization signal and the line synchronization signal is detected to be within a first time interval, the synchronization signal is determined to be in an odd field state; when the time interval between the transition edges of the field synchronization signal and the line synchronization signal is detected to be within a second time interval, the synchronization signal is determined to be in an even field state.

[0038] Taking a first time interval of [-16, 16] as an example, the second time interval can be [-16, 16]. When the time interval between the transition edges of the field synchronization signal and the line synchronization signal is detected to be within [-16, 16], the synchronization signal is determined to be in the top field state, i.e., the odd field state. When the time interval between the transition edges of the field synchronization signal and the line synchronization signal is detected to be within [htotal / 2-16, htotal / 2+16], the synchronization signal is determined to be in the bottom field state, i.e., the even field state. Here, htotal is the total horizontal period (Horizontal Total), which in the timing specification of video signals represents the total number of pixel periods per line.

[0039] S4. When any abnormality is detected in the source clock frequency, the frame header of the synchronization signal, or any timing control parameter, a corresponding abnormal interrupt is generated and reported and recorded in the register.

[0040] In one example, if the difference between the count values ​​Sclk_cnt of the source clock in two adjacent counting cycles N reaches a preset value, it is determined that the source clock frequency is abnormal.

[0041] In one example, after determining that a frame header of a synchronization signal has appeared, a preset interrupt (frame_start terminal) is generated. If no frame header is detected within a preset time after the preset interrupt, it is determined that the frame header monitoring of the synchronization signal is abnormal. Alternatively, if the continuous ineffective length of the enable signal is detected to be greater than a preset multiple of the image width; for example, in DE / CVBS_IN mode, that is, in the mode combining enable signal detection and composite video signal input (CVBS), the continuous ineffective length of the enable signal, that is, the time during which the enable signal is continuously at a low level, corresponds to the horizontal blanking period of each line of the video signal. When the continuous ineffective length of the enable signal is detected to be greater than 8 times the image width, it can be regarded as a serious fault sign of synchronization signal loss or signal abnormality, and it is determined that the frame header monitoring is abnormal.

[0042] In one example, if the detected value of the field synchronization signal is different in each field, or the detected value of the line synchronization signal is different in each line, then it is determined that the timing control parameter is abnormal.

[0043] When any of the above three items malfunction, the corresponding abnormal parameters can be written into the corresponding registers. This allows for subsequent analysis of the abnormal parameters to take appropriate actions, ensuring the system returns to normal operation and thus improving the system's stability and reliability.

[0044] S5. Based on the source clock frequency, DDR clock polarity, enable signal polarity, synchronization signal polarity, frame header, timing control parameters, and odd / even field information, the video source signal is played.

[0045] For the functions of the seven parameters—source clock frequency, DDR clock polarity, enable signal polarity, synchronization signal polarity, frame header, timing control parameters, and parity field information—please refer to existing technologies. By monitoring these seven parameters, the playback software can be configured with the correct parameters, similar to configuring the correct driver for a computer application, thereby ensuring the normal playback and display of the video signal.

[0046] Based on the methods described in S1 to S5, this application can automatically detect and obtain the corresponding timing parameters even for unknown video sources. This facilitates the automatic configuration of playback parameters to ensure the normal display of video images. The unknown video source can be regarded as a video source that does not use standard timing parameters or a video source whose timing parameters are not known in advance. For example, this application can support the normal playback of any unknown video source such as bt601, bt656, bt1120, hdmi_rx, cvbs_in. Furthermore, when any abnormality is detected in the source clock frequency, the frame header of the synchronization signal, or any timing control parameter, a corresponding abnormal interrupt is generated and reported and recorded in the register. This achieves automatic detection and reporting of abnormalities without manual intervention, allowing problems to be discovered during the design phase, avoiding rework in the subsequent production process, and saving costs and time.

[0047] This application embodiment also provides a storage medium storing a video signal processing program, also known as a processing program. This processing program is essentially a computer program, and when executed by a processor, it implements the steps of the video signal processing method of any of the foregoing examples.

[0048] The storage medium includes, but is not limited to, any one of read-only memory (ROM), random access memory (RAM), magnetic disk, and optical disk.

[0049] Since the program stored in the storage medium can execute the steps in the video signal processing method of any embodiment provided in this application, the beneficial effects that the video signal processing method of any of the foregoing embodiments can achieve can be realized. For details, please refer to the foregoing embodiments, which will not be repeated here.

[0050] This application also provides a video signal processing device or chip, including a memory and a processor. The memory stores a processing program, which, when executed by the processor, implements the steps of the video signal processing method of any of the foregoing embodiments; and / or, the video signal processing device or chip is provided with a storage medium as shown in the above example, and the processor loads the storage medium to execute the steps of the processing method, thereby achieving the beneficial effects that the processing method of the corresponding embodiment can achieve.

[0051] Figure 2 is a schematic diagram of a video signal processing device provided in an embodiment of this application. As shown in Figure 2, the video signal processing device 20, also referred to as processing device 20, includes: an acquisition module 21, used to acquire video source signals at the video interface of the video input path; a first monitoring module 22, used to monitor and obtain the source clock frequency, DDR clock polarity, enable signal polarity, and synchronization signal polarity corresponding to the video source signal based on the video source signal; a second monitoring module 23, used to monitor and obtain the frame header, timing control parameters, and parity field information of the synchronization signal after detecting the polarity of the synchronization signal based on the video source signal; an anomaly monitoring module 24, used to generate a corresponding anomaly interrupt and report and record it in a register when any one of the source clock frequency, the frame header, and timing control parameters of the synchronization signal is detected to be abnormal; and a processing module 25, used to play the video source signal based on the source clock frequency, DDR clock polarity, enable signal polarity, and the polarity, frame header, timing control parameters, and parity field information of the synchronization signal.

[0052] Through the cooperation of the above modules, the processing and playback of the video signal are completed.

[0053] It should be understood that the various modules of the processing device 20 described above can be represented as physical devices or virtual modules (i.e., commonly referred to as logical modules) in actual scenarios. A single module can be implemented by a single physical device or by two or more physical devices working together. Similarly, the function performed by a single module can be implemented by a single physical device or by two or more physical devices working together. Furthermore, the functions corresponding to each module can be implemented by the corresponding steps of the video signal processing method of any of the foregoing embodiments.

[0054] The above are only some embodiments of this application and do not limit the patent scope of this application. For those skilled in the art, any equivalent structural transformations made using the content of this specification and drawings are similarly included within the patent protection scope of this application.

[0055] The use of step designations such as S1 and S2 in this document is intended to more clearly and concisely describe the corresponding content and does not constitute a substantial restriction on the order. In specific implementation, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the protection scope of this application.

[0056] Although this document uses terms such as "first," "second," etc., to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. Furthermore, the singular forms "a," "an," and "the" are intended to also include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination thereof. Exceptions to this definition only arise when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

Claims

1. A method for processing video signals, characterized in that, include: Acquire video source signals at the video interface of the video input path; Based on the video source signal, the source clock frequency, DDR clock polarity, enable signal polarity, and synchronization signal polarity corresponding to the video source signal are monitored and obtained. After monitoring and obtaining the polarity of the synchronization signal, the frame header, timing control parameters, and odd / even field information of the synchronization signal are obtained based on the video source signal. When any abnormality is detected in the source clock frequency, the frame header of the synchronization signal, or the timing control parameters, a corresponding abnormal interrupt is generated and reported and recorded in the register; based on the source clock frequency, DDR clock polarity, enable signal polarity, synchronization signal polarity, frame header, timing control parameters, and odd / even field information, the video source signal is played.

2. The method according to claim 1, characterized in that, The method for monitoring and obtaining the source clock frequency corresponding to the video source signal includes: acquiring the IO register clock and using it as a reference clock f. IO Set the counting period N; start counting under the IO register clock and the source clock; when the count value under the IO register clock reaches N-1, generate a pulse signal; synchronize the pulse signal to the clock domain corresponding to the source clock, obtain the current count value Sclk_cnt under the source clock, and calculate the count value according to the formula f = (Sclk_cnt / N)*f IO The source clock frequency f is calculated.

3. The method according to claim 1, characterized in that, The method for monitoring the DDR clock polarity corresponding to the video source signal includes: identifying a preset mode from the video source signal, wherein the preset mode includes any one of SAV / EAV mode, VSYNC mode, HSYNC mode, and enable mode; determining the DDR clock polarity based on the clock sampling value in the preset mode, including any one of the following: in the SAV / EAV mode, if the sampling value of the rising edge of the clock is the expected code, then the DDR clock polarity is determined to be 0, and if the sampling value of the falling edge of the clock is the expected code, then the DDR clock polarity is determined to be 1; in the VSYNC mode, HSYNC mode, or enable mode, if the sampling values ​​of the rising edge and falling edge of the same clock are different, then the DDR clock polarity is determined to be 1, and if the sampling value of the falling edge of the previous clock is different from the sampling value of the rising edge of the current clock, then the DDR clock polarity is determined to be 0.

4. The method according to claim 1, characterized in that, The method for monitoring the polarity of the enable signal corresponding to the video source signal includes: taking two adjacent rising edges of the enable signal as a monitoring cycle, counting the high and low levels of the enable signal within two monitoring cycles; comparing the count values ​​of the high and low levels within the second monitoring cycle; if the count value of the high level within the second monitoring cycle is less than the count value of the low level, then determining that the polarity of the enable signal is negative; if the count value of the high level within the second monitoring cycle is greater than the count value of the low level, then determining that the polarity of the enable signal is positive; the method for monitoring the polarity of the synchronization signal corresponding to the video source signal includes: counting the high and low levels of the horizontal synchronization signal and... The rising edges of the horizontal sync signal are counted separately. When the second rising edge of the horizontal sync signal is detected, the count values ​​of the high level and the low level are compared. If the count value of the high level is greater than the count value of the low level, the polarity of the horizontal sync signal is determined to be negative; if the count value of the high level is less than the count value of the low level, the polarity of the horizontal sync signal is determined to be positive. The high level, low level, and rising edges of the vertical sync signal are counted separately. When the second rising edge of the vertical sync signal is detected, the count values ​​of the high level and the low level are compared. If the count value of the high level is greater than the count value of the low level, the polarity of the vertical sync signal is determined to be negative; if the count value of the high level is less than the count value of the low level, the polarity of the vertical sync signal is determined to be positive.

5. The method according to claim 1 or 4, characterized in that, The method of obtaining the frame header of the synchronization signal based on the video source signal monitoring includes: detecting a field synchronization signal; and detecting that the V value of the SAV signal is 1 and the V value of the EAV signal is 0.

6. The method according to claim 1 or 4, characterized in that, The method of obtaining the timing control parameters of the synchronization signal based on the video source signal monitoring includes: monitoring the length of the field synchronization signal; monitoring the length of the line synchronization signal; monitoring the length of the field display leading edge; monitoring the length of the field display trailing edge; monitoring the length of the line display leading edge; monitoring the length of the line display trailing edge; monitoring the image width and height; and monitoring the position of the pixels of the video source signal in the image.

7. The method according to claim 1 or 4, characterized in that, The method of obtaining the odd / even field information of the synchronization signal based on the video source signal monitoring includes: when the time interval between the transition edges of the field synchronization signal and the line synchronization signal is detected to be within a first time interval, the synchronization signal is determined to be in an odd field state; when the time interval between the transition edges of the field synchronization signal and the line synchronization signal is detected to be within a second time interval, the synchronization signal is determined to be in an even field state.

8. The method according to claim 1, characterized in that, The methods for monitoring abnormalities in the source clock frequency include: if the difference between the count values ​​Sclk_cnt of the source clock in two adjacent counting cycles reaches a preset value, then the source clock frequency is determined to be abnormal; the methods for monitoring abnormalities in the frame header of the synchronization signal include: after determining that a frame header of the synchronization signal has appeared, a preset interrupt is generated; if no frame header is detected within a preset time after the preset interrupt, then the frame header monitoring of the synchronization signal is determined to be abnormal; the methods for monitoring abnormalities in the timing control parameters include: if the detection value of the field synchronization signal is different in each field, or the detection value of the line synchronization signal is different in each line, then the timing control parameters are determined to be abnormal.

9. A video signal processing device, characterized in that, The processing device includes a processor and a memory, the memory storing a processing program, which, when executed by the processor, implements the steps of the method according to any one of claims 1 to 8.

10. A storage medium, characterized in that, The device contains a computer program that, when executed by a processor, implements the steps of the method as described in any one of claims 1 to 8.

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