A composite thin-film flexible transistor and its fabrication method

Abstract

This invention discloses a composite thin-film flexible transistor and its fabrication method, relating to the field of flexible semiconductor device technology. The composite thin-film flexible transistor comprises a flexible substrate, a gate electrode, a gate dielectric layer, a hybrid channel layer, a source electrode, and a drain electrode, stacked sequentially. The hybrid channel layer is formed under controlled low-temperature conditions through dual-source co-evaporation of elemental Te, forming a continuous amorphous framework phase. Te is dispersed and embedded in a supercooled liquid state and spontaneously crystallizes during natural temperature recovery, forming an interconnected conductive network. The content of Te in the hybrid channel layer is precisely controlled by the evaporation rate, achieving effective Te crystallization and carrier transport without high-temperature annealing. The flexible transistor proposed in this invention exhibits stable p-type enhancement-mode electrical characteristics at low operating voltages, possessing high mobility, high on / off ratio, and excellent bending reliability. Simultaneously, the fabrication process employs a fully low-temperature procedure, avoiding thermal damage to the flexible substrate caused by high temperatures.

Description

Technical Field

[0001] This invention relates to the field of flexible semiconductor thin-film device technology, and in particular to a composite thin-film flexible transistor and its fabrication method. Background Technology

[0002] Flexible thin-film transistors (TFTs) are core components for flexible display drivers, wearable sensor arrays, flexible logic circuits, and large-area low-temperature integrated electronic systems. As flexible electronic devices develop towards thinner, more flexible, lower power consumption, and higher reliability, flexible TFTs place higher demands on channel materials: they need to achieve high carrier mobility and on / off ratios under low-temperature processing conditions, while maintaining stable threshold voltage and electrical consistency in bending and humid environments.

[0003] Currently, commonly used channel materials for flexible TFTs mainly include metal-oxide-semiconductor (MODS), organic semiconductors, and two-dimensional materials. Among these, MODS are widely studied and applied due to their excellent uniformity and process compatibility. However, these devices typically require annealing at 200–350°C to reduce defect state density and improve carrier transport performance, making them difficult to integrate with the heat resistance of flexible substrates such as polyimide (PI), polyethylene naphthalate (PEN), and polyethylene terephthalate (PET). At low temperatures, device mobility and stability are significantly limited. While organic semiconductor channel materials can be fabricated at lower temperatures, their mobility is generally low, typically below 1 cm²·V⁻¹·s⁻¹, and they are sensitive to environmental factors such as oxygen and moisture, resulting in insufficient long-term device stability. Two-dimensional materials (such as…) While phosphorus (such as black phosphorus) has high mobility potential, it still faces significant challenges in large-area uniform preparation, interface control, and low-cost flexible integration.

[0004] Tellurium (Te), a typical p-type semiconductor material, possesses high intrinsic carrier mobility and excellent electrical potential, and has been used in recent years to construct high-performance p-type field-effect transistors (FETs) and TFTs. For example, Zhao et al. reported in Nature Nanotechnology on the use of thermally evaporated tellurium thin films for p-type FETs and circuits (DOI:10.1038 / s41565-019-0585-9), demonstrating the potential for scalable deposition and circuitization of the Te system; Kim et al. reported in npj 2D Materials and Applications on high-quality Te thin films and wafer-level consistent p-channel devices (DOI:10.1038 / s41699-021-00280-7). However, in flexible / low-temperature processing scenarios, Te thin films still face challenges such as difficulty in controlling morphology and crystallization processes, and environmental sensitivity, which can easily lead to threshold drift and decreased reliability of devices. To improve the environmental stability and reliability of Te channel devices, some studies have attempted to introduce tellurium oxide (Te) TeO2, as a stable wide bandgap oxide, has good chemical stability, environmental barrier properties, and high electrical insulation properties, and is often used in the field of device passivation or surface protection.

[0005] However, existing Many related technical solutions will Treating it as a surface protective layer, dielectric layer, or simple dopant phase, a stacked structure of "Te thin film + oxide layer" is typically employed, or a uniform oxidation / composition mixing treatment is performed on the Te thin film. While these approaches improve stability, they still have significant limitations: on the one hand, the protective layer or oxide layer is usually located on the film surface, making it difficult to effectively control the morphological evolution and crystallization behavior inside the Te film; on the other hand, the stacked or simple mixed structure introduces additional interfaces, potentially increasing the interface trap density and affecting carrier transport continuity and device consistency. More importantly, existing technologies have not yet fully understood and utilized... Amorphous materials exhibit properties such as easy formation of amorphous structures at low temperatures, good mechanical flexibility, and high compatibility with flexible substrates. In flexible electronics applications, amorphous materials typically possess isotropic mechanical response and good bending resistance, making them suitable as structural supports or framework phases in flexible devices. However, existing... The relevant plan did not include It was designed and utilized as a continuous amorphous framework structure inside the channel, but its possible regulatory effect on the crystallization behavior, grain connection mode and conductive pathway construction of Te during low-temperature deposition and subsequent warming process was not explored.

[0006] In summary, the existing The relevant flexible TFT technology still struggles to balance low-temperature manufacturing, conductive network construction, and long-term stability, mainly in the following aspects: (1) Te thin film has a narrow film formation window and the crystallization process is difficult to control under low-temperature conditions, making it difficult to achieve both film continuity and high-quality conductive pathways at the same time; (2) To obtain good crystal quality, existing solutions usually require subsequent high-temperature annealing, which contradicts the heat resistance of flexible substrates; (3) The environmental sensitivity of Te materials can easily lead to device threshold voltage drift and mobility decay; (4) There is a lack of a composite channel solution that can achieve "structural self-organization" and "conductive network construction" under controlled low-temperature processes, making it difficult to balance flexibility, environmental stability, and electrical performance.

[0007] Therefore, there is an urgent need to develop a new type of flexible TFT channel material and device structure that can directly construct a stable and continuous p-type conductive path through a low-temperature process without high-temperature annealing, while meeting the requirements of flexible substrate compatibility and long-term environmental stability. Summary of the Invention

[0008] To address the problems existing in the background technology described above, this invention provides a composite thin-film flexible transistor and its fabrication method, aiming to solve the technical challenge of simultaneously achieving thin-film continuity, conductive path construction, and device stability in p-type channel materials under low-temperature fabrication conditions in existing flexible thin-film transistors. Specifically, this invention aims to overcome the technical bottlenecks that hinder flexible substrate integration, such as the tendency of tellurium (Te) thin films to develop island-like growth during conventional deposition, reliance on high-temperature annealing for crystallization, and insufficient environmental stability. This invention introduces... As an amorphous framework phase, Te was synthesized under controlled low-temperature conditions. The co-deposition of Te utilizes the phase transformation and crystallization kinetics regulation mechanism during low-temperature deposition and subsequent natural warming process to enable Te to... Under the confinement effect of the amorphous framework, spontaneous crystallization forms a continuous p-type conductive network, thereby constructing a composite channel structure with high electrical performance, good flexibility and long-term environmental stability without introducing subsequent high-temperature thermal annealing processes, meeting the comprehensive requirements of flexible electronic devices for low-temperature processes, high performance and high reliability.

[0009] According to a first aspect of the present invention, a composite thin-film flexible transistor is provided. The specific technical solution is as follows:

[0010] A composite thin-film flexible transistor, comprising:

[0011] Flexible substrate;

[0012] A gate electrode is disposed on one side of the flexible substrate;

[0013] A gate dielectric layer covers the gate electrode;

[0014] A hybrid channel layer is disposed on the side of the gate dielectric layer away from the gate electrode; The hybrid channel layer contains a continuous Amorphous framework phase and embedded and connected to the Crystallization in amorphous framework phases;

[0015] The source electrode and drain electrode are respectively disposed on the... It is on the mixed channel layer and in electrical contact with the crystalline or semi-crystalline Te conductive network.

[0016] Furthermore, the flexible substrate is selected from polyimide, polyethylene terephthalate, polyethylene naphthalate, or ultrathin glass; the thickness of the flexible substrate is 20–50 μm.

[0017] Furthermore, the gate dielectric layer is composed of One or more of the following are used to form a dielectric thin film; the thickness of the gate dielectric layer is 20–60 nm.

[0018] Furthermore, the aforementioned The total thickness of the hybrid channel layer is 5–30 nm.

[0019] Furthermore, the gate electrode is made of Au, Mo, Ti, Cr or a combination of these metals; the thickness of the gate electrode is 30–60 nm.

[0020] Furthermore, the source electrode and drain electrode are made of Au, Pd, Pt or a combination of these metals; the thickness of the source electrode and drain electrode is 50–60 nm, and the channel length between the source electrode and drain electrode is 2–50 μm.

[0021] According to a second aspect of the present invention, a method for fabricating a composite thin-film flexible transistor is provided. The specific technical solution is as follows:

[0022] A method for fabricating a composite thin-film flexible transistor, comprising the following steps:

[0023] S1. Select a flexible substrate and form a gate electrode on the flexible substrate;

[0024] S2. A low-temperature atomic layer deposition process is used to form a gate dielectric layer on the gate electrode;

[0025] S3. Place the flexible substrate with the gate electrode and the gate dielectric layer formed thereon in the deposition chamber, and lower the deposition temperature to below -60°C, using elemental Te and Dual-source co-evaporation deposition is performed as the evaporation source to form on the gate dielectric layer. Mixed thin films; after deposition is stopped, allow the temperature to return to room temperature naturally to form... Mixed channel layer;

[0026] S4, in the Source and drain electrodes are formed on the hybrid channel layer to obtain a composite thin-film flexible transistor.

[0027] Furthermore, in step S1, before forming the gate electrode, the flexible substrate is cleaned sequentially with an organic solvent and deionized water, and then baked; the gate electrode is deposited by thermal evaporation or sputtering, and the electrode pattern is defined by mask deposition or photolithography lift-off process.

[0028] Furthermore, in step S3, the deposition temperature is controlled within a range of -100℃ to -60℃; during the dual-source co-evaporation deposition process, the elemental Te and the The evaporation rates of the elements are independently controllable. The evaporation rate of elemental Te is controlled at 0.15–0.30 Å / s, and the evaporation rate of TeO2 is controlled at 0.05–0.20 Å / s. Furthermore, the evaporation rates of elemental Te and the elements are... The ratio of their evaporation rates is 0.8:1 to 4:1.

[0029] Furthermore, in step S3, after deposition is complete, maintain a low temperature for 1–10 minutes, then stop cooling and allow the temperature to naturally return to room temperature; no further cooling is required. The mixed channel layer undergoes high-temperature heat annealing.

[0030] Compared with the prior art, the present invention has at least the following beneficial effects:

[0031] 1. This invention achieves low-temperature control of the entire device fabrication process by synergistically applying low-temperature co-evaporation deposition and low-temperature atomic layer deposition (ALD) processes. The gate dielectric layer deposition temperature is no higher than 150°C and the channel layer deposition temperature is lower than -60°C. No high-temperature annealing is required throughout the process, effectively avoiding thermal damage to the flexible substrate caused by thermal processes, and significantly improving the process adaptability and substrate selection flexibility of flexible devices.

[0032] 2. This invention utilizes The amorphous framework's spatial constraint and interface regulation of Te crystallization behavior induce spontaneous crystallization of Te during the natural warming process of the substrate after low-temperature deposition, achieving effective interconnection between grains and forming a connected conductive network. This mechanism breaks through the traditional technical path of Te-based thin films relying on high-temperature annealing to improve performance, completing the construction of p-type conductive pathways under zero additional thermal budget conditions, and providing a new low-temperature fabrication mode for flexible electronic devices.

[0033] 3. The invention constructed by this invention In the mixed channel layer, The formation of a continuous amorphous framework phase provides structural support and mechanical flexibility for the channel layer, while also acting as a good environmental barrier and interface passivation for the Te conductive network embedded within it, effectively suppressing the oxidation and defect evolution of the Te material. At the same time, the conductive network formed by Te embedded in the framework in a crystalline form ensures stable p-type carrier transport capability.

[0034] 4. The flexible transistor of the present invention The hybrid channel layer can be formed through a low-temperature co-evaporation process, eliminating the need for complex stacked structure designs or multi-step transfer processes, thus simplifying the device fabrication process. This process is highly compatible with conventional patterning techniques such as mask deposition and photolithography lift-off, and is suitable for large-area uniform fabrication and array integration, exhibiting good process scalability and promising prospects for industrial applications.

[0035] 5. The flexible transistor obtained in this invention maintains essentially unchanged electrical performance after repeated bending tests under small-radius bending conditions, with no significant drift in threshold voltage, and retains stable current modulation characteristics under dynamic mechanical stress. This flexible transistor can be widely used in flexible display driving circuits, wearable sensor arrays, flexible logic circuits, and low-temperature integrated electronic systems, meeting the comprehensive requirements of next-generation flexible electronic devices for high performance, low power consumption, and high reliability. Attached Figure Description

[0036] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0037] Figure 1 A schematic diagram of the structure of a composite thin-film flexible transistor proposed in this invention is shown;

[0038] Figure 2 The present invention presents a Te- in a composite thin-film flexible transistor. Schematic diagram of the microstructure of the hybrid channel layer;

[0039] Figure 3 A schematic flowchart of a method for fabricating a composite thin-film flexible transistor proposed in this invention is shown.

[0040] Figure 4 A schematic diagram showing the comparison of X-ray diffraction test results of the hybrid channel layer in a composite thin-film flexible transistor proposed in this invention is presented.

[0041] Figure 5 A schematic diagram of the electrical performance test curves of a composite thin-film flexible transistor proposed in this invention is shown.

[0042] Figure 6A schematic diagram showing the performance retention rate test results of a composite thin-film flexible transistor proposed in this invention under different bending conditions is presented. Detailed Implementation

[0043] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the solution proposed by the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of the present invention. Please refer to the drawings to make the objectives, features, and advantages of the present invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0044] Example 1

[0045] The first aspect of this invention provides a composite thin-film flexible transistor, see reference. Figure 1 As shown, the composite thin-film flexible transistor includes, from bottom to top, a flexible substrate 1, a gate electrode 2, and a gate dielectric layer 3. The hybrid channel layer 4, as well as the source electrode 5 and the drain electrode 6.

[0046] Specifically, the flexible substrate 1 can be selected from any one of polyimide (PI) film, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or ultrathin glass. These materials possess excellent low-temperature resistance and good dimensional stability, enabling them to adapt to low-temperature processing conditions while meeting the requirements for bending reliability of flexible devices. The thickness of the flexible substrate 1 is 20–50 μm to ensure good flexibility while maintaining mechanical support strength. In this embodiment, the flexible substrate is selected from polyethylene terephthalate (PET) film.

[0047] Specifically, the gate electrode 2 is disposed on the upper surface of the flexible substrate 1. The gate electrode 2 can be made of Au, Mo, Ti, Cr, or a combination of these metals, and is formed by thermal evaporation or sputtering to achieve a stable electric field modulation function. The thickness of the gate electrode 2 is 30–60 nm. In this embodiment, Au is specifically selected as the material because it has good conductivity and chemical stability, which can ensure effective control of the channel by the gate.

[0048] Specifically, the gate dielectric layer 3 covers the gate electrode 2. The gate dielectric layer 3 can be prepared using a low-temperature atomic layer deposition (ALD) process, and its material can be selected from... The dielectric film, or a combination thereof, is used to ensure a dense film structure and good interface quality. The thickness of the gate dielectric layer 3 is 20–60 nm. In this embodiment, the material specifically used is... To achieve a balance between low leakage current and strong gate control capability.

[0049] Specifically, the aforementioned A hybrid channel layer 4 is disposed on top of the gate dielectric layer 3. (See also...) Figure 2 As shown, the The mixed channel layer 4 is formed by low-temperature co-evaporation of Te and The mixed film, in which A continuous amorphous framework phase is formed, in which Te is embedded and connected in a crystalline form. Within the amorphous framework, dispersed or interconnected conductive networks are formed, thereby constructing a p-type semiconductor channel structure with continuous conductive pathways. No subsequent high-temperature thermal annealing is required during the formation of the hybrid channel layer 4. During the process of low-temperature deposition completion and natural recovery to room temperature with the substrate temperature, Te... The amorphous framework undergoes spontaneous crystallization and grain connection under spatial constraints and interface effects, thereby completing the construction of conductive pathways without introducing additional thermal budget.

[0050] Furthermore, the aforementioned The total thickness of the hybrid channel layer 4 is 5–30 nm. The layer formed in this embodiment... The microstructure of the hybrid channel layer 4 is as follows: A continuous amorphous framework phase is formed, uniformly distributed along the thickness direction; Te is embedded in this framework in the form of nanocrystals, with adjacent grains interconnected to form a conductive network that runs through the entire channel layer. This structure ensures both efficient carrier transport and... The skeleton provides structural support, interface passivation, and environmental barrier functions.

[0051] Specifically, the source electrode 5 and the drain electrode 6 are disposed on the The upper surface of the hybrid channel layer 4. The source electrode 5 and drain electrode 6 are formed by a mask combined with an electron beam evaporation process, and their materials can be Au, Pd, Pt, or combinations thereof. The thickness of the source electrode 5 and drain electrode 6 is 50–60 nm. The channel length can be adjusted within the range of 2–50 μm according to application requirements to balance device driving capability and integration density. In this embodiment, the source electrode 5 and drain electrode 6 are made of Au and prepared using an electron beam evaporation process to ensure good conductivity and patterning accuracy of the electrodes.

[0052] In summary, the composite thin-film flexible transistor proposed in this invention has Te– Flexible thin-film transistors with hybrid channel structures, in which A continuous amorphous framework phase is formed, providing structural support, interface passivation, and environmental barrier functions for the channel layer; Te in The framework confines the structure, leading to spontaneous crystallization and the formation of a connected conductive network, enabling the construction of a p-type conductive path without high-temperature annealing. This device exhibits a simple structure, good compatibility with flexible substrates, and excellent electrical properties and mechanical flexibility.

[0053] Example 2

[0054] The second aspect of this invention provides a method for fabricating a composite thin-film flexible transistor, see reference. Figure 3 As shown, the preparation method includes the following steps:

[0055] S1. Select a flexible substrate and form a gate electrode on the surface of the flexible substrate;

[0056] S2. A low-temperature atomic layer deposition process is used to form a gate dielectric layer on the surface of the gate electrode;

[0057] S3. Under controlled low-temperature conditions, Te and... are simultaneously evaporated through dual evaporation sources. Deposited on the surface of the gate dielectric layer Mixed channel layer;

[0058] S4, in Source and drain electrodes are formed on the surface of the hybrid channel layer to obtain a flexible thin-film transistor structure.

[0059] Step S1 above includes:

[0060] Specifically, a flexible substrate is first selected, which can be polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or ultrathin glass. In this embodiment, polyimide (PI) is selected as the flexible substrate.

[0061] Further, a gate electrode is deposited on the upper surface of the flexible substrate. Before depositing the gate electrode, the PI flexible substrate is sequentially cleaned with organic solvents such as acetone and isopropanol, followed by deionized water to remove organic contaminants and particulate residues from the substrate surface. After cleaning, it is baked at a low temperature of 60–100°C to remove residual solvents and moisture from the substrate surface. Subsequently, the gate electrode material is deposited on the cleaned PI flexible substrate surface using thermal evaporation or sputtering. The gate electrode material can be Au, Mo, Ti, Cr, or a combination of these metals. During the deposition process, the gate electrode pattern is defined using mask deposition or photolithography lift-off processes to obtain a gate electrode structure with stable gate control capability and low series resistance.

[0062] Step S2 above includes:

[0063] Specifically, a low-temperature atomic layer deposition (ALD) process is used to deposit a gate dielectric layer on the gate electrode. The gate dielectric layer material can be selected from... At least one of the following, or a composite material composed of them. During deposition, the deposition temperature is controlled not to exceed 150°C to maintain thermal compatibility with the flexible substrate, while improving the density and interface quality of the dielectric layer. The deposition thickness of the gate dielectric layer is 20–60 nm, and the specific thickness can be adjusted according to the target operating voltage and gate capacitance density.

[0064] Step S3 above includes:

[0065] Specifically, the sample with the gate electrode and gate dielectric layer formed is placed in a vacuum chamber, and the chamber is then evacuated. Preferably, the cooling and deposition processes begin after the chamber reaches a stable high vacuum. The vacuum level can be set according to the equipment capacity and does not constitute a limitation of the present invention, but it should be ensured that the residual water and oxygen content in the chamber is sufficiently low to avoid adverse effects on the sample. Mixed films cause contamination. Subsequently, the sample is fixed on a low-temperature substrate stage, and the substrate temperature is lowered to below -60°C, preferably controlled within the range of -100°C to -60°C, using a cooling liquid circulation and temperature control system. Real-time closed-loop control is performed using a temperature sensor to ensure temperature stability during deposition. Preferably, the substrate temperature is controlled within the range of -90°C to -70°C.

[0066] Furthermore, after the substrate reaches the set temperature and stabilizes, the Te evaporation source and the TeO2 evaporation source are simultaneously activated for synchronous co-evaporation deposition. The evaporation rate is monitored in real time by an evaporation rate monitoring module and controlled independently, thereby controlling the evaporation rate. The component ratios were continuously adjusted. Specifically, the evaporation rate of Te was controlled at 0.15–0.30 Å / s. The evaporation rate was controlled at 0.05–0.20 Å / s, with the preferred rate ratio between the two being 0.8:1 to 4:1; the deposition time was determined based on the target total thickness. This was achieved by adjusting Te and... The rate ratio can achieve a balance between "conductive network connectivity" and "skeleton stability and barrier passivation", thereby obtaining a channel thin film structure that combines carrier mobility and reliability. Preferably, the total thickness of the hybrid channel layer 4 is controlled to be 5–30 nm; in this embodiment, the total thickness is controlled to be 10–20 nm.

[0067] It is worth noting that after deposition, the film is kept at a low temperature for 1–10 minutes to stabilize its initial morphology. Cooling is then stopped, allowing the sample to naturally warm to room temperature in a vacuum or inert atmosphere. This invention eliminates the need for additional high-temperature thermal annealing of the hybrid channel layer; during the warming process, Te... Under the spatial constraints and interface effects of the continuous amorphous framework phase, spontaneous crystallization occurs and grain connections are achieved, forming a connected Te conductive network, thereby completing the construction of conductive pathways without introducing additional thermal budget.

[0068] Step S4 above includes:

[0069] Specifically, in the A mask is placed on the surface of the hybrid channel layer, exposing the source and drain electrode regions. Source and drain electrode materials are then deposited via vapor deposition. The source and drain electrode materials can be Au, Pd, Pt, or combinations thereof to ensure good conductivity and contact characteristics. The channel length can be designed according to device application requirements, preferably ranging from 2 to 50 μm; in this embodiment, the channel length is designed to be 20 μm. The channel width can be set according to drive current requirements and testing convenience; the width parameter does not constitute a limitation of the invention.

[0070] To illustrate the technical effect of the present invention in achieving spontaneous crystallization of Te and forming a continuous conductive path during the temperature recovery process after low-temperature co-evaporation deposition, the structure and morphology of the hybrid channel layer were characterized in this embodiment, and a comparative sample was set up for comparison and verification.

[0071] See Figure 4 The image shows a schematic diagram of the X-ray diffraction test results for the hybrid channel layer. Among them, Figure 4 (a) shows the diffraction pattern of the mixed channel layer sample after low-temperature co-evaporation deposition but before it has undergone a warming process; Figure 4 (b) shows the diffraction pattern of the same sample after it has been warmed to room temperature in a vacuum or inert atmosphere and left to stand for a period of time. Figure 4 (c) shows the diffraction pattern of a comparative sample, which is either a sample prepared using a single Te channel film or a sample prepared under non-low-temperature co-evaporation conditions. To enhance the diffraction signal of the 5–30 nm ultrathin channel film, grazing incidence was used for testing at an incidence angle of 0.2°–1.0°.

[0072] As can be seen from the comparison, the sample of the present invention, after being reheated ( Figure 4 The Te characteristic diffraction peaks in (b) are compared to those before the temperature recovery. Figure 4 The peak in (a) shows a significant enhancement, becoming sharper and with a reduced half-peak width, indicating that the crystallinity of the film increases and the grains grow during the warming process; while the comparative sample (a) shows a different enhancement. Figure 4 The peak shape and intensity variations in (c) are significantly different from those of the sample of this invention, indicating that the peak shape and intensity variations in (c) are significantly different from those of the sample of this invention. When Te is constrained by a continuous amorphous framework or lacks a low-temperature deposition-warming kinetic process, its crystallization and grain connectivity are difficult to controllably enhance. Therefore, Figure 4 The results shown demonstrate from a crystal phase perspective that the hybrid channel layer of the present invention undergoes spontaneous crystallization during the reheat stage and forms a crystal structure that is more conducive to carrier transport, thus consistent with the technical point of the present invention that "conducting conductive pathways can be constructed without subsequent thermal annealing".

[0073] Furthermore, the changes in peak intensity ratio and full width at half maximum (FWHM) were used to quantify the aforementioned crystallization enhancement trend: a representative Te characteristic peak was selected, and the peak intensity ratio after reheating was compared with that before reheating; this peak intensity ratio was 2–10 times; after reheating, the FWHM of this characteristic peak decreased by 20%–60%. Combined with grain size estimation methods, the grain size increased from several nanometers to tens of nanometers after reheating, further reflecting the improving effect of grain growth and reduced grain boundary scattering on channel transport.

[0074] See Figure 5 As shown, after the flexible thin-film transistor device was fabricated, its output and transfer characteristics were tested. Among these, Figure 5 Figures (a) and (b) show the electrical performance of the composite thin-film flexible transistor of the present invention. Figure 5 Figures (c) and (d) show the electrical performance of a comparative pure Te room-temperature deposited transistor device. The test results demonstrate that the transistor device of this invention exhibits p-type enhancement-mode operation and continuous current modulation capability. Because the hybrid channel layer undergoes spontaneous Te crystallization and grain connectivity during the warm-up process after low-temperature deposition, a stable conductive path can be formed without subsequent thermal annealing. Therefore, the device can achieve stable operation under low thermal budget process conditions compatible with flexible substrates.

[0075] Electrical tests were conducted at room temperature. In the transfer characteristic test, the gate voltage was scanned under a fixed drain voltage condition to obtain the leakage current versus gate voltage curve. In the output characteristic test, the drain voltage was scanned under different gate voltage conditions to obtain the leakage current versus drain voltage curve. Key device indicators such as on / off ratio, subthreshold swing, threshold voltage, and field-effect mobility were extracted from these curves, and the consistency between devices was statistically compared. The results show that the composite channel structure of this invention improves gate control stability and transport consistency.

[0076] See Figure 6 As shown, the device was subjected to bending tests under different bending radii. The effective mobility and current switching ratio of the device were tested before and after bending to evaluate the performance degradation trend. Figure 6 Figure (a) shows the performance changes of the composite thin-film flexible transistor of the present invention before and after. Figure 6 Figure (b) shows the performance changes of a pure Te room temperature deposited transistor device before and after comparison. The bending radius was selected from different values ​​within the range of 3–14 mm, and the number of bending cycles was selected from 10²–10⁻⁶. 7 Different levels within this range. By comparing the changes in effective mobility and on / off ratio before and after bending, it can be seen that: due to... The amorphous framework phase provides structural support in the hybrid channel layer and acts as a passivation and barrier at the interface. The device of the present invention exhibits less performance degradation under bending stress and environmental exposure conditions, and demonstrates higher flexibility, reliability and long-term stability.

[0077] The structural characterization, electrical testing, and flexibility reliability testing results above demonstrate that this invention, through simultaneous co-evaporation of Te and... And by using the subsequent warming process to induce Te in Spontaneous crystallization and grain bonding occur under the constraint of a continuous amorphous framework, forming a continuous and stable conductive path without the need for subsequent high-temperature thermal annealing. This technical solution significantly reduces the process thermal budget, improves the controllability and consistency of the channel structure, and enables the resulting flexible thin-film transistors to exhibit excellent overall advantages in both electrical performance and mechanical reliability.

[0078] Therefore, the low-temperature co-evaporation deposition method proposed in this invention... The composite thin-film flexible transistor and its fabrication method can effectively overcome the problems of high dependence on high-temperature annealing, poor compatibility with flexible substrates, and insufficient channel consistency in the existing technology, and have good engineering application value.

[0079] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0080] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0081] It should be noted that, in the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

Claims

1. A composite thin-film flexible transistor, characterized in that, include: Flexible substrate (1); A gate electrode (2) is disposed on one side of the flexible substrate (1); A gate dielectric layer (3) covers the gate electrode (2); A hybrid channel layer (4) is disposed on the side of the gate dielectric layer (3) away from the gate electrode (2); The mixed channel layer (4) contains a continuous Amorphous framework phase and embedded and connected to the A crystalline Te conductive network in an amorphous framework phase; The source electrode (5) and drain electrode (6) are respectively disposed on the... It is on the mixed channel layer (4) and in electrical contact with the crystalline Te conductive network.

2. The composite thin-film flexible transistor according to claim 1, characterized in that, The flexible substrate (1) is selected from polyimide, polyethylene terephthalate, polyethylene naphthalate or ultrathin glass; the thickness of the flexible substrate (1) is 20–50 μm.

3. The composite thin-film flexible transistor according to claim 1, characterized in that, The gate dielectric layer (3) is composed of One or more of the dielectric thin films are formed; the thickness of the gate dielectric layer (3) is 20–60 nm.

4. The composite thin-film flexible transistor according to claim 1, characterized in that, The The total thickness of the hybrid channel layer (4) is 5–30 nm.

5. The composite thin-film flexible transistor according to claim 1, characterized in that, The gate electrode (2) is made of Au, Mo, Ti, Cr or a combination of metals; the thickness of the gate electrode (2) is 30–60 nm.

6. The composite thin-film flexible transistor according to claim 1, characterized in that, The source electrode (5) and drain electrode (6) are made of Au, Pd, Pt or a combination of metals thereof; the thickness of the source electrode (5) and drain electrode (6) is 50–60 nm, and the channel length between the source electrode (5) and drain electrode (6) is 2–50 μm.

7. A method for fabricating a composite thin-film flexible transistor, used to fabricate a composite thin-film flexible transistor as described in any one of claims 1-6, characterized in that, Includes the following steps: S1. Select a flexible substrate (1) and form a gate electrode (2) on the flexible substrate (1). S2. A low-temperature atomic layer deposition process is used to form a gate dielectric layer (3) on the gate electrode (2). S3. The flexible substrate (1) on which the gate electrode (2) and the gate dielectric layer (3) are formed is placed in the deposition chamber, and the deposition temperature is lowered to below -60°C, with elemental Te and Dual-source co-evaporation deposition is performed as the evaporation source to form on the gate dielectric layer (3). Mixed thin films; after deposition is stopped, allow the temperature to return to room temperature naturally to form... Mixed channel layer (4); S4, in the A source electrode (5) and a drain electrode (6) are formed on the hybrid channel layer (4) to obtain a composite thin film flexible transistor.

8. The method for fabricating a composite thin-film flexible transistor according to claim 7, characterized in that, In step S1, before forming the gate electrode (2), the flexible substrate (1) is cleaned with organic solvent and deionized water in sequence and then baked. The gate electrode (2) is deposited by thermal evaporation or sputtering and the electrode pattern is defined by mask deposition or photolithography lift-off process.

9. The method for fabricating a composite thin-film flexible transistor according to claim 7, characterized in that, In step S3, the deposition temperature is controlled within a range of -100℃ to -60℃; during the dual-source co-evaporation deposition process, the evaporation rate of elemental Te is controlled at... The The evaporation rate is controlled at And the element Te and the The ratio of their evaporation rates is 0.8:1 to 4:

1.

10. The method for fabricating a composite thin-film flexible transistor according to claim 7 or 9, characterized in that, In step S3, after deposition, maintain a low temperature for 1–10 minutes, then stop cooling and allow the temperature to naturally return to room temperature; no further cooling is required. The mixed channel layer (4) is subjected to high-temperature heat annealing.

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