Semiconductor device, manufacturing method thereof and chip

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and a chip, relates to the technical field of semiconductors, and is used for solving the problem that the advantage of low resistance of the semiconductor device cannot be reflected when the semiconductor device is manufactured by adopting a post-metal gate process. The manufacturing method of the semiconductor device comprises the following steps: manufacturing a heterojunction film layer on a substrate; manufacturing a virtual gate structure on one side, opposite to the substrate, of the heterojunction film layer, wherein the slope angle of the side surface of the virtual gate structure is greater than 90 degrees; a second barrier layer is manufactured on the side, opposite to the substrate, of the heterojunction film layer, the second barrier layer comprises two barrier patterns, and the virtual gate structure is located between the two barrier patterns; the side surface, close to the virtual gate structure, of the barrier pattern is attached to the side surface of the virtual gate structure; two electrode structures are manufactured on the side, back on to the substrate, of the second barrier layer, and the bottoms of the electrode structures extend into the second barrier layer or the heterojunction film layer; removing the virtual gate structure to form a gate manufacturing region; and manufacturing a gate in the gate manufacturing region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, its fabrication method, and a chip. Background Technology

[0002] Gate-last (GLS) is a semiconductor device manufacturing technique primarily used to improve device performance and reduce power consumption. In this process, gate deposition occurs after other process steps, as opposed to the traditional gate-first (GLS) process. However, using GLS to fabricate semiconductor devices can sometimes result in the loss of the device's low resistance advantage. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method and chip, which solves the problem that the advantage of low resistance of semiconductor devices cannot be realized when using post-metal gate process to fabricate semiconductor devices.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A first aspect of the present invention provides a method for fabricating a semiconductor device, comprising:

[0006] A heterojunction film layer is fabricated on a substrate.

[0007] A virtual gate structure is fabricated on the side of the heterojunction film layer facing away from the substrate, and the side slope angle of the virtual gate structure is greater than 90 degrees.

[0008] A second barrier layer is formed on the side of the heterojunction film layer facing away from the substrate. The second barrier layer includes two barrier patterns, and the virtual gate structure is located between the two barrier patterns. The side of the barrier pattern close to the virtual gate structure is attached to the side of the virtual gate structure.

[0009] Two electrode structures are fabricated on the side of the second barrier layer facing away from the substrate, and the bottom of the electrode structures extends into the interior of the second barrier layer or the interior of the heterojunction film layer.

[0010] Remove the virtual gate structure to form the gate fabrication area;

[0011] A gate is fabricated in the gate fabrication region.

[0012] Optionally, the step of fabricating a virtual gate structure on the side of the heterojunction film layer facing away from the substrate specifically includes:

[0013] An etching barrier layer, a first protective layer, and a virtual gate layer are sequentially formed on the side of the heterojunction film layer facing away from the substrate.

[0014] Ion doping is performed on the portion of the virtual gate film layer located in the virtual gate structure formation region;

[0015] After doping, the portion of the virtual gate film layer that has not been ion-doped is removed, and the portion of the first protective layer that is not located in the virtual gate structure formation region and the portion of the etch barrier layer that is not located in the virtual gate structure formation region are also removed; the remaining portion of the virtual gate film layer, part of the first protective layer and part of the etch barrier layer together constitute the virtual gate structure.

[0016] Optionally, the step of fabricating a heterojunction film layer on the substrate specifically includes:

[0017] A channel layer and a first barrier layer are sequentially formed on the substrate.

[0018] The step of fabricating a second barrier layer on the side of the heterojunction film layer facing away from the substrate specifically includes:

[0019] On the side of the first barrier layer facing away from the substrate, a second barrier layer made of the same or different material is grown on both sides of the virtual gate structure.

[0020] Optionally, the step of fabricating two electrode structures on the side of the second barrier layer facing away from the substrate specifically includes:

[0021] A first insulating layer is fabricated, which covers the virtual gate structure and the second barrier layer. The first insulating layer has two connection holes that expose at least a portion of the corresponding barrier pattern.

[0022] The two electrode structures are fabricated on the side of the first insulating layer facing away from the substrate, and the electrode structures are connected to the corresponding barrier pattern through the corresponding connection holes.

[0023] Optionally, the step of removing the virtual gate structure to form the gate fabrication region specifically includes:

[0024] A second insulating layer is fabricated, which covers the first insulating layer and the two electrode structures;

[0025] A patterning process is performed on the second insulating layer and the first insulating layer to form a process window that penetrates the second insulating layer and the first insulating layer, and the process window exposes the virtual gate structure.

[0026] The virtual gate structure is removed through the process window to form the gate fabrication area.

[0027] Optionally, the steps for fabricating the etching barrier layer, the first protective layer, and the virtual gate layer specifically include:

[0028] The etching barrier layer was fabricated using ALN;

[0029] The first protective layer is made of SiO;

[0030] The virtual gate film layer is fabricated using Si;

[0031] The step of removing the virtual gate structure through the process window to form the gate fabrication region specifically includes:

[0032] The virtual gate film layer in the virtual gate structure is removed using chlorine-based gas through the process window.

[0033] Through the process window, the first protective layer and the etching barrier layer in the virtual gate structure are removed by wet etching to form the gate fabrication area.

[0034] Optionally, the step of fabricating the gate in the gate fabrication region specifically includes:

[0035] A third insulating material layer, a gate material layer, and a second protective layer are sequentially formed and stacked. The third insulating material layer, the gate material layer, and the second protective layer all fill the gate fabrication area and cover the two electrode structures.

[0036] A patterning process is performed to retain the third insulating material layer, the gate material layer, and the second protective layer filling the gate fabrication area, and to remove the third insulating material layer, the gate material layer, and the second protective layer located in other areas to form the gate.

[0037] Based on the technical solution of the above-described semiconductor device fabrication method, a second aspect of the present invention provides a semiconductor device fabricated using the above-described semiconductor device fabrication method. The semiconductor device includes a substrate and a heterojunction film layer disposed on the substrate. The semiconductor device further includes:

[0038] The second barrier layer is located on the side of the heterojunction film layer facing away from the substrate, and the second barrier layer includes two barrier patterns.

[0039] Two electrode structures are located on the side of the second barrier layer facing away from the substrate, and the bottom of the electrode structures extends into the interior of the second barrier layer or the interior of the heterojunction film layer.

[0040] A gate is located on the side of the heterojunction layer facing away from the substrate, and the orthographic projection of the gate on the substrate is located between the orthographic projections of the two barrier patterns on the substrate.

[0041] Optionally, the semiconductor device further includes a first insulating layer, a second insulating layer, a third insulating layer, and a second protective layer;

[0042] At least a portion of the first insulating layer is located between the electrode structure and the second barrier layer. The first insulating layer has two connection holes. The bottom of the electrode structure extends through the corresponding connection holes into the interior of the second barrier layer or the interior of the heterojunction layer.

[0043] The second insulating layer covers the first insulating layer and the two electrode structures;

[0044] The third insulating layer, the gate, and the second protective layer are stacked sequentially in a direction away from the substrate, and the third insulating layer, the gate, and the second protective layer are all located in the gate fabrication region of the semiconductor device.

[0045] Based on the above-described semiconductor device technical solution, a third aspect of the present invention provides a chip including the above-described semiconductor device.

[0046] The technical solution provided by this invention can form a virtual gate structure with a side slope angle greater than 90 degrees, so that the side of the subsequently formed barrier pattern near the virtual gate structure can fit with the side of the virtual gate structure, allowing the edge portion of the second barrier layer near the side of the virtual gate film layer to grow sufficiently. This results in a thicker edge portion of the second barrier layer near the side of the virtual gate film layer, giving the region of the semiconductor device near the gate a higher 2DEG concentration, ensuring that the low resistance advantage of the semiconductor device can be well utilized. Attached Figure Description

[0047] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0048] Figure 1 A process flow diagram of a semiconductor device provided in an embodiment of the present invention;

[0049] Figure 2 for Figure 1 A schematic diagram of the corresponding embodiment showing that the second barrier layer near the edge of the virtual gate structure has not grown sufficiently;

[0050] Figure 3 for Figure 1 A schematic diagram of an excessively large process window in the corresponding embodiment;

[0051] Figure 4 for Figure 1 A schematic diagram of the corresponding embodiment showing an excessively small process window;

[0052] Figure 5 Another fabrication process flow diagram of a semiconductor device provided in an embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of the fabrication of a virtual gate structure provided in an embodiment of the present invention;

[0054] Figure 7 This is a schematic diagram of the fabrication of the second barrier layer provided for an embodiment of the present invention. Detailed Implementation

[0055] To further illustrate the semiconductor devices, fabrication methods, and chips provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0056] like Figure 1 As shown, the present invention provides a method for fabricating a semiconductor device, specifically including the following steps:

[0057] Step 1: Fabricate a heterojunction film layer on the substrate 10. The heterojunction film layer includes a channel layer 11 and a first barrier layer 12 stacked together. For example, the channel layer 11 is made of GaN; the first barrier layer 12 is made of AlGaN, but it is not limited to these.

[0058] Step 2: A virtual gate layer 22 is deposited on the side of the heterojunction layer facing away from the substrate 10. For example, the virtual gate layer 22 is made of SiO, but is not limited to this.

[0059] Step 3: Perform a patterning process on the virtual gate film layer 22 to form a virtual gate structure 222. For example, the slope angle of the virtual gate structure 222 is less than 90 degrees, that is, the cross-section of the virtual gate structure 222 is a trapezoid.

[0060] Step 4: Grow the second barrier layer 13. For example, the second barrier layer 13 uses the same material as the first barrier layer 12, and the second barrier layer 13 includes two barrier patterns.

[0061] Step 5: Fabricate a first insulating layer 14, which covers the virtual gate structure 222 and the second barrier layer 13. For example, the first insulating layer 14 includes a strain film layer and an insulating film layer sequentially stacked along a direction away from the substrate 10. The strain film layer is made of AlN and the insulating film layer is made of SiN, but it is not limited to these.

[0062] Step Six: Perform patterning to form two connection holes penetrating the first insulating layer 14. For example, during the fabrication of the connection holes, the underlying second barrier layer 13 can be partially etched, not etched, or penetrated; no limitation is made here.

[0063] Step 7: Fabricate two electrode structures (as marked 15 and 16), which are connected to the corresponding barrier pattern through the corresponding connection holes.

[0064] Step 8: Fabricate the second insulating layer 17. For example, the second insulating layer 17 can be achieved by depositing SiN, but is not limited to this.

[0065] Step 9: Perform a patterning process to remove part of the virtual grid structure 222.

[0066] Step 10: Use a wet etching process to completely remove the remaining virtual gate structure 222 from Step 9 to form the gate fabrication area.

[0067] Step 11: Sequentially form a third insulating material layer 180, a gate material layer 190, and a second protective layer 300. For example, the third insulating material layer 180 may be made of Al2O3, the gate material layer 190 may be made of TiN, and the second protective layer 300 may be made of SiO, but this is not a limitation.

[0068] Step 12: Perform a patterning process, retaining the third insulating material layer 180, the gate material layer 190, and the second protective layer 300 filling the gate fabrication area, and removing the third insulating material layer 180, the gate material layer 190, and the second protective layer 300 located in other areas, thereby forming the gate 19.

[0069] Research revealed that in step three, the virtual gate layer 22, formed directly through patterning, exhibits a trapezoidal structure. This can lead to insufficient growth of the second barrier layer 13. (See details...) Figure 2 In the second barrier layer 13, the edge portion near the side of the virtual gate layer 22 is not attached to the side of the virtual gate layer 22, and the edge portion of the formed virtual gate layer 22 is very thin (e.g., Figure 2 The area circled in the middle) will result in a low concentration of 2DEG (two-dimensional electron gas) near the gate region of the semiconductor device, which in turn will prevent the semiconductor device from demonstrating its low resistance advantage.

[0070] Please see Figure 5 This invention also provides a method for fabricating a semiconductor device, comprising:

[0071] A heterojunction layer (including a channel layer 11 and a first barrier layer 12) is fabricated on the substrate 10.

[0072] A virtual gate structure (including an etching barrier layer 20, a first protective layer 21, and a virtual gate film layer 22) is fabricated on the side of the heterojunction film layer facing away from the substrate 10, and the side slope angle α of the virtual gate structure is greater than 90 degrees.

[0073] A second barrier layer 13 is formed on the side of the heterojunction film layer facing away from the substrate 10. The second barrier layer 13 includes two barrier patterns, and the virtual gate structure is located between the two barrier patterns. Figure 6 and Figure 7 As shown, the barrier pattern is attached to the side X1 of the virtual gate structure and the side X2 of the virtual gate structure.

[0074] Two electrode structures (as marked 15 and 16) are formed on the side of the second barrier layer 13 facing away from the substrate 10, and the bottom of the electrode structures extends into the interior of the second barrier layer 13 or the interior of the heterojunction layer.

[0075] Remove the virtual gate structure to form the gate fabrication area;

[0076] Gate 19 is fabricated in the gate fabrication region.

[0077] For example, the side slope angle α of the virtual gate structure fabricated on the side of the heterojunction layer facing away from the substrate 10 is greater than 90 degrees; for example, the cross-section of the virtual gate structure is an inverted trapezoid.

[0078] It should be noted that the side slope angle of the virtual gate structure refers to the angle formed between the side of the virtual gate structure and the substrate. When the side is formed as a curved surface, a specific point (such as the midpoint or bottom) can be determined on the curved surface and a tangent line can be drawn to measure the angle formed between the tangent line and the substrate.

[0079] For example, the barrier pattern is attached to the side of the virtual gate structure near the side of the virtual gate structure; the thickness of the edge portion of the barrier pattern near the virtual gate structure is greater than or equal to the thickness of the center portion of the barrier pattern.

[0080] When a semiconductor device is fabricated using the semiconductor device fabrication method provided in this embodiment of the invention, a virtual gate structure with a side slope angle greater than 90 degrees can be formed. This allows the side of the subsequently formed barrier pattern near the virtual gate structure to fit into the side of the virtual gate structure, enabling the edge portion of the second barrier layer 13 near the side of the virtual gate film layer 22 to grow sufficiently. Consequently, the edge portion of the second barrier layer 13 near the side of the virtual gate film layer 22 has a thicker thickness, resulting in a higher 2DEG concentration in the region of the semiconductor device near the gate 19. This ensures that the low resistance advantage of the semiconductor device can be well utilized.

[0081] like Figure 5 As shown, in some embodiments, the step of fabricating a virtual gate structure on the side of the heterojunction film layer facing away from the substrate 10 specifically includes:

[0082] An etching barrier layer 20, a first protective layer 21, and a virtual gate film layer 22 are sequentially formed on the side of the heterojunction film layer facing away from the substrate 10.

[0083] The portion of the virtual gate film layer 22 located in the virtual gate structure formation region is ion-doped. Specifically, a photoresist layer is formed on the surface of the virtual gate film layer 22 facing away from the substrate 10. The photoresist layer is patterned to form a photoresist pattern 23. Using the photoresist pattern 23 as a mask, the portion of the virtual gate film layer 22 located in the virtual gate structure formation region is ion-doped. The doping process includes a first doping step and a second doping step, wherein the first doping step includes a low-energy, high-dose doping process, and the second doping step includes a high-energy, low-dose doping process, thereby forming an inverted trapezoidal doped structure. The doping ion can be boron ions, but is not limited to this.

[0084] It should be noted that the entire doping process is divided into the above two steps, namely the first doping step and the second doping step. Boron ions can be used for doping in both steps. For example, in the first doping step, boron ions are used for low-energy, high-dose doping; in the second doping step, boron ions are not used for high-energy, low-dose doping.

[0085] After doping, the undoped portion of the virtual gate film layer 22 (such as marker 220) is removed, and the portions of the first protective layer 21 not located in the virtual gate structure formation region and the portions of the etch barrier layer 20 not located in the virtual gate structure formation region are also removed. The remaining portion of the virtual gate film layer 221, a portion of the first protective layer 21, and a portion of the etch barrier layer 20 together constitute the virtual gate structure. Specifically, after ion doping, the photoresist pattern 23 is removed first, and then the undoped portion of the virtual gate film layer 22 is removed. For example, the undoped virtual gate film layer 22, a portion of the etch barrier layer 20, and a portion of the first protective layer 21 can be removed using a developer. Since the doped virtual gate film layer 22 will not be washed away by the developer, the development process does not require forming a mask on the doped virtual gate film layer 22.

[0086] The above-described fabrication method not only forms a virtual gate structure with a side slope angle greater than 90 degrees, ensuring that the thickness of the second barrier layer 13 near the gate 19 region is relatively thick; it also allows for the removal of undoped portions of the virtual gate film layer 22, portions of the first protective layer 21 not located in the virtual gate structure formation region, and portions of the etch barrier layer 20 not located in the virtual gate structure formation region without the need for a mask. This not only ensures the fabrication accuracy of the virtual gate film layer 22 but also simplifies the patterning complexity of the virtual gate film layer 22.

[0087] Moreover, when the virtual gate structure is fabricated using the above method, the etching barrier layer 20 and the first protective layer 21 near the heterojunction layer can protect the heterojunction layer, so that the interface (i.e., part of the surface of the heterojunction layer) used to form the gate 19 will not be etched and damaged, thereby better ensuring the yield of the formed gate 19.

[0088] like Figure 5 As shown, in some embodiments, the step of fabricating a heterojunction film layer on the substrate 10 specifically includes: forming a channel layer 11 and a first barrier layer 12 stacked on the substrate 10 in sequence; specifically, the channel layer 11 is GaN; the first barrier layer 12 is AlGaN, but not limited thereto.

[0089] The step of fabricating the second barrier layer 13 on the side of the heterojunction layer facing away from the substrate 10 specifically includes: growing the second barrier layer 13, which is made of the same or different material as the first barrier layer 12, on the side of the first barrier layer 12 facing away from the substrate 10, on opposite sides of the virtual gate structure. Specifically, the second barrier layer 13 includes two barrier patterns.

[0090] When a semiconductor device is fabricated using the semiconductor device fabrication method provided in the above embodiments, a virtual gate structure with a side slope angle greater than 90 degrees can be formed, and the side of the formed barrier pattern near the virtual gate structure can be attached to the side of the virtual gate structure. This allows the edge portion of the second barrier layer 13 near the side of the virtual gate film layer 22 to grow sufficiently, resulting in a thicker edge portion of the second barrier layer 13 near the side of the virtual gate film layer 22. This ensures that the region of the semiconductor device near the gate 19 has a high 2DEG concentration, guaranteeing that the low resistance advantage of the semiconductor device can be well utilized.

[0091] like Figure 5 As shown, in some embodiments, the step of fabricating two electrode structures on the side of the second barrier layer 13 facing away from the substrate 10 specifically includes:

[0092] A first insulating layer 14 is fabricated, covering the virtual gate structure and the second barrier layer 13. The first insulating layer 14 has two connection holes, which expose at least a portion of the corresponding barrier pattern. Specifically, the first insulating layer 14 includes a strain film layer and an insulating film layer sequentially stacked along a direction away from the substrate 10. The strain film layer is made of AlN, and the insulating film layer is made of SiN, but is not limited thereto. After patterning the first insulating layer 14, two connection holes are formed on the first insulating layer 14. It is worth noting that during the fabrication of the connection holes, the underlying second barrier layer 13 can be partially etched, not etched, or penetrated; no limitation is made here.

[0093] The two electrode structures (as marked 15 and 16) are formed on the side of the first insulating layer 14 facing away from the substrate 10, and the electrode structures are connected to the corresponding barrier pattern through the corresponding connection holes.

[0094] It should be noted that when adopting, such as Figure 1 When the process flow is shown, such as Figure 4 As shown, during the removal of the virtual gate structure in steps nine and ten, if the process window is too small, the width of the formed gate fabrication area will be small, which may result in the fabricated gate 19 and the second barrier layer 13 possibly not being fully bonded, leading to a gate 19 filling problem. This affects the yield of the semiconductor device, and similarly, OVL control (alignment control) will also encounter problems, further exacerbating the gate 19 filling problem. Figure 3 As shown, if the process window is too large, the second barrier layer 13 may be etched, which may affect the characteristics of the semiconductor device.

[0095] like Figure 5As shown, in some embodiments, the step of removing the virtual gate structure to form the gate fabrication region specifically includes:

[0096] A second insulating layer 17 is fabricated, which covers the first insulating layer 14 and the two electrode structures; specifically, the second insulating layer 17 can be achieved by depositing SiN, but is not limited to this.

[0097] A patterning process is performed on the second insulating layer 17 and the first insulating layer 14 to form a process window that penetrates the second insulating layer 17 and the first insulating layer 14, and the process window exposes the virtual gate structure; specifically, a photoresist mask pattern can be formed first, and then the second insulating layer 17 and the first insulating layer 14 can be etched using F-based gas as a mask to form the process window.

[0098] The virtual gate structure is removed through the process window to form the gate fabrication area.

[0099] For example, the steps of fabricating the etch stop layer 20, the first protective layer 21, and the dummy gate layer 22 specifically include: fabricating the etch stop layer 20 using ALN; fabricating the first protective layer 21 using SiO; fabricating the dummy gate layer 22 using Si; and removing the dummy gate structure through the process window to form the gate fabrication region. Specifically, the steps include: removing the dummy gate layer 22 from the dummy gate structure using chlorine-based gas through the process window; and removing the first protective layer 21 and the etch stop layer 20 from the dummy gate structure by wet etching through the process window to form the gate fabrication region.

[0100] In the fabrication method provided in the above embodiments, the formed process window is relatively large, making it easier to remove the virtual gate structure and OVL control without causing gate 19 filling problems. Simultaneously, due to the presence of the etch barrier layer 20 and the first protective layer 21, and the etch barrier layer 20, the first protective layer 21, and the virtual gate film layer 22 are etched using different process distributions. Specifically, through the process window, the virtual gate film layer 22 in the virtual gate structure is removed using chlorine-based gas. Through the process window, the first protective layer 21 and the etch barrier layer 20 in the virtual gate structure are removed by wet etching to form the gate fabrication area. This ensures that during the removal of the virtual gate film layer 22, both the second barrier layer 13 and the heterojunction layer are protected by the etch barrier layer 20 and the first protective layer 21, avoiding etching damage to the second barrier layer 13 and thus guaranteeing the characteristics of the semiconductor device.

[0101] Furthermore, by using chlorine-based gas to remove the virtual gate film layer 22 in the virtual gate structure through the process window, there is almost no damage to the dielectric surface in contact with the virtual gate film layer 22. At the same time, by using wet etching to remove the first protective layer 21 and the etching barrier layer 20 in the virtual gate structure through the process window, the chlorine-based gas is effectively prevented from damaging the interface (i.e., the surface of part of the heterojunction film layer) used to form the gate 19, thereby better ensuring the yield of the formed gate 19.

[0102] like Figure 5 As shown, in some embodiments, the step of fabricating the gate 19 in the gate fabrication region specifically includes:

[0103] A third insulating material layer 180, a gate material layer 190, and a second protective layer 300 are sequentially formed and stacked. The third insulating material layer 180, the gate material layer 190, and the second protective layer 300 all fill the gate fabrication area and cover the two electrode structures. Specifically, the third insulating material layer 180 is made of Al2O3, the gate material layer 190 is made of TiN, and the second protective layer 300 is made of SiO, but it is not limited to these.

[0104] The patterning process involves retaining the third insulating material layer 180, the gate material layer 190, and the second protective layer 300 filling the gate fabrication area, while removing the third insulating material layer 180, the gate material layer 190, and the second protective layer 300 located in other areas to form the gate 19. Specifically, this patterning process also requires fabricating a photoresist mask pattern, which is then used as a mask for etching processes; details will not be elaborated here.

[0105] like Figure 5 As shown, this embodiment of the invention also provides a semiconductor device, fabricated using the semiconductor device fabrication method provided in the above embodiments. The semiconductor device includes a substrate 10 and a heterojunction film layer disposed on the substrate 10. The semiconductor device further includes:

[0106] The second barrier layer 13 is located on the side of the heterojunction film layer facing away from the substrate 10. The second barrier layer 13 includes two barrier patterns; for example, the thickness of the edge portion of the barrier pattern near the gate 19 is greater than or equal to the thickness of the center portion of the barrier pattern.

[0107] Two electrode structures are located on the side of the second barrier layer 13 facing away from the substrate 10, and the bottom of the electrode structures extends into the interior of the second barrier layer or the interior of the heterojunction film layer.

[0108] Gate 19, the gate 19 is located on the side of the heterojunction film layer facing away from the substrate 10, and the orthogonal projection of the gate 19 on the substrate 10 is located between the orthogonal projections of the two barrier patterns on the substrate 10.

[0109] For example, the semiconductor device further includes a first insulating layer 14, a second insulating layer 17, a third insulating layer, and a second protective layer 300; at least a portion of the first insulating layer 14 is located between the electrode structure and the second barrier layer 13, the first insulating layer 14 has two connection holes, and the bottom of the electrode structure extends through the corresponding connection holes into the interior of the second barrier layer or the interior of the heterojunction layer; the second insulating layer 17 covers the first insulating layer 14 and the two electrode structures; the third insulating layer, the gate 19, and the second protective layer 300 are sequentially stacked in a direction away from the substrate 10, and the third insulating layer, the gate 19, and the second protective layer 300 are all located in the gate fabrication region of the semiconductor device.

[0110] The semiconductor device fabricated using the semiconductor device fabrication method provided in the above embodiments can form a virtual gate structure with a side slope angle greater than 90 degrees. This allows the side of the subsequently formed barrier pattern near the virtual gate structure to fit with the side of the virtual gate structure, enabling the edge portion of the second barrier layer 13 near the side of the virtual gate film layer 22 to grow sufficiently. Consequently, the edge portion of the second barrier layer 13 near the side of the virtual gate film layer 22 has a thicker thickness, resulting in a higher 2DEG concentration in the region of the fabricated semiconductor device near the gate 19. This ensures that the low resistance advantage of the semiconductor device can be well utilized.

[0111] This invention also provides a chip, including the semiconductor device provided in the above embodiments.

[0112] In the semiconductor device provided in the above embodiments, the region near the gate 19 has a high 2DEG concentration, which ensures that the advantage of low resistance of the semiconductor device can be well applied. Therefore, when the chip provided in the embodiments of the present invention includes the above semiconductor device, it also has the above-mentioned beneficial effects, which will not be repeated here.

[0113] It should be noted that, in the embodiments of the present invention, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0114] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0115] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0116] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0117] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0118] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0119] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A heterojunction film layer is fabricated on a substrate. A virtual gate structure is fabricated on the side of the heterojunction film layer facing away from the substrate, and the side slope angle of the virtual gate structure is greater than 90 degrees. A second barrier layer is formed on the side of the heterojunction film layer facing away from the substrate. The second barrier layer includes two barrier patterns, and the virtual gate structure is located between the two barrier patterns. The side of the barrier pattern close to the virtual gate structure is attached to the side of the virtual gate structure. Two electrode structures are fabricated on the side of the second barrier layer facing away from the substrate, and the bottom of the electrode structures extends into the interior of the second barrier layer or the interior of the heterojunction film layer. Remove the virtual gate structure to form the gate fabrication area; A gate is fabricated in the gate fabrication region.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of fabricating a virtual gate structure on the side of the heterojunction film layer facing away from the substrate specifically includes: An etching barrier layer, a first protective layer, and a virtual gate layer are sequentially formed on the side of the heterojunction film layer facing away from the substrate. Ion doping is performed on the portion of the virtual gate film layer located in the virtual gate structure formation region; After doping, the portion of the virtual gate film layer that has not been ion-doped is removed, and the portion of the first protective layer that is not located in the virtual gate structure formation region and the portion of the etch barrier layer that is not located in the virtual gate structure formation region are also removed; the remaining portion of the virtual gate film layer, part of the first protective layer and part of the etch barrier layer together constitute the virtual gate structure.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The specific steps for fabricating a heterojunction film layer on a substrate include: A channel layer and a first barrier layer are sequentially formed on the substrate. The step of fabricating a second barrier layer on the side of the heterojunction film layer facing away from the substrate specifically includes: On the side of the first barrier layer facing away from the substrate, a second barrier layer made of the same or different material is grown on both sides of the virtual gate structure.

4. The method for fabricating a semiconductor device according to claim 2, characterized in that, The steps of fabricating two electrode structures on the side of the second barrier layer facing away from the substrate specifically include: A first insulating layer is fabricated, which covers the virtual gate structure and the second barrier layer. The first insulating layer has two connection holes that expose at least a portion of the corresponding barrier pattern. The two electrode structures are fabricated on the side of the first insulating layer facing away from the substrate, and the electrode structures are connected to the corresponding barrier pattern through the corresponding connection holes.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The steps of removing the virtual gate structure to form the gate fabrication region specifically include: A second insulating layer is fabricated, which covers the first insulating layer and the two electrode structures; A patterning process is performed on the second insulating layer and the first insulating layer to form a process window that penetrates the second insulating layer and the first insulating layer, and the process window exposes the virtual gate structure. The virtual gate structure is removed through the process window to form the gate fabrication area.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The steps for fabricating the etching barrier layer, the first protective layer, and the virtual gate layer specifically include: The etching barrier layer was fabricated using ALN; The first protective layer is made of SiO; The virtual gate film layer is fabricated using Si; The step of removing the virtual gate structure through the process window to form the gate fabrication region specifically includes: The virtual gate film layer in the virtual gate structure is removed using chlorine-based gas through the process window. Through the process window, the first protective layer and the etching barrier layer in the virtual gate structure are removed by wet etching to form the gate fabrication area.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, characterized in that, The steps for fabricating the gate in the gate fabrication region specifically include: A third insulating material layer, a gate material layer, and a second protective layer are sequentially formed and stacked. The third insulating material layer, the gate material layer, and the second protective layer all fill the gate fabrication area and cover the two electrode structures. A patterning process is performed to retain the third insulating material layer, the gate material layer, and the second protective layer filling the gate fabrication area, and to remove the third insulating material layer, the gate material layer, and the second protective layer located in other areas to form the gate.

8. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1 to 7, the semiconductor device comprising a substrate and a heterojunction layer disposed on the substrate, and the semiconductor device further comprising: The second barrier layer is located on the side of the heterojunction film layer facing away from the substrate, and the second barrier layer includes two barrier patterns. Two electrode structures are located on the side of the second barrier layer facing away from the substrate, and the bottom of the electrode structures extends into the interior of the second barrier layer or the interior of the heterojunction film layer. A gate is located on the side of the heterojunction layer facing away from the substrate, and the orthographic projection of the gate on the substrate is located between the orthographic projections of the two barrier patterns on the substrate.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes a first insulating layer, a second insulating layer, a third insulating layer, and a second protective layer; At least a portion of the first insulating layer is located between the electrode structure and the second barrier layer. The first insulating layer has two connection holes. The bottom of the electrode structure extends through the corresponding connection holes into the interior of the second barrier layer or the interior of the heterojunction layer. The second insulating layer covers the first insulating layer and the two electrode structures; The third insulating layer, the gate, and the second protective layer are stacked sequentially in a direction away from the substrate, and the third insulating layer, the gate, and the second protective layer are all located in the gate fabrication region of the semiconductor device.

10. A chip, characterized in that, Including the semiconductor device as described in claim 8 or 9.

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