Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof, the device is provided with a cellular region containing a first region and a second region and a peripheral region, and a substrate comprises a substrate and an epitaxial layer which are stacked in sequence; cellular structures are arranged in the cellular region epitaxial layer, and the gate structure extends from the cellular region to the peripheral region and corresponds to one cellular structure; the first conductive layer at least comprises a first conductive plug located in the cellular region and electrically connected with the cellular structure, and a second conductive plug located in the peripheral region and electrically connected with the gate structure; the second conductive layer comprises a source conductive part, a gate conductive part and a first connecting structure, the source conductive part is located in the first region and electrically connected with the first conductive plugs, the gate conductive part is located in the second region and electrically isolated from the cellular structure, and the first connecting structure is located in the peripheral region and connected with the second conductive plugs and the gate conductive part. According to the semiconductor device and the preparation method thereof, the effective conduction area of a chip can be increased, and the conduction resistance can be reduced.

Description

A semiconductor device and its fabrication method Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Power metal-oxide-semiconductor field-effect transistors (MOSFETs), especially silicon carbide (SiC)-based power MOSFETs, are widely used in new energy power generation, electric vehicles, and industrial power conversion due to their high switching speed, low loss, and high temperature resistance. The on-resistance and chip area utilization of these devices are key indicators for evaluating performance and cost. Increasing the effective conduction area directly reduces on-resistance, improving device efficiency and market competitiveness.

[0003] In existing designs, gate pads are used to receive external drive signals and transmit them to the internal gate system of the chip. However, the area below the gate pads typically lacks cellular devices and is only treated with heavily doped regions to ensure signal integrity and wire bonding reliability. This area cannot participate in the conduction between the source and drain, becoming an "ineffective active region," resulting in low chip area utilization.

[0004] As devices evolve towards higher integration and lower power consumption, the unused area below the gate pads becomes increasingly restrictive on the device's conduction performance and power loss, necessitating a solution to fully utilize this area to improve chip conduction efficiency. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor device and its fabrication method to address the problems of low effective conduction area utilization and high conduction resistance in existing technologies.

[0006] To achieve the above objectives, in one respect, this application provides a semiconductor device having a cellular region and a peripheral region, the cellular region including a first region and a second region, the semiconductor device comprising:

[0007] The substrate includes a substrate and an epitaxial layer stacked sequentially;

[0008] A cellular structure is located in the cellular region and within the epitaxial layer, and both the first region and the second region have the cellular structure;

[0009] A gate structure is located on the side of the epitaxial layer away from the substrate and extends from the cell region to the peripheral region, with each cell structure corresponding to a gate structure;

[0010] The first conductive layer includes at least a plurality of first conductive plugs and a plurality of second conductive plugs, wherein the first conductive plugs are located in the first region and the second region, and each first conductive plug is electrically connected to the corresponding cell structure; the second conductive plugs are located in the peripheral region, and each second conductive plug is electrically connected to the corresponding gate structure.

[0011] The second conductive layer includes a source conductive portion, a gate conductive portion, and a first connection structure. The source conductive portion is located at least in the first region and is electrically connected to the first conductive plug. The gate conductive portion is located in the second region and is electrically isolated from the cell structure in the second region. The first connection structure is located in the peripheral region and is electrically connected to a plurality of second conductive plugs and electrically connected to the gate conductive portion.

[0012] In one embodiment, the first conductive layer further includes a second connection structure, which is located at least in the second region and electrically connects all the first conductive plugs located in the second region. The source conductive portion is electrically connected to the first conductive plugs located in the first region and to the second connection structure.

[0013] In one embodiment, the orthographic projection of the second connection structure on the substrate overlaps the orthographic projection of the second region on the substrate and extends into the first region.

[0014] In one embodiment, the gate conductive portion is electrically isolated from the first conductive plug located in the second region by an isolation layer, and the orthographic projection area of ​​the isolation layer on the substrate is not smaller than the orthographic projection area of ​​the gate conductive portion on the substrate.

[0015] In one embodiment, the cell structure includes a well region, a source region, and a contact region, wherein the well region is located within the epitaxial layer, the source region is located within the well region, and the contact region is located within the well region and adjacent to the source region;

[0016] The semiconductor device further includes an interlayer dielectric layer that covers the gate structure and has a plurality of first contact holes and a plurality of second contact holes therein. The bottom of the first contact holes exposes the source region and the contact region of each cell structure, and the first conductive plug fills the first contact hole.

[0017] The bottom of the second contact hole exposes each of the gate structures, and the second conductive plug fills the second contact hole.

[0018] In one embodiment, the second contact hole is located at both ends of the gate structure along a first direction, the first direction being the direction in which the gate structure extends from the cell region to the peripheral region;

[0019] The first connection structure includes a first sub-connection structure and a second sub-connection structure that are interconnected. The first sub-connection structure extends along a second direction and is located at both ends of the gate structure along the first direction. It is electrically connected to the second conductive plug in the second contact hole corresponding to each gate structure. The second sub-connection structure extends along the first direction and is located on the side of the gate away from the source conductive portion in the second direction. The second sub-connection structure is electrically connected to the gate and the first sub-connection structure respectively. The first direction intersects the second direction.

[0020] This application also provides a method for fabricating a semiconductor device, the semiconductor device having a cellular region and a peripheral region, the cellular region including a first region and a second region, the method for fabricating the semiconductor device comprising the following steps:

[0021] A substrate is provided, the substrate comprising a substrate and an epitaxial layer stacked sequentially;

[0022] A cellular structure is formed within the epitaxial layer of the cellular region, wherein the cellular structure is formed in both the first region and the second region;

[0023] A gate structure is formed on the side of the epitaxial layer away from the substrate. The gate structure extends from the cell region to the peripheral region, and each cell structure is provided with a corresponding gate structure.

[0024] A first conductive layer is formed, the first conductive layer including at least a plurality of first conductive plugs and a plurality of second conductive plugs, wherein the first conductive plugs are located in the first region and the second region, each first conductive plug is electrically connected to the corresponding cell structure, and the second conductive plugs are located in the peripheral region, each second conductive plug is electrically connected to the corresponding gate structure.

[0025] A second conductive layer is formed, the second conductive layer including a source conductive portion, a gate conductive portion and a first connection structure, wherein the source conductive portion is at least located in the first region and is electrically connected to the first conductive plug, the gate conductive portion is located in the second region and is electrically isolated from the cell structure in the second region, the first connection structure is located in the peripheral region and is electrically connected to a plurality of second conductive plugs and electrically connected to the gate conductive portion.

[0026] In one embodiment, forming a cellular structure within the epitaxial layer of the cellular region includes:

[0027] A trap region is formed within the epitaxial layer;

[0028] A source region is formed within the well region;

[0029] A contact region is formed within the well region, and the contact region is adjacent to the source region.

[0030] In one embodiment, the first conductive layer further includes a second connection structure, the second connection structure being at least located in the second region and electrically connecting all the first conductive plugs located in the second region, wherein forming the first conductive layer includes:

[0031] An interlayer dielectric layer is formed on the side of the epitaxial layer away from the substrate, and the interlayer dielectric layer covers the gate structure;

[0032] A plurality of first contact holes and a plurality of second contact holes are formed in the interlayer dielectric layer, wherein the bottom of the first contact hole exposes the source region and the contact region corresponding to the cell structure, and the bottom of the second contact hole exposes each of the gate structures.

[0033] A first conductive material layer is formed to fill the first contact hole, the second contact hole, and cover the side of the interlayer dielectric layer away from the substrate;

[0034] The first conductive material layer covering the side of the interlayer dielectric layer away from the substrate is etched. After etching, the first conductive material layer located in the first contact hole serves as the first conductive plug, the first conductive material layer located in the second contact hole serves as the second conductive plug, and the remaining first conductive material layer located on the side of the interlayer dielectric layer away from the substrate serves as the second connection structure.

[0035] In one embodiment, the source conductive portion is electrically connected to the first conductive plug located in the first region and to the second connection structure, wherein forming the second conductive layer includes:

[0036] A second conductive material layer is formed on the side of the first conductive layer away from the substrate;

[0037] The second conductive material layer is etched, wherein the second conductive material layer located at least in the first region and electrically connected to the first conductive plug located in the first region and electrically connected to the second connection structure serves as the source conductive portion; the second conductive material layer located in the second region and electrically isolated from the cell structure in the second region serves as the gate conductive portion; and the second conductive material layer located in the peripheral region and electrically connected to a plurality of second conductive plugs and electrically connected to the gate conductive portion serves as the first connection structure.

[0038] The aforementioned semiconductor device and its fabrication method, by forming cellular structures in both the first and second regions, transforms the second region into an active region with complete conductivity. The first conductive plug enables electrical connection between the cellular structure in the second region and the source conductive portion, allowing the cellular structure in the second region to participate in the conduction path of the source conductive portion. This avoids the problem of the second region being an ineffective active region in traditional structures, significantly increasing the effective conduction area per unit area of ​​the chip, thereby effectively reducing the on-resistance of the device. Furthermore, the first conductive plug located in the first region is directly electrically connected to the source conductive portion, shortening the current transmission path of the source conductive portion, reducing contact resistance and parasitic resistance introduced by interconnection, which is beneficial for improving... In some embodiments, the high current conduction capability and low loss characteristics of the device are achieved by connecting multiple first conductive plugs in parallel through a second connection structure in the cell structure of the second region. This enables cross-region conduction without increasing the number of metal layers, reducing interconnection complexity and minimizing stress concentration and reliability issues introduced by multilayer interconnect structures. Furthermore, by electrically connecting each gate structure one by one through the second conductive plug and the first connection structure, and then electrically connecting it to the gate conductive part, the gate signal is concentrated and uniformly distributed, significantly reducing the resistance voltage drop and time delay inconsistency caused by long-distance gate transmission, and improving the consistency of gate drive and switching synchronization in large-area power devices. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 is a top view of a semiconductor device provided in one embodiment;

[0041] Figure 2 is a schematic diagram of a partial cross-sectional structure of the semiconductor device provided in Figure 1 along the XX' direction;

[0042] Figure 3 is a top view of another semiconductor device provided in one embodiment;

[0043] Figure 4 is a schematic diagram of a partial cross-sectional structure of the semiconductor device shown in Figure 3 along the XX' direction;

[0044] Figure 5 is a schematic diagram of a partial cross-sectional structure of the semiconductor device shown in Figure 3 along the YY' direction;

[0045] Figure 6 is a flowchart of a method for fabricating a semiconductor device provided in one embodiment;

[0046] Figure 7 is a top view of the semiconductor device provided in one embodiment after the formation of the first contact hole and the second contact hole;

[0047] Figure 8 is a schematic diagram of a partial cross-sectional structure of the semiconductor device shown in Figure 7 along the XX' direction;

[0048] Figure 9 is a top view of the semiconductor device provided in one embodiment after the formation of the first conductive material layer;

[0049] Figure 10 is a schematic diagram of a partial cross-sectional structure of the semiconductor device shown in Figure 9 along the XX' direction;

[0050] Figure 11 is a top view of the semiconductor device provided in one embodiment after forming the first conductive plug, the second connection structure, and the second conductive plug.

[0051] Figure 12 is a schematic diagram of a partial cross-sectional structure of the semiconductor device provided in Figure 11 along the XX' direction;

[0052] Figure 13 is a top view of a semiconductor device after the formation of an isolation material layer in one embodiment;

[0053] Figure 14 is a schematic diagram of a partial cross-sectional structure of the semiconductor device provided in Figure 13 along the second direction;

[0054] Figure 15 is a top view of a semiconductor device after the formation of an isolation layer in one embodiment;

[0055] Figure 16 is a schematic diagram of a partial cross-sectional structure of the semiconductor device provided in Figure 15 along the second direction;

[0056] Figure 17 is a top view of the semiconductor device provided in one embodiment after forming the first conductive plug and the second conductive plug;

[0057] Figure 18 is a schematic diagram of a partial cross-sectional structure of the semiconductor device provided in Figure 17 along the XX' direction;

[0058] Figure 19 is a top view of another semiconductor device provided in one embodiment after the formation of an isolation material layer;

[0059] Figure 20 is a schematic diagram of a partial cross-sectional structure of the semiconductor device provided in Figure 19 along the second direction;

[0060] Figure 21 is a top view of another semiconductor device provided in one embodiment after the formation of an isolation layer;

[0061] Figure 22 is a schematic diagram of a partial cross-sectional structure of the semiconductor device shown in Figure 21 along the XX' direction.

[0062] Explanation of reference numerals in the attached figures:

[0063] A1 - Cell region, A11 - First region, A12 - Second region, A2 - Peripheral region, 1 - Substrate, 2 - Gate structure, 3 - First conductive layer, 31 - First conductive plug, 32 - Second connection structure, 33 - Second conductive plug, 34 - First conductive material layer, 4 - Second conductive layer, 41 - Source conductive portion, 42 - Gate conductive portion, 43 - First connection structure, 431 - First sub-connection structure, 432 - Second sub-connection structure, 5 - Interlayer dielectric layer, 51 - First contact hole, 52 - Second contact hole, 6 - Isolation layer, 61 - Isolation material layer, 7 - Isolation gap. Detailed Implementation

[0064] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0066] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0067] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0068] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0069] Please refer to Figures 1 to 5. This application provides a semiconductor device having a cell region A1 and a peripheral region A2 surrounding the cell region A1. The cell region A1 includes a first region A11 and a second region A12, comprising: a substrate 1, a cell structure (not shown), a gate structure 2, a first conductive layer 3, and a second conductive layer 4. The substrate 1 includes a substrate and an epitaxial layer stacked sequentially, and the epitaxial layer includes the first region A11 and the second region A12. The cell structure is located in the cell region A1 and within the epitaxial layer, and both the first region A11 and the second region A12 have cell structures. The gate structure 2 is located on the side of the epitaxial layer away from the substrate and extends from the cell region A1 to the peripheral region A2. Each cell structure corresponds to a gate structure 2. The first conductive layer 3 includes at least a plurality of first conductive plugs 31 and a plurality of... A second conductive plug 33, wherein a first conductive plug 31 is located in a first region A11 and a second region A12, and each first conductive plug 31 is electrically connected to a corresponding cell structure; a second conductive plug 33 is located in a peripheral region A2, and each second conductive plug 33 is electrically connected to a corresponding gate structure 2; a second conductive layer 4 includes a source conductive portion 41, a gate conductive portion 42, and a first connection structure 43, wherein the source conductive portion 41 is at least located in the first region A11 and is electrically connected to the first conductive plug 31; the gate conductive portion 42 is located in the second region A12 and is electrically isolated from the cell structure in the second region A12; the first connection structure 43 is located in the peripheral region A2 and is electrically connected to a plurality of second conductive plugs 33 and is electrically connected to the gate conductive portion 42.

[0070] In the above example, by forming cell structures in both the first region A11 and the second region A12, the second region A12 is transformed into an active region with complete conductivity. A first conductive plug 31 is used to achieve electrical connection between the cell structure within the second region A12 and the source conductive portion 41, enabling the cell structure of the second region A12 to participate in the conduction path of the source conductive portion 41. This avoids the problem of the second region A12 being an ineffective active region in traditional structures, significantly increasing the effective conduction area per unit area of ​​the chip, thereby effectively reducing the on-resistance of the device. Furthermore, the first conductive plug 31 located in the first region A11 and the second region A12 is connected to the source conductive portion 41... All parts 41 can be directly electrically connected, shortening the current transmission path of the source conductive part 41, reducing contact resistance and parasitic resistance introduced by interconnection, which is beneficial to improving the high current conduction capability and low loss characteristics of the device, and reducing stress concentration and reliability risks introduced by multilayer interconnection structure; in addition, each gate structure 2 is electrically connected one by one through the second conductive plug 33 and the first connection structure 43, and then electrically connected to the gate conductive part 42, realizing the centralized collection and uniform distribution of gate signal, significantly reducing the resistance voltage drop and time delay inconsistency caused by long-distance gate transmission, and improving the consistency of gate drive and switching synchronization in large-area power devices.

[0071] For example, the substrate is made of silicon carbide. Compared to traditional silicon, silicon carbide has a higher breakdown electric field strength, higher thermal conductivity, a wider bandgap, and stronger radiation resistance, making it suitable for fabricating power devices with high voltage withstand capability, high frequency, and high power density. It should be noted that the size of the substrate can be selected according to the actual situation and is not limited here.

[0072] In one embodiment, the epitaxial layer is epitaxially grown on the substrate surface and is made of the same material as the substrate, namely silicon carbide. The epitaxial layer is used to construct the core active region of the device, providing the foundation for the subsequent formation of the cell structure, and also undertaking the critical functions of current transport and voltage withstand. It should be noted that the size of the epitaxial layer can be selected according to the actual situation and is not limited here.

[0073] In one embodiment, the cell structure includes a well region (not shown), a source region (not shown), and a contact region (not shown). The well region is located within the epitaxial layer, the source region is located within the well region, and the contact region is located within the well region and adjacent to the source region. The doping concentration of the contact region is greater than that of the well region. The well region and the contact region have the same conductivity type, while the well region and the source region have opposite conductivity types. The well region is used to form the conductive channel of the device. When a threshold voltage is applied to the gate structure 2, a channel with the same conductivity type as the source region and the epitaxial layer is induced to form on the surface of the well region near the gate dielectric layer, providing a path for carrier transport. The source region is used to provide carriers and is the input terminal of the current, realizing the collection and transport of carriers. The contact region serves as the ohmic contact area between the source conductive part and the well region. The high doping concentration design can reduce the contact resistance, ensure a stable electrical connection between the source conductive part and the well region, and at the same time help suppress parasitic transistor effects in the device, improving the reliability of the device.

[0074] For example, the substrate has a first conductivity type, the epitaxial layer has a first conductivity type, the well region has a second conductivity type, the source region has a first conductivity type, and the contact region has a second conductivity type. It should be noted that the first conductivity type and the second conductivity type are opposite conductivity types; that is, when the first conductivity type is N-type, the second conductivity type is P-type; and when the first conductivity type is P-type, the second conductivity type is N-type. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type, meaning the substrate is an N-type silicon carbide substrate, the epitaxial layer is an N-type silicon carbide epitaxial layer, the well region is a P-type well region, the source region is an N-type source region, and the contact region is a P-type heavily doped contact region.

[0075] In one embodiment, the gate structure 2 includes a gate dielectric layer (not shown) and a gate layer (not shown) stacked sequentially. The gate dielectric layer is made of silicon dioxide, silicon oxynitride, or other suitable materials, with a thickness ranging from 300 Å to 800 Å. It is used to achieve electrical isolation between the gate layer and the epitaxial layer and well region, and also serves as a coupling medium for gate signals, controlling the formation and turn-off of the channel through the electric field effect. The gate layer is made of polysilicon, with a thickness ranging from 0.2 μm to 0.5 μm. It is used to receive external gate drive signals and generate a control electric field, and is the core control component for realizing the switching function of the device.

[0076] For example, the orthographic projection of the gate structure 2 on the substrate at least partially overlaps with the orthographic projection of the source region in the corresponding cell structure on the substrate, thereby enabling the electric field formed by the gate structure 2 to be effectively coupled to the channel region between the source region and the well region. When the gate driving voltage is applied, it is beneficial to form a stable and uniform conductive channel on the surface of the well region near the gate dielectric layer, improve the turn-on efficiency and current driving capability of the cell structure, and help reduce the turn-on voltage dispersion and on-resistance of the device.

[0077] It should be noted that the division of cell region A1 and peripheral region A2, and the first region A11 and the second region A12 in cell region A1 are all pre-planned and determined in the layout design stage, used to distinguish different metal interconnect functional regions. Cell region A1 is the region that forms cell structure, and peripheral region A2 is used for wiring design between gate structure 2 and gate conductive part 42. The first region A11 is mainly used to form source conductive part 41, which is used to extract electrical signals from multiple cell structures. The second region A12 is used to form gate conductive part 42, as gate metal region, which is used to electrically connect multiple gate structures 2 and extract gate signals.

[0078] For example, the first region A11 is designed as a U-shaped structure with its opening facing the second direction on the plane formed by the first and second directions. This allows the second region A12 to be at least partially embedded within the opening area of ​​the first region A11, thereby achieving a compact layout of different functional regions without increasing the chip area. On the one hand, this structure shortens the interconnection paths between the source conductive portion 41 and the second connection structure 32, and between the gate conductive portion 42 and the first connection structure 43, significantly reducing the parasitic resistance introduced by the metal interconnection. On the other hand, it facilitates the uniform distribution of current within the first region A11, reduces the edge current concentration effect, and improves the device's conduction capability and reliability under high current operating conditions. Simultaneously, the U-shaped layout improves the space utilization of the chip layout, which is beneficial for the miniaturization and high integration of the device.

[0079] In one embodiment, the source conductive portion 41 is made of aluminum, aluminum-copper alloy, copper, tungsten, or other suitable metal materials. The source conductive portion 41 is used to realize the signal interconnection and external lead-out of the source conductive portions of all cell structures. It has low resistivity, good process compatibility, and reliable bonding performance with the conductive plug 40, so as to reduce the series resistance of the device and improve the conduction performance.

[0080] In one embodiment, the gate conductive portion 42 is made of aluminum, an aluminum-copper alloy, copper, tungsten, or other suitable metal materials. The gate conductive portion 42 serves to perform external wire bonding connections and simultaneously collect and transmit gate signals. The gate conductive portion 42 must possess sufficient mechanical strength to withstand the mechanical stress generated during the wire bonding process, and have low contact resistance and good conductivity to ensure the stability and reliability of the gate drive signal.

[0081] In one embodiment, the semiconductor device further includes an interlayer dielectric layer 5. The interlayer dielectric layer 5 is made of silicon dioxide, silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), silicon nitride, a low-dielectric-constant dielectric material, or a combination thereof. The thickness of the interlayer dielectric layer 5 ranges from 0.5 μm to 1.0 μm, used to achieve electrical isolation between different conductive structures and provide mechanical support. The interlayer dielectric layer 5 covers the gate structure 2, and a plurality of first contact holes 51 are provided within the interlayer dielectric layer 5. The bottom of each first contact hole 51 exposes the source region and contact region of the corresponding cell structure, thereby enabling the first conductive plug 31 filled in the first contact hole 51 to form a stable ohmic contact with the source region and contact region, ensuring a low-resistance electrical connection between the first conductive plug 31 and the semiconductor layer.

[0082] The first conductive plug 31 is further connected to the source region and the contact region by a first contact layer (not shown). The first contact layer is made of metal silicide, which is used to further reduce contact resistance, improve electrical connection stability, effectively suppress parasitic transistor effects, and improve device reliability.

[0083] Specifically, the first conductive plug 31 located in the first region A11 is directly electrically connected to the source conductive part 41, realizing direct conduction of the source signal. As the main active region of the device, the first region A11 has a high cell structure density and a large current carrying capacity. Therefore, by directly connecting the first conductive plug 31 to the source conductive part 41, the signal transmission path of the source conductive part can be effectively shortened, reducing contact resistance and parasitic resistance introduced by metal interconnects, thereby significantly reducing the device's on-resistance and improving its current conduction capability. Simultaneously, compared with a multilayer interconnect structure, this design can effectively alleviate the stress caused by metal layer stacking, improving the mechanical reliability of the device.

[0084] Furthermore, as shown in Figures 1 and 2, in one embodiment, the first conductive layer 3 further includes a second connection structure 32. The second connection structure 32 is located at least in the second region A12 and electrically connects all the first conductive plugs 31 located in the second region A12. The source conductive portion 41 is electrically connected to the first conductive plugs 31 located in the first region A11 and is also electrically connected to the second connection structure 32. Therefore, the second connection structure 32 is used to connect multiple first conductive plugs 31 in the second region A12 and form a bridge with the source conductive portion 41, thereby realizing the conduction between the cell structure in the second region A12 and the metal layer of the source conductive portion. Through this indirect connection method, while ensuring that the cell structure in the second region A12 participates in conduction, it avoids electrical interference with the gate conductive portion 42 in the second region A12, taking into account both conduction requirements and electrical isolation requirements, so that the overall device achieves better comprehensive performance in terms of conduction performance, signal integrity, and structural reliability.

[0085] In one embodiment, the orthographic projection of the second connection structure 32 on the substrate overlaps the orthographic projection of the second region A12 on the substrate and extends into the first region A11. This allows the second connection structure 32 to achieve sufficient contact and electrical connection with all the first conductive plugs 31 within the second region A12, while simultaneously forming a stable electrical connection with the source conductive portion 41 in the portion extending into the first region A11. Through this structural design, it is ensured that each cell structure within the second region A12, after converging via the first conductive plugs 31 and the second connection structure 32, reliably conducts to the source conductive portion 41, thereby constructing a continuous, low-resistance current conduction path and improving the overall conduction consistency and current transmission stability of the device.

[0086] In another embodiment, as shown in Figures 3 to 5, the first conductive plug 31 located in the first region A11 is directly electrically connected to the source conductive part 41. The first conductive plug 31 located in the second region A12 conducts current through the first conductive plug 31 extending into the first region A11, and is then electrically connected to the source conductive part 41. This structural design eliminates the need for a separate connecting metal covering the entire second region within the cellular structure of the second region A12. The source current can be collected and extracted through the first conductive plug 31 in the first region A11. This further reduces the metal coverage area within the second region A12 while ensuring the cellular structure of the second region A12 participates in conduction, thereby reducing the risk of thermal runoff. The risk of parasitic capacitance and inter-metal layer coupling is beneficial to improving the high-frequency characteristics and signal stability of the device. At the same time, this transduction method reduces the number of metal interconnect layers and structural complexity in the second region A12, which helps to simplify the process steps, reduce the difficulty of the process, and reduce the concentration of thermal and mechanical stress caused by metal layer stacking, thereby improving the structural reliability and long-term operating stability of the device. In addition, by concentrating the main source current collection path in the first region A11, which has a high current carrying capacity, it is beneficial to optimize and homogenize the current distribution, avoid local current congestion, reduce the on-resistance of the device as a whole, and improve the current carrying capacity and conduction consistency of the power device.

[0087] In one embodiment, the gate conductive portion 42 and the first conductive plug 31 located in the second region A12 are electrically isolated by an isolation layer 6. The isolation layer 6 is an inorganic insulating material, including but not limited to silicon oxide, silicon nitride, or silicon oxynitride, used to form a stable electrically insulating structure between the gate conductive portion 42 and the second connection structure 32, thereby effectively preventing electrical short circuits between the gate metal and the connection path of the source conductive portion, and improving the electrical safety and operational reliability of the device; at the same time, the isolation layer 6 also serves to electrically isolate the gate conductive portion 42 from the cell structure in the second region A12, preventing the gate signal from interfering with the conduction path of the source conductive portion, and achieving a compatible design between gate lead-out and conduction performance without increasing the chip area.

[0088] In one embodiment, the source conductive portion 41 and the gate conductive portion 42 are spaced apart. For example, the source conductive portion 41 and the gate conductive portion 42 are isolated by an isolation gap 7. That is, electrical insulation is achieved by forming a physical gap between the source conductive portion 41 and the gate conductive portion 42, reducing parasitic capacitance and leakage risk, and taking into account both device safety and electrical performance.

[0089] In one embodiment, the orthographic projection area of ​​the isolation layer 6 on the substrate is not smaller than the orthographic projection area of ​​the gate conductive portion 42 on the substrate, so that the isolation layer 6 can completely cover the gate conductive portion 42, thereby effectively avoiding direct contact between the gate conductive portion 42 and the second connection structure 32, and eliminating the risk of short circuit between the gate metal and the source conductive portion connection path.

[0090] In another embodiment, the gate conductive portion 42 and the second connection structure 32 are electrically isolated by an isolation layer 6, the orthographic projection area of ​​the isolation layer 6 on the substrate being smaller than the orthographic projection area of ​​the second connection structure 32 on the substrate. This dimensional limitation allows the extension of the second connection structure 32 to cross the isolation layer 6 and fully overlap with the source conductive portion 41, thereby ensuring a stable and reliable electrical connection between the second connection structure 32 and the source conductive portion 41, and ensuring the continuity of the current conduction path and low resistance characteristics of the source conductive portion 41.

[0091] In one embodiment, the interlayer dielectric layer 5 further includes a second contact hole 52, the bottom of which exposes the gate layer. A second conductive plug 33 fills the second contact hole 52, thereby achieving an electrical connection between the gate layer and the first connection structure 43. Exemplarily, the second contact hole 52 is disposed at both ends of the gate layer along a first direction to facilitate the extraction and collection of gate signals, wherein the first direction is the direction in which the gate structure 2 extends from the cell region A1 to the peripheral region.

[0092] In one embodiment, the first connection structure 43 includes a first sub-connection structure 431 and a second sub-connection structure 432 connected to each other. The first sub-connection structure 431 extends along a second direction and is located at both ends of the gate layer along a first direction. It is electrically connected to the second conductive plugs 33 in the second contact holes 52 corresponding to each gate structure, and is used to collect and conduct gate signals of multiple gate structures. The second sub-connection structure 432 extends along the first direction and is located on the side of the gate conductive portion 42 away from the source conductive portion 41 in the second direction. It is electrically connected to the gate conductive portion 42 and the first sub-connection structure 431, and is used to concentrate and transmit the gate signals in the first sub-connection structure 431 to the gate conductive portion 42, thereby ensuring the uniformity and stability of the gate drive signal distribution within the chip. It should be noted that in this embodiment, the first direction and the second direction are perpendicular to each other, and the third direction in the cross-sectional view in the accompanying drawings is the thickness direction of the substrate 1, which is perpendicular to both the first direction and the second direction.

[0093] Through the above structural arrangement, the first connection structure 43 can be electrically connected to each gate layer, thereby achieving synchronous transmission of gate signals in all cell structures, ensuring the consistency of device switching operations, and improving the operational reliability of the device. Compared with the prior art method of only connecting a portion of the gate structure with leads, this embodiment effectively reduces the resistance voltage drop and time delay differences caused by the transmission of gate signals along the polysilicon layer by providing a second contact hole 52 at each gate structure 2 and using a second conductive plug 33 for electrical connection, significantly improving the consistency and uniformity of gate driving in large-area power devices.

[0094] In one embodiment, the semiconductor device further includes a drain metal layer (not shown), which is disposed on the side of the substrate away from the epitaxial layer. The drain metal layer is made of titanium (Ti), nickel (Ni), gold (Au), or a stacked structure thereof (e.g., Ti / Ni / Au), and serves as the drain lead of the device. The drain metal layer forms a reliable ohmic contact with the substrate to achieve drain current output. It needs to have low contact resistance, good thermal conductivity, and good solderability to meet the reliability requirements of power devices under high current conditions.

[0095] In one embodiment, a second contact layer (not shown) is further included between the drain metal layer and the substrate. The second contact layer is disposed on the side of the substrate away from the epitaxial layer, located between the drain metal layer and the substrate, and its material includes metal silicide or other suitable material.

[0096] In one embodiment, the semiconductor device further includes a field oxide layer (not shown). The isolation layer 6 extends beyond the second connection structure 32 on the side furthest from the source conductive portion 41 in the second direction and is disposed in conjunction with the field oxide layer to raise the height of the second sub-connection structure 432, thereby shortening the current transmission path and reducing the interconnect resistance, which in turn improves the device's conduction performance.

[0097] In one embodiment, referring to Figure 6, this application also provides a method for fabricating a semiconductor device. The semiconductor device has a cell region A1 and a peripheral region A2. The cell region A1 includes a first region A11 and a second region A12, and includes the following steps:

[0098] Step S1: Provide substrate 1, which includes a substrate and an epitaxial layer stacked sequentially;

[0099] Step S2: Multiple cell structures are formed in the epitaxial layer of cell region A1, wherein cell structures are formed in both the first region A11 and the second region A12.

[0100] Step S3: A gate structure 2 is formed on the side of the epitaxial layer away from the substrate. The gate structure 2 extends from the cell region A1 to the peripheral region A2, and each cell structure is provided with a corresponding gate structure 2.

[0101] Step S4: Form a first conductive layer 3. The first conductive layer 3 includes at least a plurality of first conductive plugs 31 and a plurality of second conductive plugs 33. The first conductive plugs 31 are located in the first region A11 and the second region A12. Each first conductive plug 31 is electrically connected to the corresponding cell structure. The second conductive plugs 33 are located in the peripheral region A2. Each second conductive plug 33 is electrically connected to the corresponding gate structure 2.

[0102] Step S5: Form a second conductive layer 4. The second conductive layer 4 includes a source conductive portion 41, a gate conductive portion 42, and a first connection structure 43. The source conductive portion 41 is located at least in the first region A11 and is electrically connected to the first conductive plug 31. The gate conductive portion 42 is located in the second region A12 and is electrically isolated from the cell structure in the second region A12. The first connection structure 43 is located in the peripheral region A2 and is electrically connected to a plurality of second conductive plugs 33 and is electrically connected to the gate conductive portion 42.

[0103] It should be noted that in the actual process of forming the cell structure (including the fabrication of the well region, source region, contact region and gate structure 2), the process of the first region A11 and the second region A12 is not distinguished. Instead, cell structures with the same structure, size and doping parameters are formed under both the first region A11 and the second region A12, so that the cell structure under the second region A12 has the same electrical characteristics and conductivity as the cell structure under the first region A11.

[0104] Specifically, steps S1 to S2 are performed to provide a substrate 1, which includes a substrate and an epitaxial layer stacked sequentially; multiple cell structures are formed in the epitaxial layer in cell region A1, wherein cell structures are formed in both the first region A11 and the second region A12.

[0105] In one embodiment, the method for forming the epitaxial layer includes chemical vapor deposition or other suitable methods.

[0106] In one embodiment, a plurality of cellular structures are formed within the epitaxial layer, including:

[0107] A trap region is formed within the epitaxial layer;

[0108] A source region is formed within the trap region;

[0109] A contact region is formed within the well region, adjacent to the source region, with a higher doping concentration in the contact region than in the well region. The well region and the contact region have the same conductivity type, while the well region and the source region have opposite conductivity types. The formation of the well region, source region, and contact region can be achieved using ion implantation. The implantation energy and dose are selected based on the device design requirements to obtain the desired doping concentration distribution and doping depth.

[0110] Furthermore, after forming multiple cellular structures within the epitaxial layer, it also includes:

[0111] The cellular structure is annealed to activate doping and repair lattice damage.

[0112] Specifically, please refer to Figures 7 and 8. Step S3 is performed to form a gate structure 2 on the side of the epitaxial layer away from the substrate. The gate structure 2 extends from the cell region A1 to the peripheral region A2, and each cell structure is provided with a corresponding gate structure 2.

[0113] In one embodiment, before forming the gate structure 2 on the side of the epitaxial layer away from the substrate, the method further includes:

[0114] A field oxide layer (not shown) is formed on the side of the epitaxial layer away from the substrate. Methods for forming the field oxide layer include local oxidation, thermal oxidation, chemical vapor deposition, or other suitable processes.

[0115] In one embodiment, a gate structure 2 is formed on the side of the epitaxial layer away from the substrate, comprising:

[0116] A gate dielectric layer is formed on the side of the epitaxial layer away from the substrate; the method for forming the gate dielectric layer includes thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable methods;

[0117] A gate layer is formed on the side of the gate dielectric layer away from the substrate; the method for forming the gate layer includes chemical vapor deposition, sputtering, evaporation or other suitable methods.

[0118] Specifically, please refer to Figures 9 to 22. Step S4 is performed to form a first conductive layer 3. The first conductive layer 3 includes at least a plurality of first conductive plugs 31 and a plurality of second conductive plugs 33. The first conductive plugs 31 are located in the first region A11 and the second region A12. Each first conductive plug 31 is electrically connected to the corresponding cell structure. The second conductive plugs 33 are located in the peripheral region A2, and each second conductive plug 33 is electrically connected to the corresponding gate structure 2.

[0119] In one embodiment, as shown in Figures 9 to 12, the first conductive layer 3 further includes a second connection structure 32, which is located at least in the second region A12 and electrically connects all the first conductive plugs 31 located in the second region A12 to form the first conductive layer 3, including:

[0120] An interlayer dielectric layer 5 is formed on the side of the epitaxial layer away from the substrate, and the interlayer dielectric layer 5 covers the gate structure 2; the method for forming the interlayer dielectric layer 5 includes chemical vapor deposition, atomic layer deposition or other suitable methods;

[0121] Multiple first contact holes 51 and multiple second contact holes 52 are formed in the interlayer dielectric layer 5. The bottom of each first contact hole 51 exposes the source region and contact region of the corresponding cell structure to ensure that the subsequent first conductive plug 31 forms a reliable electrical connection with the source region and contact region. The method for forming the first contact hole 51 includes photolithography and dry etching. The bottom of each second contact hole 52 exposes the gate structure 2 for external electrical connection of the gate structure 2. The method for forming the second contact hole 52 includes photolithography and dry etching.

[0122] A first conductive material layer 34 is formed to fill the first contact hole 51, fill the second contact hole 52, and cover the side of the interlayer dielectric layer 5 away from the substrate; the method of forming the first conductive material layer 34 includes chemical vapor deposition, sputtering or other suitable methods.

[0123] The first conductive material layer 34 covering the interlayer dielectric layer 5 on the side away from the substrate is etched. After etching, the first conductive material layer 34 filling the first contact hole 51 serves as the first conductive plug 31, the first conductive material layer 34 filling the second contact hole 52 serves as the second conductive plug 33, and the remaining first conductive material layer 34 on the side of the interlayer dielectric layer 5 away from the substrate serves as the second connection structure 32. This structure is used to connect multiple first conductive plugs 31 in the second region A12 and to electrically connect with the source conductive part 41, thereby realizing the conduction of the cell structure in the second region A12.

[0124] In addition, the second conductive plug 33 is formed simultaneously with the first conductive plug 31. That is, the second conductive plug 33 is formed by filling the second contact hole 52 with the same first conductive material layer (such as tungsten) to realize the electrical connection between the gate structure 2 and the subsequent first connection structure 43.

[0125] In one embodiment, before forming the first conductive material layer 34 that fills the first contact hole 51, fills the second contact hole 52, and covers the interlayer dielectric layer 5 on the side away from the substrate, the method further includes:

[0126] A first contact layer is formed at the bottom of the first contact hole 51.

[0127] In one embodiment, the first conductive material layer 34 is made of tungsten and is precisely formed by an anisotropic dry etching process to cover the surface of the interlayer dielectric layer 5, creating a second connection structure 32. Tungsten material has good etching selectivity, excellent anisotropic etching characteristics, high aspect ratio filling capacity, and good thermal stability, which is beneficial for forming a complete and void-free first conductive plug 31, second conductive plug 33, and second connection structure 32, ensuring reliable electrical connections. The second connection structure 32 is formed using an etching process, enabling multiple plugs to be connected in parallel in the second region A12. This achieves cross-regional conduction without increasing the number of metal layers, reducing interconnect complexity and minimizing stress concentration and reliability risks introduced by multilayer interconnect structures.

[0128] In one embodiment, as shown in Figures 13 to 16, after forming the first conductive layer 3, the method further includes:

[0129] An isolation layer 6 is formed on the side of the second connection structure 32 away from the substrate, and the orthographic projection of the isolation layer 6 on the substrate is smaller than the orthographic projection of the second connection structure 32 on the substrate.

[0130] In one embodiment, an isolation layer 6 is formed on the side of the second connection structure 32 away from the substrate, comprising:

[0131] An isolation material layer 61 is formed on the side of the interlayer dielectric layer 5 and the first conductive layer away from the substrate;

[0132] The isolation material layer 61 is etched so that the orthogonal projection of the etched isolation material layer 61 on the substrate is smaller than the orthogonal projection of the second connection structure 32 on the substrate.

[0133] In another embodiment, as shown in Figures 9 to 10 and Figures 17 to 18, the first conductive layer 3 includes a plurality of first conductive plugs 31 and a plurality of second conductive plugs 33 to form the first conductive layer 3, comprising:

[0134] An interlayer dielectric layer 5 is formed on the side of the epitaxial layer away from the substrate, and the interlayer dielectric layer 5 covers the gate structure 2; the method for forming the interlayer dielectric layer 5 includes chemical vapor deposition, atomic layer deposition or other suitable methods;

[0135] Multiple first contact holes 51 and multiple second contact holes 52 are formed in the interlayer dielectric layer 5. The bottom of each first contact hole 51 exposes the source region and contact region of the corresponding cell structure to ensure that the subsequent first conductive plug 31 forms a reliable electrical connection with the source region and contact region. The method for forming the first contact hole 51 includes photolithography and dry etching. The bottom of each second contact hole 52 exposes the gate structure 2 for external electrical connection of the gate structure 2. The method for forming the second contact hole 52 includes photolithography and dry etching.

[0136] A first conductive material layer 34 is formed to fill the first contact hole 51, fill the second contact hole 52, and cover the side of the interlayer dielectric layer 5 away from the substrate; the method of forming the first conductive material layer 34 includes chemical vapor deposition, sputtering or other suitable methods.

[0137] Remove the first conductive material layer 34 covering the side of the interlayer dielectric layer 5 away from the substrate. After removing the first conductive material layer 34 covering the side of the interlayer dielectric layer 5 away from the substrate, the first conductive material layer 34 filling the first contact hole 51 serves as the first conductive plug 31, and the first conductive material layer 34 filling the second contact hole 52 serves as the second conductive plug 33.

[0138] In another embodiment, as shown in Figures 19 to 22, after forming the first conductive layer 3, the method further includes:

[0139] An isolation layer 6 is formed on the side of the first conductive plug 31 and the interlayer dielectric layer 5 located in the second region A12 away from the substrate.

[0140] In one embodiment, an isolation layer 6 is formed on the side of the first conductive plug 31 and the interlayer dielectric layer 5 located in the second region A12 away from the substrate, including:

[0141] An isolation material layer 61 is formed on the side of the interlayer dielectric layer 5 and the first conductive layer 3 away from the substrate;

[0142] The isolation material layer 61 is etched to obtain the isolation layer 6, wherein the isolation layer 6 shall ensure that it completely covers the orthogonal projection of the first conductive plug 31 located in the second region A12 onto the substrate.

[0143] For example, the isolation layer 6 can be a single-layer or multi-layer structure. In this embodiment, the isolation layer 6 is a single-layer structure. Under the premise of meeting the electrical isolation performance, the height difference between the isolation layer 6 and the first region A11 is reduced by controlling the thickness, so as to avoid process defects in the subsequent metal deposition or etching process.

[0144] Specifically, please continue to refer to Figures 1 to 5 and execute step S5 to form a second conductive layer 4. The second conductive layer 4 includes a source conductive portion 41, a gate conductive portion 42, and a first connection structure 43. The source conductive portion 41 is located at least in the first region A11 and is electrically connected to the first conductive plug 31. The gate conductive portion 42 is located in the second region A12 and is electrically isolated from the cell structure in the second region A12. The first connection structure 43 is located in the peripheral region A2 and is electrically connected to a plurality of second conductive plugs 33 and is electrically connected to the gate conductive portion 42.

[0145] In one embodiment, as shown in Figures 1 and 2, the source conductive portion 41 is electrically connected to the first conductive plug 31 located in the first region A11 and to the second connection structure 32, forming a second conductive layer 4, including:

[0146] A second conductive material layer is formed on the side of the first conductive layer 3 away from the substrate. The method for forming the second conductive material layer (not shown) includes chemical vapor deposition, physical vapor deposition or other suitable methods. The second conductive material layer also covers the isolation layer 6.

[0147] The second conductive material layer is etched, wherein at least one of the second conductive material layers located in the first region A11, electrically connected to the first conductive plug 31 located in the first region A11, and electrically connected to the second connection structure 32, serves as the source conductive portion 41; the second conductive material layer located in the second region A12, and electrically isolated from the cell structure within the second region A12, serves as the gate conductive portion 42; the first connection structure 43 is located in the peripheral region A2, and the second conductive material layer electrically connected to the plurality of second conductive plugs 33 and electrically connected to the gate conductive portion 42 serves as the first connection structure 43; the method for etching the second conductive material layer includes dry etching, wet etching, or other suitable methods.

[0148] In this process, after etching the second conductive material layer, an isolation gap 7 is formed, which divides the gate conductive part 42, the source conductive part 41 and the first connection structure 43, thereby achieving electrical isolation. In addition, through synchronous forming, efficient wiring is achieved while simplifying the process. After etching, the metal material layer located in the second region A12 and whose orthogonal projection on the substrate is not greater than that of the isolation layer 6 forms the gate conductive part 42.

[0149] In another embodiment, as shown in Figures 3 to 5, the first conductive plug 31 located in the first region A11 is directly electrically connected to the source conductive portion 41, and the first conductive plug 31 located in the second region A12 is electrically connected to the source conductive portion 41 through the first conductive plug 31 extending to the first region A11, forming a second conductive layer 4, including:

[0150] A second conductive material layer is formed on the side of the first conductive layer 3 away from the substrate. The method for forming the second conductive material layer (not shown) includes chemical vapor deposition, physical vapor deposition or other suitable methods. The second conductive material layer also covers the isolation layer 6.

[0151] The second conductive material layer is etched, wherein at least in the first region A11, the second conductive material layer electrically connected to the first conductive plug 31 in the first region A11 serves as the source conductive part 41; in the second region A12, the second conductive material layer electrically isolated from the cell structure in the second region A12 serves as the gate conductive part 42; and in the peripheral region A2, the second conductive material layer electrically connected to a plurality of second conductive plugs 33 and electrically connected to the gate conductive part 42 serves as the first connection structure 43. In this embodiment, since the first conductive plug 31 located in the second region A12 is transduced through the first region A11, it is no longer necessary to set the second connection structure 32 for source junction in the second region A12. This reduces the metal stacking structure of the second conductive layer 4 in the second region A12, further reducing the overall step height of the second conductive material layer. By reducing the metal step height, the coverage and uniformity of the second conductive material layer deposition and etching process can be effectively improved, reducing the risk of metal fracture, voids or residues caused by excessive steps, and improving the process window and yield. At the same time, a lower metal step helps to reduce stress concentration, improve the structural reliability and long-term working stability of the device, and help to reduce parasitic capacitance, thereby further improving the electrical performance of the device.

[0152] The first conductive plug 31 and the second conductive plug 33 are formed synchronously using the same first conductive material layer. The source conductive part 41, the gate conductive part 42 and the first connection structure 43 are simultaneously etched, which reduces photolithography and deposition processes, simplifies the process flow, reduces manufacturing costs, and improves interlayer alignment accuracy and structural consistency.

[0153] In one embodiment, after forming the second conductive layer 4, the method further includes:

[0154] A drain metal layer is formed on the side of the substrate away from the epitaxial layer, which is used for the drain lead-out of the substrate.

[0155] In addition, before forming the drain metal layer, a second contact layer can be formed at the bottom of the first contact hole 51 to improve the contact resistance, and the side of the substrate away from the epitaxial layer can be thinned to form a second contact layer to improve the uniformity of the drain current and the thermal performance of the device.

[0156] Therefore, this application, while maintaining electrical isolation and reliable packaging of the gate pad, makes full use of the second region A12 to arrange the cell structure and achieve effective electrical connection, significantly improving the effective conduction area of ​​the chip, reducing conduction resistance and power loss, while taking into account gate drive consistency and manufacturing process feasibility, and is suitable for high power density and low loss silicon carbide power devices.

[0157] It should be understood that although the steps in the flowchart of Figure 6 are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in Figure 6 may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0158] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0159] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0160] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has a cellular region and a peripheral region. The cellular region includes a first region and a second region. The semiconductor device includes: a substrate, comprising a substrate and an epitaxial layer stacked sequentially; a cellular structure located in the cellular region and within the epitaxial layer, wherein both the first region and the second region have the cellular structure; a gate structure located on the side of the epitaxial layer away from the substrate and extending from the cellular region to the peripheral region, wherein each cellular structure corresponds to a gate structure; and a first conductive layer, including at least a plurality of first conductive plugs and a plurality of second conductive plugs, wherein the first conductive plugs are located in the first region and the second region, and each... The first conductive plugs are electrically connected to the corresponding cell structures, the second conductive plugs are located in the peripheral region, and each second conductive plug is electrically connected to the corresponding gate structure; the second conductive layer includes a source conductive portion, a gate conductive portion, and a first connection structure, wherein the source conductive portion is at least located in the first region and is electrically connected to the first conductive plugs, the gate conductive portion is located in the second region and is electrically isolated from the cell structures in the second region, the first connection structure is located in the peripheral region, and the first connection structure is electrically connected to a plurality of second conductive plugs and electrically connected to the gate conductive portion.

2. The semiconductor device according to claim 1, characterized in that, The first conductive layer further includes a second connection structure, which is located at least in the second region and electrically connects all the first conductive plugs located in the second region. The source conductive portion is electrically connected to the first conductive plugs located in the first region and to the second connection structure.

3. The semiconductor device according to claim 2, characterized in that, The orthographic projection of the second connection structure on the substrate covers the orthographic projection of the second region on the substrate and extends into the first region.

4. The semiconductor device according to claim 1, characterized in that, The gate conductive portion is electrically isolated from the first conductive plug located in the second region by an isolation layer, and the orthographic projection area of ​​the isolation layer on the substrate is not smaller than the orthographic projection area of ​​the gate conductive portion on the substrate, which is a second connection structure.

5. The semiconductor device according to claim 1, characterized in that, The cell structure includes a well region, a source region, and a contact region, wherein the well region is located within the epitaxial layer, the source region is located within the well region, and the contact region is located within the well region and adjacent to the source region; the semiconductor device further includes an interlayer dielectric layer that covers the gate structure, and the interlayer dielectric layer has a plurality of first contact holes and a plurality of second contact holes, the bottom of the first contact holes exposing the source region and the contact region of each cell structure, and the first conductive plug filling the first contact hole; the bottom of the second contact holes exposes each gate structure, and the second conductive plug filling the second contact hole.

6. The semiconductor device according to claim 5, characterized in that, The second contact hole is located at both ends of the gate structure along a first direction, the first direction being the direction in which the gate structure extends from the cell region to the peripheral region; the first connection structure includes a first sub-connection structure and a second sub-connection structure that are interconnected, the first sub-connection structure extends along a second direction and is located at both ends of the gate structure along the first direction, and is electrically connected to the second conductive plug in the second contact hole corresponding to each of the gate structures, the second sub-connection structure extends along the first direction and is located on the side of the gate away from the source conductive portion in the second direction, the second sub-connection structure is electrically connected to the gate conductive portion and the first sub-connection structure, and the first direction intersects the second direction.

7. A method for fabricating a semiconductor device, characterized in that, The semiconductor device has a cellular region and a peripheral region. The cellular region includes a first region and a second region. The method for fabricating the semiconductor device includes the following steps: providing a substrate, the substrate including a substrate and an epitaxial layer stacked sequentially; forming a cellular structure within the epitaxial layer of the cellular region, wherein the cellular structure is formed in both the first region and the second region; forming a gate structure on the side of the epitaxial layer away from the substrate, the gate structure extending from the cellular region to the peripheral region, and each cellular structure corresponding to a gate structure; forming a first conductive layer, the first conductive layer including at least a plurality of first conductive plugs and a plurality of second conductive plugs, wherein the first conductive plugs are located in the first region. The system comprises a first region and a second region, wherein each of the first conductive plugs is electrically connected to the corresponding cell structure, the second conductive plugs are located in the peripheral region, and each of the second conductive plugs is electrically connected to the corresponding gate structure; a second conductive layer is formed, the second conductive layer comprising a source conductive portion, a gate conductive portion, and a first connection structure, wherein the source conductive portion is at least located in the first region and is electrically connected to the first conductive plug, the gate conductive portion is located in the second region and is electrically isolated from the cell structure in the second region, the first connection structure is located in the peripheral region, and the first connection structure is electrically connected to a plurality of second conductive plugs and electrically connected to the gate conductive portion.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The formation of a cellular structure within the epitaxial layer of the cellular region includes: forming a well region within the epitaxial layer; forming a source region within the well region; and forming a contact region within the well region, wherein the contact region is adjacent to the source region.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The first conductive layer further includes a second connection structure, the second connection structure being at least located in the second region and electrically connecting all the first conductive plugs located in the second region. The formation of the first conductive layer includes: forming an interlayer dielectric layer on the side of the epitaxial layer away from the substrate, the interlayer dielectric layer covering the gate structure; forming a plurality of first contact holes and a plurality of second contact holes within the interlayer dielectric layer, the bottom of the first contact holes exposing the source region and the contact region corresponding to the cell structure, and the bottom of the second contact holes exposing each of the gate structures; forming a first conductive material layer that fills the first contact holes and the second contact holes and covers the side of the interlayer dielectric layer away from the substrate; etching the first conductive material layer covering the side of the interlayer dielectric layer away from the substrate, wherein, after etching, the first conductive material layer located in the first contact holes serves as the first conductive plug, the first conductive material layer located in the second contact holes serves as the second conductive plug, and the remaining first conductive material layer located on the side of the interlayer dielectric layer away from the substrate serves as the second connection structure.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The source conductive portion is electrically connected to the first conductive plug located in the first region and to the second connection structure. The formation of the second conductive layer includes: forming a second conductive material layer on the side of the first conductive layer away from the substrate; etching the second conductive material layer, wherein the second conductive material layer located at least in the first region and electrically connected to the first conductive plug located in the first region and electrically connected to the second connection structure serves as the source conductive portion; the second conductive material layer located in the second region and electrically isolated from the cell structure in the second region serves as the gate conductive portion; and the second conductive material layer located in the peripheral region and electrically connected to a plurality of second conductive plugs and electrically connected to the gate conductive portion serves as the first connection structure.

Images