Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present application relate to a semiconductor device and a manufacturing method thereof. A semiconductor device of one embodiment includes a semiconductor substrate, a cell region provided on a first surface side of the semiconductor substrate, and a terminal region provided on the first surface side of the semiconductor substrate outside the cell region. The terminal region includes a plurality of first diffusion layers surrounding the cell region and containing impurities of a first conductivity type. At least one of the plurality of first diffusion layers has a first region extending from the first surface to a second surface of the semiconductor substrate in a first direction perpendicular to the first surface, and a second region extending from the first region in a second direction orthogonal to the first direction, in a cross section of the terminal region in the first direction. The second region contains the impurities of the first conductivity type at a lower concentration than the first region.

Description

[0001] This invention is a divisional application of the following application, the original application information of which is as follows: Application date: December 23, 2022 Application Number: 202211662572.7 Invention Title: Semiconductor Device and Manufacturing Method Thereof Related applications

[0002] This application claims priority to Japanese Patent Application No. 2022-151838 (filed on September 22, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0004] In the termination regions of power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), a structure typically consists of multiple P-type semiconductor layers arranged in a guard ring to maintain breakdown voltage. In this guard ring termination structure, the electric field intensifies around the P-type semiconductor layers. Therefore, forming deep, semi-circular P-type semiconductor layers is crucial to ensure breakdown voltage. However, in guard ring layers with such a cross-sectional shape, the width of the termination region increases. Consequently, the area occupied by the termination region within the power semiconductor device becomes larger, hindering the miniaturization of the device.

[0005] Therefore, there are methods to form a protective ring layer with a rectangular cross-sectional shape formed through low-temperature heat treatment, thereby reducing the area of ​​the terminal region. However, in a rectangular protective ring layer, the curvature at the corners becomes smaller. Therefore, the electric field concentrates near the corners, and the withstand voltage can be reduced. Summary of the Invention

[0006] One embodiment of a semiconductor device includes: a semiconductor substrate; a cell region disposed on a first surface of the semiconductor substrate; and a termination region disposed on the first surface of the semiconductor substrate outside the cell region. The termination region includes a plurality of first diffusion layers that continuously surround the cell region and contain a first conductivity type impurity. In a cross-section of the termination region in a first direction perpendicular to the first surface, at least one of the plurality of first diffusion layers has: a first region extending from the first surface of the semiconductor substrate to a second surface in the first direction; and a second region extending from the first region in a second direction orthogonal to the first direction. The concentration of the first conductivity type impurity contained in the second region is lower than the concentration of the first conductivity type impurity contained in the first region.

[0007] Embodiments of the present invention provide a semiconductor device and a method thereof capable of suppressing the area of ​​the terminal region and avoiding a decrease in voltage withstand capability. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view showing the general structure of the semiconductor device according to the first embodiment.

[0009] Figure 2A This is a cross-sectional view showing the formation process of the first P-type impurity layer.

[0010] Figure 2B This is a cross-sectional view showing the formation process of the second P-type impurity layer.

[0011] Figure 2C This is a cross-sectional view showing the formation process of the third P-type impurity layer.

[0012] Figure 2D This is a cross-sectional view showing the formation process of the fourth P-type impurity layer.

[0013] Figure 2E This is a cross-sectional view showing the formation process of the fifth P-type impurity layer.

[0014] Figure 2F This is a cross-sectional view showing the heat treatment process for each P-type impurity layer.

[0015] Figure 2G This is a cross-sectional view showing the process of forming the interlayer insulating film.

[0016] Figure 2H This is a cross-sectional view showing the process of forming the N-type buffer layer and the P-type collector layer.

[0017] Figure 3 This is a cross-sectional view showing the structure of the semiconductor device of the first comparative example.

[0018] Figure 4 This is a cross-sectional view showing the structure of the semiconductor device of the second comparative example.

[0019] Figure 5 This is a graph showing an example of the results of a simulation of the electric field distribution in the terminal region.

[0020] Figure 6 This is a graph representing an example of the results of a simulation of the electric field distribution in the terminal region when the width of the second region is changed.

[0021] Figure 7 This is a cross-sectional view showing the general structure of the semiconductor device according to the second embodiment.

[0022] Figure 8This is a graph showing an example of the results of a simulation of the withstand voltage.

[0023] Figure 9 This is a cross-sectional view showing the general structure of the semiconductor device according to the third embodiment.

[0024] Figure 10A This is a cross-sectional view showing the process of forming the first opening in the first interlayer insulating film.

[0025] Figure 10B This is a cross-sectional view showing the formation process of the first conductive film.

[0026] Figure 10C This is a cross-sectional view showing the process of removing a portion of the first conductive film.

[0027] Figure 10D This is a cross-sectional view showing the process of forming the second opening in the second interlayer insulating film.

[0028] Figure 10E This is a cross-sectional view showing the formation process of the second conductive film.

[0029] Figure 10F This is a cross-sectional view showing the process of removing a portion of the second conductive film.

[0030] Figure 10G This is a cross-sectional view showing the process of forming a passivation film.

[0031] Figure 11A This is a cross-sectional view showing the protective ring extending from the second region to both sides of the first region.

[0032] Figure 11B This is a cross-sectional view showing that the bottom of the second region, which extends to both sides of the first region, is positioned at a shallower location than the bottom of the first region.

[0033] Figure 11C This is a cross-sectional view showing that the bottom of the second region, which extends outward from the first region, is positioned at a shallower location than the bottom of the first region.

[0034] Figure 11D This is a cross-sectional view showing that the bottom of the second region, which extends inward toward the first region, is positioned at a shallower location than the bottom of the first region.

[0035] Figure 11E This is a cross-sectional view showing that the bottom of the second region, which extends to both sides of the first region, is located at a deeper position than the bottom of the first region.

[0036] Figure 11FThis is a cross-sectional view showing that the bottom of the second region, which extends outward from the first region, is positioned at a deeper level than the bottom of the first region.

[0037] Figure 11G This is a cross-sectional view showing that the bottom of the second region, which extends inward toward the first region, is positioned at a depth deeper than the bottom of the first region.

[0038] Figure 11H It is a cross-sectional view of the protective ring layer that extends from the second region to both sides of the first region and the bottom of the first region contacts the second region. Detailed Implementation

[0039] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments are not intended to limit the scope of the present invention.

[0040] (First Implementation) Figure 1 This is a cross-sectional view showing the general structure of the semiconductor device according to the first embodiment. Figure 1 The semiconductor device 1 shown is an IGBT with a trench gate structure. This semiconductor device 1 has a cell region 20 and a termination region 30 on the surface side of the semiconductor substrate 10. Furthermore, the cell region 20 and the termination region 30 are covered by an interlayer insulating film 40. The interlayer insulating film 40 is, for example, made of silicon oxide (SiO2) film. Additionally, the semiconductor device 1 is not limited to a trench gate IGBT; for example, it could also be a planar gate IGBT.

[0041] The semiconductor substrate 10 has a P-type collector layer 11, an N-type buffer layer 12, and an N-type base layer 13. Each layer will be described below.

[0042] The P-type collector layer 11 is disposed at the bottom layer in the semiconductor substrate 10. The P-type collector layer 11 functions as the collector of the IGBT. The thickness of the P-type collector layer 11 is, for example, 0.2 μm.

[0043] An N-type buffer layer 12 is stacked on a P-type collector layer 11. The concentration of N-type impurities contained in the N-type buffer layer 12 is higher than the concentration of N-type impurities contained in the N-type base layer 13. The thickness of the N-type buffer layer 12 is, for example, 1 μm.

[0044] The N-type base layer 13 is stacked on the N-type buffer layer 12. The N-type base layer 13 is equivalent to the first semiconductor layer, and a cell region 20 and a terminal region 30 are provided on its surface side (first surface side).

[0045] First, the cell region 20 will be described. The cell region 20 has a P-type base layer 21, a gate electrode 22, a gate insulating film 23, and an N-type emitter layer 24.

[0046] The P-type base layer 21 is equivalent to a second diffusion layer and is disposed on the surface of the semiconductor substrate 10 (N-type base layer 13). The P-type impurity concentration of the P-type base layer 21 is lower than the P-type impurity concentration contained in the first region 311 of the guard ring layer 310 disposed in the terminal region 30 described later.

[0047] The gate electrode 22 extends from the surface of the semiconductor substrate 10 through the P-type base layer 21 and terminates in the N-type base layer 13. The gate electrode 22 may contain, for example, polysilicon.

[0048] The gate insulating film 23 electrically insulates the gate electrode 22 from the N-type base layer 13, the P-type base layer 21, and the N-type emitter layer 24. The gate insulating film 23 is, for example, a silicon oxide film.

[0049] The N-type emitter layer 24 is equivalent to a third diffusion layer containing N-type impurities, and it is located inside the P-type base layer 21, separated from the gate electrode 22 by the gate insulating film 23. The N-type emitter layer 24 functions as the emitter of the IGBT.

[0050] Next, the terminal region 30, which is located outside the cell region 20, will be described. The terminal region 30 includes an N-type EQPR (EQuivalent-Potential Ring) layer 300 and a plurality of guard ring layers 310.

[0051] The EQPR layer 300 is disposed on the outermost side of the terminal region 30. The concentration of N-type impurities contained in the EQPR layer 300 is higher than that contained in the N-type base layer 13. The EQPR layer 300 and the P-type collector layer 11 are at the same potential.

[0052] Each of the multiple protective ring layers 310 is composed of annular P-type diffusion layers that continuously surround the unit region 20. In this embodiment, seven protective ring layers are disposed in the terminal region 30, but the number of protective ring layers can be multiple.

[0053] like Figure 1 As shown, the protective ring layer 310 of this embodiment has a first region 311 and a second region 312 in a cross-section of the terminal region 30 in a first direction perpendicular to the surface of the semiconductor substrate 10. The diffusion regions will be described below.

[0054] The first region 311 extends from the surface of the semiconductor substrate 10 toward the back side (second side) in the first direction. The concentration of P-type impurities contained in the first region 311 is higher than the concentration of P-type impurities contained in the P-type base layer 21 of the cell region 20.

[0055] The second region 312 extends from near the bottom of the first region 311 in a second direction orthogonal to the first direction (a direction parallel to the surface of the semiconductor substrate 10). In this embodiment, the second region 312 extends from the bottom of the first region 311 toward the EQPR layer 300 side. Furthermore, the width (W1+W2) of the bottom of each protective ring layer 310 is larger than the width (W1) of the upper part of each protective ring layer 310 located on the surface side of the semiconductor substrate 10. Furthermore, as... Figure 1 As shown, an N-type base layer 13, which serves as an N-type semiconductor layer, is provided on the upper part of the second region 312.

[0056] In this embodiment, all of the protective ring layers 310 have a first region 311 and a second region 312. However, it is also possible that a portion of the protective ring layers 310, such as the protective ring layer 310 closest to the unit region 20, consists only of the first region 311 and does not have the second region 312.

[0057] The following is for reference Figures 2A to 2H The manufacturing method of the semiconductor device according to the first embodiment described above will be explained. Here, the manufacturing process of the terminal region 30 will be mainly described.

[0058] First, such as Figure 2A As shown, a photoresist 50 is formed on the surface of a semiconductor substrate 10a composed of an N-type base layer 13. The photoresist 50 is patterned to form openings at the formation locations of the first region 311 of the protective ring layer 310.

[0059] Next, boron (B) ions are irradiated from above the resist 50. At this time, for example, the dose of boron ions is set to 1 × 10⁻⁶. 13 cm -2 The accelerating voltage was set to 3.5 MeV. For example... Figure 2A As shown, the result is that a first P-type impurity layer 311a is formed inside the N-type base layer 13.

[0060] Next, as Figure 2B As shown, the irradiation conditions were changed to irradiate boron (B) ions. The dose of boron ions was, for example, set to 3 × 10⁻⁶. 13 cm -2 This is an increase compared to when the first P-type impurity layer 311a is formed. Furthermore, the accelerating voltage is set, for example, to 2 MeV, which is a decrease compared to when the first P-type impurity layer 311a is formed. Figure 2B As shown, the result is that a second P-type impurity layer 311b is formed on the first P-type impurity layer 311a.

[0061] Next, as Figure 2C As shown, the irradiation conditions were further changed to irradiate boron (B) ions. In this case, the boron ion dose was set, for example, to 1 × 10⁻⁶.14 cm -2 This is an increase compared to when the second P-type impurity layer 311b is formed. Furthermore, the accelerating voltage is set, for example, to 1 MeV, which is a decrease compared to when the second P-type impurity layer 311b is formed. Figure 2C As shown, the result is that a third P-type impurity layer 311c is formed on the second P-type impurity layer 311b.

[0062] Next, as Figure 2D As shown, the irradiation conditions were further changed to irradiate boron (B) ions. In this case, the boron ion dose was set, for example, to 3 × 10⁻⁶. 14 cm -2 The voltage is increased compared to when the third P-type impurity layer 311c is formed. Furthermore, the accelerating voltage is set, for example, to 100 keV, which is decreased compared to when the third P-type impurity layer 311c is formed. Figure 2D As shown, the result is that a fourth P-type impurity layer 311d is formed on the third P-type impurity layer 311c. Afterwards, the resist 50 is removed.

[0063] In the above Figures 2A to 2D The first P-type impurity layer 311a to the fourth P-type impurity layer 311d formed in the process shown corresponds to the state of the first region 311 before diffusion. In this embodiment, as described above, boron ions are repeatedly injected while adjusting the dosage of boron ions and accelerating the voltage change, thereby forming the impurity layer that forms the basis of the first region 311.

[0064] Next, as Figure 2E As shown, a photoresist 60 is formed on the surface of the semiconductor substrate 10a. The photoresist 60 is patterned to form openings at the locations of the second region 312. Next, boron (B) ions are irradiated from above the photoresist 60. At this time, the dose of boron ions and the accelerating voltage are the same as those used in the formation of the first P-type impurity layer 311a, and are respectively set to 1 × 10⁻⁶. 13 cm -2 And 3.5MeV. For example... Figure 2E As shown, the result is that a fifth P-type impurity layer 312a is formed adjacent to the first P-type impurity layer 311a. The fifth P-type impurity layer 312a corresponds to the pre-diffusion state of the second region 312. Afterwards, the resist 60 is removed.

[0065] Furthermore, in this embodiment, the formation process of the first P-type impurity layer 311a to the fourth P-type impurity layer 311d is continuous with the formation process of the fifth P-type impurity layer 312a, but these processes may also be discontinuous. Additionally, in this embodiment, the fifth P-type impurity layer 312a is formed after the first P-type impurity layers 311a to the fourth P-type impurity layers 311d, but it may also be formed before them.

[0066] The first P-type impurity layer 311a to the fifth P-type impurity layer 312a, formed as described above, are subjected to heat treatment. Figure 2F As shown, the result is that boron is activated in each P-type impurity layer, forming the first region 311 and the second region 312. At this time, boron diffusion is suppressed by performing a low-temperature heat treatment below 1000°C. As a result, the cross-sectional shape of the semiconductor substrate 10 perpendicular to the first region 311 and the second region 312 can be made into a rectangular shape with rounded corners.

[0067] Next, cell region 20 is formed. Here, for example, a P-type base layer 21 and an N-type emitter layer 24 are formed by ion implantation. Furthermore, a trench terminating at the N-type emitter layer 24 is formed through the P-type base layer 21 by RIE (Reactive Ion Etching). A gate insulating film 23 and a gate electrode 22 are sequentially formed within this trench by CVD (Chemical Vapor Deposition).

[0068] Next, as Figure 2G As shown, an interlayer insulating film 40 is formed on the surface of a semiconductor substrate 10a on which a protective ring layer 310 is formed.

[0069] Finally, as Figure 2H As shown, an N-type buffer layer 12 and a P-type collector layer 11 are sequentially formed on the entire back side of the semiconductor substrate 10a. The N-type buffer layer 12 can be formed, for example, by implanting phosphorus (P) ions into the back side of the semiconductor substrate 10a and then performing an annealing process. On the other hand, the P-type collector layer 11 can be formed by implanting boron ions into the back side of the semiconductor substrate 10a and then performing an annealing process. Alternatively, the P-type collector layer 11 may not be formed in the terminal region 30.

[0070] Here, a semiconductor device of a comparative example, compared with the semiconductor device 1 of the first embodiment described above, will be described.

[0071] Figure 3 This is a cross-sectional view showing the structure of the semiconductor device of the first comparative example. In this comparative example, the same reference numerals are used to label the same components as those in the semiconductor device 1 of the first embodiment, and detailed descriptions are omitted.

[0072] The cross-sectional shape of the protective ring layer in the terminal region 30 of the semiconductor device 100 in this comparative example differs from that in the first embodiment. In this modified example, the curvature of the protective ring layer 310a becomes rounded.

[0073] The protective ring layer 310a is formed by subjecting boron implanted onto the surface of the semiconductor substrate 10 to a high-temperature and long-term heat treatment, resulting in a P-type diffusion layer that is deep and wide from the surface of the semiconductor substrate 10. That is, the cross-section of the protective ring layer 310a is approximately semi-circular. However, the W3-wide diffusion layer, such as the protective ring layer 310a, becomes a significant factor in increasing the length of the terminal region 30. Therefore, it becomes difficult to narrow the width of the terminal region 30.

[0074] Figure 4 This is a cross-sectional view showing the structure of the semiconductor device of the second comparative example. In this comparative example, the same reference numerals are used to label the same components as in the semiconductor device 1 of the first embodiment, and detailed descriptions are omitted.

[0075] In the semiconductor device 101 of this comparative example, the protective ring layer 310b of the terminal region 30 has a nearly rectangular cross-sectional shape. To suppress lateral expansion, the diffusion temperature of the protective ring layer 310b is set to a low temperature of 1000°C or below. Therefore, the width W4 of the protective ring layer 310b is narrower than the width W3 of the protective ring layer 310a in the first comparative example described above. This allows for the suppression of the size of the terminal region 30.

[0076] However, in the protective ring layer 310b, the curvature of the bottom corner is smaller compared to that of the protective ring layer 310a in the first comparative example. Therefore, the electric field concentrates near this corner, thereby reducing the withstand voltage.

[0077] In contrast, the protective ring layer 310 of this embodiment is formed by low-temperature heat treatment, similar to that of the second comparative example. Therefore, the electric field can be concentrated at the corner of the first region 311.

[0078] However, in the protective ring layer 310, a second region 312 with a lower concentration of P-type impurities than the first region 311 extends from the corner of the first region 311. This second region 312 can mitigate the electric field concentration at the corner of the first region 311.

[0079] Figure 5 This is a graph illustrating an example of the results of a simulation of the electric field distribution in the terminal region 30 with respect to this embodiment and the second comparative example. Figure 5 In the diagram, the horizontal axis represents the lateral position of the terminal region 30 when the boundary between the cell region 20 and the terminal region 30 is used as a reference. The vertical axis represents the electric field on the surface of the semiconductor substrate 10 in the terminal region 30.

[0080] according to Figure 5 The simulation results shown demonstrate that, compared to the second comparative example, this embodiment can suppress the electric field in the terminal region 30. Consequently, the withstand voltage is improved, and therefore, the expansion of the width of the terminal region 30 can be suppressed.

[0081] Figure 6 This is a graph showing an example of the results of a simulation of the electric field distribution in the terminal region 30 when the width W2 of the second region 312 was changed. Figure 6 In the diagram, the horizontal axis represents the lateral position of the terminal region 30 when the boundary between the cell region 20 and the terminal region 30 is used as a reference. The vertical axis represents the electric field on the surface of the semiconductor substrate 10 in the terminal region 30.

[0082] Figure 6 The simulation results of the electric field distribution are shown for the cases where the width W2 of the second region 312 is 2μm, 4μm, and 6μm. Additionally, Figure 6 Only the peak value of the electric field is depicted.

[0083] according to Figure 6 The simulation results show that as the width W2 of the second region 312 increases, the electric field on the surface of the semiconductor substrate 10 decreases. However, if the width W2 is large, the terminal region 30 becomes larger. Therefore, the combined width W1 of the first region 311 and the width W2 of the second region 312 is expected to be the same as, or smaller than, the width W4 of the guard ring layer 310b of the second comparative example.

[0084] According to the embodiment described above, the area of ​​the terminal region can be suppressed and the pressure resistance reduction can be avoided by using the first region 311 and the second region 312, which have rectangular cross-sectional shapes.

[0085] Furthermore, in this embodiment, the concentration of P-type impurities in the second region 312 is uniform. However, a concentration gradient may also exist within the second region 312. When forming the second region 312, the concentration gradient of the P-type impurity layer can, for example, be formed by a change in the dosage of boron ions. For example, in the second region 312, the P-type impurity concentration may decrease as it moves from the inner end, which is the portion connected to the first region 311, to the outer end, which is the portion furthest from the first region 311. Thus, by having a concentration gradient of the P-type impurity layer in the second region 312, the electric field in the terminal region 30 can be further mitigated.

[0086] (Second Implementation) Figure 7 This is a cross-sectional view showing the general structure of the semiconductor device according to the second embodiment. Figure 7 In this drawing, the same reference numerals are used to mark the same components as those in the semiconductor device 1 of the first embodiment described above, and detailed descriptions are omitted.

[0087] In the semiconductor device 1 of the first embodiment described above, the second region 312 is disposed outside the first region 311, i.e., on the EQPR layer 300 side. On the other hand, as Figure 7As shown, in the semiconductor device 2 of this embodiment, the second region 312 is disposed inside the first region 311, i.e., on the side of the unit region 20.

[0088] The semiconductor device 2 of this embodiment can also be manufactured using the same manufacturing process as the semiconductor device 1 of the first embodiment described in the first embodiment. Regarding the second region 312, a boron ion implantation resist 60 (see [reference]) can be used. Figure 2E The opening pattern is changed to the inside of the first region 311 to form the opening.

[0089] Figure 8 This is a diagram illustrating an example of the results of a voltage withstand simulation, relating to the second comparative example, the first embodiment, and the second embodiment. Figure 8 In the text, typeA, typeB, and typeC correspond to the second comparative example, the first embodiment, and the second embodiment, respectively.

[0090] Figure 8 The figure shows -5×10 11 cm -2 The collector-emitter breakdown voltage is simulated under conditions where external charges accumulate on the surface of the semiconductor substrate 10 in the terminal region 30. If a negative charge exists on the surface of the semiconductor substrate 10, the electric field extends, and therefore, there is a situation where the protective ring layer 310 cannot withstand the lateral potential. In this case, the breakdown voltage decreases.

[0091] In this embodiment, by making the cross-sectional shape of the protective ring layer 310 rectangular, the electric field on the surface of the semiconductor substrate 10 in the terminal region 30 can be mitigated. This improves charge robustness. Furthermore, in this embodiment, the second region 312 is formed to extend from the first region 311 toward the cell region 20. This ensures sufficient space for the electric field to extend on the surface of the semiconductor substrate 10, thus further improving charge robustness.

[0092] (Third Implementation) Figure 9 This is a cross-sectional view showing the general structure of the semiconductor device according to the third embodiment. Figure 9 In this drawing, the same reference numerals are used to mark the same components as those in the semiconductor device 1 of the first embodiment described above, and detailed descriptions are omitted.

[0093] In the semiconductor device 3 of this embodiment, in addition to the constituent elements of the semiconductor device 1 of the first embodiment described above, a first field plate 321 and a second field plate 322 are provided in the interlayer insulating film 40.

[0094] The first field plate 321 is positioned opposite each protective ring layer 310 through the interlayer insulating film 40. The first field plate 321 is made of a metal such as tungsten (W). The first field plate 321 is connected to the first region 311.

[0095] The second field plate 322 is laminated on the first field plate 321 through an interlayer insulating film 40. The second field plate 322 is made of a metal such as aluminum (Al).

[0096] The second field plate 322 is also connected to the first region 311 of each protective ring layer 310. Furthermore, the second field plate 322 is longer than the first field plate 321. Additionally, the second field plate 322 is thicker than the first field plate 321.

[0097] In this embodiment, each protective ring layer 310 is provided with a first field plate 321 and a second field plate 322, but the number of field plates stacked can vary depending on the protective ring layer 310. Alternatively, the first field plate 321 may contact the first region 311 of each protective ring layer 310, and then the second field plate 322 may contact the first field plate 321.

[0098] The first plate 321 and the second plate 322 are formed following the formation process of the protective ring layer 310 and the formation process of the unit region 20. Here, refer to... Figures 10A to 10G The manufacturing methods of the first plate 321 and the second plate 322 are explained.

[0099] First, such as Figure 10A As shown, a first interlayer insulating film 41 is formed on the surface of the semiconductor substrate 10a on which the protective ring layer 310 is formed. The first interlayer insulating film 41 is the lower portion of the interlayer insulating film 40. The thickness of the first interlayer insulating film 41 is, for example, 1.1 μm. Next, a first opening 411 is formed through the first interlayer insulating film 41 in such a way that a portion of each first region 311 is exposed. The first opening 411 is formed at the location where the first field plate 321 is formed.

[0100] Next, as Figure 10B As shown, a first conductive film 70 is formed on the first interlayer insulating film 41. The first conductive film 70 is, for example, a tungsten film formed by CVD. The thickness of the first conductive film 70 is, for example, 300 nm. In this process, the first opening 411 is filled by the first conductive film 70. By narrowing the opening width of the first opening 411 as much as possible, the surface of the first conductive film 70 can be made substantially flat.

[0101] Next, as Figure 10CAs shown, unwanted portions are removed from the first conductive film 70 using a removable eccentric electrode material (RIE). This completes the first field plate 321. Furthermore, the first conductive film 70, which fills the first opening 411, functions as a first contact plug electrically connecting the first field plate 321 to the first region 311.

[0102] Next, as Figure 10D As shown, a second interlayer insulating film 42 is formed on the first interlayer insulating film 41 such that it covers the first field plate 321. The second interlayer insulating film 42 is the middle layer portion of the interlayer insulating film 40. The thickness of the second interlayer insulating film 42 can be greater than the thickness of the first interlayer insulating film 41, for example, 3 μm. Next, a second opening 421 is formed to penetrate both the first interlayer insulating film 41 and the second interlayer insulating film 42, such that a portion of the first region 311 is exposed. The second opening 421 is formed at the location where the second field plate 322 is formed.

[0103] Next, as Figure 10E As shown, a second conductive film 71 is formed on the second interlayer insulating film 42. The second conductive film 71 is, for example, an aluminum film formed by physical vapor deposition (PVD). The thickness of the second conductive film 71 is, for example, 4 μm. In this process, the second opening 421 is filled with the second conductive film 71.

[0104] Next, as Figure 10F As shown, unwanted portions are removed from the second conductive film 71 using a removable eccentric electrode material (RIE). This completes the second field plate 322. Furthermore, the second conductive film 71, which fills the second opening 421, functions as a second contact plug electrically connecting the second field plate 322 to the first region 311.

[0105] Finally, as Figure 10G As shown, a passivation film 43 is formed on the second interlayer insulating film 42 in a manner that covers the second field plate 322. The passivation film 43 is the upper portion of the interlayer insulating film 40. The passivation film 43 is formed, for example, by laminating a resin film such as polyimide with a semi-insulating film or an insulating film. Subsequently, similar to the first embodiment, an N-type buffer layer 12 and a P-type collector layer 11 are sequentially formed on the entire back side of the semiconductor substrate 10a.

[0106] According to the embodiment described above, a first field plate 321 and a second field plate 322 are provided in the terminal region 30. Therefore, the electric field on the surface of the semiconductor substrate 10 in the terminal region 30 can be mitigated.

[0107] (Variation Example 1) The following is for reference Figures 11A to 11HA variation of the first embodiment will now be described. In this variation, the shape of the protective ring layer 310 differs from that of the first embodiment.

[0108] exist Figure 11A In the protective ring layer 310 shown, the second region 312 extends to both sides of the first region 311. In this case, the width of the second region 312 does not need to be the same on both sides of the first region 311. The optimal width can be designed for the inner and outer sides of the first region 311, respectively, based on the electric field distribution on the surface of the semiconductor substrate 10.

[0109] exist Figure 11B In the protective ring layer 310 shown, the bottom of the second region 312, extending to both sides of the first region 311, is positioned shallower than the bottom of the first region 311. Figure 11C In the protective ring layer 310 shown, the bottom of the second region 312, extending outward from the first region 311, is positioned shallower than the bottom of the first region 311. Figure 11D In the protective ring layer 310 shown, the bottom of the second region 312, which extends inward to the inside of the first region 311, is positioned at a shallower location than the bottom of the first region 311.

[0110] Figures 11B to 11D The positional relationship of the bottoms of the regions shown can be achieved by adjusting the accelerating voltage of boron ions. Specifically, the bottom of the first region 311 corresponds to the first P-type impurity layer 311a (refer to...). Figure 2A The accelerating voltage during formation is greater than that of the fifth P-type impurity layer 312a corresponding to the second region 312 (refer to...). Figure 2E The accelerating voltage during formation is large.

[0111] exist Figure 11E In the protective ring layer 310 shown, the bottom of the second region 312, extending to both sides of the first region 311, is positioned deeper than the bottom of the first region 311. Figure 11F In the protective ring layer 310 shown, the bottom of the second region 312, extending outward from the first region 311, is positioned deeper than the bottom of the first region 311. Figure 11G In the protective ring layer 310 shown, the bottom of the second region 312, extending inward to the inside of the first region 311, is positioned deeper than the bottom of the first region 311. Figure 11H In the protective ring layer 310 shown, the second region 312 extends to both sides of the first region 311, and the bottom of the first region 311 contacts the second region 312.

[0112] Figures 11E to 11HThe positional relationship of the bottoms of the regions shown can also be achieved by adjusting the acceleration voltage of boron ions. Specifically, the acceleration voltage during the formation of the first P-type impurity layer 311a is lower than the acceleration voltage during the formation of the fifth P-type impurity layer 312a.

[0113] In the modified example described above, since each protective ring layer 310 has a second region 312, it is also possible to suppress the area of ​​the terminal region and avoid a decrease in withstand voltage.

[0114] Furthermore, multiple protective ring layers 310 are formed in the terminal region 30, but not all of the protective ring layers 310 need to be of the same shape. In the terminal region 30, the above-mentioned Figures 11A to 11H The shapes of the first region 311 and the second region 312 shown can also coexist in combination.

[0115] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope of the invention and its equivalents as defined in the claims.

[0116] Explanation of reference numerals in the attached figures 1-3: Semiconductor devices 10: Semiconductor substrate 13: N-type base layer (first semiconductor layer) 20: Unit Area 21: P-type base layer (second diffusion layer) 22: Gate electrode 23: Gate insulating film 24: N-type emitter layer (third diffusion layer) 30: Terminal Area 310: Protective ring layer (first diffusion layer) 311: Area 1 312: Second Zone 321: First field plate (conductive layer) 322: Second field plate 322 (conductive layer)

Claims

1. A semiconductor device, wherein, have: Semiconductor substrate; A unit region is disposed on the surface side of the semiconductor substrate; and The terminal region is located on the surface side of the semiconductor substrate, outside the unit region. The terminal area has: Multiple first diffusion layers surround the unit region and contain first conductivity type impurities; Multiple second diffusion layers are disposed on the outer side of each of the multiple first diffusion layers, wherein the concentration of the first conductive impurity is lower than that of the first diffusion layer; as well as A conductive layer, located on the surface of the semiconductor substrate, opposite to the first diffusion layer and the second diffusion layer, electrically connected to the first diffusion layer, and having an outer end portion. One of the plurality of second diffusion layers is present on the semiconductor substrate side at the outer end.

2. The semiconductor device according to claim 1, wherein, Multiple conductive layers are stacked with an insulating film between them.

3. The semiconductor device according to claim 2, wherein, The plurality of conductive layers have: The first conductive layer is positioned opposite the first diffusion layer and the second diffusion layer, separated by the insulating film; as well as The second conductive layer, stacked on top of the first conductive layer through the insulating film, is longer than the first conductive layer. One of the plurality of second diffusion layers is located below the outer end of the first conductive layer and the outer end of the second conductive layer.

4. The semiconductor device according to claim 3, wherein, The first conductive layer contains tungsten (W). The second conductive layer contains aluminum (Al).

5. The semiconductor device according to claim 3, wherein, The first diffusion layer, which is closest to the unit region among the plurality of first diffusion layers, is in contact with the second diffusion layer.

6. The semiconductor device according to claim 1, wherein, The unit region has: The third diffusion layer is in contact with the first diffusion layer, which is configured closest to the unit region, and the concentration of the first conductive impurity is lower than that of the first diffusion layer. A gate electrode extends from the surface of the semiconductor substrate through the third diffusion layer; A gate insulating film is provided to electrically insulate the gate electrode from the third diffusion layer. as well as The fourth diffusion layer, located within the third diffusion layer and opposite to the gate electrode across the gate insulating film, contains a second type of conductivity impurity.

7. The semiconductor device according to claim 1, wherein, There is a concentration gradient of the first conductive impurity within the second diffusion layer.

8. The semiconductor device according to claim 7, wherein, In the second diffusion layer, the concentration of the first conductive impurity decreases as it moves from the inner end connected to the first diffusion layer to the outer end furthest from the first diffusion layer.

9. The semiconductor device according to claim 1, wherein, The plurality of second diffusion layers comprise a first layer and a second layer. The first layer is located between the second layer and the unit region. The portion of the second layer with the lowest concentration of the first conductive impurity is separated from the plurality of first diffusion layers.

10. The semiconductor device according to claim 1, wherein, The width of the first diffusion layer is smaller than the width of the second diffusion layer.

11. A method for manufacturing a semiconductor device, The semiconductor device includes: a semiconductor substrate; a unit region formed on the surface side of the semiconductor substrate; and a terminal region formed on the surface side of the semiconductor substrate outside the unit region. in, Within the terminal region, a plurality of first diffusion layers containing first conductivity type impurities are formed in such a manner that they surround the unit region. On the outer side of each of the plurality of first diffusion layers in the terminal region, a plurality of second diffusion layers are formed, wherein the concentration of the first conductive impurity is lower than that of the first diffusion layer. A conductive layer is formed on the surface of the semiconductor substrate, which is opposed to the first diffusion layer and the second diffusion layer, electrically connected to the first diffusion layer, and has an outer end portion. The conductive layer is formed such that one of the plurality of second diffusion layers is present on the semiconductor substrate side at the outer end portion.

12. The method of manufacturing a semiconductor device according to claim 11, wherein, There is a concentration gradient of the first conductive impurity within the second diffusion layer.

13. The method for manufacturing a semiconductor device according to claim 12, wherein, The concentration gradient of the first conductive impurity is formed by varying the dosage of the first conductive impurity during the formation of the second diffusion layer.

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