A semiconductor device, its manufacturing method, and an electronic device

Abstract

This invention discloses a semiconductor device, its manufacturing method, and an electronic device, relating to the field of semiconductor technology. It addresses the problem that etching a buffer layer during bit line etching reduces the area of ​​the contact portion of the subsequently formed memory node, resulting in a sidewall tail structure. The semiconductor device includes: a substrate having a cell region and a peripheral region; a buffer layer covering the cell region; a bit line contact structure located in the cell region, extending through the buffer layer; bit lines formed on the bit line contact structure; and a conductive layer formed between the bit line contact structure and the bit lines. The manufacturing method of the semiconductor device is used to manufacture semiconductor devices. The semiconductor device provided by this invention is used in electronic devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, its manufacturing method, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. DRAM has a simple structure; each bit of data requires only one capacitor and one transistor for processing. Furthermore, DRAM has high density and high capacity per unit volume, resulting in lower cost.

[0003] As semiconductor memory devices become highly integrated, during the manufacturing process of DRAM, the buffer layer is etched when etching the bit line material layer, which reduces the area of ​​the contact portion of the subsequently formed memory node and easily forms a sidewall tail structure, affecting the performance of the semiconductor device during subsequent manufacturing processes. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device, a method for manufacturing the same, and an electronic device, to avoid the problem of etching the bit line material layer to the buffer layer, which reduces the area of ​​the contact portion of the subsequently formed memory node and forms a sidewall tail structure.

[0005] To achieve the above objectives, the present invention provides a semiconductor device. The semiconductor device includes:

[0006] The substrate has a unit region and a peripheral region;

[0007] Buffer layer, the buffer layer covers the unit area;

[0008] The bit line contact structure is located in the cell region and extends through the buffer layer;

[0009] Bit lines formed on the bit line contact structure;

[0010] And a conductive layer formed between the bit line contact structure and the bit line.

[0011] Compared with existing technologies, in the semiconductor device provided by this invention, the bit line contact structure penetrates the buffer layer, and a conductive layer is formed on the surface of the bit line contact structure. Furthermore, the etching selectivity of the conductive layer is greater than that of the buffer layer. When the bit line material layer is formed on the surface of the conductive layer, etching of this material layer avoids directly etching the buffer layer. It also ensures that the width of the etched conductive layer and bit line is controlled within a certain range, preventing the formation of a funnel-shaped pattern below the bit line. This provides sufficient process margin for the subsequent formation of the memory node contact portion and sidewalls, and avoids the formation of sidewall tail structures, thereby improving the performance of the semiconductor device.

[0012] The present invention also provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes:

[0013] A substrate is provided, the substrate having a cell region and a peripheral region;

[0014] A buffer layer, a bit line contact structure, and a conductive layer are sequentially formed on a substrate; the buffer layer covers the cell region; the bit line contact structure penetrates the buffer layer.

[0015] A conductive layer is formed on the bit line contact structure;

[0016] Additionally, bit lines are formed on the conductive layer.

[0017] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided by the present invention are the same as those of the semiconductor device described in the above technical solutions, and will not be repeated here.

[0018] The present invention also provides an electronic device, comprising the semiconductor device described above; and / or,

[0019] Electronic devices are communication devices or terminal devices.

[0020] Compared with the prior art, the beneficial effects of the electronic device provided by the present invention are the same as those of the semiconductor device described in the above technical solution, and will not be repeated here. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0022] Figure 1 A layout diagram of a semiconductor device provided in an embodiment of the present invention is shown;

[0023] Figure 2 A cross-sectional view of a semiconductor device in the prior art is shown;

[0024] Figure 3 A cross-sectional view of a semiconductor device provided in an embodiment of the present invention is shown;

[0025] Figure 4 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention is shown;

[0026] Figures 5 to 14 This illustrates the various stages along which the semiconductor device is manufactured in embodiments of the present invention. Figure 1 A schematic diagram of a cross-section embodiment of line A-A' in the diagram;

[0027] Figure 15 This illustrates the process of forming bit lines during the fabrication of a semiconductor device in an embodiment of the present invention. Figure 1 A schematic diagram of a cross-section embodiment of line A-A' in the diagram;

[0028] Figure 16 This illustrates the process of forming sidewalls during the fabrication of a semiconductor device in an embodiment of the present invention. Figure 1 A schematic diagram of a cross-section of line A-A' in the diagram.

[0029] Figure label:

[0030] Substrate 100, buffer layer 102, bit line contact structure 104, conductive layer 106, bit line 108, cell region 110, peripheral region 112, isolation region 114, contact hole 116, gate stack 118, gate dielectric layer 120, gate electrode 122, upper gate electrode 124, lower gate electrode 126, first buffer layer 128, second buffer layer 130, mask 132, buffer film 134, contact structure 136, second mask 138, cap layer 140, upper gate electrode material layer 142, lower gate electrode material layer 144, memory node contact portion 146, bit line material layer 148, sidewall 150. Detailed Implementation

[0031] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0032] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0033] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0035] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0036] Dynamic Random Access Memory (DRAM) is a type of volatile memory that consists of memory regions composed of cells and a peripheral region surrounding the cells. Each cell contains a transistor electrically connected to a capacitor. The transistor controls the storage and release of charge in the capacitor to store data. Each cell is located and its data access is controlled by word lines (WL) and bit lines (BL) that span the memory region and are electrically connected to each cell.

[0037] Analysis of the aforementioned semiconductor devices reveals that during DRAM manufacturing, the cell region 110, the peripheral region 112, and the partition region 114 located between the cell region 110 and the peripheral region 112 (in the prior art, the partition region 114 is generally included within the cell region 110; for ease of description later, the partition region 114 and the cell region 110 will be described separately below, such as...) Figure 1 (As shown).

[0038] In the prior art, after the bit lines are formed, an etching process can be used to partially etch the bit line contact structures exposed by the bit lines. At this time, each bit line contact structure can have a small width, which can be substantially the same as the width of each bit line. In one embodiment, a bit line structure can be formed from a bit line and an insulating pattern. The bit line can include a first conductive pattern and a second conductive pattern. The first conductive pattern can include titanium nitride. The second conductive pattern can include tungsten. Sidewalls can be sidewalls covering the bit line structure and the bit line contact structures. The sidewalls can be formed by forming an insulating layer to ensure coverage of the top surface of the buffer layer, the sidewalls of the bit line contact structures, the sidewalls of the bit lines, and the sidewalls and top surface of the insulating pattern. An etch-back process on the insulating layer can then be used to expose the top surface of the buffer layer.

[0039] When the material layer below the bit line is a silicon nitride buffer layer or an oxide buffer layer, during plasma etching, due to the low etching selectivity between the bit line 108 and the buffer layer 102, the buffer layer 102 will be etched while the bit line material layer is being etched. This results in the buffer layer 102 below the bit line 108 forming a funnel-shaped pattern, which can cause the subsequently formed memory node contact portion 146 (such as...) to... Figure 2 The reduced area (as shown) and the tendency to form a sidewall tail structure may cause a short circuit when contacting the storage node contact 146, thus reducing the performance of the semiconductor device.

[0040] To avoid the aforementioned problems, embodiments of the present invention provide a semiconductor device, a method for manufacturing the same, and an electronic device. A conductive layer is deposited on the surface of the bit line contact structure. Because the etching selectivity ratio between the bit line and the conductive layer is greater than that between the bit line and the buffer layer, it ensures that the buffer layer is not directly etched when etching the bit line material layer. This provides sufficient process margin for the subsequent formation of the memory node contact portion and the sidewalls, and also avoids the formation of sidewall tail structures, thereby improving the performance of the semiconductor device (e.g., ...). Figure 3 (As shown).

[0041] For ease of description, the following only describes the differences between the semiconductor devices provided in the embodiments of the present invention and those in the prior art. Other structures not described can be referred to the descriptions in the prior art. Of course, those skilled in the art can also improve other existing semiconductor devices based on the following descriptions of the embodiments of the present invention.

[0042] In response to the above problems, Figure 1 This diagram shows a layout of a semiconductor device provided in an embodiment of the present invention. Figures 5 to 16 It shows along Figure 1 The cross-sectional view taken by line A-A' in the diagram. (See diagram below.) Figure 16 As shown, the semiconductor device includes: a substrate 100, a buffer layer 102, a bit line contact structure 104, a conductive layer 106, and a bit line 108.

[0043] like Figure 16 As shown, the substrate 100 has a unit region 110 and a peripheral region 112. The substrate 100 can be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate formed by epitaxial growth. The following description uses a silicon substrate as an example.

[0044] For example, a first transistor and a second transistor are formed on substrate 100. The first transistor is located in cell region 110, and the second transistor is located in peripheral region 112. In practical applications, the number of first transistors can be one or more. When there are multiple first transistors, they can be arranged in an array in cell region 110. When there are multiple second transistors, they are arranged around the first transistor in peripheral region 112.

[0045] The first transistor within the cell region can be any common type of transistor, such as a bottom-gate transistor or a top-gate transistor. It can also be a buried channel array transistor (BCAT), but is not limited to these. The second transistor in the peripheral region can be any type of transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0046] like Figure 16As shown, the buffer layer 102 covers the cell region 110. This exposes the substrate 100 in the peripheral region 112, facilitating subsequent deposition, photolithography, and etching processes in the peripheral region 112. A bit line contact structure 104 penetrates the buffer layer 102 and is located in the cell region 110. The bit line contact structure 104 is electrically connected to the active region of the first transistor. A bit line 108 is formed on the bit line contact structure 104. In practical applications, the buffer layer 102 has contact holes (…). Figure 16 (Not shown in the image), bit line 108 is electrically connected to the active region of the first transistor via bit line contact structure 104 subsequently formed in the contact hole and conductive layer 106 located above bit line contact structure 104. It should be understood that the number of bit line contact structure 104, bit line 108, and conductive layer 106 can be one or more, depending on the actual situation. One bit line 108 is connected to one first transistor.

[0047] like Figure 16 As shown, the conductive layer 106 is formed between the bit line contact structure 104 and the bit line 108. The conductive layer 106 is formed on the surface of the bit line contact structure 104 and is electrically connected to the bit line 108. The etching selectivity ratio between the bit line 108 and the conductive layer 106 is greater than the etching selectivity ratio between the bit line 108 and the buffer layer 102.

[0048] In the prior art, a buffer layer 102 is located below the bit line 108, and the material used for the buffer layer 102 is typically silicon nitride or oxide. Because the etching selectivity of the materials contained in the bit line 108 and the buffer layer 102 is relatively low, during the etching process of the bit line 108, the buffer layer 102 is etched, resulting in a funnel-shaped pattern in the buffer layer 102. This reduces the area of ​​the subsequently formed memory node contact portion 146 and also easily leads to the formation of sidewall tail structures, potentially causing short circuits in subsequent contacts with the memory node contact portion 146 (e.g., ...). Figure 2 (As shown), this reduces the performance of semiconductor devices.

[0049] Furthermore, since chlorine-based gas is used to etch the bit line material layer 148, a certain over-etching process must be employed to ensure complete etching of the bit line material layer 148. The chemical etching reaction between chlorine-based gas and the buffer layer 102 is weak; physical etching plays a dominant role. Therefore, during the over-etching process, the buffer layer 102 will inevitably be etched into a slope shape. Simultaneously, ion sputtering during the etching process will further erode and narrow the formed bit lines 108, which will affect the performance of the subsequently formed semiconductor device.

[0050] In this embodiment of the invention, since the conductive layer 106 lies beneath the bit line 108, and the material of the conductive layer 106 can be doped polysilicon, the doped polysilicon has similar metallic properties to the bit line material layer 148, i.e., it has a strong chemical reaction with the chlorine-based gas used to etch the bit line material layer 148, and physical etching no longer plays a dominant role. During the over-etching stage of the bit line material layer 148, the conductive layer 106 will still form a vertical morphology, and the width of the bit line 108 will not decrease due to the weakening effect of physical sputtering etching. To ensure that the buffer layer 102 is not damaged during the etching of the conductive layer 106 after the bit line material layer 148 has been over-etched, a bromine-based gas can be used to finally complete the etching of the conductive layer 106. Since the physical etching of this gas is weak, it can avoid etching the buffer layer 102 into a slope shape. The conductive layer 106, with its vertical morphology, is used as a hard mask. A fluorine-based gas is then used to etch the buffer layer 102, ensuring that the buffer layer 102 forms a vertical structure consistent with the width of the bit line 108 and the conductive layer 106, thus avoiding a sloping funnel-shaped pattern. During subsequent etching of the sidewalls 150, a more controllable sidewall morphology is obtained, with its space dimensions matching the design. No sidewall tailing structures caused by the funnel-shaped pattern appear, ensuring the stability of semiconductor device characteristics (e.g., ...). Figure 3 (As shown).

[0051] In practical applications, such as Figure 4 As shown, a stacked upper gate electrode material layer 142 and bit line material layer 148 are formed on the surface of the buffer layer 102, and the etching selectivity ratio of bit line 108 to upper gate electrode material layer 142 is defined to be greater than the etching selectivity ratio of bit line 108 to buffer layer 102.

[0052] Based on this, the bit line material layer 148 is etched to form the bit line ( Figure 4 During the process (not shown), the upper gate electrode material layer 142 will be etched into a conductive layer (not shown in the image). Figure 4 (Not shown in the image), due to the buffering effect of the conductive layer during the over-etching process, the buffer layer 102 is prevented from being etched into a slope shape. Therefore, in this embodiment of the invention, by controlling the etching selectivity ratio between the bit line and the conductive layer, the buffer layer 102 can be prevented from being etched into a slope shape during the over-etching process of the bit line material layer 148. Simultaneously, this embodiment of the invention can also control the width of the conductive layer and the bit line 108 within a certain range by controlling the etching process conditions, so that the area of ​​the subsequently formed memory node contact portion remains constant, thereby further improving the performance of the semiconductor device. In this case, the buffer layer formed in the semiconductor device provided by this embodiment of the invention will not form a slope shape as described above. Figure 2 The funnel-shaped pattern shown.

[0053] It should be noted that, as Figure 16As shown, the conductive layer 106 is a doped polysilicon conductive layer. The thickness of the conductive layer 106 is 10 nm to 100 nm. It should be understood that the conductive layer 106 can be made of other materials, its core function being to serve as an etching buffer layer for the bit line material layer during over-etching. A material with similar metallic properties to the bit line 108 can be used as the conductive layer 106, meaning that a vertical structure can be formed during the over-etching process of the bit line material layer. The conductive layer 106 can be other conductive materials, including but not limited to doped polysilicon. The thickness of the conductive layer 106 can be set according to actual conditions. Furthermore, the conductive layer 106 can be a single-layer conductive layer or multiple-layer conductive layers. In the embodiment provided by this invention, the conductive layer 106 is a single-layer doped polysilicon conductive layer. It should be understood that the number of layers in the conductive layer 106 can be set according to actual conditions.

[0054] As one possible implementation, such as Figure 16 As shown, when bit line material layer 148 and upper gate electrode material layer 142 are etched to form bit line 108 and conductive layer 106, the difference between the width of conductive layer 106 and the width of bit line 108 is within a preset difference range. At this time, it can be considered that the width of conductive layer 106 is approximately the same as the width of bit line 108. It should be understood that the preset range is ±4 angstroms. It should be understood that the preset difference value can be set according to actual conditions. Furthermore, the etching rate of the etchant on bit line 108 is much greater than the etching rate of the etchant on conductive layer 106. At this time, when etching conductive layer 106, the etching effect on bit line 108 is small, ensuring that the shape of bit line 108 meets the requirements.

[0055] As one possible implementation, such as Figure 16 As shown, the substrate 100 also has a partition region 114 located between the cell region 110 and the peripheral region 112, and the buffer layer 102 also covers the partition region 114. The gate stack 118 covers the peripheral region 112 and the partition region 114.

[0056] Since the buffer layer 102 also covers the isolation region 114, and the gate stack 118 covers both the peripheral region 112 and the isolation region 114, the size of the area occupied by the gate stack 118 and the buffer layer 102 in the peripheral region 112 can be set according to actual conditions. Without affecting subsequent operations, this facilitates the formation of the bit line 108, avoiding open circuits during the formation of the bit line material layer, which would affect subsequent processing and the performance of the semiconductor device.

[0057] Generally, there is a partition region 114 between the cell region 110 where the buried trench array transistor BCAT is located and the peripheral region 112 where the metal-oxide-semiconductor field-effect transistor is located, and the partition region 114 is covered with an insulating film (Spin-on Dielectrics, abbreviated as SOD).

[0058] As one possible implementation, such as Figure 16 As shown, the buffer layer 102 includes at least one first buffer layer 128 and at least one second buffer layer 130. At least one first buffer layer 128 is formed on the substrate 100. The at least one first buffer layer 128 covers the cell region 110 and the partition region 114, exposing the peripheral region 112. At least one second buffer layer 130 is formed on the at least one first buffer layer 128.

[0059] The number of the first buffer layer 128 and the second buffer layer 130 can be one or more, depending on the actual situation. When there are multiple first buffer layers 128, the first buffer layer 128 is formed on the substrate 100 and covers the cell region 110 and the partition region 114. When there are multiple second buffer layers 130, the second buffer layer 130 is formed on the multiple first buffer layers 128.

[0060] In one alternative approach, such as Figure 16 As shown, at least one of the aforementioned first buffer layers 128 includes a mask 132 and a buffer film 134. The mask 132 is formed on the substrate 100. The buffer film 134 is formed on the mask 132. The mask 132 is an oxide mask. The buffer film 134 is a silicon nitride buffer film. At least one second buffer layer 130 includes an oxide buffer film.

[0061] For example, the mask 132 formed on the substrate 100 is a hard mask. In the embodiments of the present invention, the mask 132 used is an oxide mask. Of course, the material of the mask 132 can also be selected according to the actual situation, such as silicon nitride, silicon carbide, etc., but is not limited to this. The buffer film 134 is a buffer film such as silicon nitride, silicon carbide, etc. Of course, the material of the buffer film 134 can also be selected according to the actual situation, such as a buffer film made of silicon nitride, silicon carbide, etc. The second buffer layer 130 is an oxide buffer film. Of course, the material of the second buffer layer 130 can also be selected according to the actual situation, such as a buffer film made of silicon nitride, silicon carbide, etc.

[0062] As one possible implementation, such as Figure 16As shown, the semiconductor device provided in this embodiment of the invention further includes a gate stack 118 disposed in the peripheral region 112. The gate stack 118 includes a gate dielectric layer 120 and a gate electrode 122. The gate dielectric layer 120 is formed on the substrate 100 and is located in the peripheral region 112. The gate electrode 122 may be formed on the gate dielectric layer 120. The gate electrode 122 is located in the peripheral region 112 and the isolation region 114. This arrangement not only makes full use of space but also facilitates subsequent processing. The gate electrode 122 includes an upper gate electrode 124 and a lower gate electrode 126. The lower gate electrode 126 may be formed on the gate dielectric layer 120, and the upper gate electrode 124 is stacked on the lower gate electrode 126. It should be understood that while the lower gate electrode 126 is formed on the gate dielectric layer 120, the lower gate electrode 126 and the upper gate electrode 124 are located in the peripheral region 112 and the isolation region 114.

[0063] Both the upper gate electrode 124 and the lower gate electrode 126 can be made of conductive materials. These conductive materials can be doped polysilicon. For example, the upper gate electrode 124 can be a doped polysilicon upper gate electrode, and the lower gate electrode 126 can also be a doped polysilicon lower gate electrode. The materials of the upper gate electrode 124 and the lower gate electrode 126 can be the same. In the prior art, the lower gate electrode 126 formed in the peripheral region 112 is made only of doped polysilicon. In this case, the conductivity of the lower gate electrode 126 is better than that formed using both metal and doped polysilicon materials, resulting in more stable performance of the semiconductor device formed later. In this embodiment of the invention, by depositing doped polysilicon materials in the unit region 110 and the peripheral region 112 respectively, the upper gate electrode 124 and the lower gate electrode 126 are formed. This ensures that the lower gate electrode 126 in the peripheral region 112 has the same conductivity as the lower gate electrode 126 in the prior art. Of course, the materials of both the upper gate electrode 124 and the lower gate electrode 126 can also be metals, but this is not limited to these materials. The thickness of the upper gate electrode 124 can be 10nm to 100nm, and the thickness of the lower gate electrode 126 can also be 10nm to 100nm. It should be understood that the thicknesses of the upper gate electrode 124 and the lower gate electrode 126 can be set according to the actual situation.

[0064] At this time, the conductive layer 106 and the upper gate electrode 124 are made of the same material, which saves manufacturing steps in the semiconductor device manufacturing process. The conductive layer 106 and the upper gate electrode 124 can be formed by depositing material once.

[0065] like Figure 16As shown, the thickness of the conductive layer 106 in the unit region 110 is 10 nm to 100 nm, and the thicknesses of the upper gate electrode 124 and lower gate electrode 126 in the peripheral region 112 are also 10 nm to 100 nm. When the conductive layer 106, the upper gate electrode 124, and the lower gate electrode 126 are all made of doped polysilicon, the thickness of the doped polysilicon material in the unit region 110 is less than the thickness of the doped polysilicon material in the peripheral region 112. When the thickness of the doped polysilicon material in the unit region 110 is smaller, the problem of parasitic capacitance generated in the bit line 108 formed in the unit region 110 can be avoided, resulting in better performance of the semiconductor device.

[0066] This invention also provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes:

[0067] like Figure 16 As shown, firstly, a substrate 100 is provided. The substrate 100 has a cell region 110 and a peripheral region 112. The selection of the substrate 100 can be referred to the previous text and will not be repeated here.

[0068] like Figure 16 As shown, a buffer layer 102, a bit line contact structure 104, and a conductive layer 106 are then sequentially formed on the substrate 100. The buffer layer 102 covers the cell region 110. The bit line contact structure 104 penetrates the buffer layer 102.

[0069] like Figure 16 As shown, a conductive layer 106 is then formed on the bit line contact structure 104. Bit lines 108 are then formed on the conductive layer 106.

[0070] In the upper gate electrode material layer ( Figure 16 A bit line material layer is formed on (not shown in the image). Figure 16 (Not shown in the image), the bit line material layer is etched to form a bit line 108, and the upper gate electrode material layer is etched to form a conductive layer 106. The bit line contact structure 104 formed through the contact hole electrically connects the bit line 108 to the active region of the first transistor located in the substrate 100.

[0071] Compared with the prior art, the semiconductor device manufacturing method provided in the embodiments of the present invention has the same beneficial effects as the semiconductor device provided in the above embodiments, and will not be repeated here.

[0072] As one possible implementation, such as Figure 16As shown, the difference between the width of the conductive layer 106 and the width of the bit line 108 is within a preset range. At this point, it can be considered that the width of the conductive layer 106 and the width of the bit line 108 are approximately the same. In the embodiment provided by this invention, the preset range is ±4 angstroms. It should be understood that the preset range can be set according to actual conditions. The conductive layer 106 can be a doped polysilicon conductive layer, and the thickness of the conductive layer 106 can be 10 nm to 100 nm. It should be understood that the conductive layer 106 can be made of other materials, and its core function is to serve as an etching buffer layer for the bit line material layer during over-etching. A material with similar metallic properties to the bit line 108 can be used as the conductive layer 106, that is, a vertical structure can be formed during the over-etching process of the bit line material layer. The conductive layer 106 can be other conductive materials, including but not limited to doped polysilicon. The thickness of the conductive layer 106 can be set according to actual conditions.

[0073] As one possible implementation, such as Figure 16 As shown, the substrate 100 further includes a partition region 114 located between the cell region 110 and the peripheral region 112. Before forming the buffer layer 102 on the substrate 100, the method for manufacturing the semiconductor device further includes:

[0074] like Figure 16 As shown, a partition structure is formed in the partition region 114. The buffer layer 102 also covers the partition region 114. The upper gate electrode 124, the lower gate electrode 126, and the gate dielectric layer 120 cover the peripheral region 112 and the partition region 114.

[0075] As one possible implementation, such as Figure 16 As shown, the formation of a buffer layer 102, a bit line contact structure 104, and a conductive layer 106 sequentially on the substrate 100 includes:

[0076] like Figure 16 As shown, a buffer layer 102 is formed on a substrate 100. For example, a first transistor and a second transistor are formed on the substrate 100. The first transistor is located in cell region 110, and the second transistor is located in peripheral region 112. The first transistor can be a BCAT transistor, etc. The second transistor can be a MOSFET transistor, etc.

[0077] like Figure 5 As shown, a mask 132 can be formed on the substrate 100, wherein the mask 132 can be an oxide mask. A cap layer 140 is formed on the oxide mask, wherein the cap layer 140 can be a silicon nitride cap layer. The aforementioned oxide mask and silicon nitride cap layer are located in the cell region 110, the partition region 114, and the peripheral region 112. It is understood that the materials of the mask 132 and the cap layer 140 can be other suitable materials.

[0078] like Figure 6As shown, the resulting cap layer ( Figure 6 (Not shown in the image) Removal. For example, the cap layer can be removed by sputter etching; it is understood that other practically suitable methods can also be used to remove the cap layer.

[0079] Subsequently, silicon nitride is deposited on the oxide mask (i.e., mask 132) to form a silicon nitride buffer film. An oxide is then deposited on the silicon nitride buffer film to form an oxide buffer film (i.e., the second buffer layer 130). The silicon nitride buffer film or the oxide buffer film can be formed using any of a variety of deposition techniques. For example, the silicon nitride buffer film or the oxide buffer film can be formed using low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and other suitable deposition techniques.

[0080] For example, silicon nitride buffer films and oxide buffer films can be formed using chemical vapor deposition. It is understood that other practically suitable methods can also be used to form silicon nitride buffer films and oxide buffer films.

[0081] like Figure 7 As shown, the buffer layer 102 located in the outer region 112 is graphically represented, exposing the active area of ​​the outer region 112. Figure 7 (Not shown in the image).

[0082] like Figure 7 As shown, the buffer layer 102 located in the peripheral region 112 is etched, selectively removing portions of the mask 132, buffer film 134, and second buffer layer 130. The above patterning process can employ dry etching or wet etching to etch the buffer layer 102 located in the peripheral region 112. For example, when using dry etching, plasma etching can be utilized. That is, plasma etching or wet etching can be used to selectively remove portions of the oxide mask, silicon nitride buffer film, and oxide buffer film to expose the peripheral region 112, facilitating subsequent deposition, photolithography, and etching processes in the peripheral region 112. It is understood that other practically suitable methods can also be used to remove portions of the oxide mask, silicon nitride buffer film, and oxide buffer film.

[0083] like Figure 8 As shown, after exposing the active region of the peripheral region 112, an oxide layer 120 is formed by depositing oxide on the active region. That is, an oxide layer 120 is deposited on the substrate 100. The method of depositing the oxide can be referred to above and will not be repeated here. In the embodiment of the present invention, the oxide layer 120 is formed by depositing the oxide layer using atomic layer deposition.

[0084] It should be noted that the above-mentioned gate dielectric layer can be formed in various ways. How the gate dielectric layer is formed is not a key feature of the embodiments of this invention; therefore, it is only briefly described in this specification to enable those skilled in the art to easily implement the embodiments provided by this invention. Those skilled in the art can certainly conceive of other methods for manufacturing the gate dielectric layer.

[0085] like Figures 8 to 16 As shown, forming a bit line contact structure 104 on the buffer layer 102 and forming a lower gate electrode 126 located in the peripheral region 112 on the substrate 100 includes:

[0086] like Figure 8 As shown, a lower gate electrode material layer 144 is formed on the buffer layer 102 and the gate dielectric layer 120. For example, doped polysilicon is deposited on the buffer layer 102 and the gate dielectric layer 120 as the lower gate electrode material layer 144, and the thickness of the lower gate electrode material layer 144 is 10 nm to 100 nm. The thinner the lower gate electrode material layer 144, the better the performance of the semiconductor device. The lower gate electrode material layer 144 is located in the cell region 110 and the peripheral region 112. Of course, the material contained in the lower gate electrode material layer 144 can also be other suitable conductive materials. The method of depositing doped polysilicon can be referred to the previous text and will not be repeated here.

[0087] like Figure 8 As shown, a second mask 138 is formed on the lower gate electrode material layer 144. The second mask 138 is an oxide mask. The second mask 138 covers the cell region 110 and the peripheral region 112. Of course, the second mask 138 can also cover the partition region 114.

[0088] like Figure 9 As shown, the second mask 138, the lower gate electrode material layer 144 and the buffer layer 102 are etched to form a contact hole 116 that penetrates the oxide mask, the lower gate electrode material layer 144 and the buffer layer 102. The contact hole 116 is located in the cell region 110.

[0089] like Figure 9 and Figure 10As shown, the contact structure 136 can be formed in the contact hole 116. The contact structure 136 can be formed by forming the contact hole 116 on the second mask 138, the lower gate electrode material layer 144 and the buffer layer 102, and filling the contact hole 116 with doped polysilicon, wherein the top surface of the contact structure 136 is lower than the top surface of the oxide mask.

[0090] like Figure 11 and Figure 12 As shown, the lower gate electrode material layer 144 and the buffer layer 102 are processed to obtain the bit line contact structure 104. The lower gate electrode material layer 144 is etched to obtain the lower gate electrode 126 located on the gate dielectric layer 120.

[0091] like Figure 10 and Figure 11 As shown, the oxide mask formed on the lower gate electrode material layer 144 is removed, and a portion of the lower gate electrode material layer 144 is etched to expose the cell region 110, thus obtaining the lower gate electrode 126 located on the gate dielectric layer 120. For example, the lower gate electrode material layer 144 can be etched using either dry etching or wet etching. For instance, when using dry etching, plasma etching can be employed. The oxide mask is removed using sputter etching. It should be understood that other practically suitable methods can also be used to etch the lower gate electrode material layer 144 and the oxide mask. The thickness of the lower gate electrode 126 is 10 nm to 100 nm. It should be understood that the thickness of the lower gate electrode 126 can be set according to actual conditions.

[0092] like Figure 11 and Figure 12 As shown, the partial contact structure 136 is etched to expose the top surface of the oxide buffer film, at which point a bit line contact structure 104 is formed on the buffer layer 102.

[0093] like Figures 13 to 15 As shown, an upper gate electrode material layer 142 is formed on the buffer layer 102 and the lower gate electrode 126. The upper gate electrode material layer 142 is processed to obtain a conductive layer 106 and an upper gate electrode 124 located in the peripheral region 112. The upper gate electrode 124 covers the lower gate electrode 126. Since the conductive layer 106 and the upper gate electrode 124 are made of the same material, a manufacturing step is saved in the semiconductor device manufacturing process; the conductive layer 106 and the upper gate electrode 124 can be formed in a single material deposition.

[0094] Doped polysilicon is deposited on the buffer layer 102 and the lower gate electrode 126 as the upper gate electrode material layer 142, and the thickness of the upper gate electrode material layer 142 is 10 nm to 100 nm. The thinner the lower gate electrode material layer 144, the better the performance of the semiconductor device. The upper gate electrode material layer 142 is located in the cell region 110, the isolation region 114, and the peripheral region 112. It should be understood that the material contained in the upper gate electrode material layer 142 can also be other suitable conductive materials. As for the method of depositing doped polysilicon, please refer to the previous text, which will not be repeated here. After processing the upper gate electrode material layer 142, a conductive layer 106 covering the bit line contact structure 104 and an upper gate electrode 124 covering the lower gate electrode 126 are obtained. The thickness of the upper gate electrode 124 is 10 nm to 100 nm. It should be understood that the thickness of the upper gate electrode 124 can be set according to the actual situation.

[0095] One possible implementation involves forming word lines in the substrate, which are electrically connected to the gate. By creating contact holes in the buffer layer, the bit lines formed on the buffer layer are electrically connected to the active region of the first transistor formed in the substrate through the bit line contact structure and conductive layer formed by the contact holes.

[0096] like Figure 16 As shown, after forming the bit line 108, an etching process can be used to partially etch the bit line contact structures 104 exposed by the bit line 108 and the conductive layer 106. At this time, each bit line contact structure 104 can have a small width, which can be substantially the same as the width of each bit line 108 and the conductive layer 106. In one embodiment, a bit line structure ( Figure 16 (Not shown in the image) can consist of a bit line and an insulating pattern ( Figure 16 (Not shown in the image) is formed. The bit line may include a first conductive pattern and a second conductive pattern. The first conductive pattern may include titanium nitride. The second conductive pattern may include tungsten. Figure 16 As shown, the sidewall 150 can be a sidewall covering the bit line 108, the conductive layer 106, and the bit line contact structure 104. The sidewall 150 can be formed by forming an insulating layer to ensure that the top surface of the buffer layer 102, the sidewall of the bit line contact structure 104, the sidewall of the bit line 108, and the sidewall of the conductive layer 106 are covered. Then, an etch-back process on the insulating layer can be used to expose the top surface of the buffer layer 102.

[0097] This invention also provides an electronic device. The electronic device includes... Figure 4 The semiconductor device shown. The above electronic device can be a communication device or a terminal device.

[0098] As one possible implementation, the electronic device provided in this embodiment of the invention may include, for example, communication devices such as base stations and terminal devices such as mobile phones, tablets, and wearable devices, but is not limited thereto. Further, the electronic device includes smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks. It may also include computers, mobile phones, base stations, servers, etc., but is not limited thereto.

[0099] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0100] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: The substrate has a unit region and a peripheral region; A buffer layer that covers the unit region; A bit line contact structure located in the unit region, the bit line contact structure penetrating the buffer layer; Bit lines formed on the bit line contact structure; And a conductive layer formed between the bit line contact structure and the bit line; The etching selectivity ratio between the bit line and the conductive layer is greater than the etching selectivity ratio between the bit line and the buffer layer; The buffer layer includes at least one first buffer layer and at least one second buffer layer; the at least one first buffer layer is formed on the substrate; the at least one second buffer layer is formed on the at least one first buffer layer; The at least one first buffer layer includes a mask and a buffer film; The mask is formed on the substrate; the buffer film is formed on the surface of the mask.

2. The semiconductor device according to claim 1, characterized in that, The substrate further has a partition region located between the cell region and the peripheral region, and the buffer layer further covers the partition region; and / or, The semiconductor device further includes a gate stack disposed in the peripheral region and the isolation region; the gate stack includes a gate dielectric layer and a gate electrode; the gate dielectric layer is formed on the substrate and is located in the peripheral region; the gate electrode is formed on the gate dielectric layer; the gate electrode is located in the peripheral region and the isolation region; the gate electrode includes an upper gate electrode and a lower gate electrode; the lower gate electrode is formed on the gate dielectric layer, and the upper gate electrode is stacked on the lower gate electrode; The conductive layer and the upper gate electrode are made of the same material; and / or, The conductive layer, the upper gate electrode, and the lower gate electrode are all made of conductive materials; the conductive material is doped polycrystalline silicon. And / or, The thickness of the conductive layer, the upper gate electrode, and the lower gate electrode are all 10 nm to 100 nm.

3. The semiconductor device according to claim 1 or 2, characterized in that, The conductive layer is a single-layer conductive layer; or, The conductive layer is a multilayer conductive layer.

4. The semiconductor device according to claim 2, characterized in that, The mask is an oxide mask; the buffer film is a silicon nitride buffer film; and the at least one second buffer layer includes an oxide buffer film.

5. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate having a cell region and a peripheral region; A buffer layer, a bit line contact structure, and a conductive layer are sequentially formed on the substrate; The buffer layer covers the unit region; the bit line contact structure penetrates the buffer layer; A conductive layer is formed on the bit line contact structure; Additionally, bit lines are formed on the conductive layer; the etching selectivity ratio of the bit lines to the conductive layer is greater than the etching selectivity ratio of the bit lines to the buffer layer. The buffer layer includes at least one first buffer layer and at least one second buffer layer; the at least one first buffer layer is formed on the substrate; the at least one second buffer layer is formed on the at least one first buffer layer; The at least one first buffer layer includes a mask and a buffer film; The mask is formed on the substrate; the buffer film is formed on the surface of the mask.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The substrate further has a partition region located between the unit region and the peripheral region; forming a buffer layer, a bit line contact structure, and a conductive layer on the substrate includes: A partition structure is formed in the partition area: A buffer layer is formed on the substrate; the buffer layer also covers the partition region. A bit line contact structure is formed on the buffer layer, and a lower gate electrode located in the peripheral region is formed on the substrate; An upper gate electrode material layer is formed on the buffer layer and the lower gate electrode; The upper gate electrode material layer is processed to obtain a conductive layer and an upper gate electrode located in the peripheral region, the upper gate electrode covering the lower gate electrode.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, After forming a buffer layer on the substrate, forming a bit line contact structure on the buffer layer, and before forming a lower gate electrode located in the peripheral region on the substrate, the method for manufacturing the semiconductor device further includes: The buffer layer located in the peripheral region is patterned to expose the active area of ​​the peripheral region, and a gate dielectric layer is formed on the active area. The step of forming a bit line contact structure on the buffer layer and forming a lower gate electrode located in the peripheral region on the substrate includes: A lower gate electrode material layer is formed on the buffer layer and the gate dielectric layer; The lower gate electrode material layer and the buffer layer are processed to obtain a bit line contact structure; The lower gate electrode material layer is etched to obtain the lower gate electrode located on the gate dielectric layer; The conductive layer and the upper gate electrode are made of the same material; and / or, The conductive layer, the upper gate electrode material layer, and the lower gate electrode material layer all contain conductive materials; the conductive material is doped polycrystalline silicon; and / or, The thickness of both the upper gate electrode material layer and the lower gate electrode material layer is 10nm~100nm.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The etching method used in the patterning process of the buffer layer located in the peripheral region includes dry etching; or, Wet etching; The dry etching method includes plasma etching.

9. The method for manufacturing a semiconductor device according to claim 7, wherein after forming a lower gate electrode material layer on the buffer layer and the gate dielectric layer, and before processing the lower gate electrode material layer and the buffer layer to obtain a bit line contact structure, the method for manufacturing the semiconductor device further includes: A second mask is formed on the lower gate electrode material layer; The second mask is an oxide mask; The second mask covers the unit area and the peripheral area.

10. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 4; and / or, The electronic device is a communication device or a terminal device.

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