Ultrathin DFN device packaging processing method
By using a combination of peelable copper plate and epoxy resin film in DFN device packaging, the problem of difficult reduction in device thickness is solved, and the heat dissipation and packaging quality of ultra-thin packaging are improved, ensuring the reliability and accuracy of the chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN XINYOU MICROELECTRONICS TECH CO LTD
- Filing Date
- 2025-12-19
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional packaging methods make it difficult to reduce device thickness to within 200µm, resulting in poor heat dissipation and increased space occupancy. Furthermore, the frame limits the thinness of the device, failing to effectively improve packaging quality and reliability.
By employing a combination of peelable copper plates and epoxy resin films, and through processes such as grooving, etching, and laser drilling, direct chip coverage and interconnection are achieved, reducing device thickness while ensuring positioning and identification accuracy, and avoiding damage to the chip from the carrier.
This achieves overall device thickness control within 30µm, improving heat dissipation and packaging quality, reducing defect rate, increasing alignment accuracy and packaging efficiency, and ensuring chip performance is not compromised.
Smart Images
Figure CN121969205A_ABST
Abstract
Description
A method for packaging and fabricating ultra-thin DFN devices Technical Field
[0001] This invention belongs to the field of device packaging technology, and particularly relates to a method for packaging and processing ultra-thin DFN devices. Background Technology
[0002] In traditional packaging processes, a frame is used as a carrier to place the chip before processing. However, the frame itself is limited by the overall process characteristics, and its thinnest thickness can only be 100um. This means that the thickness of the plastic package is at least 100 micrometers thicker than the chip. At the same time, since the top of the chip is an organic insulating layer, a minimum insulation thickness of 70um is required to prevent laser marking from damaging the chip or the WN line itself. Therefore, the thickness of the traditionally packaged product is at least 170um thicker than the chip body, resulting in poor heat dissipation and increased space occupation.
[0003] Furthermore, due to limitations in carrier manufacturing capabilities, even if existing processing methods reduce the overall device thickness by thinning the carrier or chip, they cannot guarantee that the overall device thickness will be reduced to within 200µm.
[0004] Therefore, in view of the above situation, there is an urgent need to develop an ultra-thin DFN device packaging and processing method to overcome the shortcomings in current practical applications. Summary of the Invention
[0005] In view of the shortcomings of the existing technology, the purpose of this invention is to provide an ultra-thin DFN device packaging and processing method to solve the problems mentioned in the background.
[0006] To achieve the above objectives, the present invention provides the following technical solution: a method for packaging and processing ultra-thin DFN devices, comprising: S100. Copper plate coating: applying an epoxy resin film to a peelable copper plate to obtain a double-sided copper-clad laminate, wherein the film is in a semi-cured state; S110. Slotting and etching of the copper plate: designing the array pattern according to the finished device size, and slotting the double-sided copper-clad laminate according to the chip size; the A side of the copper-clad laminate serves as the chip mounting alignment surface, and alignment identification points are made around each slot, with all copper in other positions etched away; the B side of the copper-clad laminate serves as the chip I / O port alignment surface, and a laser drilling alignment target is made, with all copper outside the target removed by etching; S120. Core bonding: bonding the core with the fabricated pattern circuit onto the epoxy resin film by bonding, with no copper surface on it bonded to the epoxy resin film; S130. Chip mounting: mounting the chip onto the copper-clad laminate pre-formed... S140. Chip Coating: Apply an epoxy resin film to the back of the chip in S130, and bake it at high temperature with a laminating machine to fill the gaps at the bottom of the chip and around it with the uncured epoxy resin film; S150. Mounting of the Peelable Copper Plate: Add a peelable copper plate to the upper surface of the epoxy resin film; S160. Peeling the Epoxy Resin Film: Peel off the epoxy resin film layer with the copper side in S120, remove the copper layer by etching, and then drill holes in the chip with a laser drill to expose the chip's I / O ports; S170. Chip Interconnection: Interconnect the chip's I / O ports with the external electrode layer; S180. Fabrication of External Electrodes: Fabricate the external electrodes of the device on the electroplated copper layer using an image etching process; S190. Cutting: Cut the large board obtained in S180 into individual devices of the required size.
[0007] As a further technical solution of the present invention, in S100, the size of the peelable copper plate is 400*400mm.
[0008] As a further technical solution of the present invention, in S100 and S140, the thickness of the epoxy resin film is 10 μm.
[0009] As a further technical solution of the present invention, in S120, the thickness of the double-sided copper clad laminate is 60-100um.
[0010] As a further technical solution of the present invention, in S120, the grooves of the copper-clad laminate are stamped using a die.
[0011] As a further technical solution of the present invention, in S130, the chip mounting process adopts a flip-chip process.
[0012] As a further technical solution of the present invention, in S170, the interconnection process between the chip's I / O port and the external electrode layer adopts a copper plating process.
[0013] Compared with existing technologies, the beneficial effects of this invention are as follows: By reusing the peelable copper plate, the epoxy resin film encapsulating the chip can be separated from the copper plate with the overall thickness controlled within 30µm greater than the chip thickness, improving the overall heat dissipation of the device, reducing the space occupied by the device, and the peelable copper plate plays a core supporting role in the process, preventing the product from breaking due to excessively thin material, improving the packaging quality of the product, and reducing the defect rate of packaged products; at the same time, there is no need to set a carrier on the back of the chip, and directly covering it with a 10µm epoxy resin film can ensure the performance characteristics of the product, and the laser marking on the back of the epoxy resin film will not damage the active area on the front of the chip, improving the reliability of the product; the grooved double-sided copper-clad laminate can not only play a positioning role, but also a recognition role, greatly improving the overall alignment accuracy of the product, thereby improving the packaging efficiency and packaging quality of the product.
[0014] To more clearly illustrate the structural features and effects of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description
[0015] Figure 1 is a schematic diagram of the packaging of the ultra-thin DFN device provided in an embodiment of the present invention.
[0016] Figure 2 is a schematic diagram of the packaging of an ultra-thin DFN device provided in another embodiment of the present invention.
[0017] Figure reference numerals: 1-copper plate, 2-epoxy resin film, 3-core, 4-chip. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0019] The specific implementation of the present invention will be described in detail below with reference to specific embodiments.
[0020] As shown in Figure 1, an ultra-thin DFN device packaging processing method provided as an embodiment of the present invention includes: S100. Coating of copper plate 1: Applying an epoxy resin film 2 to a peelable copper plate 1 to obtain a double-sided copper-clad laminate 1, the film needing to be in a semi-cured state; S110. Grooving and etching of copper plate 1: Designing the array pattern according to the finished device size, and grooving on the double-sided copper-clad laminate 1 according to the chip 4 size; the A side of the copper-clad laminate 1 serves as the mounting alignment surface, and grooves need to be formed around each groove. Alignment points are established, and all copper in other locations is etched away. The B-side of the copper-clad laminate 1 serves as the alignment surface for the I / O ports of chip 4. A laser drilling alignment target is created, and all copper outside the target is removed by etching. S120. Core 3 lamination: The Core 3 with its patterned circuitry is laminated onto the epoxy resin film 2, ensuring that no copper surface adheres to the epoxy resin film 2. S130. Chip 4 mounting: Chip 4 is mounted into the pre-made slots on the copper-clad laminate 1, ensuring proper contact between chip 4 and the slots. S140. Coating of Chip 4: Apply a layer of epoxy resin film 2 to the back of chip 4 in S130, and bake it at high temperature with a laminating machine to allow the uncured epoxy resin film 2 to fully fill the gaps at the bottom and around the chip 4; S150. Installation of Peelable Copper Plate 1: Add a peelable copper plate 1 to the upper surface of epoxy resin film 2 to facilitate the removal of the bottom peelable layer, while ensuring the strength of the overall structure; S160. Epoxy Resin Film 2 peeling: Peel off the epoxy resin film 2 layer with copper surface in S120, remove the copper layer by etching, and then drill holes in chip 4 by laser drilling to expose the I / O port of chip 4; S170. Chip 4 interconnection: Interconnect the I / O port of chip 4 with the external electrode layer; S180. External electrode fabrication: Fabricate the external electrode of the device on the electroplated copper layer by image etching process; S190. Cutting: Cut the large board obtained in S180 into individual devices of the required size.
[0021] In this embodiment, by reusing the peelable copper plate 1, the epoxy resin film 2 is used to separate the chip 4 from the copper plate 1. The overall thickness can be controlled to be within 30µm greater than the thickness of the chip 4, which improves the overall heat dissipation of the device, reduces the space ratio of the device, and the peelable copper plate 1 plays a core supporting role in the process, preventing the product from breaking due to the material being too thin, improving the packaging quality of the product, and reducing the defect rate of the packaged product. At the same time, there is no need to set a carrier on the back of the chip 4. Directly covering it with the 10µm epoxy resin film 2 can ensure the performance characteristics of the product. Moreover, the laser marking on the back of the epoxy resin film 2 will not damage the active area on the front of the chip 4, improving the reliability of the product. The grooved double-sided copper-clad laminate 1 can not only play a positioning role, but also an identification role, which greatly improves the overall alignment accuracy of the product, thereby improving the packaging efficiency and packaging quality of the product.
[0022] As shown in Figure 1, in a preferred embodiment of the present invention, in S100, the size of the peelable copper plate 1 is 400*400mm or larger.
[0023] As shown in Figure 1, in a preferred embodiment of the present invention, the thickness of the epoxy resin film 2 in S100 and S140 is about 10 μm.
[0024] As shown in Figure 1, in a preferred embodiment of the present invention, in S120, the thickness of the double-sided copper clad laminate 1 is about 60-100 μm.
[0025] As shown in Figure 1, in a preferred embodiment of the present invention, in S120, the groove of the copper-clad laminate 1 can be stamped by a mold or made by laser burning process.
[0026] As shown in Figure 1, in a preferred embodiment of the present invention, in S130, the chip 4 is attached using a flip-chip process.
[0027] As shown in Figure 1, in a preferred embodiment of the present invention, in S170, the interconnection process between the I / O port of chip 4 and the external electrode layer adopts a copper plating process.
[0028] As shown in Figure 2, another embodiment of the present invention provides a method for packaging and processing an ultra-thin DFN device, including: S200. Coating of copper plate 1: Applying a layer of epoxy resin film 2 of about 10um to a peelable copper plate 1 to obtain a double-sided copper-clad board 1. The epoxy resin film 2 needs to be in a semi-cured state. The size of the peelable copper plate 1 is greater than 400*400mm; S210. Grooving and etching of copper plate 1: Designing the array pattern according to the finished device size, grooving is performed on a single-sided copper-clad board 1 with a thickness of about 60-100um according to the size of chip 4. The copper surface of the copper-clad board 1 serves as the alignment surface. It is necessary to make a chip alignment identification point around each slot. A laser drilling alignment target and a pattern etching target are made on the edge of the board. All copper in other positions is etched away (the copper-clad board 1 can be formed by grooving with a mold or by laser burning process); S220. Lamination of Core 3: The Core 3 with the patterned circuit is laminated onto the epoxy resin film. On film 2, without copper surface, adhere to epoxy resin film 2; S230. Chip 4 mounting: Chip 4 is attached to the pre-made slot on copper-clad laminate 1 using flip-chip technology, ensuring that the edge of chip 4 faces epoxy resin film 2; S240. Chip 4 lamination: Apply a layer of epoxy resin film 2 of about 10um to the back of chip 4 in S230, and bake it at high temperature with a laminator to allow the uncured epoxy resin film 2 to fully fill the gaps at the bottom and around the chip 4. S250. Exposing the I / O ports: Drilling the chip 4 in S240 using a laser drill exposes the I / O ports of chip 4; S260. Interconnecting chip 4: Interconnecting the I / O ports of chip 4 with the external electrode layer using a copper plating process; S270. Fabrication of external electrodes: Fabricating the external electrodes of the device on the copper plating layer using an image etching process; S280. Peeling and cutting: Separating the adhesive layer in S200 from the copper plate 1, and cutting the separated large plate into individual devices of the required size.
[0029] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for packaging and fabricating an ultra-thin DFN device, characterized in that, include: S100. Copper Plate Coating: Apply an epoxy resin film to a peelable copper plate to obtain a double-sided copper-clad laminate. The film must be in a semi-cured state. S110. Copper Plate Slotting and Etching: Design the array pattern according to the finished device size, and slot the double-sided copper-clad laminate according to the chip size. The A side of the copper-clad laminate serves as the chip alignment surface. Alignment identification points need to be made around each slot, and all copper in other areas is etched away. The B side of the copper-clad laminate serves as the chip I / O port alignment surface. A laser drilling alignment target is made, and all copper outside the target is removed by etching. S120. Core Lamination: The core with the fabricated circuit pattern is laminated onto the epoxy resin film, ensuring that no copper surface adheres to the epoxy resin film. S130. Chip Mounting: The chip is mounted into the pre-made slots on the copper-clad laminate, with the edge of the chip facing the epoxy resin film. S140. Chip Coating: Apply an epoxy resin film to the back of the chip in S130, and bake it at high temperature using a laminating machine to allow the uncured epoxy resin film to fill the gaps at the bottom of the chip and around it; S150. Mounting of the Peelable Copper Plate: Add a peelable copper plate to the upper surface of the epoxy resin film; S160. Peeling the Epoxy Resin Film: Peel the epoxy resin film layer with the copper side in S120, remove the copper layer by etching, and then drill holes in the chip using a laser drill to expose the chip's I / O ports; S170. Chip Interconnection: Interconnect the chip's I / O ports to the external electrode layer; S180. Fabrication of External Electrodes: Fabricate the external electrodes of the device on the electroplated copper layer using an image etching process; S190. Cutting: Cut the large board obtained in S180 into individual devices of the required size.
2. The ultra-thin DFN device packaging and processing method according to claim 1, characterized in that, In S100, the size of the peelable copper plate is 400*400mm.
3. The ultra-thin DFN device packaging and processing method according to claim 1, characterized in that, In S100 and S140, the thickness of the epoxy resin film is 10 μm.
4. The ultra-thin DFN device packaging and processing method according to claim 1, characterized in that, In S120, the thickness of the double-sided copper clad laminate is 60-100um.
5. The ultra-thin DFN device packaging and processing method according to claim 4, characterized in that, In S120, the grooves of the copper clad laminate are stamped using a die.
6. The ultra-thin DFN device packaging and processing method according to claim 1, characterized in that, In the S130, the chip is attached using a flip-chip process.
7. The ultra-thin DFN device packaging and processing method according to claim 1, characterized in that, In the S170, the interconnection process between the chip's I / O ports and the external electrode layer uses a copper plating process.