Driving circuit, driving method, driving module and display device

Abstract

The invention discloses a driving circuit, a driving method, a driving module and a display device. The driving circuit comprises a latch circuit (12), an input circuit (11) and a signal output circuit (13); the input circuit (11) provides an output control signal and an inverted output signal according to an input signal under the control of a control clock signal and a first reset signal; the latch circuit (12) provides an enable signal to the signal output circuit (13) under the control of a second reset signal and a signal provided by the input circuit (11); the signal output circuit (13) generates a first output signal according to a signal provided by the input circuit (11) and a signal provided by the latch circuit (12). The drive circuit can be switched between high-frequency refresh and low-frequency refresh, and can control a signal output by the drive circuit not to be influenced by an enable signal within a frame of time.

Description

Drive circuit, drive method, drive module and display device

[0001] This disclosure relates to the field of display technology, and in particular to a driving circuit, driving method, driving module and display device.

[0002] When the display panel is working, partial refresh is a means to further reduce power consumption and plays an important role in minimizing module driving power consumption. Therefore, a driving circuit that can easily and flexibly perform high-frequency and low-frequency refresh is required.

[0003]

[0004] In one aspect, embodiments of this disclosure provide a driving circuit, including a latching circuit, an input circuit, and a signal output circuit;

[0005] The input circuit is electrically connected to the input signal terminal, the control clock signal terminal, the first reset terminal, the latch circuit, and the signal output circuit, respectively, and is used to provide an output control signal and an inverted output signal according to the input signal provided by the input signal terminal under the control of the control clock signal provided by the control clock signal terminal and the first reset signal provided by the first reset terminal;

[0006] The latching circuit is electrically connected to the second reset terminal, the input circuit, the enable terminal and the signal output circuit respectively, and is used to provide the enable signal provided by the enable terminal to the signal output circuit under the control of the second reset signal provided by the second reset terminal and the signal provided by the input circuit;

[0007] The signal output circuit is electrically connected to the first output terminal and is used to generate and provide a first output signal through the first output terminal based on the signal provided by the input circuit and the signal provided by the latch circuit.

[0008] Optionally, the latching circuit includes a first NOR gate, a second NOR gate, and a first transmission gate;

[0009] The first input terminal of the first NOR gate is electrically connected to the second reset terminal, the second input terminal of the first NOR gate is electrically connected to the second node, and the output terminal of the first NOR gate is electrically connected to the first node.

[0010] The first input terminal of the second NOR gate is electrically connected to the first node, the second input terminal of the second NOR gate is electrically connected to the fifth node, and the output terminal of the second NOR gate is electrically connected to the second node; the input terminal of the first transmission gate is electrically connected to the enable terminal, the output terminal of the first transmission gate is electrically connected to the third node, the positive phase control terminal of the first transmission gate is electrically connected to the first node, and the negative phase control terminal of the first transmission gate is electrically connected to the second node.

[0011] Optionally, the input circuit includes a second transmission gate, a third NOR gate, a third transmission gate, and a first inverter; the control clock signal terminal includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal.

[0012] The input terminal of the second transmission gate is electrically connected to the input signal terminal, the output terminal of the second transmission gate is electrically connected to the fourth node, the positive phase control terminal of the second transmission gate is electrically connected to the fourth clock signal terminal, and the negative phase control terminal of the second transmission gate is electrically connected to the third clock signal terminal.

[0013] The first input terminal of the third NOR gate is electrically connected to the first reset terminal, the second input terminal of the third NOR gate is electrically connected to the fourth node, and the output terminal of the third NOR gate is electrically connected to the fifth node.

[0014] The input terminal of the third transmission gate is electrically connected to the fourth node, the output terminal of the third transmission gate is electrically connected to the sixth node, the positive phase control terminal of the third transmission gate is electrically connected to the second clock signal terminal, and the negative phase control terminal of the third transmission gate is electrically connected to the first clock signal terminal.

[0015] The input terminal of the first inverter is electrically connected to the fifth node, and the output terminal of the first inverter is electrically connected to the sixth node.

[0016] Optionally, the signal output circuit includes a fourth NOR gate;

[0017] The first input terminal of the fourth NOR gate is electrically connected to the sixth node, the second input terminal of the fourth NOR gate is electrically connected to the third node, and the output terminal of the fourth NOR gate is electrically connected to the first output terminal.

[0018] Optionally, the signal output circuit includes a first NAND gate;

[0019] The first input terminal of the first NAND gate is electrically connected to the fifth node, the second input terminal of the first NAND gate is electrically connected to the third node, and the output terminal of the first NAND gate is electrically connected to the first output terminal.

[0020] Optional,

[0021] The fourth NOR gate also includes a third input terminal, which is electrically connected to the control clock signal terminal.

[0022] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a driving enhancement circuit; the driving enhancement circuit includes an N-stage output inverter; N is an integer greater than 1;

[0023] The input terminal of the first output inverter is electrically connected to the first output terminal;

[0024] The output terminal of the nth output inverter is electrically connected to the input terminal of the (n+1)th output inverter, and the output terminal of the Nth output inverter is electrically connected to the drive signal output terminal; n is a positive integer less than N;

[0025] The output inverter is used to invert the signal input to its input terminal, and generate an inverted signal that is provided through the output terminal of the output inverter.

[0026] Optionally, the driving circuit includes multiple driving enhancement circuits;

[0027] At least one of the plurality of drive enhancement circuits is used to provide a drive output signal;

[0028] At least one of the plurality of drive enhancement circuits is used to provide an inverted drive output signal;

[0029] The drive output signal is out of phase with the inverting drive output signal.

[0030] Optionally, the signal output circuit is also electrically connected to the output control clock signal terminal, and is used to generate and provide a first output signal through the first output terminal under the control of the output control clock signal provided by the output control clock signal terminal, the signal provided by the input circuit and the signal provided by the latch circuit.

[0031] Optionally, the first reset terminal and the second reset terminal are the same reset terminal.

[0032] Optionally, the latching circuit is used to transmit the enable signal provided by the enable terminal to the third node within one frame, between the time point when the second reset terminal starts to provide a valid second reset signal and the time point when the first control terminal first starts to provide a valid first control signal. After the time point when the first control terminal first starts to provide a valid first control signal, the control starts latching and stops transmitting the enable signal to the third node.

[0033] In a second aspect, embodiments of this disclosure provide a driving circuit, including a latching circuit, an input circuit, a control circuit, and a signal output circuit;

[0034] The input circuit is electrically connected to the input signal terminal, the control clock signal terminal, and the control circuit, respectively, and is used to provide an inverted output signal according to the input signal provided by the input signal terminal under the control of the control clock signal provided by the control clock signal terminal.

[0035] The control circuit is electrically connected to the first reset terminal and is used to provide an output control signal under the control of the first reset signal provided by the first reset terminal and the inverted output signal.

[0036] The latching circuit is electrically connected to the second reset terminal, the enable terminal, the input circuit, the control circuit, and the signal output circuit, respectively, and is used to transmit the enable signal provided by the enable terminal to the signal output circuit under the control of the second reset signal provided by the second reset terminal, the output control signal, and the inverted output signal.

[0037] The signal output circuit is electrically connected to the control circuit and the first output terminal respectively, and is used to generate and provide a first output signal through the first output terminal according to the output control signal and the signal provided by the latch circuit.

[0038] Optionally, the latch circuit includes a first NAND gate, a second NAND gate, and a first transmission gate;

[0039] The first input terminal of the first NAND gate is electrically connected to the sixth node, the second input terminal of the first NAND gate is electrically connected to the first node, and the output terminal of the first NAND gate is electrically connected to the second node.

[0040] The first input terminal of the second NAND gate is electrically connected to the second node, the second input terminal of the second NAND gate is electrically connected to the second reset terminal, and the output terminal of the second NAND gate is electrically connected to the first node.

[0041] The input terminal of the first transmission gate is electrically connected to the enable terminal, the output terminal of the first transmission gate is electrically connected to the third node, the positive phase control terminal of the first transmission gate is electrically connected to the first node, and the negative phase control terminal of the first transmission gate is electrically connected to the second node.

[0042] Optionally, the latching circuit includes a first NOR gate, a second NOR gate, and a first transmission gate;

[0043] The first input terminal of the first NOR gate is electrically connected to the sixth node, the second input terminal of the first NOR gate is electrically connected to the second node, and the output terminal of the first NOR gate is electrically connected to the first node.

[0044] The first input terminal of the second NOR gate is electrically connected to the first node, the second input terminal of the second NOR gate is electrically connected to the second reset terminal, and the output terminal of the second NOR gate is electrically connected to the second node.

[0045] The input terminal of the first transmission gate is electrically connected to the enable terminal, the output terminal of the first transmission gate is electrically connected to the third node, the positive phase control terminal of the first transmission gate is electrically connected to the first node, and the negative phase control terminal of the first transmission gate is electrically connected to the second node.

[0046] Optionally, the input circuit includes a second transmission gate, a first inverter, a third transmission gate, and a second inverter;

[0047] The control clock signal terminal includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;

[0048] The input terminal of the second transmission gate is electrically connected to the input signal terminal, the output terminal of the second transmission gate is electrically connected to the fourth node, the positive phase control terminal of the second transmission gate is electrically connected to the fourth clock signal terminal, and the negative phase control terminal of the second transmission gate is electrically connected to the third clock signal terminal.

[0049] The input terminal of the third transmission gate is electrically connected to the fourth node, the output terminal of the third transmission gate is electrically connected to the output terminal of the second inverter, the non-inverting control terminal of the third transmission gate is electrically connected to the second clock signal terminal, and the inverting control terminal of the third transmission gate is electrically connected to the first clock signal terminal.

[0050] The input terminal of the first inverter is electrically connected to the fourth node, and the output terminal of the first inverter is electrically connected to the fifth node;

[0051] The input terminal of the second inverter is electrically connected to the fifth node.

[0052] Optionally, the control circuit includes a third NAND gate;

[0053] The first input terminal of the third NAND gate is electrically connected to the first reset terminal, the second input terminal of the third NAND gate is electrically connected to the fifth node, and the output terminal of the third NAND gate is electrically connected to the sixth node.

[0054] Optionally, the signal output circuit includes a first NOR gate;

[0055] The first input terminal of the first NOR gate is electrically connected to the sixth node, the second input terminal of the first NOR gate is electrically connected to the third node, and the output terminal of the first NOR gate is electrically connected to the first output terminal.

[0056] Optionally, the signal output circuit includes a first NOR gate;

[0057] The first input terminal of the first NOR gate is electrically connected to the output control clock signal terminal, the second input terminal of the first NOR gate is electrically connected to the sixth node, the third input terminal of the first NOR gate is electrically connected to the control output node, and the output terminal of the first NOR gate is electrically connected to the first output terminal.

[0058] Optionally, the input circuit includes a second transmission gate, a third transmission gate, a first inverter, and a second inverter; the control clock signal terminal includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal.

[0059] The input terminal of the second transmission gate is electrically connected to the input signal terminal, the output terminal of the second transmission gate is electrically connected to the fourth node, the positive phase control terminal of the second transmission gate is electrically connected to the fourth clock signal terminal, and the negative phase control terminal of the second transmission gate is electrically connected to the third clock signal terminal.

[0060] The input terminal of the third transmission gate is electrically connected to the fourth node, the output terminal of the third transmission gate is electrically connected to the output terminal of the second inverter, the non-inverting control terminal of the third transmission gate is electrically connected to the second clock signal terminal, and the inverting control terminal of the third transmission gate is electrically connected to the first clock signal terminal.

[0061] The input terminal of the first inverter is electrically connected to the fourth node, and the output terminal of the first inverter is electrically connected to the fifth node;

[0062] The input terminal of the second inverter is electrically connected to the fifth node.

[0063] Optionally, the control circuit includes a third NOR gate;

[0064] The first input terminal of the third NOR gate is electrically connected to the first reset terminal, the second input terminal of the third NOR gate is electrically connected to the fifth node, and the output terminal of the third NAND gate is electrically connected to the sixth node.

[0065] Optionally, the signal output circuit includes a first NAND gate;

[0066] The first input terminal of the first NAND gate is electrically connected to the sixth node, the second input terminal of the first NAND gate is electrically connected to the third node, and the output terminal of the first NAND gate is electrically connected to the first output terminal.

[0067] Optionally, the signal output circuit includes a first NAND gate;

[0068] The first input terminal of the first NAND gate is electrically connected to the output control clock signal terminal, the second input terminal of the first NAND gate is electrically connected to the sixth node, the third input terminal of the first NAND gate is electrically connected to the third node, and the output terminal of the first NAND gate is electrically connected to the first output terminal.

[0069] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a driving enhancement circuit; the driving enhancement circuit includes an N-stage output inverter; N is an integer greater than 1;

[0070] The input terminal of the first output inverter is electrically connected to the first output terminal;

[0071] The output terminal of the nth output inverter is electrically connected to the input terminal of the (n+1)th output inverter, and the output terminal of the Nth output inverter is electrically connected to the drive signal output terminal; n is a positive integer less than N;

[0072] The output inverter is used to invert the signal input to its input terminal, and generate an inverted signal that is provided through the output terminal of the output inverter.

[0073] Optionally, the driving circuit includes multiple driving enhancement circuits;

[0074] At least one of the plurality of drive enhancement circuits is used to provide a drive output signal;

[0075] At least one of the plurality of drive enhancement circuits is used to provide an inverted drive output signal;

[0076] The drive output signal is out of phase with the inverting drive output signal.

[0077] Optionally, the signal output circuit is also electrically connected to the output control clock signal terminal, and is used to generate and provide a first output signal through the first output terminal under the control of the output control clock signal provided by the output control clock signal terminal, the output control signal, and the signal provided by the latch circuit.

[0078] Optionally, the first reset terminal and the second reset terminal are the same reset terminal.

[0079] Optionally, the latching circuit is used to transmit the enable signal provided by the enable terminal to the third node within one frame, between the time point when the second reset terminal begins to provide a valid second reset signal and the time point when the first control terminal first begins to provide a valid first control signal. After the time point when the first control terminal first begins to provide a valid first control signal, the control starts latching and stops transmitting the enable signal to the third node.

[0080] In a third aspect, embodiments of this disclosure provide a driving method applied to the aforementioned driving circuit. The driving method includes: within a frame time, between the time point at which the second reset terminal begins to provide a valid second reset signal and the time point at which the first control terminal first begins to provide a valid first control signal, a latching circuit transmits an enable signal provided by an enable terminal to a third node; after the time point at which the first control terminal first begins to provide a valid first control signal, the latching circuit controls the start of latching and stops transmitting the enable signal to the third node.

[0081] In a fourth aspect, embodiments of this disclosure provide a driving module including multiple levels of the driving circuits described above;

[0082] The input signal terminal of the first-stage driving circuit is electrically connected to the starting signal terminal, and the sixth node of the nth-stage driving circuit is electrically connected to the input signal terminal of the (n+1)th driving circuit, where n is a positive integer.

[0083] Optionally, the first reset terminal and the second reset terminal are the same reset terminal; the reset terminals of the multi-stage drive circuit are all electrically connected to the frame reset terminal.

[0084] Optionally, the first reset terminal and the second reset terminal are the same reset terminal; the drive module also includes multiple control transmission gates and multiple terminals for generating control clock signals;

[0085] The reset terminal of the first-stage drive circuit is electrically connected to the frame reset terminal;

[0086] The reset terminal of the m-th stage driving circuit is electrically connected to the output terminal of the (m-1)-th control transmission gate. The input terminal of the (m-1)-th control transmission gate is electrically connected to the second node in the (m-1)-th stage driving circuit. The positive control terminal of the (m-1)-th control transmission gate is electrically connected to the first generation control clock signal terminal. The inverting control terminal of the (m-1)-th control transmission gate is electrically connected to the second generation control clock signal terminal.

[0087] m is an integer greater than 1.

[0088] Optionally, the first reset terminal and the second reset terminal are the same reset terminal;

[0089] The reset terminal of the nth drive circuit is electrically connected to the output terminal of the nth control drive signal.

[0090] Optionally, the drive module further includes multiple control transmission gates and multiple control clock signal generation terminals;

[0091] The first reset terminal of the multi-stage driving circuit is electrically connected to the frame reset terminal; the second reset terminal of the first-stage driving circuit is electrically connected to the frame reset terminal.

[0092] The second reset terminal of the m-th stage driving circuit is electrically connected to the output terminal of the (m-1)-th control transmission gate. The input terminal of the (m-1)-th control transmission gate is electrically connected to the second node in the (m-1)-th stage driving circuit. The positive control terminal of the (m-1)-th control transmission gate is electrically connected to the first generation control clock signal terminal. The inverting control terminal of the (m-1)-th control transmission gate is electrically connected to the second generation control clock signal terminal.

[0093] m is an integer greater than 1.

[0094] Optionally, the first reset terminal of the multi-stage drive circuit is electrically connected to the frame reset terminal; the second reset terminal of the nth drive circuit is electrically connected to the nth control drive signal output terminal.

[0095] Optionally, the first reset terminal of the multi-stage drive circuit is electrically connected to the frame reset terminal;

[0096] The second reset terminals of the a×n-a+1th stage drive circuit to the second reset terminal of the a×nth stage drive circuit are all electrically connected to the nth control drive signal output terminal; a is a positive integer.

[0097] In a fifth aspect, embodiments of this disclosure provide a display device including the driving module described above.

[0098] Optionally, the display device described in at least one embodiment of this disclosure further includes a control drive signal generation module; the control drive signal generation module includes a multi-level control drive signal generation circuit.

[0099] The m-th stage control drive signal generation circuit includes a first generation transmission gate, a second generation transmission gate, a NOR gate, a first generation inverter, a second generation inverter, and a third generation inverter.

[0100] The input terminal of the m-th level first generation transmission gate is electrically connected to the m-th level generation input terminal, the output terminal of the m-th level first generation transmission gate is electrically connected to the first input terminal of the m-th level generation NOR gate, the positive phase control terminal of the m-th level first generation transmission gate is electrically connected to the first drive control clock signal terminal, and the negative phase control terminal of the m-th level first generation transmission gate is electrically connected to the second drive control clock signal terminal.

[0101] The input terminal of the m-th stage second generation transmission gate is electrically connected to the output terminal of the m-th stage first generation transmission gate, the output terminal of the m-th stage second generation transmission gate is electrically connected to the output terminal of the m-th stage first generation inverter, the non-inverting control terminal of the m-th stage second generation transmission gate is electrically connected to the second drive control clock signal terminal, and the inverting control terminal of the m-th stage second generation transmission gate is electrically connected to the first drive control clock signal terminal.

[0102] The second input terminal of the m-th generation NOR gate is electrically connected to the third reset terminal, and the output terminal of the m-th generation NOR gate is electrically connected to the input terminal of the m-th stage second generation inverter.

[0103] The output terminal of the m-th stage second generating inverter is electrically connected to the input terminal of the m-th stage third generating inverter, and the output terminal of the m-th stage third generating inverter is electrically connected to the m-th control drive signal output terminal.

[0104] m is a positive integer.

[0105] Figure 1 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0106] Figure 2 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0107] Figure 3 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0108] Figure 4 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0109] Figure 5 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0110] Figures 6A and 6B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 5 of this disclosure;

[0111] Figure 7 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0112] Figure 8 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0113] Figures 9A and 9B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 7 of this disclosure;

[0114] Figure 10 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0115] Figure 11 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0116] Figures 12A and 12B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 10 of this disclosure;

[0117] Figure 12C is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0118] Figures 12D and 12E are timing diagrams of at least one embodiment of the driving circuit shown in Figure 12C of this disclosure;

[0119] Figure 13 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0120] Figure 14 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0121] Figure 15 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0122] Figure 16 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0123] Figure 17 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0124] Figures 18A and 18B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 16 of this disclosure;

[0125] Figure 19 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0126] Figures 20A and 20B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 19 of this disclosure;

[0127] Figure 21 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0128] Figure 22 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0129] Figures 23A and 23B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 21 of this disclosure;

[0130] Figure 23C is a simulation timing diagram of at least one embodiment of the driving circuit shown in Figure 21;

[0131] Figure 23D is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0132] Figure 24 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0133] Figures 25A and 25B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 24 of this disclosure;

[0134] Figure 26 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0135] Figure 27 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0136] Figures 28A and 28B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 26 of this disclosure;

[0137] Figure 29 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0138] Figures 30A and 30B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 29 of this disclosure;

[0139] Figure 31 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0140] Figure 32 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0141] Figures 33A and 33B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 31 of this disclosure;

[0142] Figure 34 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0143] Figure 35 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0144] Figure 36 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0145] Figure 37 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0146] Figure 38 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0147] Figure 39 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0148] Figure 40 is a circuit diagram of at least one embodiment of the pixel circuit;

[0149] Figure 41 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 40;

[0150] Figure 42 is a circuit diagram of at least one embodiment of the m-th level control drive signal generation circuit.

[0151] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0152] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0153] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0154] As shown in Figure 1, the driving circuit described in this embodiment includes an input circuit 11, a latch circuit 12, and a signal output circuit 13.

[0155] The input circuit 11 is electrically connected to the input signal terminal GI, the control clock signal terminal CKC, the first reset terminal Trst1, the latch circuit 12, and the signal output circuit 13, respectively. It is used to provide an output control signal and an inverted output signal according to the input signal provided by the input signal terminal GI under the control of the control clock signal provided by the control clock signal terminal CKC and the first reset signal provided by the first reset terminal Trst1.

[0156] The latching circuit 12 is electrically connected to the second reset terminal Trst2, the enable terminal EN and the signal output circuit 13 respectively, and is used to provide the enable signal provided by the enable terminal EN to the signal output circuit 13 under the control of the second reset signal provided by the second reset terminal Trst2 and the signal provided by the input circuit 11.

[0157] The signal output circuit 13 is electrically connected to the first output terminal G1 and is used to generate and provide a first output signal through the first output terminal G1 based on the signal provided by the input circuit 11 and the signal provided by the latch circuit 12.

[0158] In at least one embodiment of this disclosure, the latching circuit is used to transmit the enable signal provided by the enable terminal to the third node within one frame, between the time point when the second reset terminal begins to provide a valid second reset signal and the time point when the first control terminal first begins to provide a valid first control signal. After the time point when the first control terminal first begins to provide a valid first control signal, the circuit controls the latching to begin and stops transmitting the enable signal to the third node. The driving circuit described in this disclosure embodiment can switch between high-frequency refresh and low-frequency refresh, and can control the signal output by the driving circuit to be unaffected by the enable signal within one frame.

[0159] In at least one embodiment of this disclosure, the first reset terminal and the second reset terminal may be the same reset terminal to reduce the number of reset terminals used.

[0160] The driving circuit described in at least one embodiment of this disclosure further includes a driving enhancement circuit; the driving enhancement circuit includes an N-stage output inverter; N is an integer greater than 1;

[0161] The input terminal of the first output inverter is electrically connected to the first output terminal;

[0162] The output terminal of the nth output inverter is electrically connected to the input terminal of the (n+1)th output inverter, and the output terminal of the Nth output inverter is electrically connected to the drive signal output terminal; n is a positive integer less than N;

[0163] The output inverter is used to invert the signal input to its input terminal, and generate an inverted signal that is provided through the output terminal of the output inverter.

[0164] In a specific implementation, the driving circuit may further include a driving enhancement circuit, which includes a multi-stage output inverter to provide an enhanced driving output signal or an inverted output signal.

[0165] As shown in Figure 2, based on at least one embodiment of the driving circuit shown in Figure 1, the driving circuit described in at least one embodiment of this disclosure further includes a driving enhancement circuit 20;

[0166] The input terminal of the drive enhancement circuit 20 is electrically connected to the first output terminal G1, and the output terminal of the drive enhancement circuit 20 is electrically connected to the second output terminal G2.

[0167] In at least one embodiment of this disclosure, the driving circuit includes a plurality of driving enhancement circuits;

[0168] At least one of the plurality of drive enhancement circuits is used to provide a drive output signal;

[0169] At least one of the plurality of drive enhancement circuits is used to provide an inverted drive output signal;

[0170] The drive output signal is out of phase with the inverting drive output signal.

[0171] In a specific implementation, the driving circuit may include multiple driving enhancement circuits, which can simultaneously provide a driving output signal and an inverted driving output signal, wherein the driving output signal is inverted from the inverted driving output signal.

[0172] Optionally, the signal output circuit is also electrically connected to the output control clock signal terminal, and is used to generate and provide a first output signal through the first output terminal under the control of the output control clock signal provided by the output control clock signal terminal, the signal provided by the input circuit and the signal provided by the latch circuit.

[0173] In a specific implementation, the signal output circuit can also be electrically connected to the output control clock signal terminal. Under the control of the output control clock signal, the signal provided by the input circuit, and the signal provided by the latch circuit, the signal output circuit provides a first output signal.

[0174] As shown in Figure 3, based on at least one embodiment of the driving circuit shown in Figure 2, the signal output circuit 13 is also electrically connected to the output control clock signal terminal CKO, and is used to generate and provide a first output signal through the first output terminal G1 under the control of the output control clock signal provided by the output control clock signal terminal CKO, the signal provided by the input circuit 11 and the signal provided by the latch circuit 12.

[0175] In at least one embodiment of this disclosure, the latch circuit includes a first NOR gate, a second NOR gate, and a first transmission gate;

[0176] The first input terminal of the first NOR gate is electrically connected to the second reset terminal, the second input terminal of the first NOR gate is electrically connected to the second node, and the output terminal of the first NOR gate is electrically connected to the first node.

[0177] The first input terminal of the second NOR gate is electrically connected to the first node, the second input terminal of the second NOR gate is electrically connected to the fifth node, and the output terminal of the second NOR gate is electrically connected to the second node.

[0178] The input terminal of the first transmission gate is electrically connected to the enable terminal, the output terminal of the first transmission gate is electrically connected to the third node, the positive phase control terminal of the first transmission gate is electrically connected to the first node, and the negative phase control terminal of the first transmission gate is electrically connected to the second node.

[0179] In a specific implementation, the latching circuit may further include a first NOR gate, a second NOR gate, and a first transmission gate. The first NOR gate performs a NOR operation on the second reset signal provided by the second reset terminal and the signal provided by the second node to obtain the signal provided by the first node. The second NOR gate performs a NOR operation on the signal provided by the first node and the signal provided by the fifth node to obtain the signal provided by the second node. Under the control of the potential provided by the first node and the potential provided by the second node, the first transmission gate transmits the enable signal provided by the enable terminal to the third node.

[0180] In at least one embodiment of this disclosure, the input circuit includes a second transmission gate, a third NOR gate, a third transmission gate, and a first inverter; the control clock signal terminal includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal.

[0181] The input terminal of the second transmission gate is electrically connected to the input signal terminal, the output terminal of the second transmission gate is electrically connected to the fourth node, the positive phase control terminal of the second transmission gate is electrically connected to the fourth clock signal terminal, and the negative phase control terminal of the second transmission gate is electrically connected to the third clock signal terminal.

[0182] The first input terminal of the third NOR gate is electrically connected to the first reset terminal, the second input terminal of the third NOR gate is electrically connected to the fourth node, and the output terminal of the third NOR gate is electrically connected to the fifth node.

[0183] The input terminal of the third transmission gate is electrically connected to the fourth node, the output terminal of the third transmission gate is electrically connected to the sixth node, the positive phase control terminal of the third transmission gate is electrically connected to the second clock signal terminal, and the negative phase control terminal of the third transmission gate is electrically connected to the first clock signal terminal.

[0184] The input terminal of the first inverter is electrically connected to the fifth node, and the output terminal of the first inverter is electrically connected to the sixth node.

[0185] In a specific implementation, the input circuit may further include a first transmission gate, a third NOR gate, a third transmission gate, and a first inverter; the second transmission gate, under the control of the fourth clock signal and the third clock signal, transmits the signal provided by the input signal terminal to the fourth node; the third NOR gate performs a NOR operation on the first reset signal provided by the first reset terminal and the signal provided by the fourth node to obtain the signal provided by the fifth node; the third transmission gate, under the control of the second clock signal and the first clock signal, transmits the signal provided by the fourth node to the sixth node; the first inverter inverts the signal provided by the fifth node to obtain the signal provided by the sixth node.

[0186] Optionally, the signal output circuit includes a fourth NOR gate;

[0187] The first input terminal of the fourth NOR gate is electrically connected to the sixth node, the second input terminal of the fourth NOR gate is electrically connected to the third node, and the output terminal of the fourth NOR gate is electrically connected to the first output terminal.

[0188] In a specific implementation, the signal output circuit may further include a fourth NOR gate, which performs a NOR operation on the signal provided by the sixth node and the signal provided by the third node to obtain the first output signal.

[0189] Optionally, the signal output circuit includes a first NAND gate;

[0190] The first input terminal of the first NAND gate is electrically connected to the fifth node, the second input terminal of the first NAND gate is electrically connected to the third node, and the output terminal of the first NAND gate is electrically connected to the first output terminal.

[0191] In a specific implementation, the signal output circuit may include a first NAND gate, which performs a NAND operation on the signal provided by the fifth node and the signal provided by the third node to obtain a first output signal.

[0192] Optionally, the fourth NOR gate further includes a third input terminal, which is electrically connected to the control clock signal terminal.

[0193] In a specific implementation, the signal output circuit may include a fourth NOR gate, which performs a NOR operation on the output control clock signal, the signal provided by the sixth node, and the signal provided by the third node to obtain a first output signal.

[0194] As shown in Figure 4, based on at least one embodiment of the driving circuit shown in Figure 2, the latching circuit includes a first NOR gate NOR1, a second NOR gate NOR2, and a first transmission gate Tg1.

[0195] The first input terminal of the first NOR gate NOR1 is electrically connected to the reset terminal Trst, the second input terminal of the first NOR gate NOR1 is electrically connected to the second node QB, and the output terminal of the first NOR gate NOR1 is electrically connected to the first node Q.

[0196] The first input terminal of the second NOR gate NOR2 is electrically connected to the first node Q, the second input terminal of the second NOR gate NOR2 is electrically connected to the fifth node NF, and the output terminal of the second NOR gate NOR2 is electrically connected to the second node QB.

[0197] The input terminal of the first transmission gate Tg1 is electrically connected to the enable terminal EN, the output terminal of the first transmission gate Tg1 is electrically connected to the third node NC, the positive phase control terminal of the first transmission gate Tg1 is electrically connected to the second node QB, and the negative phase control terminal of the first transmission gate Tg1 is electrically connected to the first node Q.

[0198] The input circuit includes a second transmission gate Tg2, a third NOR gate NOR3, a third transmission gate Tg3, and a first inverter INV1; the control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn.

[0199] The input terminal of the second transmission gate Tg2 is electrically connected to the input signal terminal GI, the output terminal of the second transmission gate Tg2 is electrically connected to the fourth node Q_m, the positive phase control terminal of the second transmission gate Tg2 is electrically connected to the fourth clock signal terminal CKn, and the inverting phase control terminal of the second transmission gate Tg2 is electrically connected to the third clock signal terminal CB.

[0200] The first input terminal of the third NOR gate NOR3 is electrically connected to the reset terminal Trst, the second input terminal of the third NOR gate NOR3 is electrically connected to the fourth node Q_m, and the output terminal of the third NOR gate Q_m is electrically connected to the fifth node NF.

[0201] The input terminal of the third transmission gate Tg3 is electrically connected to the fourth node Q_m, the output terminal of the third transmission gate Tg3 is electrically connected to the sixth node NS, the positive phase control terminal of the third transmission gate Tg3 is electrically connected to the second clock signal terminal CBn, and the negative phase control terminal of the third transmission gate Tg3 is electrically connected to the first clock signal terminal CK.

[0202] The input terminal of the first inverter INV1 is electrically connected to the fifth node NF, and the output terminal of the first inverter INV1 is electrically connected to the sixth node NS.

[0203] The signal output circuit includes a fourth NOR gate (NOR4).

[0204] The first input terminal of the fourth NOR gate NOR4 is electrically connected to the sixth node NS, the second input terminal of the fourth NOR gate NOR4 is electrically connected to the third node NC, and the output terminal of the fourth NOR gate NOR4 is electrically connected to the first output terminal G1.

[0205] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, and a third output inverter IV3;

[0206] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, and the output terminal of IV3 is electrically connected to the second output terminal G2.

[0207] At least one embodiment of the driving circuit shown in Figure 4 can be used to control T5-T9 in the pixel circuit shown in Figure 40.

[0208] In at least one embodiment of the driving circuit shown in Figure 4, the first reset terminal and the second reset terminal are the same reset terminal Trst.

[0209] At least one embodiment of the driving circuit shown in Figure 4 of this disclosure, when in operation,

[0210] Between the rising edge of the reset signal provided by Trst and the rising edge of the signal provided by NF, the enable signal provided by EN can be output to NC through Tg1. After that, Tg1 is locked, and the enable signal provided by EN cannot be transmitted to NC.

[0211] Figure 5 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.

[0212] Figures 6A and 6B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 4.

[0213] In at least one embodiment of this disclosure, during operation, a reset latch is performed using the reset signal provided by Trst, enabling the first transmission gate Tg1 in all driving circuits to open. The enable signal provided by EN can enter NOR4 in real time. When the first pulse of the signal provided by NS of the driving circuit in this frame is output (or before the output), the enable signal entering NOR4 is latched, thereby locking the output enable state of the driving circuit in this frame. This can achieve the following: in the high-frequency refresh area, G2 outputs a multi-pulse driving signal (the number of pulses or the pulse width changes with the starting signal); or in the low-frequency refresh area, there is no pulse output. After the first output, the signal output by G2 no longer changes with the state of the enable signal in this frame.

[0214] In at least one embodiment of the driving circuit shown in Figure 4, EN provides a low voltage signal in the high-frequency refresh region;

[0215] In at least one embodiment of the drive circuit shown in Figure 4, EN provides a high voltage signal during the low-frequency refresh region.

[0216] As shown in Figure 6A, the m-th row drive circuit (the structure of the m-th row drive circuit is shown in Figure 4) is in operation.

[0217] During the reset period S0, Trst provides a high voltage signal, NOR1 outputs a low voltage signal to Q, Q's potential is low, NF's potential is low, NOR2 outputs a high voltage signal to QB, making QB's potential high, Tg1 is turned on, and the enable signal provided by EN can be transmitted to NC through Tg1.

[0218] Between the reset time period S0 and the first output time period S11, when EN provides a voltage signal, Q has a low potential and QB has a high potential, the voltage signal provided by EN is transmitted to NC through Tg1.

[0219] When the potential of the signal provided by NF jumps from low voltage to high voltage, NOR2 outputs a low voltage signal to QB. At this time, Trst provides a low voltage signal and NOR1 provides a high voltage signal to Q, so that the potential of Q becomes high voltage and the potential of QB becomes low voltage. Tg1 is cut off, and NC maintains the potential when it is cut off until Tg1 is turned on again.

[0220] During the first output time period S11, G2 in the m-th row drive circuit outputs a low voltage signal;

[0221] During the second output time period S12, even if EN outputs a high voltage signal, since Tg1 is cut off, the signal output by G2 is not affected by the signal provided by EN, and G2 in the m-th row drive circuit outputs a low voltage signal.

[0222] As shown in Figure 6B, the m-th row drive circuit (the structure of the m-th row drive circuit is shown in Figure 4) is in operation.

[0223] During the reset period S0, Trst provides a high voltage signal, NOR1 outputs a low voltage signal to Q, Q's potential is low, NF's potential is low, NOR2 outputs a high voltage signal to QB, making QB's potential high, Tg1 is turned on, and the enable signal provided by EN can be transmitted to NC through Tg1.

[0224] Between the reset time period S0 and the first output time period S11, when EN provides a high voltage signal, Q has a low voltage potential, and QB has a high voltage potential, the high voltage signal provided by EN is transmitted to NC through Tg1.

[0225] When the potential of the signal provided by NF jumps from low voltage to high voltage, NOR2 outputs a low voltage signal to QB. At this time, Trst provides a low voltage signal, NOR1 provides a high voltage signal to Q, the potential of Q becomes high voltage, the potential of QB becomes low voltage, and Tg1 is cut off.

[0226] During the driving time period S2 of the m-th row, G2 in the driving circuit of the m-th row outputs a high voltage signal;

[0227] During the driving time period S2 of the m-th row, even if EN outputs a low voltage signal, since Tg1 is in the off state, the signal output by G2 is not affected by the signal provided by EN, and G2 in the driving circuit of the m-th row outputs a high voltage signal.

[0228] As shown in Figure 6A, the period of the first clock signal provided by CK can be 2H (1H is the scan time of one line), the period of the second clock signal provided by CBn can be 2H, the period of the third clock signal provided by CB can be 2H, the period of the fourth clock signal provided by CKn can be 2H, the first clock signal is out of phase with the second clock signal, and the third clock signal is out of phase with the fourth clock signal.

[0229] The period of each clock signal can be adjusted according to the number of driven pixel rows, and the period of each clock signal can also be 4H, 8H, etc.; among them, the first clock signal can differ from the third clock signal by 1H (which can be adjusted according to the number of driving circuit groups or the number of driven pixel rows); the low-level width of the first clock signal and the low-level width of the third clock signal are generally less than 1H by Δt, and Δt is generally set to 0-2μs, selected according to the RC (resistor-capacitor) load at each clock signal terminal, mainly to eliminate the influence of clock delay and avoid the simultaneous activation of Tg2 and Tg3, which may cause the risk of NOR3 and INV1 competition during input state switching. The reset signal provided by Trst resets the driving circuit when power is turned on / off, or when the blanking time of each frame becomes high.

[0230] EN is the local refresh enable signal. When EN provides a low voltage signal, or when the potential of the signal provided by NF changes from low voltage to high voltage for the first time within a frame, the drive circuit outputs a normal drive signal. When EN provides a high voltage signal, or when the potential of the signal provided by NF changes from low voltage to high voltage for the first time within a frame, the drive circuit outputs a high voltage signal.

[0231] In the driving circuit of at least one embodiment of this disclosure, dual high-voltage terminals and dual low-voltage terminals are used for power supply. Under normal circumstances, the voltage value of the second low-voltage signal provided by VGL2 is not higher than the voltage value of the first low-voltage signal provided by VGL1, and the voltage value of the second high-voltage signal provided by VGH2 is not lower than the voltage value of the first high-voltage signal provided by VGH1. The driving circuit described in at least one embodiment of this disclosure uses dual-voltage driving, which can accelerate the charging and discharging speed of IV3, thereby improving the driving capability of the driving circuit. Under normal circumstances, the channel width of the transistor included in IV3 is relatively large, and the threshold voltage of the transistor included in IV3 is also closer to 0V. For the oxide transistor (n-type transistor) included in IV3, if the threshold voltage is less than 0V, when a single power supply is used, the gate-source voltage Vgs of the transistor is at least 0V, and the transistor cannot be turned off. Therefore, when G2 outputs a high-voltage signal, there is a long-term leakage current, which increases the power consumption of the driving circuit. If the threshold voltage Vth is severely negatively biased, it may cause the potential of the second output signal provided by G2 to be unable to be pulled high, thereby making the driving circuit unable to work normally. The driving circuit described in at least one embodiment of this disclosure employs dual low voltage. By lowering the voltage value of the second low voltage signal provided by VGL2, the voltage difference between the second low voltage signal provided by VGL2 and the first low voltage signal provided by VGL1 is made greater than the absolute value of Vth. This ensures that the oxide transistor in IV3 can switch normally, enabling the driving circuit to operate normally, reducing DC leakage current, and saving power consumption. Dual high voltage can also solve the problem of the threshold voltage of the p-type transistor in IV3 drifting to zero, thus avoiding consistency with dual low voltage.

[0232] As shown in Figure 5, based on at least one embodiment of the driving circuit shown in Figure 4, the first transmission gate includes a first transmission transistor Mc1 and a second transmission transistor Mc2, the second transmission gate includes a third transmission transistor Mc3 and a fourth transmission transistor Mc4, and the third transmission gate includes a fifth transmission transistor Mc5 and a sixth transmission transistor Mc6.

[0233] The gate of Mc1 is electrically connected to Q, the source of Mc1 is electrically connected to EN, and the drain of Mc1 is electrically connected to NC.

[0234] Mc2’s gate is electrically connected to QB, Mc2’s source is electrically connected to EN, and Mc2’s drain is electrically connected to NC.

[0235] Mc1 is an n-type transistor, and Mc2 is a p-type transistor;

[0236] The gate of Mc3 is electrically connected to CKn, the source of Mc3 is electrically connected to GI, and the drain of Mc3 is electrically connected to Q_m.

[0237] The gate of Mc4 is electrically connected to CB, the source of Mc4 is electrically connected to GI, and the drain of Mc4 is electrically connected to Q_m.

[0238] Mc3 is an n-type transistor, and Mc4 is a p-type transistor;

[0239] The gate of Mc5 is electrically connected to CBn, the source of Mc5 is electrically connected to Q_m, and the drain of Mc5 is electrically connected to NS.

[0240] The gate of Mc6 is electrically connected to CK, the source of Mc6 is electrically connected to Q_m, and the drain of Mc6 is electrically connected to NS.

[0241] Mc5 is an n-type transistor, and Mc6 is a p-type transistor;

[0242] The first NOR gate includes a first NOR control transistor Mn1, a second NOR control transistor Mn2, a third NOR control transistor Mn3, and a fourth NOR control transistor Mn4;

[0243] The gate of Mn1 is electrically connected to Trst, the source of Mn1 is electrically connected to the first high voltage terminal VGH1, and the drain of Mn1 is electrically connected to the source of Mn2.

[0244] The gate of Mn2 is electrically connected to Q, the drain of Mn2 is electrically connected to the source of Mn3, and the drain of Mn2 is electrically connected to QB.

[0245] The gate of Mn3 is electrically connected to Trst, the source of Mn3 is electrically connected to the source of Mn4, and the drain of Mn3 is electrically connected to the first low voltage terminal VGL1.

[0246] The gate of Mn4 is electrically connected to Q, and the drain of Mn4 is electrically connected to VGL1.

[0247] Mn1 and Mn2 are p-type transistors, while Mn3 and Mn4 are n-type transistors;

[0248] The second NOR gate includes the fifth NOR control transistor Mn5, the sixth NOR control transistor Mn6, the seventh NOR control transistor Mn7, and the eighth NOR control transistor Mn8.

[0249] The gate of Mn5 is electrically connected to NF, the source of Mn5 is electrically connected to VGH1, and the drain of Mn5 is electrically connected to the source of Mn6.

[0250] The gate of Mn6 is electrically connected to QB, the drain of Mn6 is electrically connected to the source of Mn7, and the drain of Mn6 is electrically connected to Q.

[0251] The gate of Mn7 is electrically connected to NF, and the drain of Mn7 is electrically connected to VGL1.

[0252] The gate of Mn8 is electrically connected to QB, the source of Mn8 is electrically connected to the source of Mn7, and the drain of Mn8 is electrically connected to VGL1.

[0253] Mn5 and Mn6 are p-type transistors, while Mn7 and Mn8 are n-type transistors;

[0254] The third NOR gate includes the ninth NOR control transistor Mn9, the tenth NOR control transistor Mn10, the eleventh NOR control transistor Mn11, and the twelfth NOR control transistor Mn12.

[0255] The gate of Mn9 is electrically connected to Trst, the source of Mn9 is electrically connected to VGH1, and the drain of Mn9 is electrically connected to the source of Mn10.

[0256] The gate of Mn10 is electrically connected to Q_m, and the drain of Mn10 is connected to NF;

[0257] The gate of Mn11 is electrically connected to Q_m, the source of Mn11 is electrically connected to NF, and the drain of Mn11 is electrically connected to VGL1.

[0258] The gate of Mn12 is electrically connected to Trst, the source of Mn12 is electrically connected to NF, and Mn12 is electrically connected to VGL1.

[0259] Mn9 and Mn10 are p-type transistors, while Mn11 and Mn12 are n-type transistors;

[0260] The fourth NOR gate includes the thirteenth NOR control transistor Mn13, the fourteenth NOR control transistor Mn14, the fifteenth NOR control transistor Mn15, and the sixteenth NOR control transistor Mn16;

[0261] The gate of Mn13 is electrically connected to NC, the source of Mn13 is electrically connected to VGH1, and the drain of Mn13 is electrically connected to the source of Mn14.

[0262] The gate of Mn14 is electrically connected to NS, and the drain of Mn14 is electrically connected to G1.

[0263] The gate of Mn15 is electrically connected to NS, the source of Mn15 is electrically connected to G1, and the drain of Mn15 is electrically connected to VGL1.

[0264] The gate of Mn16 is electrically connected to NC, the source of Mn16 is electrically connected to G1, and the drain of Mn16 is electrically connected to VGL1.

[0265] Mn13 and Mn14 are p-type transistors, while Mn15 and Mn16 are n-type transistors;

[0266] The first inverter includes a first inverting transistor Mf1 and a second inverting transistor Mf2;

[0267] The gate of Mf1 is electrically connected to NF, the source of Mf1 is electrically connected to VGH1, and the drain of Mf1 is electrically connected to NS.

[0268] The gate of Mf2 is electrically connected to NF, the source of Mf2 is electrically connected to NS, and the drain of Mf2 is electrically connected to VGL1.

[0269] Mf1 is a p-type transistor, and Mf2 is an n-type transistor;

[0270] The first output inverter includes a first output inverter transistor Ms1 and a second output inverter transistor Ms2;

[0271] The gate of Ms1 is electrically connected to G1, the source of Ms1 is electrically connected to VGH1, and the drain of Ms1 is electrically connected to the source of Ms2.

[0272] The gate of Ms2 is electrically connected to G1, and the drain of Ms2 is electrically connected to VGL1.

[0273] Ms1 is a p-type transistor, and Ms2 is an n-type transistor;

[0274] The second output inverter includes a third output inverter transistor Ms3 and a fourth output inverter transistor Ms4;

[0275] The gate of Ms3 is electrically connected to the drain of Ms1, the source of Ms3 is electrically connected to VGH1, and the drain of Ms3 is electrically connected to the source of Ms4.

[0276] The gate of Ms4 is electrically connected to the drain of Ms1, and the drain of Ms4 is electrically connected to VGL1.

[0277] Ms3 is a p-type transistor, and Ms4 is an n-type transistor;

[0278] The third output inverter includes the fifth output inverter transistor Ms5 and the sixth output inverter transistor Ms6;

[0279] The gate of Ms5 is electrically connected to the drain of Ms3, the source of Ms5 is electrically connected to the second high voltage terminal VGH2, and the drain of Ms5 is electrically connected to the source of Ms6.

[0280] The gate of Ms6 is electrically connected to the drain of Ms3, and the drain of Ms6 is electrically connected to the second low voltage terminal VGL2.

[0281] Ms5 is a p-type transistor, and Ms6 is an n-type transistor.

[0282] In Figure 5, the capacitor labeled C1 is the first capacitor.

[0283] As shown in Figure 7, based on at least one embodiment of the driving circuit shown in Figure 2, the latching circuit includes a first NOR gate NOR1, a second NOR gate NOR2, and a first transmission gate Tg1.

[0284] The first input terminal of the first NOR gate NOR1 is electrically connected to the reset terminal Trst, the second input terminal of the first NOR gate NOR1 is electrically connected to the second node QB, and the output terminal of the first NOR gate NOR1 is electrically connected to the first node Q.

[0285] The first input terminal of the second NOR gate NOR2 is electrically connected to the first node Q, the second input terminal of the second NOR gate NOR2 is electrically connected to the fifth node NF, and the output terminal of the second NOR gate NOR2 is electrically connected to the second node QB.

[0286] The input terminal of the first transmission gate Tg1 is electrically connected to the enable terminal EN, the output terminal of the first transmission gate Tg1 is electrically connected to the third node NC, the inverting control terminal of the first transmission gate Tg1 is electrically connected to the first node Q, and the non-inverting control terminal of the first transmission gate Tg1 is electrically connected to the second node QB.

[0287] The input circuit includes a second transmission gate Tg2, a third NOR gate NOR3, a third transmission gate Tg3, and a first inverter INV1; the control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn.

[0288] The input terminal of the second transmission gate Tg2 is electrically connected to the input signal terminal GI, the output terminal of the second transmission gate Tg2 is electrically connected to the fourth node Q_m, the positive phase control terminal of the second transmission gate Tg2 is electrically connected to the fourth clock signal terminal CKn, and the inverting phase control terminal of the second transmission gate Tg2 is electrically connected to the third clock signal terminal CB.

[0289] The first input terminal of the third NOR gate NOR3 is electrically connected to the reset terminal Trst, the second input terminal of the third NOR gate NOR3 is electrically connected to the fourth node Q_m, and the output terminal of the third NOR gate Q_m is electrically connected to the fifth node NF.

[0290] The input terminal of the third transmission gate Tg3 is electrically connected to the fourth node Q_m, the output terminal of the third transmission gate Tg3 is electrically connected to the sixth node NS, the positive phase control terminal of the third transmission gate Tg3 is electrically connected to the second clock signal terminal CBn, and the negative phase control terminal of the third transmission gate Tg3 is electrically connected to the first clock signal terminal CK.

[0291] The input terminal of the first inverter INV1 is electrically connected to the fifth node NF, and the output terminal of the first inverter INV1 is electrically connected to the sixth node NS.

[0292] The signal output circuit includes a first NAND gate NAD1;

[0293] The first input terminal of the first NAND gate NAD1 is electrically connected to the fifth node NF, the second input terminal of the first NAND gate NAD1 is electrically connected to the third node NC, and the output terminal of the first NAND gate NAD1 is electrically connected to the first output terminal G1.

[0294] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, and a third output inverter IV3;

[0295] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, and the output terminal of IV3 is electrically connected to the second output terminal G2.

[0296] In at least one embodiment of the driving circuit shown in Figure 7, the first reset terminal and the second reset terminal are the same reset terminal Trst.

[0297] At least one embodiment of the driving circuit shown in Figure 7 can be used to control T1-T2 in the pixel circuit shown in Figure 40.

[0298] Figure 8 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure.

[0299] Figures 9A and 9B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 7.

[0300] As shown in Figure 8, based on at least one embodiment of the driving circuit shown in Figure 7, the first transmission gate includes a first transmission transistor Mc1 and a second transmission transistor Mc2, the second transmission gate includes a third transmission transistor Mc3 and a fourth transmission transistor Mc4, and the third transmission gate includes a fifth transmission transistor Mc5 and a sixth transmission transistor Mc6.

[0301] The gate of Mc1 is electrically connected to Q, the source of Mc1 is electrically connected to EN, and the drain of Mc1 is electrically connected to NC.

[0302] Mc2’s gate is electrically connected to QB, Mc2’s source is electrically connected to EN, and Mc2’s drain is electrically connected to NC.

[0303] Mc1 is an n-type transistor, and Mc2 is a p-type transistor;

[0304] The gate of Mc3 is electrically connected to CKn, the source of Mc3 is electrically connected to GI, and the drain of Mc3 is electrically connected to Q_m.

[0305] The gate of Mc4 is electrically connected to CB, the source of Mc4 is electrically connected to GI, and the drain of Mc4 is electrically connected to Q_m.

[0306] Mc3 is an n-type transistor, and Mc4 is a p-type transistor;

[0307] The gate of Mc5 is electrically connected to CBn, the source of Mc5 is electrically connected to Q_m, and the drain of Mc5 is electrically connected to NS.

[0308] The gate of Mc6 is electrically connected to CK, the source of Mc6 is electrically connected to Q_m, and the drain of Mc6 is electrically connected to NS.

[0309] Mc5 is an n-type transistor, and Mc6 is a p-type transistor;

[0310] The first NOR gate includes a first NOR control transistor Mn1, a second NOR control transistor Mn2, a third NOR control transistor Mn3, and a fourth NOR control transistor Mn4;

[0311] The gate of Mn1 is electrically connected to Trst, the source of Mn1 is electrically connected to the first high voltage terminal VGH1, and the drain of Mn1 is electrically connected to the source of Mn2.

[0312] The gate of Mn2 is electrically connected to Q, the drain of Mn2 is electrically connected to the source of Mn3, and the drain of Mn2 is electrically connected to QB.

[0313] The gate of Mn3 is electrically connected to Trst, the source of Mn3 is electrically connected to the source of Mn4, and the drain of Mn3 is electrically connected to the first low voltage terminal VGL1.

[0314] The gate of Mn4 is electrically connected to Q, and the drain of Mn4 is electrically connected to VGL1.

[0315] Mn1 and Mn2 are p-type transistors, while Mn3 and Mn4 are n-type transistors;

[0316] The second NOR gate includes the fifth NOR control transistor Mn5, the sixth NOR control transistor Mn6, the seventh NOR control transistor Mn7, and the eighth NOR control transistor Mn8.

[0317] The gate of Mn5 is electrically connected to NF, the source of Mn5 is electrically connected to VGH1, and the drain of Mn5 is electrically connected to the source of Mn6.

[0318] The gate of Mn6 is electrically connected to QB, the drain of Mn6 is electrically connected to the source of Mn7, and the drain of Mn6 is electrically connected to Q.

[0319] The gate of Mn7 is electrically connected to NF, and the drain of Mn7 is electrically connected to VGL1.

[0320] The gate of Mn8 is electrically connected to QB, the source of Mn8 is electrically connected to the source of Mn7, and the drain of Mn8 is electrically connected to VGL1.

[0321] Mn5 and Mn6 are p-type transistors, while Mn7 and Mn8 are n-type transistors;

[0322] The third NOR gate includes the ninth NOR control transistor Mn9, the tenth NOR control transistor Mn10, the eleventh NOR control transistor Mn11, and the twelfth NOR control transistor Mn12.

[0323] The gate of Mn9 is electrically connected to Trst, the source of Mn9 is electrically connected to VGH1, and the drain of Mn9 is electrically connected to the source of Mn10.

[0324] The gate of Mn10 is electrically connected to Q_m, and the drain of Mn10 is connected to NF;

[0325] The gate of Mn11 is electrically connected to Q_m, the source of Mn11 is electrically connected to NF, and the drain of Mn11 is electrically connected to VGL1.

[0326] The gate of Mn12 is electrically connected to Trst, the source of Mn12 is electrically connected to NF, and Mn12 is electrically connected to VGL1.

[0327] Mn9 and Mn10 are p-type transistors, while Mn11 and Mn12 are n-type transistors;

[0328] The first NAND gate includes a first NAND control transistor Ma1, a second NAND control transistor Ma2, a third NAND control transistor Ma3, and a fourth NAND control transistor Ma4;

[0329] The gate of Ma1 is electrically connected to NF, the source of Ma1 is electrically connected to VGH1, and the drain of Ma1 is electrically connected to G1.

[0330] The gate of Ma2 is electrically connected to NC, the source of Ma2 is electrically connected to VGH1, and the drain of Ma2 is electrically connected to G1.

[0331] The gate of Ma3 is electrically connected to NF, the source of Ma3 is electrically connected to G1, and the drain of Ma3 is electrically connected to the source of Ma4.

[0332] The gate of Ma4 is electrically connected to NC, and the drain of Ma4 is electrically connected to VGL1.

[0333] Ma1 and Ma2 are p-type transistors, while Ma3 and Ma4 are n-type transistors;

[0334] The first inverter includes a first inverting transistor Mf1 and a second inverting transistor Mf2;

[0335] The gate of Mf1 is electrically connected to NF, the source of Mf1 is electrically connected to VGH1, and the drain of Mf1 is electrically connected to NS.

[0336] The gate of Mf2 is electrically connected to NF, the source of Mf2 is electrically connected to NS, and the drain of Mf2 is electrically connected to VGL1.

[0337] Mf1 is a p-type transistor, and Mf2 is an n-type transistor;

[0338] The first output inverter includes a first output inverter transistor Ms1 and a second output inverter transistor Ms2;

[0339] The gate of Ms1 is electrically connected to G1, the source of Ms1 is electrically connected to VGH1, and the drain of Ms1 is electrically connected to the source of Ms2.

[0340] The gate of Ms2 is electrically connected to G1, and the drain of Ms2 is electrically connected to VGL1.

[0341] Ms1 is a p-type transistor, and Ms2 is an n-type transistor;

[0342] The second output inverter includes a third output inverter transistor Ms3 and a fourth output inverter transistor Ms4;

[0343] The gate of Ms3 is electrically connected to the drain of Ms1, the source of Ms3 is electrically connected to VGH1, and the drain of Ms3 is electrically connected to the source of Ms4.

[0344] The gate of Ms4 is electrically connected to the drain of Ms1, and the drain of Ms4 is electrically connected to VGL1.

[0345] Ms3 is a p-type transistor, and Ms4 is an n-type transistor;

[0346] The third output inverter includes the fifth output inverter transistor Ms5 and the sixth output inverter transistor Ms6;

[0347] The gate of Ms5 is electrically connected to the drain of Ms3, the source of Ms5 is electrically connected to the second high voltage terminal VGH2, and the drain of Ms5 is electrically connected to the source of Ms6.

[0348] The gate of Ms6 is electrically connected to the drain of Ms3, and the drain of Ms6 is electrically connected to the second low voltage terminal VGL2.

[0349] Ms5 is a p-type transistor, and Ms6 is an n-type transistor.

[0350] In Figure 8, the capacitor labeled C1 is the first capacitor.

[0351] In at least one embodiment of the drive circuit shown in Figure 7, when operating, EN provides a high voltage signal during high-frequency refresh and a low voltage signal during low-frequency refresh.

[0352] As shown in Figure 9A, the m-th row driving circuit (the structure of the m-th row driving circuit is shown in Figure 7) operates during high-frequency refresh.

[0353] During the reset period S0, Trst provides a high voltage signal, NOR1 outputs a low voltage signal to Q, Q's potential is low, NF's potential is low, NOR2 outputs a high voltage signal to QB, making QB's potential high, Tg1 is turned on, and the enable signal provided by EN can be transmitted to NC through Tg1.

[0354] Between the reset time period S0 and the first output time period S11, when EN provides a high voltage signal, Q has a low voltage signal, and QB has a high voltage signal, the high voltage signal provided by EN is transmitted to NC through Tg1.

[0355] When the potential of the signal provided by NF jumps from low voltage to high voltage, NOR2 outputs a low voltage signal to QB, and the potential of QB is low voltage; Trst provides a low voltage signal, NOR1 provides a high voltage signal to Q, the potential of Q becomes high voltage, the potential of QB becomes low voltage, and Tg1 is cut off.

[0356] During the first output time period S11, G2 outputs a high voltage signal to control the corresponding transistor in the pixel circuit to turn on.

[0357] During the second output time period S12, even if EN provides a low voltage signal, since Tg1 is in the off state, the enable signal provided by EN will not affect the second output signal provided by G2. Therefore, G2 outputs a high voltage signal to control the corresponding transistor in the pixel circuit to turn on.

[0358] As shown in Figure 9B, when the m-th row driving circuit (the structure of the m-th row driving circuit is shown in Figure 7) is working, during low-frequency refresh,

[0359] During the reset period S0, Trst provides a high voltage signal, NOR1 outputs a low voltage signal to Q, Q's potential is low, NF's potential is low, NOR2 outputs a high voltage signal to QB, making QB's potential high, Tg1 is turned on, and the enable signal provided by EN can be transmitted to NC through Tg1.

[0360] Between the reset time period S0 and the m-th row drive time period S2, when EN provides a low voltage signal, the potential of Q is low voltage, and the potential of QB is high voltage. The low voltage signal provided by EN is transmitted to NC through Tg1.

[0361] When the potential of the signal provided by NF jumps from low voltage to high voltage, NOR2 outputs a low voltage signal to QB, and the potential of QB is low voltage; Trst provides a low voltage signal, NOR1 provides a high voltage signal to Q, the potential of Q becomes high voltage, the potential of QB becomes low voltage, and Tg1 is cut off.

[0362] During the driving time period S2 of the m-th row, G2 in the driving circuit of the m-th row outputs a low voltage signal;

[0363] During the driving time period S2 of the m-th row, even if EN provides a high voltage signal, since Tg1 is in the off state, the enable signal provided by EN will not affect the second output signal provided by G2. Therefore, G2 outputs a low voltage signal to control the corresponding transistor in the pixel circuit to turn off.

[0364] As shown in Figure 10, based on at least one embodiment of the driving circuit shown in Figure 3, the latching circuit includes a first NOR gate NOR1, a second NOR gate NOR2, and a first transmission gate Tg1.

[0365] The first input terminal of the first NOR gate NOR1 is electrically connected to the reset terminal Trst, the second input terminal of the first NOR gate NOR1 is electrically connected to the second node QB, and the output terminal of the first NOR gate NOR1 is electrically connected to the first node Q.

[0366] The first input terminal of the second NOR gate NOR2 is electrically connected to the first node Q, the second input terminal of the second NOR gate NOR2 is electrically connected to the fifth node NF, and the output terminal of the second NOR gate NOR2 is electrically connected to the second node QB.

[0367] The input terminal of the first transmission gate Tg1 is electrically connected to the enable terminal EN, the output terminal of the first transmission gate Tg1 is electrically connected to the third node NC, the inverting control terminal of the first transmission gate Tg1 is electrically connected to the first node Q, and the non-inverting control terminal of the first transmission gate Tg1 is electrically connected to the second node QB.

[0368] The input circuit includes a second transmission gate Tg2, a third NOR gate, a third transmission gate Tg3, and a first inverter INV1; the control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn.

[0369] The input terminal of the second transmission gate Tg2 is electrically connected to the input signal terminal GI, the output terminal of the second transmission gate Tg2 is electrically connected to the fourth node Q_m, the positive phase control terminal of the second transmission gate Tg2 is electrically connected to the fourth clock signal terminal CKn, and the inverting phase control terminal of the second transmission gate Tg2 is electrically connected to the third clock signal terminal CB.

[0370] The first input terminal of the third NOR gate NOR3 is electrically connected to the reset terminal Trst, the second input terminal of the third NOR gate NOR3 is electrically connected to the fourth node Q_m, and the output terminal of the third NOR gate Q_m is electrically connected to the fifth node NF.

[0371] The input terminal of the third transmission gate Tg3 is electrically connected to the fourth node Q_m, the output terminal of the third transmission gate Tg3 is electrically connected to the sixth node NS, the positive phase control terminal of the third transmission gate Tg3 is electrically connected to the second clock signal terminal CBn, and the negative phase control terminal of the third transmission gate Tg3 is electrically connected to the first clock signal terminal CK.

[0372] The input terminal of the first inverter INV1 is electrically connected to the fifth node NF, and the output terminal of the first inverter INV1 is electrically connected to the sixth node NS.

[0373] The signal output circuit includes a fourth NOR gate (NOR4).

[0374] The first input terminal of the fourth NOR gate NOR4 is electrically connected to the sixth node NS, the second input terminal of the fourth NOR gate is electrically connected to the third node NC, the third input terminal of the fourth NOR gate NOR4 is electrically connected to the first clock signal terminal CK, and the output terminal of the fourth NOR gate NOR4 is electrically connected to the first output terminal G1.

[0375] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, and a third output inverter IV3;

[0376] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, and the output terminal of IV3 is electrically connected to the second output terminal G2.

[0377] In at least one embodiment of the driving circuit shown in Figure 10, the first reset terminal and the second reset terminal are the same reset terminal Trst, and the output control clock signal terminal is the first clock signal terminal CK.

[0378] In at least one embodiment of this disclosure, the output control clock signal terminal can be a separate clock signal terminal, which can be used to adjust the low-level width of the low-voltage signal provided by G2.

[0379] In at least one embodiment of the driving circuit shown in Figure 10, the pulse width of the second output signal provided by G2 is adjustable and can be used to control T4-T9 in Figure 40.

[0380] In at least one embodiment of the driving circuit shown in Figure 10, NOR4 includes three input terminals. The first input terminal of NOR4 is electrically connected to CK, the second input terminal of NOR4 is electrically connected to NS, and the third input terminal of NOR4 is electrically connected to NC. G1 can only output a low voltage signal when CK, NS, and NC all output low voltage signals, thereby realizing the low level width of the second output signal provided by G2 and the low level width of the first clock signal provided by CK.

[0381] Figure 11 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.

[0382] Figures 12A and 12B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 10.

[0383] As shown in Figure 11, based on at least one embodiment of the driving circuit shown in Figure 10,

[0384] The first transmission gate includes a first transmission transistor Mc1 and a second transmission transistor Mc2, the second transmission gate includes a third transmission transistor Mc3 and a fourth transmission transistor Mc4, and the third transmission gate includes a fifth transmission transistor Mc5 and a sixth transmission transistor Mc6.

[0385] The gate of Mc1 is electrically connected to Q, the source of Mc1 is electrically connected to EN, and the drain of Mc1 is electrically connected to NC.

[0386] Mc2’s gate is electrically connected to QB, Mc2’s source is electrically connected to EN, and Mc2’s drain is electrically connected to NC.

[0387] Mc1 is an n-type transistor, and Mc2 is a p-type transistor;

[0388] The gate of Mc3 is electrically connected to CKn, the source of Mc3 is electrically connected to GI, and the drain of Mc3 is electrically connected to Q_m.

[0389] The gate of Mc4 is electrically connected to CB, the source of Mc4 is electrically connected to GI, and the drain of Mc4 is electrically connected to Q_m.

[0390] Mc3 is an n-type transistor, and Mc4 is a p-type transistor;

[0391] The gate of Mc5 is electrically connected to CBn, the source of Mc5 is electrically connected to Q_m, and the drain of Mc5 is electrically connected to NS.

[0392] The gate of Mc6 is electrically connected to CK, the source of Mc6 is electrically connected to Q_m, and the drain of Mc6 is electrically connected to NS.

[0393] Mc5 is an n-type transistor, and Mc6 is a p-type transistor;

[0394] The first NOR gate includes a first NOR control transistor Mn1, a second NOR control transistor Mn2, a third NOR control transistor Mn3, and a fourth NOR control transistor Mn4;

[0395] The gate of Mn1 is electrically connected to Trst, the source of Mn1 is electrically connected to the first high voltage terminal VGH1, and the drain of Mn1 is electrically connected to the source of Mn2.

[0396] The gate of Mn2 is electrically connected to Q, the drain of Mn2 is electrically connected to the source of Mn3, and the drain of Mn2 is electrically connected to QB.

[0397] The gate of Mn3 is electrically connected to Trst, the source of Mn3 is electrically connected to the source of Mn4, and the drain of Mn3 is electrically connected to the first low voltage terminal VGL1.

[0398] The gate of Mn4 is electrically connected to Q, and the drain of Mn4 is electrically connected to VGL1.

[0399] Mn1 and Mn2 are p-type transistors, while Mn3 and Mn4 are n-type transistors;

[0400] The second NOR gate includes the fifth NOR control transistor Mn5, the sixth NOR control transistor Mn6, the seventh NOR control transistor Mn7, and the eighth NOR control transistor Mn8.

[0401] The gate of Mn5 is electrically connected to NF, the source of Mn5 is electrically connected to VGH1, and the drain of Mn5 is electrically connected to the source of Mn6.

[0402] The gate of Mn6 is electrically connected to QB, the drain of Mn6 is electrically connected to the source of Mn7, and the drain of Mn6 is electrically connected to Q.

[0403] The gate of Mn7 is electrically connected to NF, and the drain of Mn7 is electrically connected to VGL1.

[0404] The gate of Mn8 is electrically connected to QB, the source of Mn8 is electrically connected to the source of Mn7, and the drain of Mn8 is electrically connected to VGL1.

[0405] Mn5 and Mn6 are p-type transistors, while Mn7 and Mn8 are n-type transistors;

[0406] The third NOR gate includes the ninth NOR control transistor Mn9, the tenth NOR control transistor Mn10, the eleventh NOR control transistor Mn11, and the twelfth NOR control transistor Mn12.

[0407] The gate of Mn9 is electrically connected to Trst, the source of Mn9 is electrically connected to VGH1, and the drain of Mn9 is electrically connected to the source of Mn10.

[0408] The gate of Mn10 is electrically connected to Q_m, and the drain of Mn10 is connected to NF;

[0409] The gate of Mn11 is electrically connected to Q_m, the source of Mn11 is electrically connected to NF, and the drain of Mn11 is electrically connected to VGL1.

[0410] The gate of Mn12 is electrically connected to Trst, the source of Mn12 is electrically connected to NF, and Mn12 is electrically connected to VGL1.

[0411] Mn9 and Mn10 are p-type transistors, while Mn11 and Mn12 are n-type transistors;

[0412] The fourth NOR gate includes the thirteenth NOR control transistor Mn13, the fourteenth NOR control transistor Mn14, the fifteenth NOR control transistor Mn15, the sixteenth NOR control transistor Mn16, the seventeenth NOR control transistor Mn17, and the eighteenth NOR control transistor Mn18.

[0413] The gate of Mn13 is electrically connected to CK, the source of Mn13 is electrically connected to VGH1, and the drain of Mn13 is electrically connected to the source of Mn14.

[0414] The gate of Mn14 is electrically connected to NC, and the drain of Mn14 is electrically connected to the source of Mn15.

[0415] The gate of Mn15 is electrically connected to NS, and the drain of Mn15 is electrically connected to G1.

[0416] The gate of Mn16 is electrically connected to NS, the source of Mn16 is electrically connected to G1, and the drain of Mn16 is electrically connected to VGL1.

[0417] The gate of Mn17 is electrically connected to NC, the source of Mn17 is electrically connected to G1, and the drain of Mn17 is electrically connected to VGL1.

[0418] The gate of Mn18 is electrically connected to CK, the source of Mn17 is electrically connected to G1, and the drain of Mn17 is electrically connected to VGL1.

[0419] Mn13 and Mn14 are p-type transistors, while Mn15, Mn16, Mn17 and Mn18 are n-type transistors.

[0420] The first inverter includes a first inverting transistor Mf1 and a second inverting transistor Mf2;

[0421] The gate of Mf1 is electrically connected to NF, the source of Mf1 is electrically connected to VGH1, and the drain of Mf1 is electrically connected to NS.

[0422] The gate of Mf2 is electrically connected to NF, the source of Mf2 is electrically connected to NS, and the drain of Mf2 is electrically connected to VGL1.

[0423] Mf1 is a p-type transistor, and Mf2 is an n-type transistor;

[0424] The first output inverter includes a first output inverter transistor Ms1 and a second output inverter transistor Ms2;

[0425] The gate of Ms1 is electrically connected to G1, the source of Ms1 is electrically connected to VGH1, and the drain of Ms1 is electrically connected to the source of Ms2.

[0426] The gate of Ms2 is electrically connected to G1, and the drain of Ms2 is electrically connected to VGL1.

[0427] Ms1 is a p-type transistor, and Ms2 is an n-type transistor;

[0428] The second output inverter includes a third output inverter transistor Ms3 and a fourth output inverter transistor Ms4;

[0429] The gate of Ms3 is electrically connected to the drain of Ms1, the source of Ms3 is electrically connected to VGH1, and the drain of Ms3 is electrically connected to the source of Ms4.

[0430] The gate of Ms4 is electrically connected to the drain of Ms1, and the drain of Ms4 is electrically connected to VGL1.

[0431] Ms3 is a p-type transistor, and Ms4 is an n-type transistor;

[0432] The third output inverter includes the fifth output inverter transistor Ms5 and the sixth output inverter transistor Ms6;

[0433] The gate of Ms5 is electrically connected to the drain of Ms3, the source of Ms5 is electrically connected to the second high voltage terminal VGH2, and the drain of Ms5 is electrically connected to the source of Ms6.

[0434] The gate of Ms6 is electrically connected to the drain of Ms3, and the drain of Ms6 is electrically connected to the second low voltage terminal VGL2.

[0435] Ms5 is a p-type transistor, and Ms6 is an n-type transistor.

[0436] In Figure 11, the capacitor labeled C1 is the first capacitor.

[0437] In at least one embodiment of the driving circuit shown in FIG10 of this disclosure, NOR4 has three input terminals. The first input terminal of NOR4 is electrically connected to CK, the second input terminal of NOR4 is electrically connected to NS, and the third input terminal of NOR4 is electrically connected to NC. When the driving circuit normally outputs the driving signal, the low-level width of the second output signal provided by G2 is equal to the low-level width of the first clock signal provided by CK.

[0438] As shown in Figure 12A, the m-th row driving circuit (the structure of the m-th row driving circuit is shown in Figure 10, where m is a positive integer) performs high-frequency refresh.

[0439] During the reset period S0, Trst provides a high voltage signal, NOR1 outputs a low voltage signal to Q, Q's potential is low, NF's potential is low, NOR2 outputs a high voltage signal to QB, making QB's potential high, Tg1 is turned on, and the enable signal provided by EN can be transmitted to NC through Tg1.

[0440] Before the first output time period S11, EN provides a low voltage signal, Q has a low voltage potential, and QB has a high voltage potential. The low voltage signal provided by EN is transmitted to NC through Tg1.

[0441] When the potential of the signal provided by NF jumps from low voltage to high voltage, NOR2 outputs a low voltage signal to QB, Trst provides a low voltage signal, NOR1 outputs a high voltage signal to Q, the potential of Q becomes high voltage, the potential of QB becomes low voltage, and Tg1 is cut off.

[0442] During the first output time period S11, G2 provides a low voltage signal to control the corresponding transistor in the pixel circuit to turn on;

[0443] During the time period between the first output time period S11 and the second output time period S12, even if EN provides a high voltage signal, the enable signal provided by EN will not affect the second output signal of G2 because Tg1 is in the off state.

[0444] During the second output time period S12, G2 provides a low voltage signal to control the corresponding transistor in the pixel circuit to turn on.

[0445] As shown in Figure 12B, the m-th row driving circuit (the structure of the m-th row driving circuit is shown in Figure 10, where m is a positive integer) performs low-frequency refresh.

[0446] During the reset period S0, Trst provides a high voltage signal, NOR1 outputs a low voltage signal to Q, Q's potential is low, NF's potential is low, NOR2 outputs a high voltage signal to QB, making QB's potential high, Tg1 is turned on, and the enable signal provided by EN can be transmitted to NC through Tg1.

[0447] Before the driving time period S2 of the m-th row, EN provides a high voltage signal, Q has a low voltage potential, and QB has a high voltage potential. The high voltage signal provided by EN is transmitted to NC through Tg1.

[0448] When the potential of the signal provided by NF jumps from low voltage to high voltage, NOR2 outputs a low voltage signal to QB, Trst provides a low voltage signal, NOR1 outputs a high voltage signal to Q, the potential of Q becomes high voltage, the potential of QB becomes low voltage, and Tg1 is cut off.

[0449] During the driving time period S2 of the m-th row, G2 provides a high voltage signal to control the corresponding transistor in the pixel circuit to turn off;

[0450] During the driving time period S2 in the m-th row, even if EN provides a low voltage signal, the enable signal provided by EN will not affect the second output signal of G2 because Tg1 is in the off state.

[0451] The difference between at least one embodiment of the driving circuit shown in Figure 12C and at least one embodiment of the driving circuit shown in Figure 10 is that the first input terminal of NOR3 is electrically connected to the first reset terminal Trst1, and the first input terminal of NOR1 is electrically connected to the second reset terminal Trst2.

[0452] In at least one embodiment of the driving circuit shown in Figure 12C, NOR4 includes three input terminals. The first input terminal of NOR4 is electrically connected to CK, the second input terminal of NOR4 is electrically connected to NS, and the third input terminal of NOR4 is electrically connected to NC. G1 can only output a low voltage signal when CK, NS, and NC all output low voltage signals, thereby realizing the low level width of the second output signal provided by G2 and the low level width of the first clock signal provided by CK.

[0453] Figures 12D and 12E are timing diagrams of at least one embodiment of the driving circuit shown in Figure 12C.

[0454] In at least one embodiment of the driving circuit shown in Figure 12C of this disclosure, when in operation, Tg1 is reset by a second reset signal provided by Trst2. When Trst2 provides a high voltage signal, Tg1 is turned on, and when NS provides a low voltage signal, Tg1 is turned off until Trst2 outputs a high voltage signal again.

[0455] As shown in Figure 12D, the m-th row driving circuit (the structure of the m-th row driving circuit is shown in Figure 12C, where m is a positive integer) performs high-frequency refresh.

[0456] During the reset period S0, Trst2 provides a high voltage signal, NOR1 outputs a low voltage signal to Q, Q's potential is low, NF's potential is low, NOR2 outputs a high voltage signal to QB, making QB's potential high, Tg1 is turned on, and the enable signal provided by EN can be transmitted to NC through Tg1.

[0457] Before the first output time period S11, EN provides a low voltage signal, Q has a low voltage potential, and QB has a high voltage potential. The low voltage signal provided by EN is transmitted to NC through Tg1.

[0458] When the potential of the signal provided by NF jumps from low voltage to high voltage, NOR2 outputs a low voltage signal to QB, Trst provides a low voltage signal, NOR1 outputs a high voltage signal to Q, the potential of Q becomes high voltage, the potential of QB becomes low voltage, and Tg1 is cut off.

[0459] During the first output time period S11, G2 provides a low voltage signal to control the corresponding transistor in the pixel circuit to turn on;

[0460] During the time period between the first output time period S11 and the second output time period S12, even if EN provides a high voltage signal, the enable signal provided by EN will not affect the second output signal of G2 because Tg1 is in the off state.

[0461] During the second output time period S12, G2 provides a low voltage signal to control the corresponding transistor in the pixel circuit to turn on.

[0462] As shown in Figure 12E, the m-th row driving circuit (the structure of the m-th row driving circuit is shown in Figure 12C, where m is a positive integer) performs low-frequency refresh.

[0463] During the reset period S0, Trst2 provides a high voltage signal, NOR1 outputs a low voltage signal to Q, Q's potential is low, NF's potential is low, NOR2 outputs a high voltage signal to QB, making QB's potential high, Tg1 is turned on, and the enable signal provided by EN can be transmitted to NC through Tg1.

[0464] Before the driving time period S2 of the m-th row, EN provides a high voltage signal, Q has a low voltage potential, and QB has a high voltage potential. The high voltage signal provided by EN is transmitted to NC through Tg1.

[0465] When the potential of the signal provided by NF jumps from low voltage to high voltage, NOR2 outputs a low voltage signal to QB, Trst provides a low voltage signal, NOR1 outputs a high voltage signal to Q, the potential of Q becomes high voltage, the potential of QB becomes low voltage, and Tg1 is cut off.

[0466] During the driving time period S2 of the m-th row, G2 provides a high voltage signal to control the corresponding transistor in the pixel circuit to turn off;

[0467] During the driving time period S2 in the m-th row, even if EN provides a low voltage signal, the enable signal provided by EN will not affect the second output signal of G2 because Tg1 is in the off state.

[0468] As shown in Figure 13, the driving circuit described in this embodiment includes an input circuit 11, a latch circuit 12, a control circuit 10, and a signal output circuit 13.

[0469] The input circuit 11 is electrically connected to the input signal terminal GI, the control clock signal terminal CKC, and the control circuit 10, respectively, and is used to provide an inverted output signal according to the input signal provided by the input signal terminal GI under the control of the control clock signal provided by the control clock signal terminal CKC.

[0470] The control circuit 10 is electrically connected to the first reset terminal Trst1 and is used to provide an output control signal under the control of the first reset signal provided by the first reset terminal Trst1 and the inverted output signal.

[0471] The latch circuit 12 is electrically connected to the second reset terminal Trst2, the enable terminal EN, the input circuit 11, the control circuit 10, and the signal output circuit 13, respectively, and is used to transmit the enable signal provided by the enable terminal EN to the signal output circuit 13 under the control of the second reset signal provided by the second reset terminal Trst2, the output control signal, and the inverted output signal.

[0472] The signal output circuit 13 is electrically connected to the control circuit 10 and the first output terminal G1, respectively, and is used to generate and provide a first output signal through the first output terminal G1 according to the output control signal and the signal provided by the latch circuit 12.

[0473] In at least one embodiment of this disclosure, the first reset terminal and the second reset terminal may be the same reset terminal.

[0474] In practice, the first reset terminal and the second reset terminal can be the same reset terminal to reduce the number of reset terminals used.

[0475] In at least one embodiment of this disclosure, the latching circuit is configured to transmit the enable signal provided by the enable terminal to the third node within a frame time, between the time point when the second reset terminal begins to provide a valid second reset signal and the time point when the first control terminal first begins to provide a valid first control signal. After the time point when the first control terminal first begins to provide a valid first control signal, the control starts latching and stops transmitting the enable signal to the third node.

[0476] The driving circuit described in at least one embodiment of this disclosure further includes a driving enhancement circuit; the driving enhancement circuit includes an N-stage output inverter; N is an integer greater than 1;

[0477] The input terminal of the first output inverter is electrically connected to the first output terminal;

[0478] The output terminal of the nth output inverter is electrically connected to the input terminal of the (n+1)th output inverter, and the output terminal of the Nth output inverter is electrically connected to the drive signal output terminal; n is a positive integer less than N;

[0479] The output inverter is used to invert the signal input to its input terminal, and generate an inverted signal that is provided through the output terminal of the output inverter.

[0480] In a specific implementation, the driving circuit may further include a driving enhancement circuit, which includes a multi-stage output inverter to provide an enhanced driving output signal or an inverted output signal.

[0481] In at least one embodiment of this disclosure, the driving circuit includes a plurality of driving enhancement circuits;

[0482] At least one of the plurality of drive enhancement circuits is used to provide a drive output signal;

[0483] At least one of the plurality of drive enhancement circuits is used to provide an inverted drive output signal;

[0484] The drive output signal is out of phase with the inverting drive output signal.

[0485] As shown in FIG14, based on at least one embodiment of the driving circuit shown in FIG13, the driving circuit of at least one embodiment of the present disclosure further includes a driving enhancement circuit 20;

[0486] The input terminal of the drive enhancement circuit 20 is electrically connected to the first output terminal G1, and the output terminal of the drive enhancement circuit 20 is electrically connected to the second output terminal G2.

[0487] Optionally, the signal output circuit is also electrically connected to the output control clock signal terminal, and is used to generate and provide a first output signal through the first output terminal under the control of the output control clock signal provided by the output control clock signal terminal, the output control signal, and the signal provided by the latch circuit.

[0488] As shown in Figure 15, based on at least one embodiment of the driving circuit shown in Figure 14, the signal output circuit 13 is also electrically connected to the output control clock signal terminal CKO, and is used to generate and provide a first output signal through the first output terminal G1 under the control of the output control clock signal provided by the output control clock signal terminal CKO, the output control signal, and the signal provided by the latch circuit 12.

[0489] In at least one embodiment of this disclosure, the latch circuit includes a first NAND gate, a second NAND gate, and a first transmission gate;

[0490] The first input terminal of the first NAND gate is electrically connected to the sixth node, the second input terminal of the first NAND gate is electrically connected to the first node, and the output terminal of the first NAND gate is electrically connected to the second node.

[0491] The first input terminal of the second NAND gate is electrically connected to the second node, the second input terminal of the second NAND gate is electrically connected to the second reset terminal, and the output terminal of the second NAND gate is electrically connected to the first node.

[0492] The input terminal of the first transmission gate is electrically connected to the enable terminal, the output terminal of the first transmission gate is electrically connected to the third node, the positive phase control terminal of the first transmission gate is electrically connected to the first node, and the negative phase control terminal of the first transmission gate is electrically connected to the second node.

[0493] In a specific implementation, the latching circuit may include a first NAND gate, a second NAND gate, and a first transmission gate; the first NAND gate performs a NAND operation on the signal provided by the sixth node and the signal provided by the first node to obtain the signal provided by the second node; the second NAND gate performs a NAND operation on the signal provided by the second node and the second reset signal provided by the second reset terminal to obtain the signal provided by the first node; the first transmission gate transmits the enable signal provided by the enable terminal to the second node based on the signal provided by the first node and the signal provided by the second node.

[0494] In at least one embodiment of this disclosure, the input circuit includes a second transmission gate, a first inverter, a third transmission gate, and a second inverter;

[0495] The control clock signal terminal includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;

[0496] The input terminal of the second transmission gate is electrically connected to the input signal terminal, the output terminal of the second transmission gate is electrically connected to the fourth node, the positive phase control terminal of the second transmission gate is electrically connected to the fourth clock signal terminal, and the negative phase control terminal of the second transmission gate is electrically connected to the third clock signal terminal.

[0497] The input terminal of the third transmission gate is electrically connected to the fourth node, the output terminal of the third transmission gate is electrically connected to the output terminal of the second inverter, the non-inverting control terminal of the third transmission gate is electrically connected to the second clock signal terminal, and the inverting control terminal of the third transmission gate is electrically connected to the first clock signal terminal.

[0498] The input terminal of the first inverter is electrically connected to the fourth node, and the output terminal of the first inverter is electrically connected to the fifth node;

[0499] The input terminal of the second inverter is electrically connected to the fifth node.

[0500] In a specific implementation, the input circuit may include a second transmission gate, a first inverter, a third transmission gate, and a second inverter; under the control of a fourth clock signal and a third clock signal, the second transmission gate transmits the input signal provided by the input signal terminal to the fourth node, and under the control of a second clock signal and a first clock signal, the third transmission gate transmits the signal provided by the fourth node to the output terminal of the second inverter.

[0501] In at least one embodiment of this disclosure, the control circuit includes a third NAND gate;

[0502] The first input terminal of the third NAND gate is electrically connected to the first reset terminal, the second input terminal of the third NAND gate is electrically connected to the fifth node, and the output terminal of the third NAND gate is electrically connected to the sixth node.

[0503] In a specific implementation, the control circuit may include a third NAND gate; the third NAND gate performs a NAND operation on the first reset signal provided by the first reset terminal and the signal provided by the fifth node to obtain the signal provided by the sixth node.

[0504] Optionally, the signal output circuit includes a first NOR gate;

[0505] The first input terminal of the first NOR gate is electrically connected to the sixth node, the second input terminal of the first NOR gate is electrically connected to the third node, and the output terminal of the first NOR gate is electrically connected to the first output terminal.

[0506] In a specific implementation, the signal output circuit may include a first NOR gate, which performs a NOR operation on the signal provided by the sixth node and the signal provided by the third node to obtain a first output signal.

[0507] Optionally, the signal output circuit includes a first NOR gate;

[0508] The first input terminal of the first NOR gate is electrically connected to the output control clock signal terminal, the second input terminal of the first NOR gate is electrically connected to the sixth node, the third input terminal of the first NOR gate is electrically connected to the third node, and the output terminal of the first NOR gate is electrically connected to the first output terminal.

[0509] In a specific implementation, the signal output circuit may include a first NOR gate, which performs a NOR operation on the output control clock signal and the signal provided by the sixth node to obtain a first output signal.

[0510] As shown in Figure 16, based on at least one embodiment of the driving circuit shown in Figure 14,

[0511] The latching circuit includes a first NAND gate NAD1, a second NAND gate NAD2, and a first transmission gate Tg1;

[0512] The first input terminal of the first NAND gate NAD1 is electrically connected to the sixth node NS, the second input terminal of the first NAND gate NAD1 is electrically connected to the first node Q, and the output terminal of the first NAND gate NAD1 is electrically connected to the second node QB.

[0513] The first input terminal of the second NAND gate NAD2 is electrically connected to the second node QB, the second input terminal of the second NAND gate NAD2 is electrically connected to the reset terminal Trst, and the output terminal of the second NAND gate NAD2 is electrically connected to the first node Q.

[0514] The input terminal of the first transmission gate Tg1 is electrically connected to the enable terminal EN, the output terminal of the first transmission gate Tg1 is electrically connected to the third node NC, the positive phase control terminal of the first transmission gate Tg1 is electrically connected to the first node Q, and the negative phase control terminal of the first transmission gate is electrically connected to the second node QB.

[0515] The input circuit includes a second transmission gate Tg2, a first inverter INV1, a third transmission gate Tg3, and a second inverter INV2;

[0516] The control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn;

[0517] The input terminal of the second transmission gate Tg2 is electrically connected to the input signal terminal GI, the output terminal of the second transmission gate Tg2 is electrically connected to the fourth node Q_m, the positive phase control terminal of the second transmission gate Tg2 is electrically connected to the fourth clock signal terminal CKn, and the inverting phase control terminal of the second transmission gate Tg2 is electrically connected to the third clock signal terminal CB.

[0518] The input terminal of the third transmission gate Tg3 is electrically connected to the fourth node Q_m, the output terminal of the third transmission gate Tg3 is electrically connected to the output terminal of the second inverter INV2, the positive phase control terminal of the third transmission gate Tg3 is electrically connected to the second clock signal terminal CBn, and the negative phase control terminal of the third transmission gate Tg3 is electrically connected to the first clock signal terminal CK.

[0519] The input terminal of the first inverter INV1 is electrically connected to the fourth node Q_m, and the output terminal of the first inverter INV1 is electrically connected to the fifth node NF.

[0520] The input terminal of the second inverter INV2 is electrically connected to the fifth node NF;

[0521] The control circuit includes a third NAND gate, NAD3;

[0522] The first input terminal of the third NAND gate NAD3 is electrically connected to the reset terminal Trst, the second input terminal of the third NAND gate NAD3 is electrically connected to the fifth node NF, and the output terminal of the third NAND gate NAD3 is electrically connected to the sixth node NS.

[0523] The signal output circuit includes a first NOR gate (NOR1).

[0524] The first input terminal of the first NOR gate NOR1 is electrically connected to the sixth node NS, the second input terminal of the first NOR gate NOR1 is electrically connected to the third node NC, and the output terminal of the first NOR gate NOR1 is electrically connected to the first output terminal G1.

[0525] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, and a third output inverter IV3;

[0526] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, and the output terminal of IV3 is electrically connected to the second output terminal G2.

[0527] In at least one embodiment of the driving circuit shown in Figure 16, the first reset terminal and the second reset terminal are the same reset terminal.

[0528] Figure 17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.

[0529] Figures 18A and 18B are timing diagrams of at least one embodiment of the drive circuit shown in Figure 16.

[0530] As shown in Figure 17, based on at least one embodiment of the driving circuit shown in Figure 16, the first transmission gate includes a first transmission transistor Mc1 and a second transmission transistor Mc2.

[0531] The gate of Mc1 is electrically connected to Q, the source of Mc1 is electrically connected to EN, and the drain of Mc1 is electrically connected to NC.

[0532] Mc2’s gate is electrically connected to QB, Mc2’s source is electrically connected to EN, and Mc2’s drain is electrically connected to NC.

[0533] Mc1 is an n-type transistor, and Mc2 is a p-type transistor;

[0534] The second transmission gate includes a third transmission transistor Mc3 and a fourth transmission transistor Mc4;

[0535] The gate of Mc3 is electrically connected to CKn, the source of Mc3 is electrically connected to GI, and the drain of Mc3 is electrically connected to Q_m.

[0536] The gate of Mc4 is electrically connected to CB, the source of Mc4 is electrically connected to GI, and the drain of Mc4 is electrically connected to Q_m.

[0537] Mc3 is an n-type transistor, and Mc4 is a p-type transistor;

[0538] The third transmission gate includes the fifth transmission transistor Mc5 and the sixth transmission transistor Mc6;

[0539] The gate of Mc5 is electrically connected to CBn, the source of Mc3 is electrically connected to Q_m, and the drain of Mc3 is electrically connected to the drain of Mf3.

[0540] The gate of Mc6 is electrically connected to CK, the source of Mc6 is electrically connected to Q_m, and the drain of Mc6 is electrically connected to the drain of Mf3.

[0541] Mc5 is an n-type transistor, and Mc6 is a p-type transistor;

[0542] The first NOR gate includes a first NOR control transistor Mn1, a second NOR control transistor Mn2, a third NOR control transistor Mn3, and a fourth NOR control transistor Mn4;

[0543] The gate of Mn1 is electrically connected to NS, the source of Mn1 is electrically connected to VGH1, and the drain of Mn1 is electrically connected to the source of Mn2.

[0544] The gate of Mn2 is electrically connected to NC, and the drain of Mn2 is electrically connected to the source of Mn3.

[0545] The gate of Mn3 is electrically connected to NC, and the drain of Mn3 is electrically connected to VGL1.

[0546] The gate of Mn4 is electrically connected to NS, the source of Mn4 is electrically connected to G1, and the drain of Mn4 is electrically connected to VGL1.

[0547] Mn1 and Mn2 are p-type transistors, while Mn3 and Mn4 are n-type transistors;

[0548] The first NAND gate includes a first NAND control transistor Ma1, a second NAND control transistor Ma2, a third NAND control transistor Ma3, and a fourth NAND control transistor Ma4;

[0549] The gate of Ma1 is electrically connected to Q, the source of Ma1 is electrically connected to VGH1, and the drain of Ma1 is electrically connected to the drain of Ma2.

[0550] The gate of Ma2 is electrically connected to NS, the source of Ma2 is electrically connected to VGH1, and the drain of Ma2 is electrically connected to QB.

[0551] The gate of Ma3 is electrically connected to Q, the source of Ma3 is electrically connected to QB, and the drain of Ma3 is electrically connected to the source of Ma4.

[0552] The gate of Ma4 is electrically connected to NS, and the drain of Ma4 is electrically connected to VGL1.

[0553] Ma1 and Ma2 are p-type transistors, while Ma3 and Ma4 are n-type transistors;

[0554] The second NAND gate includes the fifth NAND control transistor Ma5, the sixth NAND control transistor Ma6, the seventh NAND control transistor Ma7, and the eighth NAND control transistor Ma8;

[0555] The gate of Ma5 is electrically connected to Trst, the source of Ma5 is electrically connected to VGH1, and the drain of Ma5 is electrically connected to Q.

[0556] The gate of Ma6 is electrically connected to QB, the source of Ma6 is electrically connected to VGH1, and the drain of Ma6 is electrically connected to Q.

[0557] The gate of Ma7 is electrically connected to QB, the source of Ma7 is electrically connected to Q, and the drain of Ma7 is electrically connected to the source of Ma8.

[0558] The gate of Ma8 is electrically connected to Trst, and the drain of Ma8 is electrically connected to VGL1.

[0559] Ma5 and Ma6 are p-type transistors, while Ma7 and Ma8 are n-type transistors;

[0560] The third NAND gate includes the ninth NAND control transistor Ma9, the tenth NAND control transistor Ma10, the eleventh NAND control transistor Ma11, and the twelfth NAND control transistor Ma12;

[0561] The gate of Ma9 is electrically connected to NF, the source of Ma9 is electrically connected to VGH1, and the drain of Ma9 is electrically connected to NS.

[0562] The gate of Ma10 is electrically connected to Trst, the source of Ma10 is electrically connected to VGH1, and the drain of Ma10 is electrically connected to NS.

[0563] The gate of Ma11 is electrically connected to NF, the source of Ma11 is electrically connected to NS, and the drain of Ma11 is electrically connected to the source of Ma12.

[0564] The gate of Ma12 is electrically connected to Trst, and the drain of Ma12 is electrically connected to VGL1.

[0565] Ma9 and Ma10 are p-type transistors, while Ma11 and Ma12 are n-type transistors;

[0566] The first inverter includes a first inverter transistor Mf1 and a second inverter transistor Mf2, and the second inverter includes a third inverter transistor Mf3 and a fourth inverter transistor Mf4;

[0567] The gate of Mf1 is electrically connected to Q_m, the source of Mf1 is electrically connected to VGH1, and the drain of Mf1 is electrically connected to NF.

[0568] The gate of Mf2 is electrically connected to Q_m, the source of Mf2 is electrically connected to NF, and the drain of Mf2 is electrically connected to VGL1.

[0569] The gate of Mf3 is electrically connected to NF, the source of Mf3 is electrically connected to VGH1, and the drain of Mf3 is electrically connected to the source of Mf4.

[0570] The gate of Mf4 is electrically connected to NF, and the drain of Mf4 is electrically connected to VGL1.

[0571] Mf1 and Mf3 are p-type transistors, while Mf2 and Mf4 are n-type transistors;

[0572] The first output inverter includes a first output inverter transistor Ms1 and a second output inverter transistor Ms2;

[0573] The gate of Ms1 is electrically connected to G1, the source of Ms1 is electrically connected to VGH1, and the drain of Ms1 is electrically connected to the source of Ms2.

[0574] The gate of Ms2 is electrically connected to G1, and the drain of Ms2 is electrically connected to VGL1.

[0575] Ms1 is a p-type transistor, and Ms2 is an n-type transistor;

[0576] The second output inverter includes a third output inverter transistor Ms3 and a fourth output inverter transistor Ms4;

[0577] The gate of Ms3 is electrically connected to the drain of Ms1, the source of Ms3 is electrically connected to VGH1, and the drain of Ms3 is electrically connected to the source of Ms4.

[0578] The gate of Ms4 is electrically connected to the drain of Ms1, and the drain of Ms4 is electrically connected to VGL1.

[0579] Ms3 is a p-type transistor, and Ms4 is an n-type transistor;

[0580] The third output inverter includes the fifth output inverter transistor Ms5 and the sixth output inverter transistor Ms6;

[0581] The gate of Ms5 is electrically connected to the drain of Ms3, the source of Ms5 is electrically connected to the second high voltage terminal VGH2, and the drain of Ms5 is electrically connected to the source of Ms6.

[0582] The gate of Ms6 is electrically connected to the drain of Ms3, and the drain of Ms6 is electrically connected to the second low voltage terminal VGL2.

[0583] Ms5 is a p-type transistor, and Ms6 is an n-type transistor.

[0584] In Figure 17, the capacitor labeled C1 is the first capacitor.

[0585] In at least one embodiment of the driving circuit shown in FIG16 of this disclosure, when in operation, the control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn; the first clock signal provided by CK is inverted with the second clock signal provided by CBn, and the third clock signal provided by CB is inverted with the fourth clock signal provided by CKn.

[0586] In at least one embodiment of the driving circuit shown in Figure 16 of this disclosure, when in operation, the input signal provided by GI is the start signal of this unit. The low-level width of the input signal is suggested to be one cycle of the first clock signal provided by CK (the first row can also be the width and phase corresponding to the low level of the third clock signal provided by CB, or the low-level width of the input signal can also be multiple cycles of the first clock signal, and the driving circuit can output multiple pulses).

[0587] In addition, the reset signal provided by the reset terminal Trst is low during power-on, power-off, and blank periods to reset the drive circuit, improve power-on reliability, and enable reset. It is high at other times.

[0588] When the reset signal provided by Trst is a low voltage signal, the potential of Q is a high voltage, and the potential of QB is a low voltage, then Tg1 is turned on, and the enable signal provided by EN can enter NC normally.

[0589] When the signal provided by NS changes from low voltage to high voltage, the potential of QB becomes high voltage, the potential of Q becomes low voltage, and Tg1 is cut off. After that, as long as the potential of the reset signal provided by Trst does not go low again, the state of Tg1 will not switch again, that is, Tg1 remains cut off. The subsequent change of the potential of the enable signal provided by EN will no longer affect the potential of the signal provided by NC, so multi-pulse or pulse width enhancement can be achieved.

[0590] As shown in Figure 18A, in at least one embodiment of the driving circuit shown in Figure 16 of this disclosure, when operating in the high-frequency refresh region, EN provides a low voltage signal, and G2 can output the driving signal normally.

[0591] As shown in Figure 18B, in at least one embodiment of the driving circuit shown in Figure 16 of this disclosure, when operating in the low-frequency refresh region, EN provides a high-voltage signal and G2 continuously outputs a high-voltage signal.

[0592] As shown in Figure 18A, during the reset time period S0, Trst provides a low voltage signal, NAD2 provides a high voltage signal to Q, NS has a high voltage, NAD1 outputs a low voltage signal to QB, Q has a high voltage, and QB has a low voltage, which enables Tg1 to turn on. The enable signal provided by EN can pass through Tg1 to NC, and the potential of NC changes with the potential of EN.

[0593] During the output period S1, NS provides a low voltage signal, NAD1 outputs a high voltage signal to QB, Trst provides a high voltage signal, QB's potential is high, NAD2 provides a low voltage signal to Q, Q's potential is low, and Tg1 is cut off; NC's potential is low, NS provides a low voltage signal, NOR1 outputs a high voltage signal to G1, and G2 outputs a low voltage signal to control the corresponding transistors in the pixel circuit to turn on;

[0594] After the output time period S1, NS provides a high voltage signal, NOR1 provides a low voltage signal to G1, and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn on.

[0595] As shown in Figure 18B, during the reset time period S0, Trst provides a low voltage signal, NAD2 provides a high voltage signal to Q, NS has a high voltage, NAD1 outputs a low voltage signal to QB, Q has a high voltage, QB has a low voltage, which enables Tg1 to turn on, and the enable signal provided by EN can pass through Tg to NC, NC has a low voltage.

[0596] During the output period S1, NS provides a low voltage signal, NAD1 outputs a high voltage signal to QB, Trst provides a high voltage signal, QB's potential is high voltage, NAD2 provides a low voltage signal to Q, Q's potential is low voltage, and Tg1 is cut off; NC's potential is high voltage, NS provides a low voltage signal, NOR1 outputs a low voltage signal to G1, and G2 outputs a high voltage signal.

[0597] During the period following the output time S1, NS provides a high voltage signal, NC maintains a high voltage potential, NOR1 outputs a low voltage signal to G1, and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn off.

[0598] In at least one embodiment of the driving circuit shown in Figure 16 of this disclosure, the low voltage period of the reset signal provided by Trst is adjusted according to the row number of the driving circuit. Alternatively, different reset signals can be connected to each row driving circuit. The reset time is before the signal provided by G2 of the current row driving circuit goes low, but the advance time should not exceed the row blanking time.

[0599] Based on at least one embodiment of the driving circuit shown in FIG16 of this disclosure, the potential of the signal output by the driving circuit can be reversed when an output inverter is added or removed.

[0600] At least one embodiment of the drive circuit shown in Figure 16 of this disclosure can output at least one pulse signal, or output a high voltage signal; when powered on, powered off, or during a blank period, the potential of the reset signal provided by Trst can be set to a low voltage to control the enable signal provided by EN to be transmitted to NC through Tg1, thereby controlling G1 and G2 to output corresponding signals.

[0601] The drive signal provided by at least one embodiment of the drive circuit shown in FIG16 of this disclosure can be used to control T5-T9 in FIG40.

[0602] As shown in Figure 19, based on at least one embodiment of the driving circuit shown in Figure 14,

[0603] The latching circuit includes a first NAND gate NAD1, a second NAND gate NAD2, and a first transmission gate Tg1;

[0604] The first input terminal of the first NAND gate NAD1 is electrically connected to the sixth node NS, the second input terminal of the first NAND gate NAD1 is electrically connected to the first node Q, and the output terminal of the first NAND gate NAD1 is electrically connected to the second node QB.

[0605] The first input terminal of the second NAND gate NAD2 is electrically connected to the second node QB, the second input terminal of the second NAND gate NAD2 is electrically connected to the second reset terminal Trst2, and the output terminal of the second NAND gate NAD2 is electrically connected to the first node Q.

[0606] The input terminal of the first transmission gate Tg1 is electrically connected to the enable terminal EN, the output terminal of the first transmission gate Tg1 is electrically connected to the third node NC, the positive phase control terminal of the first transmission gate Tg1 is electrically connected to the first node Q, and the negative phase control terminal of the first transmission gate is electrically connected to the second node QB.

[0607] The input circuit includes a second transmission gate Tg2, a first inverter INV1, a third transmission gate Tg3, and a second inverter INV2;

[0608] The control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn;

[0609] The input terminal of the second transmission gate Tg2 is electrically connected to the input signal terminal GI, the output terminal of the second transmission gate Tg2 is electrically connected to the fourth node Q_m, the positive phase control terminal of the second transmission gate Tg2 is electrically connected to the fourth clock signal terminal CKn, and the inverting phase control terminal of the second transmission gate Tg2 is electrically connected to the third clock signal terminal CB.

[0610] The input terminal of the third transmission gate Tg3 is electrically connected to the fourth node Q_m, the output terminal of the third transmission gate Tg3 is electrically connected to the output terminal of the second inverter INV2, the positive phase control terminal of the third transmission gate Tg3 is electrically connected to the second clock signal terminal CBn, and the negative phase control terminal of the third transmission gate Tg3 is electrically connected to the first clock signal terminal CK.

[0611] The input terminal of the first inverter INV1 is electrically connected to the fourth node Q_m, and the output terminal of the first inverter INV1 is electrically connected to the fifth node NF.

[0612] The input terminal of the second inverter INV2 is electrically connected to the fifth node NF;

[0613] The control circuit includes a third NAND gate, NAD3;

[0614] The first input terminal of the third NAND gate NAD3 is electrically connected to the first reset terminal Trst1, the second input terminal of the third NAND gate NAD3 is electrically connected to the fifth node NF, and the output terminal of the third NAND gate NAD3 is electrically connected to the sixth node NS.

[0615] The signal output circuit includes a first NOR gate (NOR1).

[0616] The first input terminal of the first NOR gate NOR1 is electrically connected to the sixth node NS, the second input terminal of the first NOR gate NOR1 is electrically connected to the third node NC, and the output terminal of the first NOR gate NOR1 is electrically connected to the first output terminal G1.

[0617] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, and a third output inverter IV3;

[0618] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, and the output terminal of IV3 is electrically connected to the second output terminal G2.

[0619] In at least one embodiment of the driving circuit shown in Figure 19, the first reset terminal and the second reset terminal are different reset terminals.

[0620] Figures 20A and 20B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 19.

[0621] Figure 20A is the timing diagram of the driving circuit shown in Figure 19 in the high-frequency refresh region;

[0622] Figure 20B is a timing diagram of the driving circuit shown in Figure 19 in the low-frequency refresh region.

[0623] The difference between at least one embodiment of the driving circuit shown in Figure 19 and at least one embodiment of the driving circuit shown in Figure 16 is that:

[0624] The first input terminal of NAD3 is electrically connected to the first reset terminal Trst1, and the second input terminal of NAD2 is electrically connected to the second reset terminal Trst2.

[0625] The waveform of the first reset signal provided by Trst1 can be the same as the waveform of the reset signal provided by Trst.

[0626] The second reset signal provided by Trst2 can remain at a low voltage for a longer period than the first reset signal provided by Trst1 remains at a low voltage for a longer period. The reset time is adjusted according to the number of pixel rows corresponding to the driving circuit.

[0627] The drive signal provided by at least one embodiment of the drive circuit shown in FIG19 of this disclosure can be used to control T5-T9 in FIG40.

[0628] As shown in Figure 20A, at least one embodiment of the driving circuit shown in Figure 19 of this disclosure outputs a low voltage signal EN during high-frequency refresh.

[0629] During the reset period S0, Trst2 provides a low voltage signal, NAD2 provides a high voltage signal to Q, NS is at a high voltage, Q is at a high voltage, NAD1 provides a low voltage signal to QB, QB is at a low voltage, Tg1 is turned on, so that the enable signal provided by EN can be transmitted to NC through Tg1, EN provides a low voltage signal, and NC outputs a low voltage signal.

[0630] During the output time period S1, NS provides a low voltage signal, NAD1 outputs a high voltage signal to QB, Trst2 provides a high voltage signal, QB's potential is high, NAD2 outputs a low voltage signal to Q, making Q's potential low, and Tg1 is cut off; NC provides a low voltage signal, NS provides a low voltage signal, NOR1 provides a high voltage signal to G1, and G2 outputs a low voltage signal to control the corresponding transistors in the pixel circuit to turn on;

[0631] After the output time period S1, NS provides a high voltage signal, NC provides a low voltage signal, NOR1 outputs a low voltage signal to G1, and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn on.

[0632] As shown in Figure 20B, at least one embodiment of the driving circuit shown in Figure 19 of this disclosure outputs a high voltage signal EN during high-frequency refresh.

[0633] During the reset period S0, Trst2 provides a low voltage signal, NAD2 provides a high voltage signal to Q, NS is at a high voltage, Q is at a high voltage, NAD1 provides a low voltage signal to QB, QB is at a low voltage, Tg1 is turned on, so that the enable signal provided by EN can be transmitted to NC through Tg1, EN provides a high voltage signal, and NC outputs a high voltage signal.

[0634] During the output time period S1, NS provides a low voltage signal, NAD1 outputs a high voltage signal to QB, Trst2 provides a high voltage signal, QB's potential is high, NAD2 outputs a low voltage signal to Q, making Q's potential low, and Tg1 is cut off; NC provides a high voltage signal, NS provides a low voltage signal, NOR1 provides a low voltage signal to G1, and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn off;

[0635] After the output time period S1, NS provides a high voltage signal, NC provides a high voltage signal, NOR1 outputs a low voltage signal to G1, and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn off.

[0636] As shown in Figure 21, based on at least one embodiment of the driving circuit shown in Figure 15,

[0637] The latching circuit includes a first NAND gate NAD1, a second NAND gate NAD2, and a first transmission gate Tg1;

[0638] The first input terminal of the first NAND gate NAD1 is electrically connected to the sixth node NS, the second input terminal of the first NAND gate NAD1 is electrically connected to the first node Q, and the output terminal of the first NAND gate NAD1 is electrically connected to the second node QB.

[0639] The first input terminal of the second NAND gate NAD2 is electrically connected to the second node QB, the second input terminal of the second NAND gate NAD2 is electrically connected to the reset terminal Trst, and the output terminal of the second NAND gate NAD2 is electrically connected to the first node Q.

[0640] The input terminal of the first transmission gate Tg1 is electrically connected to the enable terminal EN, the output terminal of the first transmission gate Tg1 is electrically connected to the third node NC, the positive phase control terminal of the first transmission gate Tg1 is electrically connected to the first node Q, and the negative phase control terminal of the first transmission gate is electrically connected to the second node QB.

[0641] The input circuit includes a second transmission gate Tg2, a first inverter INV1, a third transmission gate Tg3, and a second inverter INV2;

[0642] The control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn;

[0643] The input terminal of the second transmission gate Tg2 is electrically connected to the input signal terminal GI, the output terminal of the second transmission gate Tg2 is electrically connected to the fourth node Q_m, the positive phase control terminal of the second transmission gate Tg2 is electrically connected to the fourth clock signal terminal CKn, and the inverting phase control terminal of the second transmission gate Tg2 is electrically connected to the third clock signal terminal CB.

[0644] The input terminal of the third transmission gate Tg3 is electrically connected to the fourth node Q_m, the output terminal of the third transmission gate Tg3 is electrically connected to the output terminal of the second inverter INV2, the positive phase control terminal of the third transmission gate Tg3 is electrically connected to the second clock signal terminal CBn, and the negative phase control terminal of the third transmission gate Tg3 is electrically connected to the first clock signal terminal CK.

[0645] The input terminal of the first inverter INV1 is electrically connected to the fourth node Q_m, and the output terminal of the first inverter INV1 is electrically connected to the fifth node NF.

[0646] The input terminal of the second inverter INV2 is electrically connected to the fifth node NF;

[0647] The control circuit includes a third NAND gate, NAD3;

[0648] The first input terminal of the third NAND gate NAD3 is electrically connected to the reset terminal Trst, the second input terminal of the third NAND gate NAD3 is electrically connected to the fifth node NF, and the output terminal of the third NAND gate NAD3 is electrically connected to the sixth node NS.

[0649] The signal output circuit includes a first NOR gate (NOR1).

[0650] The first input terminal of the first NOR gate NOR1 is electrically connected to the first clock signal terminal CK, the second input terminal of the first NOR gate NOR1 is electrically connected to the sixth node NS, the third input terminal of the first NOR gate NOR1 is electrically connected to the third node NC, and the output terminal of the first NOR gate NOR1 is electrically connected to the first output terminal G1.

[0651] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, and a third output inverter IV3;

[0652] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, and the output terminal of IV3 is electrically connected to the second output terminal G2.

[0653] In at least one embodiment of the driving circuit shown in Figure 21, the first reset terminal and the second reset terminal are the same reset terminal.

[0654] In at least one embodiment of the driving circuit shown in Figure 21, the output control clock signal terminal is the first clock signal terminal CK.

[0655] At least one embodiment of the drive circuit shown in FIG21 of this disclosure can be used to control T1 and T2 in FIG40.

[0656] Figure 22 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure.

[0657] Figures 23A and 23B are timing diagrams of at least one embodiment of the drive circuit shown in Figure 21.

[0658] As shown in Figure 22, based on at least one embodiment of the driving circuit shown in Figure 21,

[0659] The first transmission gate includes a first transmission transistor Mc1 and a second transmission transistor Mc2;

[0660] The gate of Mc1 is electrically connected to Q, the source of Mc1 is electrically connected to EN, and the drain of Mc1 is electrically connected to NC.

[0661] Mc2’s gate is electrically connected to QB, Mc2’s source is electrically connected to EN, and Mc2’s drain is electrically connected to NC.

[0662] Mc1 is an n-type transistor, and Mc2 is a p-type transistor;

[0663] The second transmission gate includes a third transmission transistor Mc3 and a fourth transmission transistor Mc4;

[0664] The gate of Mc3 is electrically connected to CKn, the source of Mc3 is electrically connected to GI, and the drain of Mc3 is electrically connected to Q_m.

[0665] The gate of Mc4 is electrically connected to CB, the source of Mc4 is electrically connected to GI, and the drain of Mc4 is electrically connected to Q_m.

[0666] Mc3 is an n-type transistor, and Mc4 is a p-type transistor;

[0667] The third transmission gate includes the fifth transmission transistor Mc5 and the sixth transmission transistor Mc6;

[0668] The gate of Mc5 is electrically connected to CBn, the source of Mc5 is electrically connected to Q_m, and the drain of Mc5 is electrically connected to the drain of Mf3.

[0669] The gate of Mc6 is electrically connected to CK, the source of Mc6 is electrically connected to Q_m, and the drain of Mc6 is electrically connected to the drain of Mf3.

[0670] Mc5 is an n-type transistor, and Mc6 is a p-type transistor;

[0671] The first NAND gate includes a first NAND control transistor Ma1, a second NAND control transistor Ma2, a third NAND control transistor Ma3, and a fourth NAND control transistor Ma4;

[0672] The gate of Ma1 is electrically connected to Q, the source of Ma1 is electrically connected to VGH1, and the drain of Ma1 is electrically connected to the drain of Ma2.

[0673] The gate of Ma2 is electrically connected to NS, the source of Ma2 is electrically connected to VGH1, and the drain of Ma2 is electrically connected to QB.

[0674] The gate of Ma3 is electrically connected to Q, the source of Ma3 is electrically connected to QB, and the drain of Ma3 is electrically connected to the source of Ma4.

[0675] The gate of Ma4 is electrically connected to NS, and the drain of Ma4 is electrically connected to VGL1.

[0676] Ma1 and Ma2 are p-type transistors, while Ma3 and Ma4 are n-type transistors;

[0677] The second NAND gate includes the fifth NAND control transistor Ma5, the sixth NAND control transistor Ma6, the seventh NAND control transistor Ma7, and the eighth NAND control transistor Ma8;

[0678] The gate of Ma5 is electrically connected to Trst, the source of Ma5 is electrically connected to VGH1, and the drain of Ma5 is electrically connected to Q.

[0679] The gate of Ma6 is electrically connected to QB, the source of Ma6 is electrically connected to VGH1, and the drain of Ma6 is electrically connected to Q.

[0680] The gate of Ma7 is electrically connected to QB, the source of Ma7 is electrically connected to Q, and the drain of Ma7 is electrically connected to the source of Ma8.

[0681] The gate of Ma8 is electrically connected to Trst, and the drain of Ma8 is electrically connected to VGL1.

[0682] Ma5 and Ma6 are p-type transistors, while Ma7 and Ma8 are n-type transistors;

[0683] The third NAND gate includes the ninth NAND control transistor Ma9, the tenth NAND control transistor Ma10, the eleventh NAND control transistor Ma11, and the twelfth NAND control transistor Ma12;

[0684] The gate of Ma9 is electrically connected to NF, the source of Ma9 is electrically connected to VGH1, and the drain of Ma9 is electrically connected to NS.

[0685] The gate of Ma10 is electrically connected to Trst, the source of Ma10 is electrically connected to VGH1, and the drain of Ma10 is electrically connected to NS.

[0686] The gate of Ma11 is electrically connected to NF, the source of Ma11 is electrically connected to NS, and the drain of Ma11 is electrically connected to the source of Ma12.

[0687] The gate of Ma12 is electrically connected to Trst, and the drain of Ma12 is electrically connected to VGL1.

[0688] Ma9 and Ma10 are p-type transistors, while Ma11 and Ma12 are n-type transistors;

[0689] The first NOR gate includes a first NOR control transistor Mn1, a second NOR control transistor Mn2, a third NOR control transistor Mn3, a fourth NOR control transistor Mn4, a fifth NOR control transistor Mn5, and a sixth NOR control transistor Mn6.

[0690] The gate of Mn1 is electrically connected to CK, the source of Mn1 is electrically connected to VGH1, and the drain of Mn1 is electrically connected to the source of Mn2.

[0691] The gate of Mn2 is electrically connected to NC, and the drain of Mn2 is electrically connected to the source of Mn3.

[0692] The gate of Ma3 is electrically connected to NS, and the drain of Mn3 is electrically connected to the source of Mn4.

[0693] The gate of Mn4 is electrically connected to NS, and the drain of Mn4 is electrically connected to VGL1.

[0694] The gate of Mn5 is electrically connected to NC, the source of Mn5 is electrically connected to G1, and the drain of Mn5 is electrically connected to VGL1.

[0695] The gate of Mn6 is electrically connected to CK, the source of Mn5 is electrically connected to G1, and the drain of Mn5 is electrically connected to VGL1.

[0696] Mn1, Mn2, and Mn3 are p-type transistors, while Mn4, Mn5, and Mn6 are n-type transistors.

[0697] The first inverter includes a first inverter transistor Mf1 and a second inverter transistor Mf2, and the second inverter includes a third inverter transistor Mf3 and a fourth inverter transistor Mf4;

[0698] The gate of Mf1 is electrically connected to Q_m, the source of Mf1 is electrically connected to VGH1, and the drain of Mf1 is electrically connected to NF.

[0699] The gate of Mf2 is electrically connected to Q_m, the source of Mf2 is electrically connected to NF, and the drain of Mf2 is electrically connected to VGL1.

[0700] The gate of Mf3 is electrically connected to NF, the source of Mf3 is electrically connected to VGH1, and the drain of Mf3 is electrically connected to the source of Mf4.

[0701] The gate of Mf4 is electrically connected to NF, and the drain of Mf4 is electrically connected to VGL1.

[0702] Mf1 and Mf3 are p-type transistors, while Mf2 and Mf4 are n-type transistors;

[0703] The first output inverter includes a first output inverter transistor Ms1 and a second output inverter transistor Ms2;

[0704] The gate of Ms1 is electrically connected to G1, the source of Ms1 is electrically connected to VGH1, and the drain of Ms1 is electrically connected to the source of Ms2.

[0705] The gate of Ms2 is electrically connected to G1, and the drain of Ms2 is electrically connected to VGL1.

[0706] Ms1 is a p-type transistor, and Ms2 is an n-type transistor;

[0707] The second output inverter includes a third output inverter transistor Ms3 and a fourth output inverter transistor Ms4;

[0708] The gate of Ms3 is electrically connected to the drain of Ms1, the source of Ms3 is electrically connected to VGH1, and the drain of Ms3 is electrically connected to the source of Ms4.

[0709] The gate of Ms4 is electrically connected to the drain of Ms1, and the drain of Ms4 is electrically connected to VGL1.

[0710] Ms3 is a p-type transistor, and Ms4 is an n-type transistor;

[0711] The third output inverter includes the fifth output inverter transistor Ms5 and the sixth output inverter transistor Ms6;

[0712] The gate of Ms5 is electrically connected to the drain of Ms3, the source of Ms5 is electrically connected to the second high voltage terminal VGH2, and the drain of Ms5 is electrically connected to the source of Ms6.

[0713] The gate of Ms6 is electrically connected to the drain of Ms3, and the drain of Ms6 is electrically connected to the second low voltage terminal VGL2.

[0714] Ms5 is a p-type transistor, and Ms6 is an n-type transistor.

[0715] In Figure 22, the capacitor labeled C1 is the first capacitor.

[0716] In at least one embodiment of the drive circuit shown in Figure 21 of this disclosure, when the reset signal provided by Trst is a low voltage signal, the potential of Q is a high voltage, and the potential of QB is a low voltage, then Tg1 is turned on, and the enable signal provided by EN can enter NC normally.

[0717] When the signal provided by NS changes from high voltage to low voltage, the potential of QB becomes high voltage, the potential of Q becomes low voltage, and Tg1 is cut off.

[0718] At least one embodiment of the driving circuit shown in FIG21 of this disclosure is adapted to output one or more pulses, or output a high voltage signal, when in operation.

[0719] In at least one embodiment of the driving circuit shown in FIG21 of this disclosure, the control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn; the first clock signal provided by CK is inverted with the second clock signal provided by CBn, and the third clock signal provided by CB is inverted with the fourth clock signal provided by CKn;

[0720] NOR1 includes three input terminals. The first input terminal of NOR1 is electrically connected to CK, the second input terminal of NOR1 is electrically connected to NS, and the third input terminal of NOR1 is electrically connected to NC. G1 can only output a low voltage signal when CK, NS, and NC all output low voltage signals, thereby realizing the low level width of the second output signal provided by G2 and the low level width of the first clock signal provided by CK.

[0721] Figure 23A is a timing diagram of at least one embodiment of the driving circuit shown in Figure 21 in the high-frequency refresh region, and Figure 23B is a timing diagram of at least one embodiment of the driving circuit shown in Figure 21 in the low-frequency refresh region.

[0722] Figure 23C is a simulation timing diagram of at least one embodiment of the drive circuit shown in Figure 21.

[0723] As shown in Figure 23A, in at least one embodiment of the driving circuit shown in Figure 21 of this disclosure, during high-frequency refresh, EN provides a low-voltage signal.

[0724] During the reset period S0, Trst provides a low voltage signal, NAD2 outputs a high voltage signal to Q, Q's potential is high voltage, NS provides a high voltage signal, NAD1 provides a low voltage signal to QB, QB's potential is low voltage, Tg1 is turned on, and the low voltage signal provided by EN is transmitted to NC through Tg1.

[0725] Between the reset time period S0 and the output time period S1, the signal provided by NS changes from a high voltage signal to a low voltage signal. NAD1 outputs a high voltage signal to QB, and QB's potential is high voltage. Trst provides a high voltage signal. NAD2 outputs a low voltage signal to Q, and Q's potential is low voltage. Tg1 is cut off.

[0726] Between the reset time period S0 and the output time period S1, when NS provides a low voltage signal and CK outputs a high voltage signal, NOR1 outputs a low voltage signal to G1 and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn off.

[0727] During the output time period S1, CK outputs a low voltage signal, NS provides a low voltage signal, NC provides a low voltage signal, NOR outputs a high voltage signal to G1, and G2 outputs a low voltage signal to control the corresponding transistors in the pixel circuit to turn on.

[0728] After the output time period S1, NS provides a high voltage signal, NOR outputs a low voltage signal to G1, and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn off.

[0729] As shown in Figure 23B, in at least one embodiment of the driving circuit shown in Figure 21 of this disclosure, during low-frequency refresh, EN provides a high-voltage signal.

[0730] During the reset period S0, Trst provides a low voltage signal, NAD2 outputs a high voltage signal to Q, Q's potential is high voltage, NS provides a high voltage signal, NAD1 provides a low voltage signal to QB, QB's potential is low voltage, Tg1 is turned on, and the high voltage signal provided by EN is transmitted to NC through Tg1.

[0731] After the reset period S0, when the signal provided by NS changes from a high voltage signal to a low voltage signal, NAD1 outputs a high voltage signal to QB, QB's potential is high voltage, Trst provides a high voltage signal, NAD2 outputs a low voltage signal to Q, Q's potential is low voltage, and Tg1 is cut off.

[0732] During the output period S1, NC outputs a high voltage signal, NOR1 outputs a low voltage signal to G1, and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn off.

[0733] The differences between at least one embodiment of the driving circuit shown in Figure 23D and at least one embodiment of the driving circuit shown in Figure 21 are as follows:

[0734] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, a third output inverter IV3, and a fourth output inverter IV4;

[0735] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, the output terminal of IV3 is electrically connected to the input terminal of IV4, and the output terminal of IV4 is electrically connected to the second output terminal G2.

[0736] At least one embodiment of the driving circuit shown in Figure 23D can be used to control T1 and T2 in the pixel circuit shown in Figure 40.

[0737] As shown in Figure 24, based on at least one embodiment of the driving circuit shown in Figure 15,

[0738] The latching circuit includes a first NAND gate NAD1, a second NAND gate NAD2, and a first transmission gate Tg1;

[0739] The first input terminal of the first NAND gate NAD1 is electrically connected to the sixth node NS, the second input terminal of the first NAND gate NAD1 is electrically connected to the first node Q, and the output terminal of the first NAND gate NAD1 is electrically connected to the second node QB.

[0740] The first input terminal of the second NAND gate NAD2 is electrically connected to the second node QB, the second input terminal of the second NAND gate NAD2 is electrically connected to the second reset terminal Trst2, and the output terminal of the second NAND gate NAD2 is electrically connected to the first node Q.

[0741] The input terminal of the first transmission gate Tg1 is electrically connected to the enable terminal EN, the output terminal of the first transmission gate Tg1 is electrically connected to the third node NC, the positive phase control terminal of the first transmission gate Tg1 is electrically connected to the first node Q, and the negative phase control terminal of the first transmission gate is electrically connected to the second node QB.

[0742] The input circuit includes a second transmission gate Tg2, a first inverter INV1, a third transmission gate Tg3, and a second inverter INV2;

[0743] The control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn;

[0744] The input terminal of the second transmission gate Tg2 is electrically connected to the input signal terminal GI, the output terminal of the second transmission gate Tg2 is electrically connected to the fourth node Q_m, the positive phase control terminal of the second transmission gate Tg2 is electrically connected to the fourth clock signal terminal CKn, and the inverting phase control terminal of the second transmission gate Tg2 is electrically connected to the third clock signal terminal CB.

[0745] The input terminal of the third transmission gate Tg3 is electrically connected to the fourth node Q_m, the output terminal of the third transmission gate Tg3 is electrically connected to the output terminal of the second inverter INV2, the positive phase control terminal of the third transmission gate Tg3 is electrically connected to the second clock signal terminal CBn, and the negative phase control terminal of the third transmission gate Tg3 is electrically connected to the first clock signal terminal CK.

[0746] The input terminal of the first inverter INV1 is electrically connected to the fourth node Q_m, and the output terminal of the first inverter INV1 is electrically connected to the fifth node NF.

[0747] The input terminal of the second inverter INV2 is electrically connected to the fifth node NF;

[0748] The control circuit includes a third NAND gate, NAD3;

[0749] The first input terminal of the third NAND gate NAD3 is electrically connected to the first reset terminal Trst1, the second input terminal of the third NAND gate NAD3 is electrically connected to the fifth node NF, and the output terminal of the third NAND gate NAD3 is electrically connected to the sixth node NS.

[0750] The signal output circuit includes a first NOR gate (NOR1).

[0751] The first input terminal of the first NOR gate NOR1 is electrically connected to the first clock signal terminal CK, the second input terminal of the first NOR gate NOR1 is electrically connected to the sixth node NS, the third input terminal of the first NOR gate NOR1 is electrically connected to the third node NC, and the output terminal of the first NOR gate NOR1 is electrically connected to the first output terminal G1.

[0752] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, and a third output inverter IV3;

[0753] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, and the output terminal of IV3 is electrically connected to the second output terminal G2.

[0754] In at least one embodiment of the driving circuit shown in Figure 24, the first reset terminal and the second reset terminal are different reset terminals.

[0755] In at least one embodiment of the driving circuit shown in Figure 24, the output control clock signal terminal is the first clock signal terminal CK.

[0756] At least one embodiment of the driving circuit shown in Figure 24 can be used to control T5-T9 in the pixel circuit shown in Figure 40.

[0757] Figures 25A and 25B are timing diagrams of at least one embodiment of the drive circuit shown in Figure 24.

[0758] In at least one embodiment of the driving circuit shown in FIG24 of this disclosure, the first input terminal of NAD3 is electrically connected to the first reset terminal Trst1, and the second input terminal of NAD2 is electrically connected to the second reset terminal Trst2. The reset time is adjusted according to the number of pixel rows corresponding to the driving circuit.

[0759] The waveform of the first reset signal provided by Trst1 can be the same as the waveform of the reset signal provided by Trst; the low-level duration of the second reset signal provided by Trst2 is longer than the low-level duration of the first reset signal provided by Trst1.

[0760] The time when the potential of the second reset signal provided by Trst2 goes low can be adjusted according to the number of rows of the driving circuit. Alternatively, each row of the driving circuit can be connected to a different second reset signal, or groups (the number of driving circuits in each group should not exceed the number of pixel charging rows corresponding to the blanking time) can be connected to different second reset signals. The reset time is before the potential of the second output signal provided by the second output terminal G2 of the current row goes low, but the advance time should not exceed the row blanking time.

[0761] Figure 25A is a timing diagram of at least one embodiment of the driving circuit shown in Figure 24 in the high-frequency refresh region, and Figure 25B is a timing diagram of at least one embodiment of the driving circuit shown in Figure 24 in the low-frequency refresh region.

[0762] As shown in Figure 25A, in at least one embodiment of the driving circuit shown in Figure 24 of this disclosure, when operating, EN outputs a low voltage signal during high-frequency refresh;

[0763] During the reset period S0, Trst2 provides a low voltage signal, NAD2 outputs a high voltage signal to Q, Q has a high voltage potential, NS outputs a high voltage signal, NAD1 outputs a low voltage signal to QB, Tg1 starts, the low voltage signal provided by EN can be transmitted to NC through Tg1, NC outputs a low voltage signal.

[0764] Between the reset time period S0 and the output time period S1, when the signal provided by NS changes from a high voltage signal to a low voltage signal, NAD1 outputs a high voltage signal to QB, and the potential of QB is high voltage. Trst2 provides a high voltage signal, and NAD2 outputs a low voltage signal to Q, and the potential of Q is low voltage. Tg1 is cut off.

[0765] Before the output time period S1, when CK outputs a high voltage signal, NOR1 outputs a low voltage signal to G1, and G2 outputs a high voltage signal.

[0766] During the output time period S1, CK outputs a low voltage signal, NS provides a low voltage signal, NC outputs a low voltage signal, NOR1 outputs a high voltage signal to G1, and G2 outputs a low voltage signal to control the corresponding transistors in the pixel circuit to turn on.

[0767] After the output time period S1, when CK provides a high voltage signal and / or NS outputs a high voltage signal, NOR1 outputs a low voltage signal to G1, and G2 outputs a high voltage signal.

[0768] As shown in Figure 25B, in at least one embodiment of the driving circuit shown in Figure 24 of this disclosure, when operating, EN outputs a high voltage signal during low-frequency refresh;

[0769] During the reset period S0, Trst2 provides a low voltage signal, NAD2 outputs a high voltage signal to Q, Q has a high voltage potential, NS outputs a high voltage signal, NAD1 outputs a low voltage signal to QB, Tg1 starts, the high voltage signal provided by EN can be transmitted to NC through Tg1, NC outputs a high voltage signal.

[0770] After the reset period S0, when the signal provided by NS changes from a high voltage signal to a low voltage signal, NAD1 outputs a high voltage signal to QB, and the potential of QB is high voltage. Trst2 provides a high voltage signal, and NAD2 outputs a low voltage signal to Q, and the potential of Q is low voltage. Tg1 is cut off.

[0771] During the output period S1, NC outputs a high voltage signal, NOR1 outputs a low voltage signal to G1, and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn off.

[0772] In at least one embodiment of this disclosure, the latch circuit includes a first NOR gate, a second NOR gate, and a first transmission gate;

[0773] The first input terminal of the first NOR gate is electrically connected to the sixth node, the second input terminal of the first NOR gate is electrically connected to the second node, and the output terminal of the first NOR gate is electrically connected to the first node.

[0774] The first input terminal of the second NOR gate is electrically connected to the first node, the second input terminal of the second NOR gate is electrically connected to the second reset terminal, and the output terminal of the second NOR gate is electrically connected to the second node.

[0775] The input terminal of the first transmission gate is electrically connected to the enable terminal, the output terminal of the first transmission gate is electrically connected to the third node, the positive phase control terminal of the first transmission gate is electrically connected to the first node, and the negative phase control terminal of the first transmission gate is electrically connected to the second node.

[0776] In a specific implementation, the latching circuit may include a first NOR gate, a second NOR gate, and a first transmission gate; the first NOR gate performs a NOR operation on the signal provided by the sixth node and the signal provided by the second node to obtain the signal provided by the first node; the second NOR gate performs a NOR operation on the signal provided by the first node and the second reset signal provided by the second reset terminal to obtain the signal provided by the second node; under the control of the signal provided by the first node and the signal provided by the second node, the first transmission gate transmits the enable signal provided by the enable terminal to the second node.

[0777] In at least one embodiment of this disclosure, the input circuit includes a second transmission gate, a third transmission gate, a first inverter, and a second inverter; the control clock signal terminal includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal.

[0778] The input terminal of the second transmission gate is electrically connected to the input signal terminal, the output terminal of the second transmission gate is electrically connected to the fourth node, the positive phase control terminal of the second transmission gate is electrically connected to the fourth clock signal terminal, and the negative phase control terminal of the second transmission gate is electrically connected to the third clock signal terminal.

[0779] The input terminal of the third transmission gate is electrically connected to the fourth node, the output terminal of the third transmission gate is electrically connected to the output terminal of the second inverter, the non-inverting control terminal of the third transmission gate is electrically connected to the second clock signal terminal, and the inverting control terminal of the third transmission gate is electrically connected to the first clock signal terminal.

[0780] The input terminal of the first inverter is electrically connected to the fourth node, and the output terminal of the first inverter is electrically connected to the fifth node;

[0781] The input terminal of the second inverter is electrically connected to the fifth node.

[0782] In a specific implementation, the input circuit includes a second transmission gate, a third transmission gate, a first inverter, and a second inverter; under the control of a fourth clock signal and a third clock signal, the second transmission gate transmits the input signal provided by the input signal terminal to the fourth node, and under the control of the second clock signal and the first clock signal, the third transmission gate transmits the signal provided by the fourth node to the output terminal of the second inverter.

[0783] In at least one embodiment of this disclosure, the control circuit includes a third NOR gate;

[0784] The first input terminal of the third NOR gate is electrically connected to the first reset terminal, the second input terminal of the third NOR gate is electrically connected to the fifth node, and the output terminal of the third NAND gate is electrically connected to the sixth node.

[0785] In a specific implementation, the control circuit may include a third NOR gate, which performs a NOR operation on the first reset signal provided by the first reset terminal and the signal provided by the fifth node to obtain the signal provided by the sixth node.

[0786] Optionally, the signal output circuit includes a first NAND gate;

[0787] The first input terminal of the first NAND gate is electrically connected to the sixth node, the second input terminal of the first NAND gate is electrically connected to the third node, and the output terminal of the first NAND gate is electrically connected to the first output terminal.

[0788] In a specific implementation, the signal output circuit may include a first NAND gate, which performs a NAND operation on the signal provided by the sixth node and the signal provided by the third node to obtain a first output signal.

[0789] Optionally, the signal output circuit includes a first NAND gate;

[0790] The first input terminal of the first NAND gate is electrically connected to the output control clock signal terminal, the second input terminal of the first NAND gate is electrically connected to the sixth node, the third input terminal of the first NAND gate is electrically connected to the third node, and the output terminal of the first NAND gate is electrically connected to the first output terminal.

[0791] In a specific implementation, the signal output circuit may include a first NAND gate, which performs a NAND operation on the output control clock signal provided by the output control clock signal terminal and the signal provided by the sixth node to obtain a first output signal.

[0792] As shown in Figure 26, based on at least one embodiment of the driving circuit shown in Figure 14,

[0793] The latching circuit includes a first NOR gate NOR1, a second NOR gate NOR2, and a first transmission gate Tg1;

[0794] The first input terminal of the first NOR gate NOR1 is electrically connected to the sixth node NS, the second input terminal of the first NOR gate NOR1 is electrically connected to the second node QB, and the output terminal of the first NOR gate NOR1 is electrically connected to the first node Q.

[0795] The first input terminal of the second NOR gate NOR2 is electrically connected to the first node Q, the second input terminal of the second NOR gate NOR2 is electrically connected to the reset terminal Trst, and the output terminal of the second NOR gate NOR2 is electrically connected to the second node QB.

[0796] The input terminal of the first transmission gate Tg1 is electrically connected to the enable terminal EN, the output terminal of the first transmission gate Tg1 is electrically connected to the third node NC, the positive phase control terminal of the first transmission gate Tg1 is electrically connected to the first node Q, and the negative phase control terminal of the first transmission gate Tg1 is electrically connected to the second node QB.

[0797] The input circuit includes a second transmission gate Tg2, a third transmission gate Tg3, a first inverter INV1, and a second inverter INV2; the control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn.

[0798] The input terminal of the second transmission gate Tg2 is electrically connected to the input signal terminal GI, the output terminal of the second transmission gate Tg2 is electrically connected to the fourth node Q_m, the positive phase control terminal of the second transmission gate Tg2 is electrically connected to the fourth clock signal terminal CKn, and the inverting phase control terminal of the second transmission gate Tg2 is electrically connected to the third clock signal terminal CB.

[0799] The input terminal of the third transmission gate Tg3 is electrically connected to the fourth node Q_m, the output terminal of the third transmission gate Tg3 is electrically connected to the output terminal of the second inverter INV2, the positive phase control terminal of the third transmission gate Tg3 is electrically connected to the second clock signal terminal CBn, and the negative phase control terminal of the third transmission gate Tg3 is electrically connected to the first clock signal terminal CK.

[0800] The input terminal of the first inverter INV1 is electrically connected to the fourth node Q_m, and the output terminal of the first inverter INV1 is electrically connected to the fifth node NF.

[0801] The input terminal of the second inverter INV2 is electrically connected to the fifth node NF;

[0802] The control circuit includes a third NOR gate (NOR3);

[0803] The first input terminal of the third NOR gate NOR3 is electrically connected to the reset terminal Trst, the second input terminal of the third NOR gate NOR3 is electrically connected to the fifth node NF, and the output terminal of the third NOR gate is electrically connected to the sixth node NS.

[0804] The signal output circuit includes a first NAND gate NAD1;

[0805] The first input terminal of the first NAND gate NAD1 is electrically connected to the sixth node NS, the second input terminal of the first NAND gate NAD1 is electrically connected to the third node NC, and the output terminal of the first NAND gate NAD1 is electrically connected to the first output terminal G1.

[0806] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, and a third output inverter IV3;

[0807] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, and the output terminal of IV3 is electrically connected to the second output terminal G2.

[0808] In at least one embodiment of the driving circuit shown in Figure 26, the first reset terminal and the second reset terminal are the same reset terminal.

[0809] At least one embodiment of the driving circuit shown in Figure 26 can be used to control T1 and T2 in the pixel circuit shown in Figure 40.

[0810] Figure 27 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.

[0811] Figures 28A and 28B are timing diagrams of at least one embodiment of the drive circuit shown in Figure 26.

[0812] As shown in Figure 28A, in at least one embodiment of the driving circuit shown in Figure 26, when performing high-frequency refresh, EN outputs a high-voltage signal;

[0813] During the reset period S0, Trst outputs a high voltage signal, NOR2 outputs a low voltage signal to QB, QB's potential is low voltage, NS outputs a low voltage signal, NOR1 outputs a high voltage signal to Q, Q's potential is high voltage, Tg1 is turned on, and the high voltage signal provided by EN is transmitted to NC through Tg1; NC outputs a high voltage signal.

[0814] During the output period S1, NS outputs a high voltage signal, NOR1 outputs a low voltage signal to Q, Trst outputs a low voltage signal, Q's potential is low voltage, NOR2 outputs a high voltage signal to QB, QB's potential is high voltage, Tg1 is cut off, NC outputs a high voltage signal to NAD1, NAD1 outputs a low voltage signal to G1, and G1 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn on.

[0815] As shown in Figure 28B, at least one embodiment of the driving circuit shown in Figure 26 outputs a low voltage signal during low-frequency refresh when it is in operation.

[0816] During the reset period S0, Trst outputs a high voltage signal, NOR2 outputs a low voltage signal to QB, QB's potential is low voltage, NS outputs a low voltage signal, NOR1 outputs a high voltage signal to Q, Q's potential is high voltage, Tg1 is turned on, and the low voltage signal provided by EN is transmitted to NC through Tg1; NC outputs a low voltage signal.

[0817] During the output time period S1, when NS provides a high voltage signal, NOR1 outputs a low voltage signal to Q, Q's potential is low voltage, Trst outputs a low voltage signal, NOR2 outputs a high voltage signal to QB, QB's potential is high voltage, and Tg1 is cut off.

[0818] During the output period, NC outputs a low voltage signal, NAD1 outputs a high voltage signal to G1, and G2 outputs a low voltage signal to control the corresponding transistors in the pixel circuit to turn off.

[0819] As shown in Figure 27, based on at least one embodiment of the driving circuit shown in Figure 26,

[0820] The first transmission gate includes a first transmission transistor Mc1 and a second transmission transistor Mc2;

[0821] The gate of Mc1 is electrically connected to Q, the source of Mc1 is electrically connected to EN, and the drain of Mc1 is electrically connected to NC.

[0822] Mc2’s gate is electrically connected to QB, Mc2’s source is electrically connected to EN, and Mc2’s drain is electrically connected to NC.

[0823] Mc1 is an n-type transistor, and Mc2 is a p-type transistor;

[0824] The second transmission gate includes a third transmission transistor Mc3 and a fourth transmission transistor Mc4;

[0825] The gate of Mc3 is electrically connected to CKn, the source of Mc3 is electrically connected to GI, and the drain of Mc1 is electrically connected to Q_m.

[0826] The gate of Mc4 is electrically connected to CB, the source of Mc4 is electrically connected to GI, and the drain of Mc4 is electrically connected to Q_m.

[0827] Mc3 is an n-type transistor, and Mc4 is a p-type transistor;

[0828] The third transmission gate includes the fifth transmission transistor Mc5 and the sixth transmission transistor Mc6;

[0829] The gate of Mc5 is electrically connected to CBn, the source of Mc5 is electrically connected to Q_m, and the drain of Mc5 is electrically connected to the drain of Mf3.

[0830] The gate of Mc6 is electrically connected to CK, the source of Mc6 is electrically connected to Q_m, and the drain of Mc6 is electrically connected to the drain of Mf3.

[0831] Mc5 is an n-type transistor, and Mc6 is a p-type transistor;

[0832] The first NOR gate includes a first NOR control transistor Mn1, a second NOR control transistor Mn2, a third NOR control transistor Mn3, and a fourth NOR control transistor Mn4;

[0833] The gate of Mn1 is electrically connected to NS, the source of Mn1 is electrically connected to VGH1, and the drain of Mn1 is electrically connected to the source of Mn2.

[0834] The gate of Mn2 is electrically connected to QB, and the drain of Mn2 is electrically connected to Q.

[0835] The gate of Mn3 is electrically connected to QB, the source of Mn3 is electrically connected to Q, and the drain of Mn3 is electrically connected to VGL1.

[0836] The gate of Mn4 is electrically connected to NS, the source of Mn4 is electrically connected to Q, and the drain of Mn4 is electrically connected to VGL1.

[0837] Mn1 and Mn2 are p-type transistors, while Mn3 and Mn4 are n-type transistors;

[0838] The second NOR gate includes the fifth NOR control transistor Mn5, the sixth NOR control transistor Mn6, the seventh NOR control transistor Mn7, and the eighth NOR control transistor Mn8.

[0839] The gate of Mn5 is electrically connected to Trst, the source of Mn5 is electrically connected to VGH1, and the drain of Mn5 is electrically connected to the source of Mn6.

[0840] The gate of Mn6 is electrically connected to Q, and the drain of Mn6 is electrically connected to QB.

[0841] The gate of Mn7 is electrically connected to Trst, the source of Mn7 is electrically connected to QB, and the drain of Mn7 is electrically connected to VGL1.

[0842] The gate of Mn8 is electrically connected to Q, the source of Mn8 is electrically connected to QB, and the drain of Mn8 is electrically connected to VGL1.

[0843] Mn5 and Mn6 are p-type transistors, while Mn7 and Mn8 are n-type transistors;

[0844] The third NOR gate includes the ninth NOR control transistor Mn9, the tenth NOR control transistor Mn10, the eleventh NOR control transistor Mn11, and the twelfth NOR control transistor Mn12.

[0845] The gate of Mn9 is electrically connected to Trst, the source of Mn9 is electrically connected to VGH1, and the drain of Mn9 is electrically connected to the source of Mn10.

[0846] The gate of Mn10 is electrically connected to NF, and the drain of Mn10 is electrically connected to NS.

[0847] The gate of Mn11 is electrically connected to NF, the source of Mn11 is electrically connected to NS, and the drain of Mn11 is electrically connected to VGL1.

[0848] The gate of Mn12 is electrically connected to Trst, the source of Mn12 is electrically connected to NS, and the drain of Mn12 is electrically connected to VGL1.

[0849] Mn9 and Mn10 are p-type transistors, while Mn11 and Mn12 are n-type transistors;

[0850] The first NAND gate includes a first NAND control transistor Ma1, a second NAND control transistor Ma2, a third NAND control transistor Ma3, and a fourth NAND control transistor Ma4;

[0851] The gate of Ma1 is electrically connected to NC, the source of Ma1 is electrically connected to VGH1, and the drain of Ma1 is electrically connected to G1.

[0852] The gate of Ma2 is electrically connected to NS, the source of Ma2 is electrically connected to VGH1, and the drain of Ma2 is electrically connected to G1.

[0853] The gate of Ma3 is electrically connected to NS, the source of Ma3 is electrically connected to G1, and the drain of Ma3 is electrically connected to the source of Ma4.

[0854] The gate of Ma4 is electrically connected to NC, and the drain of Ma4 is electrically connected to VGL1.

[0855] Ma1 and Ma2 are p-type transistors, while Ma3 and Ma4 are n-type transistors;

[0856] The first inverter includes a first inverter transistor Mf1 and a second inverter transistor Mf2, and the second inverter includes a third inverter transistor Mf3 and a fourth inverter transistor Mf4;

[0857] The gate of Mf1 is electrically connected to Q_m, the source of Mf1 is electrically connected to VGH1, and the drain of Mf1 is electrically connected to NF.

[0858] The gate of Mf2 is electrically connected to Q_m, the source of Mf2 is electrically connected to NF, and the drain of Mf2 is electrically connected to VGL1.

[0859] Mf1 is a p-type transistor, and Mf2 is an n-type transistor;

[0860] The gate of Mf3 is electrically connected to NF, the source of Mf3 is electrically connected to VGH1, and the drain of Mf3 is electrically connected to the source of Mf4.

[0861] The gate of Mf4 is electrically connected to NF, and the drain of Mf4 is electrically connected to VGL1.

[0862] Mf3 is a p-type transistor, and Mf4 is an n-type transistor;

[0863] The first output inverter includes a first output inverter transistor Ms1 and a second output inverter transistor Ms2;

[0864] The gate of Ms1 is electrically connected to G1, the source of Ms1 is electrically connected to VGH1, and the drain of Ms1 is electrically connected to the source of Ms2.

[0865] The gate of Ms2 is electrically connected to G1, and the drain of Ms2 is electrically connected to VGL1.

[0866] Ms1 is a p-type transistor, and Ms2 is an n-type transistor;

[0867] The second output inverter includes a third output inverter transistor Ms3 and a fourth output inverter transistor Ms4;

[0868] The gate of Ms3 is electrically connected to the drain of Ms1, the source of Ms3 is electrically connected to VGH1, and the drain of Ms3 is electrically connected to the source of Ms4.

[0869] The gate of Ms4 is electrically connected to the drain of Ms1, and the drain of Ms4 is electrically connected to VGL1.

[0870] Ms3 is a p-type transistor, and Ms4 is an n-type transistor;

[0871] The third output inverter includes the fifth output inverter transistor Ms5 and the sixth output inverter transistor Ms6;

[0872] The gate of Ms5 is electrically connected to the drain of Ms3, the source of Ms5 is electrically connected to the second high voltage terminal VGH2, and the drain of Ms5 is electrically connected to the source of Ms6.

[0873] The gate of Ms6 is electrically connected to the drain of Ms3, and the drain of Ms6 is electrically connected to the second low voltage terminal VGL2.

[0874] Ms5 is a p-type transistor, and Ms6 is an n-type transistor.

[0875] In at least one embodiment of the drive circuit shown in Figure 26, when NS provides a high voltage signal, Tg1 is locked.

[0876] The duration of the high voltage of the second output signal from G2 can be the period of the first clock signal provided by CK. The second output signal from G2 can be delayed by T / 2 compared to the signal provided by GI, where T is the period of the first clock signal.

[0877] At least one embodiment of the driving circuit shown in Figure 26 can output a driving signal (the driving signal may have at least one pulse), or it can output a low voltage signal.

[0878] At least one embodiment of the drive circuit shown in Figure 26 can set the potential of the reset signal provided by Trst to a high voltage during power-on / power-off or during a blank period to reset the drive circuit, while at other times the potential of the reset signal is a low voltage.

[0879] When Trst provides a high voltage signal, Q has a high voltage potential, and QB has a low voltage potential, Tg1 is turned on, and the enable signal provided by EN can be transmitted to NC normally. When the signal provided by NS jumps from low voltage to high voltage, the potential of QB becomes high, the potential of Q becomes low, and Tg1 is turned off. Moreover, as long as the potential of the reset signal provided by Trst does not become high again, Tg1 remains in the off state, and NC locks the potential of the enable signal provided by EN at this time, that is, locks the state of whether the drive circuit allows output. Subsequent changes in the potential of the enable signal provided by EN will no longer affect the potential of the signal provided by NC, so multi-pulse signals or pulse width can be output.

[0880] As shown in Figure 28A, when at least one embodiment of the driving circuit shown in Figure 26 is operating in the high-frequency refresh region, EN outputs a high-voltage signal and G2 outputs a normal driving signal.

[0881] When at least one embodiment of the driving circuit shown in Figure 26 is operating in the low-frequency refresh region, EN outputs a low-voltage signal and G2 outputs a low-voltage signal.

[0882] As shown in Figure 29, based on at least one embodiment of the driving circuit shown in Figure 14,

[0883] The latching circuit includes a first NOR gate NOR1, a second NOR gate NOR2, and a first transmission gate Tg1;

[0884] The first input terminal of the first NOR gate NOR1 is electrically connected to the sixth node NS, the second input terminal of the first NOR gate NOR1 is electrically connected to the second node QB, and the output terminal of the first NOR gate NOR1 is electrically connected to the first node Q.

[0885] The first input terminal of the second NOR gate NOR2 is electrically connected to the first node Q, the second input terminal of the second NOR gate NOR2 is electrically connected to the second reset terminal Trst2, and the output terminal of the second NOR gate NOR2 is electrically connected to the second node QB.

[0886] The input terminal of the first transmission gate Tg1 is electrically connected to the enable terminal EN, the output terminal of the first transmission gate Tg1 is electrically connected to the third node NC, the positive phase control terminal of the first transmission gate Tg1 is electrically connected to the first node Q, and the negative phase control terminal of the first transmission gate Tg1 is electrically connected to the second node QB.

[0887] The input circuit includes a second transmission gate Tg2, a third transmission gate Tg3, a first inverter INV1, and a second inverter INV2; the control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn.

[0888] The input terminal of the second transmission gate Tg2 is electrically connected to the input signal terminal GI, the output terminal of the second transmission gate Tg2 is electrically connected to the fourth node Q_m, the positive phase control terminal of the second transmission gate Tg2 is electrically connected to the fourth clock signal terminal CKn, and the inverting phase control terminal of the second transmission gate Tg2 is electrically connected to the third clock signal terminal CB.

[0889] The input terminal of the third transmission gate Tg3 is electrically connected to the fourth node Q_m, the output terminal of the third transmission gate Tg3 is electrically connected to the output terminal of the second inverter INV2, the positive phase control terminal of the third transmission gate Tg3 is electrically connected to the second clock signal terminal CBn, and the negative phase control terminal of the third transmission gate Tg3 is electrically connected to the first clock signal terminal CK.

[0890] The input terminal of the first inverter INV1 is electrically connected to the fourth node Q_m, and the output terminal of the first inverter INV1 is electrically connected to the fifth node NF.

[0891] The input terminal of the second inverter INV2 is electrically connected to the fifth node NF;

[0892] The control circuit includes a third NOR gate (NOR3);

[0893] The first input terminal of the third NOR gate NOR3 is electrically connected to the first reset terminal Trst1, the second input terminal of the third NOR gate NOR3 is electrically connected to the fifth node NF, and the output terminal of the third NAND gate is electrically connected to the sixth node.

[0894] The signal output circuit includes a first NAND gate NAD1;

[0895] The first input terminal of the first NAND gate NAD1 is electrically connected to the sixth node NS, the second input terminal of the first NAND gate NAD1 is electrically connected to the third node NC, and the output terminal of the first NAND gate NAD1 is electrically connected to the first output terminal G1.

[0896] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, and a third output inverter IV3;

[0897] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, and the output terminal of IV3 is electrically connected to the second output terminal G2.

[0898] In at least one embodiment of the driving circuit shown in Figure 29, the first reset terminal and the second reset terminal are different reset terminals.

[0899] At least one embodiment of the driving circuit shown in Figure 29 can be used to control T1 and T2 in the pixel circuit shown in Figure 40.

[0900] Figures 30A and 30B are timing diagrams of at least one embodiment of the drive circuit shown in Figure 29.

[0901] As shown in Figure 30A, in at least one embodiment of the driving circuit shown in Figure 29 of this disclosure, when operating, EN outputs a high voltage signal during high-frequency refresh;

[0902] During the reset period S0, Trst2 outputs a high voltage signal, NOR2 outputs a low voltage signal to QB, NS provides a low voltage signal, QB's potential is low voltage, NOR1 outputs a high voltage signal to Q, Q's potential is high voltage, Tg1 is turned on; the high voltage signal output by EN is transmitted to NC.

[0903] During the output period S1, NS provides a high voltage signal, NOR1 outputs a low voltage signal to Q, Trst2 outputs a low voltage signal, NOR2 outputs a high voltage signal to QB, and Tg1 is cut off; NC outputs a high voltage signal, NAD1 outputs a low voltage signal to G1, and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn on.

[0904] After the output time period S1, NS outputs a low voltage signal, NAD1 outputs a high voltage signal to G1, and G2 outputs a low voltage signal.

[0905] As shown in Figure 30B, in at least one embodiment of the driving circuit shown in Figure 29 of this disclosure, when operating, EN outputs a low voltage signal during low-frequency refresh;

[0906] During the reset period S0, Trst2 outputs a high voltage signal, NOR2 outputs a low voltage signal to QB, NS outputs a low voltage signal, QB's potential is low voltage, NOR1 outputs a high voltage signal to Q, Q's potential is high voltage, Tg1 is turned on, EN outputs a low voltage signal to NC, NC outputs a low voltage signal, NAD1 outputs a high voltage signal to G1, and G2 outputs a low voltage signal.

[0907] During the output time period S1, when NS outputs a high voltage signal, NOR1 outputs a low voltage signal to Q, and Q's potential is low voltage. Trst2 outputs a low voltage signal, NOR2 outputs a high voltage signal to QB, and QB's potential is high voltage. Tg1 is cut off.

[0908] During the output period S1, NC outputs a low voltage signal, NAD1 outputs a high voltage signal to G1, and G2 outputs a low voltage signal to control the corresponding transistors in the pixel circuit to turn off.

[0909] The difference between at least one embodiment of the driving circuit shown in Figure 29 of this disclosure and at least one embodiment of the driving circuit shown in Figure 26 of this disclosure is that:

[0910] The first input terminal of NOR3 is electrically connected to the first reset terminal Trst1, and the second input terminal of NOR2 is electrically connected to the second reset terminal Trst2.

[0911] The waveform of the first reset signal provided by Trst1 is the same as the waveform of the reset signal provided by Trst;

[0912] The second reset signal provided by Trst2 has a high voltage for a longer period than the first reset signal provided by Trst1 has a high voltage for a longer period. The reset time is adjusted according to the number of pixel rows corresponding to the driving circuit.

[0913] In at least one embodiment of the driving circuit shown in Figure 29 of this disclosure, the time for the voltage of the second reset signal provided by Trst2 to be high is adjusted according to the number of rows of the driving circuit. Alternatively, each row of driving circuits may be connected to a different second reset signal, or different second reset signals may be connected in groups (the number of driving circuits included in each group of driving circuits should not exceed the number of pixel charging rows corresponding to the blanking time). The reset time is before the voltage of the second output signal provided by the second output terminal of each row of driving circuits becomes high, but the advance time should not exceed the row blanking time.

[0914] As shown in Figure 31, based on at least one embodiment of the driving circuit shown in Figure 15,

[0915] The latching circuit includes a first NOR gate NOR1, a second NOR gate NOR2, and a first transmission gate Tg1;

[0916] The first input terminal of the first NOR gate NOR1 is electrically connected to the sixth node NS, the second input terminal of the first NOR gate NOR1 is electrically connected to the second node QB, and the output terminal of the first NOR gate NOR1 is electrically connected to the first node Q.

[0917] The first input terminal of the second NOR gate NOR2 is electrically connected to the first node Q, the second input terminal of the second NOR gate NOR2 is electrically connected to the reset terminal Trst, and the output terminal of the second NOR gate NOR2 is electrically connected to the second node QB.

[0918] The input terminal of the first transmission gate Tg1 is electrically connected to the enable terminal EN, the output terminal of the first transmission gate Tg1 is electrically connected to the third node NC, the positive phase control terminal of the first transmission gate Tg1 is electrically connected to the first node Q, and the negative phase control terminal of the first transmission gate Tg1 is electrically connected to the second node QB.

[0919] The input circuit includes a second transmission gate Tg2, a third transmission gate Tg3, a first inverter INV1, and a second inverter INV2; the control clock signal terminal includes a first clock signal terminal CK, a second clock signal terminal CBn, a third clock signal terminal CB, and a fourth clock signal terminal CKn.

[0920] The input terminal of the second transmission gate Tg2 is electrically connected to the input signal terminal GI, the output terminal of the second transmission gate Tg2 is electrically connected to the fourth node Q_m, the positive phase control terminal of the second transmission gate Tg2 is electrically connected to the fourth clock signal terminal CKn, and the inverting phase control terminal of the second transmission gate Tg2 is electrically connected to the third clock signal terminal CB.

[0921] The input terminal of the third transmission gate Tg3 is electrically connected to the fourth node Q_m, the output terminal of the third transmission gate Tg3 is electrically connected to the output terminal of the second inverter INV2, the positive phase control terminal of the third transmission gate Tg3 is electrically connected to the second clock signal terminal CBn, and the negative phase control terminal of the third transmission gate Tg3 is electrically connected to the first clock signal terminal CK.

[0922] The input terminal of the first inverter INV1 is electrically connected to the fourth node Q_m, and the output terminal of the first inverter INV1 is electrically connected to the fifth node NF.

[0923] The input terminal of the second inverter INV2 is electrically connected to the fifth node NF;

[0924] The control circuit includes a third NOR gate (NOR3);

[0925] The first input terminal of the third NOR gate NOR3 is electrically connected to the reset terminal Trst, the second input terminal of the third NOR gate NOR3 is electrically connected to the fifth node NF, and the output terminal of the third NOR gate is electrically connected to the sixth node NS.

[0926] The signal output circuit includes a first NAND gate NAD1;

[0927] The first input terminal of the first NAND gate NAD1 is electrically connected to the second clock signal terminal CBn, the second input terminal of the first NAND gate NAD1 is electrically connected to the sixth node NS, the third input terminal of the first NAND gate NAD1 is electrically connected to the third node NC, and the output terminal of the first NAND gate NAD1 is electrically connected to the first output terminal G1.

[0928] The drive enhancement circuit includes a first output inverter IV1, a second output inverter IV2, and a third output inverter IV3;

[0929] The input terminal of IV1 is electrically connected to the first output terminal G1, the output terminal of IV1 is electrically connected to the input terminal of IV2, the output terminal of IV2 is electrically connected to the input terminal of IV3, and the output terminal of IV3 is electrically connected to the second output terminal G2.

[0930] In at least one embodiment of the driving circuit shown in Figure 31, the first reset terminal and the second reset terminal are the same reset terminal.

[0931] In at least one embodiment of the driving circuit shown in Figure 31, the output clock signal terminal is the third clock signal terminal CB.

[0932] In at least one embodiment of the driving circuit shown in Figure 31, the output control clock signal terminal is the second clock signal terminal CBn.

[0933] At least one embodiment of the driving circuit shown in Figure 31 can be used to control T1 and T2 in the pixel circuit shown in Figure 40.

[0934] Figure 32 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure.

[0935] Figures 33A and 33B are timing diagrams of at least one embodiment of the driving circuit shown in Figure 31.

[0936] As shown in Figure 32, based on at least one embodiment of the driving circuit shown in Figure 31, the first transmission gate includes a first transmission transistor Mc1 and a second transmission transistor Mc2.

[0937] The gate of Mc1 is electrically connected to Q, the source of Mc1 is electrically connected to EN, and the drain of Mc1 is electrically connected to NC.

[0938] Mc2’s gate is electrically connected to QB, Mc2’s source is electrically connected to EN, and Mc2’s drain is electrically connected to NC.

[0939] Mc1 is an n-type transistor, and Mc2 is a p-type transistor;

[0940] The second transmission gate includes a third transmission transistor Mc3 and a fourth transmission transistor Mc4;

[0941] The gate of Mc3 is electrically connected to CKn, the source of Mc3 is electrically connected to GI, and the drain of Mc3 is electrically connected to Q_m.

[0942] The gate of Mc4 is electrically connected to CB, the source of Mc4 is electrically connected to GI, and the drain of Mc2 is electrically connected to Q_m.

[0943] Mc3 is an n-type transistor, and Mc4 is a p-type transistor;

[0944] The third transmission gate includes the fifth transmission transistor Mc5 and the sixth transmission transistor Mc6;

[0945] The gate of Mc5 is electrically connected to CBn, the source of Mc5 is electrically connected to Q_m, and the drain of Mc5 is electrically connected to the drain of Mf3.

[0946] The gate of Mc6 is electrically connected to CK, the source of Mc6 is electrically connected to Q_m, and the drain of Mc6 is electrically connected to the drain of Mf3.

[0947] Mc5 is an n-type transistor, and Mc6 is a p-type transistor;

[0948] The first NOR gate includes a first NOR control transistor Mn1, a second NOR control transistor Mn2, a third NOR control transistor Mn3, and a fourth NOR control transistor Mn4;

[0949] The gate of Mn1 is electrically connected to NS, the source of Mn1 is electrically connected to VGH1, and the drain of Mn1 is electrically connected to the source of Mn2.

[0950] The gate of Mn2 is electrically connected to QB, and the drain of Mn2 is electrically connected to Q.

[0951] The gate of Mn3 is electrically connected to QB, the source of Mn3 is electrically connected to Q, and the drain of Mn3 is electrically connected to VGL1.

[0952] The gate of Mn4 is electrically connected to NS, the source of Mn4 is electrically connected to Q, and the drain of Mn4 is electrically connected to VGL1.

[0953] Mn1 and Mn2 are p-type transistors, while Mn3 and Mn4 are n-type transistors;

[0954] The second NOR gate includes the fifth NOR control transistor Mn5, the sixth NOR control transistor Mn6, the seventh NOR control transistor Mn7, and the eighth NOR control transistor Mn8.

[0955] The gate of Mn5 is electrically connected to Trst, the source of Mn5 is electrically connected to VGH1, and the drain of Mn5 is electrically connected to the source of Mn6.

[0956] The gate of Mn6 is electrically connected to Q, and the drain of Mn6 is electrically connected to QB.

[0957] The gate of Mn7 is electrically connected to Trst, the source of Mn7 is electrically connected to QB, and the drain of Mn7 is electrically connected to VGL1.

[0958] The gate of Mn8 is electrically connected to Q, the source of Mn8 is electrically connected to QB, and the drain of Mn8 is electrically connected to VGL1.

[0959] Mn5 and Mn6 are p-type transistors, while Mn7 and Mn8 are n-type transistors;

[0960] The third NOR gate includes the ninth NOR control transistor Mn9, the tenth NOR control transistor Mn10, the eleventh NOR control transistor Mn11, and the twelfth NOR control transistor Mn12.

[0961] The gate of Mn9 is electrically connected to Trst, the source of Mn9 is electrically connected to VGH1, and the drain of Mn9 is electrically connected to the source of Mn10.

[0962] The gate of Mn10 is electrically connected to NF, and the drain of Mn10 is electrically connected to NS.

[0963] The gate of Mn11 is electrically connected to NF, the source of Mn11 is electrically connected to NS, and the drain of Mn11 is electrically connected to VGL1.

[0964] The gate of Mn12 is electrically connected to Trst, the source of Mn12 is electrically connected to NS, and the drain of Mn12 is electrically connected to VGL1.

[0965] Mn9 and Mn10 are p-type transistors, while Mn11 and Mn12 are n-type transistors;

[0966] The first NAND gate includes a first NAND control transistor Ma1, a second NAND control transistor Ma2, a third NAND control transistor Ma3, a fourth NAND control transistor Ma4, a fifth NAND control transistor Ma5, and a sixth NAND control transistor Ma6;

[0967] The gate of Ma1 is electrically connected to CBn, the source of Ma1 is electrically connected to VGH1, and the drain of Ma1 is electrically connected to G1.

[0968] The gate of Ma2 is electrically connected to NC, the source of Ma2 is electrically connected to VGH1, and the drain of Ma2 is electrically connected to G1.

[0969] The gate of Ma3 is electrically connected to NS, the source of Ma3 is electrically connected to VGH1, and the drain of Ma3 is electrically connected to G1.

[0970] The gate of Ma4 is electrically connected to NS, the source of Ma4 is electrically connected to G1, and the drain of Ma4 is electrically connected to the source of Ma5.

[0971] The gate of Ma5 is electrically connected to CBn, and the drain of Ma5 is electrically connected to the source of Ma6.

[0972] The gate of Ma6 is electrically connected to NC, and the drain of Ma6 is electrically connected to VGL1.

[0973] Ma1, Ma2, and Ma3 are p-type transistors, while Ma4, Ma5, and Ma6 are n-type transistors.

[0974] The first inverter includes a first inverter transistor Mf1 and a second inverter transistor Mf2, and the second inverter includes a third inverter transistor Mf3 and a fourth inverter transistor Mf4;

[0975] The gate of Mf1 is electrically connected to Q_m, the source of Mf1 is electrically connected to VGH1, and the drain of Mf1 is electrically connected to NF.

[0976] The gate of Mf2 is electrically connected to Q_m, the source of Mf2 is electrically connected to NF, and Mf2 is electrically connected to VGL1.

[0977] Mf1 is a p-type transistor, and Mf2 is an n-type transistor;

[0978] The gate of Mf3 is electrically connected to NF, the source of Mf3 is electrically connected to VGH1, and the drain of Mf3 is electrically connected to the source of Mf4.

[0979] The gate of Mf4 is electrically connected to NF, and the drain of Mf4 is electrically connected to VGL1.

[0980] Mf3 is a p-type transistor, and Mf4 is an n-type transistor;

[0981] The first output inverter includes a first output inverter transistor Ms1 and a second output inverter transistor Ms2;

[0982] The gate of Ms1 is electrically connected to G1, the source of Ms1 is electrically connected to VGH1, and the drain of Ms1 is electrically connected to the source of Ms2.

[0983] The gate of Ms2 is electrically connected to G1, and the drain of Ms2 is electrically connected to VGL1.

[0984] Ms1 is a p-type transistor, and Ms2 is an n-type transistor;

[0985] The second output inverter includes a third output inverter transistor Ms3 and a fourth output inverter transistor Ms4;

[0986] The gate of Ms3 is electrically connected to the drain of Ms1, the source of Ms3 is electrically connected to VGH1, and the drain of Ms3 is electrically connected to the source of Ms4.

[0987] The gate of Ms4 is electrically connected to the drain of Ms1, and the drain of Ms4 is electrically connected to VGL1.

[0988] Ms3 is a p-type transistor, and Ms4 is an n-type transistor;

[0989] The third output inverter includes the fifth output inverter transistor Ms5 and the sixth output inverter transistor Ms6;

[0990] The gate of Ms5 is electrically connected to the drain of Ms3, the source of Ms5 is electrically connected to the second high voltage terminal VGH2, and the drain of Ms5 is electrically connected to the source of Ms6.

[0991] The gate of Ms6 is electrically connected to the drain of Ms3, and the drain of Ms6 is electrically connected to the second low voltage terminal VGL2.

[0992] Ms5 is a p-type transistor, and Ms6 is an n-type transistor.

[0993] In at least one embodiment of the driving circuit shown in Figure 31, when the potential of the signal provided by NS jumps from low voltage to high voltage, Tg1 is locked, locked 1H in advance, and the potential of the second output signal provided by G2 remains at high voltage for less than T / 2, where T is the period of the first clock signal provided by CK; the high-level width of the potential of the second clock signal provided by CBn can be adjusted.

[0994] In at least one embodiment of the driving circuit shown in Figure 31, NAD1 has three input terminals. The first input terminal of NAD1 is electrically connected to CBn, the second input terminal of NAD1 is electrically connected to NS, and the third input terminal of NAD1 is electrically connected to NC. G2 can only output a high voltage signal when CB, NS, and NC all provide high voltage signals, thereby realizing that the high-level width of the second output signal provided by G2 is the same as the low-level width of the second clock signal provided by CB.

[0995] As shown in Figure 33A, at least one embodiment of the driving circuit shown in Figure 31 of this disclosure outputs a high voltage signal EN during high-frequency refresh.

[0996] During the reset period S0, Trst outputs a high voltage signal, NOR2 outputs a low voltage signal to QB, QB's potential is low voltage, NS provides a low voltage signal, NOR1 outputs a high voltage signal to Q, Q's potential is high voltage, Tg1 is turned on, and the high voltage signal provided by EN is transmitted to NC through Tg1.

[0997] Between the reset time period S0 and the output time period S1, when NS outputs a high voltage signal, NOR1 outputs a low voltage signal to Q, Q's potential is low voltage, Trst outputs a low voltage signal, NOR2 outputs a high voltage signal to QB, QB's potential is high voltage, and Tg1 is cut off.

[0998] Between the reset time period S0 and the output time period S1, when CBn outputs a low voltage signal, NAD1 outputs a high voltage signal to G1, and G2 outputs a low voltage signal.

[0999] During the output time period S1, NS outputs a high voltage signal, CBn outputs a high voltage signal, NC outputs a high voltage signal, NAD1 outputs a low voltage signal to G1, and G2 outputs a high voltage signal to control the corresponding transistors in the pixel circuit to turn on.

[1000] After the output time period S2, when NS outputs a low voltage signal and / or CBn outputs a low voltage signal, NAD1 outputs a high voltage signal to G1, and G2 outputs a low voltage signal.

[1001] As shown in Figure 33B, at least one embodiment of the driving circuit shown in Figure 31 of this disclosure outputs a low voltage signal EN during low-frequency refresh.

[1002] During the reset period S0, Trst outputs a high voltage signal, NOR2 outputs a low voltage signal to QB, QB's potential is low voltage, NS provides a low voltage signal, NOR1 outputs a high voltage signal to Q, Q's potential is high voltage, Tg1 is turned on, and the low voltage signal provided by EN is transmitted to NC through Tg1.

[1003] During the output time period S1, when NS outputs a high voltage signal, NOR1 outputs a low voltage signal to Q, Trst outputs a low voltage signal, NOR2 outputs a high voltage signal to QB, QB has a high voltage potential, and Tg1 is cut off.

[1004] During the output period S1, NC outputs a low voltage signal, NAD1 outputs a high voltage signal to G1, and G2 outputs a low voltage signal to control the corresponding transistors in the pixel circuit to turn off.

[1005] The driving method described in this embodiment is applied to the aforementioned driving circuit. The driving method includes: within one frame, between the time point when the second reset terminal begins to provide a valid second reset signal and the time point when the first control terminal first begins to provide a valid first control signal, the latch circuit transmits the enable signal provided by the enable terminal to the third node. After the time point when the first control terminal first begins to provide a valid first control signal, the latch circuit controls the start of latching and stops transmitting the enable signal to the third node, thereby locking the output enable state of the driving circuit in this row. This can achieve the following: in the high-frequency refresh area, the second output terminal outputs a multi-pulse driving signal (the number of pulses or the pulse width varies with the starting signal); or in the low-frequency refresh area, there is no pulse output, and after the first output, the signal output by the second output terminal no longer changes with the state of the enable signal within the same frame.

[1006] The driving module described in this embodiment includes multiple stages of the above-described driving circuits;

[1007] The input signal terminal of the first-stage driving circuit is electrically connected to the starting signal terminal, and the sixth node of the nth-stage driving circuit is electrically connected to the input signal terminal of the (n+1)th driving circuit, where n is a positive integer.

[1008] In a specific implementation, the driving circuit may include multiple levels of the above-mentioned driving circuits. The input signal terminal of the first-level driving circuit is electrically connected to the starting signal terminal. Adjacent driving circuits are cascaded together. The sixth node of the nth-level driving circuit is electrically connected to the input signal terminal of the (n+1)th driving circuit.

[1009] In one embodiment of this disclosure, the first reset terminal and the second reset terminal are the same reset terminal; the reset terminals of the multi-stage driving circuit are all electrically connected to the frame reset terminal.

[1010] In practical implementation, the first reset terminal and the second reset terminal can be the same reset terminal, and the reset terminals of the multi-stage drive circuit can all be electrically connected to the frame reset terminal.

[1011] In one embodiment of this disclosure, the first reset terminal and the second reset terminal are the same reset terminal; the drive module further includes multiple control transmission gates and multiple control clock signal generation terminals;

[1012] The reset terminal of the first-stage drive circuit is electrically connected to the frame reset terminal;

[1013] The reset terminal of the m-th stage driving circuit is electrically connected to the output terminal of the (m-1)-th control transmission gate. The input terminal of the (m-1)-th control transmission gate is electrically connected to the second node in the (m-1)-th stage driving circuit. The positive control terminal of the (m-1)-th control transmission gate is electrically connected to the first generation control clock signal terminal. The inverting control terminal of the (m-1)-th control transmission gate is electrically connected to the second generation control clock signal terminal.

[1014] m is an integer greater than 1.

[1015] In specific implementation, the first reset terminal and the second reset terminal can be the same reset terminal. The first reset terminal of the first stage driving circuit can be electrically connected to the frame reset terminal. The reset terminal of the m-th stage driving circuit can be electrically connected to the output terminal of the (m-1)-th control transmission gate. Under the control of the first generation control clock signal and the second generation control clock signal, the (m-1)-th control transmission gate can transmit the signal provided by the inverted control signal node in the (m-1)-th stage driving circuit to the reset terminal of the m-th stage driving circuit.

[1016] The second generation control clock signal terminal can be the first clock signal terminal, and the first generation control clock signal terminal can be the fourth clock signal terminal.

[1017] In one embodiment of this disclosure, the first reset terminal and the second reset terminal are the same reset terminal;

[1018] The reset terminal of the nth drive circuit is electrically connected to the output terminal of the nth control drive signal.

[1019] In specific implementation, the first reset terminal and the second reset terminal can be the same reset terminal, and the reset signal provided by the reset terminal of the nth driving circuit can be provided by the nth control driving signal output terminal.

[1020] In at least one embodiment of this disclosure, the drive module further includes a plurality of control transmission gates and a plurality of control clock signal generation terminals;

[1021] The first reset terminal of the multi-stage driving circuit is electrically connected to the frame reset terminal; the second reset terminal of the first-stage driving circuit is electrically connected to the frame reset terminal.

[1022] The second reset terminal of the m-th stage driving circuit is electrically connected to the output terminal of the (m-1)-th control transmission gate. The input terminal of the (m-1)-th control transmission gate is electrically connected to the second node in the (m-1)-th stage driving circuit. The positive control terminal of the (m-1)-th control transmission gate is electrically connected to the first generation control clock signal terminal. The inverting control terminal of the (m-1)-th control transmission gate is electrically connected to the second generation control clock signal terminal.

[1023] m is an integer greater than 1;

[1024] The second generation control clock signal terminal can be the first clock signal terminal, and the first generation control clock signal terminal can be the fourth clock signal terminal.

[1025] In specific implementation, the first reset terminal of the multi-stage driving circuit and the second reset terminal of the first-stage driving circuit are both electrically connected to the frame reset terminal. The (m-1)th control transmission gate can write the signal provided by the second node in the (m-1)th stage driving circuit into the second reset terminal of the m-th stage driving circuit under the control of the first clock signal and the fourth clock signal.

[1026] In at least one embodiment of this disclosure, the first reset terminal of the multi-stage driving circuit is electrically connected to the frame reset terminal; the second reset terminal of the nth driving circuit is electrically connected to the nth control driving signal output terminal.

[1027] In practical implementation, the first reset terminal of the multi-stage drive circuit can be electrically connected to the frame reset terminal, and the second reset terminal of the nth drive circuit can be provided by the nth control drive signal output terminal.

[1028] In at least one embodiment of this disclosure, the first reset terminal of the multi-stage driving circuit is electrically connected to the frame reset terminal;

[1029] The second reset terminals of the a×n-a+1th stage drive circuit to the second reset terminal of the a×nth stage drive circuit are all electrically connected to the nth control drive signal output terminal; a is a positive integer.

[1030] In practical implementation, the first reset terminal of the multi-stage driving circuit can be electrically connected to the frame reset terminal, and the second reset terminal of the adjacent a-stage driving circuit can be provided by the nth control drive signal output terminal.

[1031] As shown in Figure 34, at least one embodiment of the driving module may include a b-stage driving circuit; where b is an integer greater than 3.

[1032] In Figure 34, GA1 is the first-stage driving circuit of the driving module, GA2 is the second-stage driving circuit of the driving module, GAb-1 is the (b-1)th-stage driving circuit of the driving module, and GAb is the b-th-stage driving circuit of the driving module.

[1033] In Figure 34, Strst is the frame reset terminal, CKL is the first clock signal line, CBL is the third clock signal line, CKnL is the fourth clock signal line, and CBnL is the second clock signal line.

[1034] The reset terminals of GA1, GA2, GAb-1, and GAb are all electrically connected to the frame reset terminal Strst.

[1035] The input signal terminal of GA1 is electrically connected to the start signal terminal STV;

[1036] The second output terminal of GA1 is electrically connected to the first-stage drive signal terminal SG1;

[1037] The first clock signal terminal of GA1 is electrically connected to CKL, the third clock signal terminal of GA1 is electrically connected to CBL, the fourth clock signal terminal of GA1 is electrically connected to CKnL, and the second clock signal terminal of GA1 is electrically connected to CBnL.

[1038] The sixth node of GA1 is electrically connected to the input signal terminal of GA2;

[1039] The second output terminal of GA2 is electrically connected to the second-stage drive signal terminal SG2;

[1040] The first clock signal terminal of GA2 is electrically connected to CBL, the third clock signal terminal of GA2 is electrically connected to CKL, the fourth clock signal terminal of GA2 is electrically connected to CBnL, and the second clock signal terminal of GA2 is electrically connected to CKnL.

[1041] The second output terminal of GAb-1 is electrically connected to the (b-1)th stage drive signal terminal SGb-1;

[1042] The first clock signal terminal of GAb-1 is electrically connected to CKL, the third clock signal terminal of GAb-1 is electrically connected to CBL, the fourth clock signal terminal of GAb-1 is electrically connected to CKnL, and the second clock signal terminal of GAb-1 is electrically connected to CBnL.

[1043] The sixth node of GAb-1 is electrically connected to the input signal terminal of GAb;

[1044] The second output terminal of GAb is electrically connected to the b-th stage drive signal terminal SGb.

[1045] The first clock signal terminal of GAb is electrically connected to CBL, the third clock signal terminal of GAb is electrically connected to CKL, the fourth clock signal terminal of GAb is electrically connected to CBnL, and the second clock signal terminal of GAb is electrically connected to CKnL.

[1046] In at least one embodiment of the drive module shown in Figure 34, each stage of the drive circuit uses a reset terminal Trst.

[1047] As shown in Figure 34, at least one embodiment of the drive module uses two high-voltage terminals and two low-voltage terminals for power supply. Under normal circumstances, the voltage value of the second low-voltage signal provided by VGL2 is not higher than the voltage value of the first low-voltage signal provided by VGL1, and the voltage value of the second high-voltage signal provided by VGH2 is not lower than the voltage value of the first high-voltage signal provided by VGH1. Using dual-voltage drive can accelerate the charging and discharging speed of the output inverter that directly outputs the second output signal, thereby improving the driving capability. Under normal circumstances, the output transistor included in the output inverter that directly outputs the second output signal has a relatively large channel width, and the threshold voltage of the output transistor is also closer to 0V. For the oxide transistor (n-type transistor) included in the output inverter that directly outputs the second output signal, if the threshold voltage is less than 0, when using a single power supply, the minimum gate-source voltage of the oxide transistor is 0V, so the oxide transistor cannot be turned off. Therefore, when the second output terminal G2 outputs a high-voltage signal, there is a long-term leakage current, which increases the power consumption of the drive circuit. If the threshold voltage is severely negatively biased, it may also cause the potential of the second output signal provided by the second output terminal G2 to be unable to be pulled high, thereby making the drive module unable to work normally. When the driving module described in at least one embodiment of this disclosure uses dual low-voltage terminals, the voltage value of the second low-voltage signal provided by VGL2 can be reduced so that the voltage difference between the second low-voltage signal provided by VGL2 and the first low-voltage signal provided by VGL1 is greater than the absolute value of the threshold voltage of the oxide transistor. This ensures that the oxide transistor in the output inverter that directly outputs the second output signal can switch normally, allowing the driving circuit to work normally, reducing DC leakage current, and saving power consumption. The driving module described in at least one embodiment of this disclosure using dual high-voltage terminals can also solve the problem of the threshold voltage of the p-type transistor in the output inverter that directly outputs the second output signal being positively biased to zero.

[1048] In the driving module described in at least one embodiment of this disclosure, in the odd-numbered row driving circuit, CK and CKL are electrically connected, CB and CBL are electrically connected, CKn and CKnL are electrically connected, and CBn and CBnL are electrically connected.

[1049] In the even-numbered row drive circuit, CK is electrically connected to CBL, CB is electrically connected to CKL, CKn is electrically connected to CBnL, and CBn is electrically connected to CKnL.

[1050] In the driving module described in at least one embodiment of this disclosure, if there is a Dummy timing requirement or driving load, a Dummy driving circuit can be added before the first driving circuit and after the last driving circuit.

[1051] As shown in Figure 35, at least one embodiment of the driving module may include a b-level driving circuit; where b is an integer greater than 3.

[1052] In Figure 35, GA1 is the first-stage driving circuit of the driving module, GA2 is the second-stage driving circuit of the driving module, Gab-1 is the (b-1)th-stage driving circuit of the driving module, and Gab is the b-th-stage driving circuit of the driving module.

[1053] In Figure 35, the line labeled CKL is the first clock signal line, the line labeled CBL is the third clock signal line, the line labeled CKnL is the fourth clock signal line, and the line labeled CBnL is the second clock signal line.

[1054] The reset terminal of GA1 is electrically connected to the first control drive signal output terminal GS1;

[1055] The reset terminal of GA2 is electrically connected to the second control drive signal output terminal GS2;

[1056] The reset terminal of GAb-1 is electrically connected to the b-1 control drive signal output terminal GSb-1;

[1057] The reset terminal of GAb is electrically connected to the b-th control drive signal output terminal GSb.

[1058] The input signal terminal of GA1 is electrically connected to the start signal terminal STV;

[1059] The second output terminal of GA1 is electrically connected to the first-stage drive signal terminal SG1;

[1060] The first clock signal terminal of GA1 is electrically connected to CKL, the third clock signal terminal of GA1 is electrically connected to CBL, the fourth clock signal terminal of GA1 is electrically connected to CKnL, and the second clock signal terminal of GA1 is electrically connected to CBnL.

[1061] The sixth node of GA1 is electrically connected to the input signal terminal of GA2;

[1062] The second output terminal of GA2 is electrically connected to the second-stage drive signal terminal SG2;

[1063] The first clock signal terminal of GA2 is electrically connected to CBL, the third clock signal terminal of GA2 is electrically connected to CKL, the fourth clock signal terminal of GA2 is electrically connected to CBnL, and the second clock signal terminal of GA2 is electrically connected to CKnL.

[1064] The second output terminal of GAb-1 is electrically connected to the (b-1)th stage drive signal terminal SGb-1;

[1065] The first clock signal terminal of GAb-1 is electrically connected to CKL, the third clock signal terminal of GAb-1 is electrically connected to CBL, the fourth clock signal terminal of GAb-1 is electrically connected to CKnL, and the second clock signal terminal of GAb-1 is electrically connected to CBnL.

[1066] The sixth node of GAb-1 is electrically connected to the input signal terminal of GAb;

[1067] The second output terminal of GAb is electrically connected to the b-th stage drive signal terminal SGb.

[1068] The first clock signal terminal of GAb is electrically connected to CBL, the third clock signal terminal of GAb is electrically connected to CKL, the fourth clock signal terminal of GAb is electrically connected to CBnL, and the second clock signal terminal of GAb is electrically connected to CKnL.

[1069] In at least one embodiment of the drive module shown in Figure 35, the reset signals for each stage of the drive circuit are provided by the control drive signal generation module.

[1070] In at least one embodiment of the drive module shown in Figure 35, each stage of the drive circuit uses a reset terminal Trst.

[1071] As shown in Figure 36, at least one embodiment of the driving module may include a b-level driving circuit; where b is an integer greater than 3.

[1072] In Figure 36, GA1 is the first-stage driving circuit of the driving module, GA2 is the second-stage driving circuit of the driving module, Gab-1 is the (b-1)th-stage driving circuit of the driving module, and Gab is the b-th-stage driving circuit of the driving module.

[1073] In Figure 36, the line labeled CKL is the first clock signal line, the line labeled CBL is the third clock signal line, the line labeled CKnL is the fourth clock signal line, and the line labeled CBnL is the second clock signal line.

[1074] The reset terminal of GA1 is electrically connected to the frame reset terminal Strst;

[1075] At least one embodiment of the drive module may further include multiple control transmission gates;

[1076] In Figure 36, Tc1 is the first control transmission gate Tc1, Tcb-2 is the (b-2)th control transmission gate, and Tcb-1 is the (b-1)th control transmission gate.

[1077] The positive control terminal of Tc1 is electrically connected to CBnL, the negative control terminal of Tc1 is electrically connected to CBL, the input terminal of Tc1 is electrically connected to the second node in the first drive circuit GA1, and the output terminal of Tc1 is electrically connected to the reset terminal of the second drive circuit GA2.

[1078] The positive control terminal of Tcb-2 is electrically connected to CKnL, the inverting control terminal of Tcb-2 is electrically connected to CKL, the input terminal of Tcb-2 is electrically connected to the second node in the (b-2)th drive circuit GAb-2, and the output terminal of Tcb-2 is electrically connected to the reset terminal of the (b-1)th stage drive circuit GAb-1.

[1079] The positive control terminal of Tcb-1 is electrically connected to CBnL, the negative control terminal of Tcb-1 is electrically connected to CBL, the input terminal of Tcb-1 is electrically connected to the second node in the (b-1)th drive circuit GAb-1, and the output terminal of Tcb-1 is electrically connected to the reset terminal of the b-th drive circuit GAb.

[1080] The input signal terminal of GA1 is electrically connected to the start signal terminal STV;

[1081] The second output terminal of GA1 is electrically connected to the first-stage drive signal terminal SG1;

[1082] The first clock signal terminal of GA1 is electrically connected to CKL, the third clock signal terminal of GA1 is electrically connected to CBL, the fourth clock signal terminal of GA1 is electrically connected to CKnL, and the second clock signal terminal of GA1 is electrically connected to CBnL.

[1083] The sixth node of GA1 is electrically connected to the input signal terminal of GA2;

[1084] The second output terminal of GA2 is electrically connected to the second-stage drive signal terminal SG2;

[1085] The first clock signal terminal of GA2 is electrically connected to CBL, the third clock signal terminal of GA2 is electrically connected to CKL, the fourth clock signal terminal of GA2 is electrically connected to CBnL, and the second clock signal terminal of GA2 is electrically connected to CKnL.

[1086] The second output terminal of GAb-1 is electrically connected to the (b-1)th stage drive signal terminal SGb-1;

[1087] The first clock signal terminal of GAb-1 is electrically connected to CKL, the third clock signal terminal of GAb-1 is electrically connected to CBL, the fourth clock signal terminal of GAb-1 is electrically connected to CKnL, and the second clock signal terminal of GAb-1 is electrically connected to CBnL.

[1088] The sixth node of GAb-1 is electrically connected to the input signal terminal of GAb;

[1089] The second output terminal of GAb is electrically connected to the b-th stage drive signal terminal SGb.

[1090] The first clock signal terminal of GAb is electrically connected to CBL, the third clock signal terminal of GAb is electrically connected to CKL, the fourth clock signal terminal of GAb is electrically connected to CBnL, and the second clock signal terminal of GAb is electrically connected to CKnL.

[1091] In at least one embodiment of the driving module shown in Figure 36, the reset terminal of the first row or the first two rows of driving circuits is electrically connected to the frame reset terminal Strst. The reset signal of the reset terminal of the subsequent driving circuits is provided by the corresponding control transmission gate to realize the latch reset with a step-by-step delay of 1H. This allows the latch to reset the first transmission gate 1H (or multiple H, but less than the number of rows corresponding to the blanking time) before the first output in a frame, so that the enable signal provided by EN can be input to the driving circuit. At the first output, or before the first output, the first transmission gate is locked to realize the line-by-line control of the enable signal, without affecting the high and low refresh states due to multiple pulses in a frame.

[1092] In at least one embodiment of the drive module shown in Figure 36, each stage of the drive circuit uses a reset terminal Trst.

[1093] As shown in Figure 37, at least one embodiment of the driving module may include a b-level driving circuit; where b is an integer greater than 3.

[1094] In Figure 37, GA1 is the first-stage driving circuit of the driving module, GA2 is the second-stage driving circuit of the driving module, Gab-1 is the (b-1)th-stage driving circuit of the driving module, and Gab is the b-th-stage driving circuit of the driving module.

[1095] In Figure 37, the line labeled CKL is the first clock signal line, the line labeled CBL is the third clock signal line, the line labeled CKnL is the fourth clock signal line, and the line labeled CBnL is the second clock signal line.

[1096] Both the first reset terminal and the second reset terminal of GA1 are electrically connected to the frame reset terminal Strst.

[1097] The first reset terminal of GA2, the first reset terminal of GAb-1, and the first reset terminal of GAb are all electrically connected to the frame reset terminal Strst.

[1098] At least one embodiment of the drive module may further include multiple control transmission gates;

[1099] In Figure 37, Tc1 is the first control transmission gate Tc1, Tcb-2 is the (b-2)th control transmission gate, and Tcb-1 is the (b-1)th control transmission gate.

[1100] The positive control terminal of Tc1 is electrically connected to CBnL, the negative control terminal of Tc1 is electrically connected to CBL, the input terminal of Tc1 is electrically connected to the second node in the first drive circuit GA1, and the output terminal of Tc1 is electrically connected to the second reset terminal of the second drive circuit GA2.

[1101] The positive control terminal of Tcb-2 is electrically connected to CKnL, the inverting control terminal of Tcb-2 is electrically connected to CKL, the input terminal of Tcb-2 is electrically connected to the second node in the (b-2)th drive circuit GAb-2, and the output terminal of Tcb-2 is electrically connected to the second reset terminal of the (b-1)th stage drive circuit GAb-1.

[1102] The positive control terminal of Tcb-1 is electrically connected to CBnL, the negative control terminal of Tcb-1 is electrically connected to CBL, the input terminal of Tcb-1 is electrically connected to the second node in the (b-1)th drive circuit GAb-1, and the output terminal of Tcb-1 is electrically connected to the second reset terminal of the b-th drive circuit GAb.

[1103] The input signal terminal of GA1 is electrically connected to the start signal terminal STV;

[1104] The second output terminal of GA1 is electrically connected to the first-stage drive signal terminal SG1;

[1105] The first clock signal terminal of GA1 is electrically connected to CKL, the third clock signal terminal of GA1 is electrically connected to CBL, the fourth clock signal terminal of GA1 is electrically connected to CKnL, and the second clock signal terminal of GA1 is electrically connected to CBnL.

[1106] The sixth node of GA1 is electrically connected to the input signal terminal of GA2;

[1107] The second output terminal of GA2 is electrically connected to the second-stage drive signal terminal SG2;

[1108] The first clock signal terminal of GA2 is electrically connected to CBL, the third clock signal terminal of GA2 is electrically connected to CKL, the fourth clock signal terminal of GA2 is electrically connected to CBnL, and the second clock signal terminal of GA2 is electrically connected to CKnL.

[1109] The second output terminal of GAb-1 is electrically connected to the (b-1)th stage drive signal terminal SGb-1;

[1110] The first clock signal terminal of GAb-1 is electrically connected to CKL, the third clock signal terminal of GAb-1 is electrically connected to CBL, the fourth clock signal terminal of GAb-1 is electrically connected to CKnL, and the second clock signal terminal of GAb-1 is electrically connected to CBnL.

[1111] The sixth node of GAb-1 is electrically connected to the input signal terminal of GAb;

[1112] The second output terminal of GAb is electrically connected to the b-th stage drive signal terminal SGb.

[1113] The first clock signal terminal of GAb is electrically connected to CBL, the third clock signal terminal of GAb is electrically connected to CKL, the fourth clock signal terminal of GAb is electrically connected to CBnL, and the second clock signal terminal of GAb is electrically connected to CKnL.

[1114] In at least one embodiment of the driving module shown in Figure 37, the first reset terminal of each row driving circuit is electrically connected to the frame reset terminal Strst, and the second reset terminal of the first row or the first two rows driving circuits is electrically connected to the frame reset terminal Strst. The second reset signal of the second reset terminal of the subsequent driving circuit is provided by the corresponding control transmission gate to realize the latch reset with a step-by-step delay of 1H. This allows the latch to reset the first transmission gate 1H (or multiple H, but less than the number of rows corresponding to the blanking time) before the first output in a frame, so that the enable signal provided by EN can be input to the driving circuit. At the first output, or before the first output, the first transmission gate is locked to realize the line-by-line control of the enable signal, without affecting the high and low refresh states due to multiple pulses in a frame.

[1115] In at least one embodiment of the drive module shown in Figure 37, each stage of the drive circuit employs a first reset terminal Trst1 and a second reset terminal Trst2.

[1116] As shown in Figure 38, at least one embodiment of the driving module may include a b-stage driving circuit; where b is an integer greater than 3.

[1117] In Figure 38, GA1 is the first-stage driving circuit of the driving module, GA2 is the second-stage driving circuit of the driving module, Gab-1 is the (b-1)th-stage driving circuit of the driving module, and Gab is the b-th-stage driving circuit of the driving module.

[1118] In Figure 38, the line labeled CKL is the first clock signal line, the line labeled CBL is the third clock signal line, the line labeled CKnL is the fourth clock signal line, and the line labeled CBnL is the second clock signal line.

[1119] The first reset terminals of GA1, GA2, GAb-1, and GAb are all electrically connected to the frame reset terminal Strst.

[1120] The second reset terminal of GA1 is electrically connected to the first control drive signal output terminal GS1;

[1121] The second reset terminal of GA2 is electrically connected to the second control drive signal output terminal GS2;

[1122] The second reset terminal of GAb-1 is electrically connected to the b-1 control drive signal output terminal GSb-1;

[1123] The second reset terminal of GAb is electrically connected to the b-th control drive signal output terminal GSb.

[1124] The input signal terminal of GA1 is electrically connected to the start signal terminal STV;

[1125] The second output terminal of GA1 is electrically connected to the first-stage drive signal terminal SG1;

[1126] The first clock signal terminal of GA1 is electrically connected to CKL, the third clock signal terminal of GA1 is electrically connected to CBL, the fourth clock signal terminal of GA1 is electrically connected to CKnL, and the second clock signal terminal of GA1 is electrically connected to CBnL.

[1127] The sixth node of GA1 is electrically connected to the input signal terminal of GA2;

[1128] The second output terminal of GA2 is electrically connected to the second-stage drive signal terminal SG2;

[1129] The first clock signal terminal of GA2 is electrically connected to CBL, the third clock signal terminal of GA2 is electrically connected to CKL, the fourth clock signal terminal of GA2 is electrically connected to CBnL, and the second clock signal terminal of GA2 is electrically connected to CKnL.

[1130] The second output terminal of GAb-1 is electrically connected to the (b-1)th stage drive signal terminal SGb-1;

[1131] The first clock signal terminal of GAb-1 is electrically connected to CKL, the third clock signal terminal of GAb-1 is electrically connected to CBL, the fourth clock signal terminal of GAb-1 is electrically connected to CKnL, and the second clock signal terminal of GAb-1 is electrically connected to CBnL.

[1132] The sixth node of GAb-1 is electrically connected to the input signal terminal of GAb;

[1133] The second output terminal of GAb is electrically connected to the b-th stage drive signal terminal SGb.

[1134] The first clock signal terminal of GAb is electrically connected to CBL, the third clock signal terminal of GAb is electrically connected to CKL, the fourth clock signal terminal of GAb is electrically connected to CBnL, and the second clock signal terminal of GAb is electrically connected to CKnL.

[1135] In at least one embodiment of the drive module shown in Figure 38, each stage of the drive circuit employs a first reset terminal Trst1 and a second reset terminal Trst2.

[1136] As shown in Figure 39, at least one embodiment of the driving module may include a multi-stage driving circuit;

[1137] The circuit labeled GA1 is the first-stage drive circuit, the circuit labeled GA2 is the second-stage drive circuit, the circuit labeled GAa-1 is the (a-1)th-stage drive circuit, and the circuit labeled GAa is the a-th-stage drive circuit.

[1138] The circuit labeled GAa×n-a+1 is the a×n-a+1 level drive circuit, the circuit labeled GAa×n-a+2 is the a×n-a+2 level drive circuit, the circuit labeled GAa×n-1 is the a×n-1 level drive circuit, and the circuit labeled GAa×n is the a×n level drive circuit.

[1139] The first reset terminal of the multi-stage driving circuit is electrically connected to the frame reset terminal Strst.

[1140] The second reset terminals of GA1, GA2, GAa-1, and GAa are all electrically connected to the first control drive signal output terminal GS1.

[1141] The second reset terminals of GAa×n-a+1, GAa×n-a+2, GAa×n-1, and GAa×n are all electrically connected to the nth control drive signal output terminal GSn.

[1142] The second output terminal of GA1 is electrically connected to the first drive signal output terminal SG1;

[1143] The second output terminal of GA2 is electrically connected to the second drive signal output terminal SG2;

[1144] The second output terminal of GA a-1 is electrically connected to the (a-1)th drive signal output terminal SGa-1;

[1145] The second output terminal of GA a is electrically connected to the a-th drive signal output terminal SGa;

[1146] The second output terminal of GAa×n-a+1 is electrically connected to the a×n-a+1th drive signal output terminal SGa×n-a+1.

[1147] The second output terminal of GAa×n-a+2 is electrically connected to the a×n-a+2th drive signal output terminal SGa×n-a+2.

[1148] The second output terminal of GAa×n-1 is electrically connected to the a×n-1th drive signal output terminal SGa×n-1;

[1149] The second output terminal of GAa×n is electrically connected to the a×nth drive signal output terminal SGa×n;

[1150] The input signal terminal of GA1 is electrically connected to the start signal terminal STV;

[1151] The sixth node of GA1 is electrically connected to the input signal terminal of GA2;

[1152] The sixth node of GA a-1 is electrically connected to the input signal terminal of GA a;

[1153] The sixth node of GAa×n-a+1 is electrically connected to the input signal terminal of GAa×n-a+2;

[1154] The sixth node of GAa×n-1 is electrically connected to the input signal terminal of GAa×n.

[1155] In at least one embodiment of the driving module shown in Figure 39, the second reset signal of the second reset terminal of the multi-level adjacent driving circuits is provided by the corresponding driving signal output terminal, wherein the number of driving circuits electrically connected to the same driving signal output terminal does not exceed the number of rows corresponding to the blanking time.

[1156] In at least one embodiment of the drive module shown in Figure 39, each stage of the drive circuit employs a first reset terminal Trst1 and a second reset terminal Trst2.

[1157] As shown in Figure 40, at least one embodiment of the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a storage capacitor Cst.

[1158] The gate of T1 is electrically connected to the first reset terminal RST1, the source of T1 is electrically connected to the first initial voltage terminal I1, and the drain of T1 is electrically connected to the first node N1.

[1159] The gate of T2 is electrically connected to the first scan terminal NGT, the source of T2 is electrically connected to the fifth node N5, and the drain of T2 is electrically connected to the third node N3.

[1160] The gate of T3 is electrically connected to the first node N1, the source of T3 is electrically connected to the second node N2, and the drain of T3 is electrically connected to the third node N3.

[1161] The gate of T4 is electrically connected to the second scan terminal PGT, the source of T4 is electrically connected to the data line DL, and the drain of T4 is electrically connected to the second node N2.

[1162] The gate of T5 is electrically connected to the first light-emitting control terminal EM1, the source of T5 is electrically connected to the power supply voltage terminal VDD, and the drain of T5 is electrically connected to the second node N2.

[1163] The gate of T6 is electrically connected to the second light-emitting control terminal EM2, the source of T6 is electrically connected to the third node N3, the drain of T6 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[1164] The gate of T7 is electrically connected to the second reset terminal RST2, the source of T7 is electrically connected to the second initial voltage terminal I2, the drain of T7 is electrically connected to the fourth node N4, and the anode of O1 is electrically connected to N4.

[1165] The gate of T8 is electrically connected to the third reset terminal RST3, the source of T8 is electrically connected to the third initial voltage terminal I3, and the drain of T8 is electrically connected to the second node N2.

[1166] The gate of T9 is electrically connected to the second scan terminal PGT, the source of T9 is electrically connected to the first node N1, and the drain of T9 is electrically connected to the fifth node N5.

[1167] The first end of Cst is electrically connected to the first node N1, and the second end of Cst is electrically connected to the power supply voltage terminal VDD.

[1168] T1 and T2 are n-type transistors, and T3-T9 are p-type transistors.

[1169] Figure 41 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 40.

[1170] As shown in Figure 41, in at least one embodiment of the pixel circuit shown in Figure 40, the display cycle includes sequential settings during operation;

[1171] During the initialization phase S1, EM1 and EM2 provide high voltage signals, NGT provides a low voltage signal, PGT provides a high voltage signal, RST1 provides a low voltage signal, and RST2 and RST3 output low voltage signals sequentially. When RST2 outputs a low voltage signal, T7 turns on, I2 provides a second initial voltage Vinit2 to N4, T8 turns on, and I3 provides a third initial voltage Vinit3 to N2.

[1172] During the write phase S2, when PGT provides a low voltage signal, T4 turns on, and DL provides the data voltage Vdata to N2.

[1173] During the write phase S2 and the first reset phase S3, when RST1 provides a high voltage signal, T1 is turned on, and I1 provides the first initial voltage Vinit1 to N5.

[1174] During the compensation phase S4, NGT provides a high voltage signal, T2 is turned on, and N5 and N3 are connected; when PGT provides a low voltage signal, T9 and T4 are turned on, and DL provides the data voltage Vdata to N2; T3 is turned on, and Vdata charges Cst through T4, T3, T2 and T9 until T3 is turned off. At this time, the potential of N1 is Vdata + Vth3, and Vth3 is the threshold voltage of T3.

[1175] In the second reset phase S5, when RST2 outputs a low voltage signal, T7 turns on, I2 provides the second initial voltage Vinit2 to N4, T8 turns on, and I3 provides the third initial voltage Vinit3 to N2; if Vinit3 is greater than Vdata, then the potential of N3 is Vinit3 + Vth3, otherwise the potential of N3 remains unchanged.

[1176] In the third reset phase S6, EM1 provides a low voltage signal, T5 is turned on. If the voltage value Vdd of the power supply voltage signal provided by VDD is greater than Vdata, then the potential of N3 is Vdd+Vth3. Otherwise, the potential of N3 remains unchanged.

[1177] During the light-emitting stage S7, both EM1 and EM2 provide low voltage signals, T5 and T6 are turned on, and T3 drives O1 to emit light; the light-emitting current is determined by the potentials of N1 and N2, where the potential of N1 is Vdata+Vth3 and the potential of N2 is Vdd, then Id is K×(Vdata-Vdd)2; K is the current coefficient of T3, and Id is the light-emitting current.

[1178] The display device described in this disclosure includes the driving module described above.

[1179] The display device described in at least one embodiment of this disclosure further includes a control drive signal generation module; the control drive signal generation module includes a multi-level control drive signal generation circuit;

[1180] The m-th stage control drive signal generation circuit includes a first generation transmission gate, a second generation transmission gate, a NOR gate, a first generation inverter, a second generation inverter, and a third generation inverter.

[1181] The input terminal of the m-th level first generation transmission gate is electrically connected to the m-th level generation input terminal, the output terminal of the m-th level first generation transmission gate is electrically connected to the first input terminal of the m-th level generation NOR gate, the positive phase control terminal of the m-th level first generation transmission gate is electrically connected to the first drive control clock signal terminal, and the negative phase control terminal of the m-th level first generation transmission gate is electrically connected to the second drive control clock signal terminal.

[1182] The input terminal of the m-th stage second generation transmission gate is electrically connected to the output terminal of the m-th stage first generation transmission gate, the output terminal of the m-th stage second generation transmission gate is electrically connected to the output terminal of the m-th stage first generation inverter, the non-inverting control terminal of the m-th stage second generation transmission gate is electrically connected to the second drive control clock signal terminal, and the inverting control terminal of the m-th stage second generation transmission gate is electrically connected to the first drive control clock signal terminal.

[1183] The second input terminal of the m-th generation NOR gate is electrically connected to the third reset terminal, and the output terminal of the m-th generation NOR gate is electrically connected to the input terminal of the m-th stage second generation inverter.

[1184] The output terminal of the m-th stage second generating inverter is electrically connected to the input terminal of the m-th stage third generating inverter, and the output terminal of the m-th stage third generating inverter is electrically connected to the m-th control drive signal output terminal.

[1185] m is a positive integer.

[1186] As shown in Figure 42, at least one embodiment of the m-th stage control drive signal generation circuit includes a first generation transmission gate Ts1, a second generation transmission gate Ts2, a NOR gate NORs, a first generation inverter F1, a second generation inverter F2, and a third generation inverter F3.

[1187] The input terminal of the m-th stage first generation transmission gate Ts1 is electrically connected to the m-th stage generation input terminal NGI, the output terminal of the m-th stage first generation transmission gate Ts1 is electrically connected to the first input terminal of the m-th stage generation NOR gate NORs, the non-inverting control terminal of the m-th stage first generation transmission gate Ts1 is electrically connected to the first driving control clock signal terminal GCK, and the inverting control terminal of the m-th stage first generation transmission gate Ts1 is electrically connected to the second driving control clock signal terminal GCKB.

[1188] The input terminal of the m-th stage second generation transmission gate Ts2 is electrically connected to the output terminal of the m-th stage first generation transmission gate Ts1, the output terminal of the m-th stage second generation transmission gate Ts2 is electrically connected to the output terminal of the m-th stage first generation inverter F1, the non-inverting control terminal of the m-th stage second generation transmission gate Ts2 is electrically connected to the second drive control clock signal terminal GCKB, and the inverting control terminal of the m-th stage second generation transmission gate Ts2 is electrically connected to the first drive control clock signal terminal GCK.

[1189] The second input terminal of the m-th stage generating NOR gate is electrically connected to the third reset terminal Trst3, and the output terminal of the m-th stage generating NOR gate is electrically connected to the input terminal of the m-th stage second generating inverter F2.

[1190] The output terminal of the m-th stage second inverter F2 is electrically connected to the input terminal of the m-th stage third inverter F3, and the output terminal of the m-th stage third inverter F3 is electrically connected to the m-th control drive signal output terminal NGO.

[1191] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

A driving circuit includes a latch circuit, an input circuit, and a signal output circuit. The input circuit is electrically connected to an input signal terminal, a control clock signal terminal, a first reset terminal, the latch circuit, and the signal output circuit, respectively. Under the control of a control clock signal provided by the control clock signal terminal and a first reset signal provided by the first reset terminal, the input circuit, the latch circuit, and the signal output circuit, the input circuit provides an output control signal and an inverted output signal based on the input signal provided by the input signal terminal. The latch circuit is electrically connected to a second reset terminal, the input circuit, an enable terminal, and the signal output circuit, respectively. Under the control of a second reset signal provided by the second reset terminal and a signal provided by the input circuit, the input circuit provides an enable signal to the signal output circuit. The signal output circuit is electrically connected to a first output terminal, and generates and provides a first output signal through the first output terminal based on the signal provided by the input circuit and the signal provided by the latch circuit. The driving circuit as described in claim 1, wherein, The latching circuit includes a first NOR gate, a second NOR gate, and a first transmission gate; the first input terminal of the first NOR gate is electrically connected to the second reset terminal, the second input terminal of the first NOR gate is electrically connected to the second node, and the output terminal of the first NOR gate is electrically connected to the first node; the first input terminal of the second NOR gate is electrically connected to the first node, the second input terminal of the second NOR gate is electrically connected to the fifth node, and the output terminal of the second NOR gate is electrically connected to the second node; the input terminal of the first transmission gate is electrically connected to the enable terminal, the output terminal of the first transmission gate is electrically connected to the third node, the positive phase control terminal of the first transmission gate is electrically connected to the first node, and the negative phase control terminal of the first transmission gate is electrically connected to the second node. The driving circuit as described in claim 2, wherein, The input circuit includes a second transmission gate, a third NOR gate, a third transmission gate, and a first inverter; The control clock signal terminal includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal; the input terminal of the second transmission gate is electrically connected to the input signal terminal, the output terminal of the second transmission gate is electrically connected to the fourth node, the positive phase control terminal of the second transmission gate is electrically connected to the fourth clock signal terminal, and the inverting phase control terminal of the second transmission gate is electrically connected to the third clock signal terminal; the first input terminal of the third NOR gate is electrically connected to the first reset terminal, the second input terminal of the third NOR gate is electrically connected to the fourth node, and the output terminal of the third NOR gate is electrically connected to the fifth node; the input terminal of the third transmission gate is electrically connected to the fourth node, the output terminal of the third transmission gate is electrically connected to the sixth node, the positive phase control terminal of the third transmission gate is electrically connected to the second clock signal terminal, and the inverting phase control terminal of the third transmission gate is electrically connected to the first clock signal terminal; the input terminal of the first inverter is electrically connected to the fifth node, and the output terminal of the first inverter is electrically connected to the sixth node. The driving circuit as described in claim 3, wherein, The signal output circuit includes a fourth NOR gate; the first input terminal of the fourth NOR gate is electrically connected to the sixth node, the second input terminal of the fourth NOR gate is electrically connected to the third node, and the output terminal of the fourth NOR gate is electrically connected to the first output terminal. The driving circuit as described in claim 3, wherein, The signal output circuit includes a first NAND gate; the first input terminal of the first NAND gate is electrically connected to the fifth node, the second input terminal of the first NAND gate is electrically connected to the third node, and the output terminal of the first NAND gate is electrically connected to the first output terminal. The driving circuit as described in claim 4, wherein, The fourth NOR gate also includes a third input terminal, which is electrically connected to the control clock signal terminal. The driving circuit as described in claim 1, wherein, It also includes a drive enhancement circuit; the drive enhancement circuit includes N-stage output inverters; N is an integer greater than 1; the input terminal of the first output inverter is electrically connected to the first output terminal; the output terminal of the nth output inverter is electrically connected to the input terminal of the (n+1)th output inverter, and the output terminal of the Nth output inverter is electrically connected to the drive signal output terminal; n is a positive integer less than N; the output inverter is used to invert the signal input to its input terminal, generate and provide the inverted signal through the output terminal of the output inverter. The driving circuit as described in claim 7, wherein, The driving circuit includes multiple driving enhancement circuits; at least one of the multiple driving enhancement circuits is used to provide a driving output signal. At least one of the plurality of drive enhancement circuits is used to provide an inverted drive output signal; the drive output signal is inverted compared to the inverted drive output signal. The driving circuit as described in claim 1, wherein, The signal output circuit is also electrically connected to the control clock signal terminal, and is used to generate and provide a first output signal through the first output terminal under the control of the control clock signal provided by the control clock signal terminal, the signal provided by the input circuit and the signal provided by the latch circuit. The driving circuit as described in claim 1, wherein, The first reset terminal and the second reset terminal are the same reset terminal. The driving circuit according to any one of claims 1 to 10, wherein, The latching circuit is used to transmit the enable signal provided by the enable terminal to the third node within one frame, from the time point when the second reset terminal starts to provide a valid second reset signal to the time point when the first control terminal first starts to provide a valid first control signal. After the time point when the first control terminal first starts to provide a valid first control signal, the control starts latching and stops transmitting the enable signal to the third node. A driving circuit includes a latching circuit, an input circuit, a control circuit, and a signal output circuit. The input circuit is electrically connected to an input signal terminal, a control clock signal terminal, and the control circuit, respectively, and is used to provide an inverted output signal based on an input signal provided by the input signal terminal under the control of a control clock signal provided by the control clock signal terminal. The control circuit is electrically connected to a first reset terminal and is used to provide an output control signal under the control of a first reset signal provided by the first reset terminal and the inverted output signal. The latching circuit is electrically connected to a second reset terminal, an enable terminal, the input circuit, the control circuit, and the signal output circuit, respectively, and is used to transmit an enable signal provided by the enable terminal to the signal output circuit under the control of a second reset signal provided by the second reset terminal and a signal provided by the control circuit. The signal output circuit is electrically connected to the control circuit and a first output terminal, and is used to generate and provide a first output signal through the first output terminal based on the output control signal and the signal provided by the latching circuit. The driving circuit as described in claim 12, wherein, The latching circuit includes a first NAND gate, a second NAND gate, and a first transmission gate; the first input terminal of the first NAND gate is electrically connected to the sixth node, the second input terminal of the first NAND gate is electrically connected to the first node, and the output terminal of the first NAND gate is electrically connected to the second node; the first input terminal of the second NAND gate is electrically connected to the second node, the second input terminal of the second NAND gate is electrically connected to the second reset terminal, and the output terminal of the second NAND gate is electrically connected to the first node; the input terminal of the first transmission gate is electrically connected to the enable terminal, the output terminal of the first transmission gate is electrically connected to the third node, the positive phase control terminal of the first transmission gate is electrically connected to the first node, and the inverting phase control terminal of the first transmission gate is electrically connected to the second node. The driving circuit as described in claim 12, wherein, The latching circuit includes a first NOR gate, a second NOR gate, and a first transmission gate; the first input terminal of the first NOR gate is electrically connected to the sixth node, the second input terminal of the first NOR gate is electrically connected to the second node, and the output terminal of the first NOR gate is electrically connected to the first node; the first input terminal of the second NOR gate is electrically connected to the first node, the second input terminal of the second NOR gate is electrically connected to the second reset terminal, and the output terminal of the second NOR gate is electrically connected to the second node; the input terminal of the first transmission gate is electrically connected to the enable terminal, the output terminal of the first transmission gate is electrically connected to the third node, the positive phase control terminal of the first transmission gate is electrically connected to the first node, and the inverting phase control terminal of the first transmission gate is electrically connected to the second node. The driving circuit as described in claim 13, wherein, The input circuit includes a second transmission gate, a first inverter, a third transmission gate, and a second inverter; The control clock signal terminal includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal; the input terminal of the second transmission gate is electrically connected to the input signal terminal, the output terminal of the second transmission gate is electrically connected to the fourth node, the inverting control terminal of the second transmission gate is electrically connected to the fourth clock signal terminal, and the inverting control terminal of the second transmission gate is electrically connected to the third clock signal terminal; the input terminal of the third transmission gate is electrically connected to the fourth node, the output terminal of the third transmission gate is electrically connected to the output terminal of the second inverter, the inverting control terminal of the third transmission gate is electrically connected to the second clock signal terminal, and the inverting control terminal of the third transmission gate is electrically connected to the first clock signal terminal; the input terminal of the first inverter is electrically connected to the fourth node, the output terminal of the first inverter is electrically connected to the fifth node; and the input terminal of the second inverter is electrically connected to the fifth node. The driving circuit as described in claim 13, wherein, The control circuit includes a third NAND gate; the first input terminal of the third NAND gate is electrically connected to the first reset terminal, the second input terminal of the third NAND gate is electrically connected to the fifth node, and the output terminal of the third NAND gate is electrically connected to the sixth node. The driving circuit as described in claim 13, wherein, The signal output circuit includes a first NOR gate; the first input terminal of the first NOR gate is electrically connected to the sixth node, the second input terminal of the first NOR gate is electrically connected to the third node, and the output terminal of the first NOR gate is electrically connected to the first output terminal. The driving circuit as described in claim 13, wherein, The signal output circuit includes a first NOR gate; the first input terminal of the first NOR gate is electrically connected to the output control clock signal terminal, the second input terminal of the first NOR gate is electrically connected to the sixth node, the third input terminal of the first NOR gate is electrically connected to the third node, and the output terminal of the first NOR gate is electrically connected to the first output terminal. The driving circuit as described in claim 14, wherein, The input circuit includes a second transmission gate, a third transmission gate, a first inverter, and a second inverter; The control clock signal terminal includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal; the input terminal of the second transmission gate is electrically connected to the input signal terminal, the output terminal of the second transmission gate is electrically connected to the fourth node, the inverting control terminal of the second transmission gate is electrically connected to the fourth clock signal terminal, and the inverting control terminal of the second transmission gate is electrically connected to the third clock signal terminal; the input terminal of the third transmission gate is electrically connected to the fourth node, the output terminal of the third transmission gate is electrically connected to the output terminal of the second inverter, the inverting control terminal of the third transmission gate is electrically connected to the second clock signal terminal, and the inverting control terminal of the third transmission gate is electrically connected to the first clock signal terminal; the input terminal of the first inverter is electrically connected to the fourth node, the output terminal of the first inverter is electrically connected to the fifth node; and the input terminal of the second inverter is electrically connected to the fifth node. The driving circuit as described in claim 14, wherein, The control circuit includes a third NOR gate; the first input terminal of the third NOR gate is electrically connected to the first reset terminal, the second input terminal of the third NOR gate is electrically connected to the fifth node, and the output terminal of the third NAND gate is electrically connected to the sixth node. The driving circuit as described in claim 14, wherein, The signal output circuit includes a first NAND gate; the first input terminal of the first NAND gate is electrically connected to the sixth node, the second input terminal of the first NAND gate is electrically connected to the third node, and the output terminal of the first NAND gate is electrically connected to the first output terminal. The driving circuit as described in claim 14, wherein, The signal output circuit includes a first NAND gate; the first input terminal of the first NAND gate is electrically connected to the output control clock signal terminal, the second input terminal of the first NAND gate is electrically connected to the sixth node, the third input terminal of the first NAND gate is electrically connected to the third node, and the output terminal of the first NAND gate is electrically connected to the first output terminal. The driving circuit as described in claim 12, wherein, It also includes a drive enhancement circuit; the drive enhancement circuit includes N-stage output inverters; N is an integer greater than 1; the input terminal of the first output inverter is electrically connected to the first output terminal; the output terminal of the nth output inverter is electrically connected to the input terminal of the (n+1)th output inverter, and the output terminal of the Nth output inverter is electrically connected to the drive signal output terminal; n is a positive integer less than N; the output inverter is used to invert the signal input to its input terminal, generate and provide the inverted signal through the output terminal of the output inverter. The driving circuit as described in claim 23, wherein, The driving circuit includes multiple driving enhancement circuits; at least one of the multiple driving enhancement circuits is used to provide a driving output signal. At least one of the plurality of drive enhancement circuits is used to provide an inverted drive output signal; the drive output signal is inverted compared to the inverted drive output signal. The driving circuit as described in claim 12, wherein, The signal output circuit is also electrically connected to the output control clock signal terminal, and is used to generate and provide a first output signal through the first output terminal under the control of the output control clock signal provided by the output control clock signal terminal, the output control signal, and the signal provided by the latch circuit. The driving circuit as described in claim 12, wherein, The first reset terminal and the second reset terminal are the same reset terminal. The driving circuit according to any one of claims 12 to 26, wherein, The latching circuit is used to transmit the enable signal provided by the enable terminal to the third node within one frame, between the time point when the second reset terminal starts to provide a valid second reset signal and the time point when the first control terminal first starts to provide a valid first control signal. After the time point when the first control terminal first starts to provide a valid first control signal, the control starts latching and stops transmitting the enable signal to the third node. A driving method, applied to the driving circuit as described in any one of claims 1 to 27, wherein, The driving method includes: within one frame, between the time point when the second reset terminal begins to provide a valid second reset signal and the time point when the first control terminal first begins to provide a valid first control signal, the latch circuit transmits the enable signal provided by the enable terminal to the third node; after the time point when the first control terminal first begins to provide a valid first control signal, the latch circuit controls the start of latching and stops transmitting the enable signal to the third node. A driving module includes multiple driving circuits as described in any one of claims 1 to 27; the input signal terminal of the first-stage driving circuit is electrically connected to the starting signal terminal, and the sixth node of the nth-stage driving circuit is electrically connected to the input signal terminal of the (n+1)th driving circuit, where n is a positive integer. The drive module as described in claim 29, wherein, The first reset terminal and the second reset terminal are the same reset terminal; the reset terminals of the multi-stage drive circuit are all electrically connected to the frame reset terminal. The drive module as described in claim 29, wherein, The first reset terminal and the second reset terminal are the same reset terminal; the driving module also includes multiple control transmission gates and multiple generation control clock signal terminals; the reset terminal of the first-stage driving circuit is electrically connected to the frame reset terminal; the reset terminal of the m-th stage driving circuit is electrically connected to the output terminal of the (m-1)-th control transmission gate, the input terminal of the (m-1)-th control transmission gate is electrically connected to the second node in the (m-1)-th stage driving circuit, the positive phase control terminal of the (m-1)-th control transmission gate is electrically connected to the first generation control clock signal terminal, and the inverting phase control terminal of the (m-1)-th control transmission gate is electrically connected to the second generation control clock signal terminal; m is an integer greater than 1. The drive module as described in claim 29, wherein, The first reset terminal and the second reset terminal are the same reset terminal; the reset terminal of the nth drive circuit is electrically connected to the nth control drive signal output terminal. The drive module as described in claim 29, wherein, The driving module further includes multiple control transmission gates and multiple generation control clock signal terminals; the first reset terminal of the multi-stage driving circuit is electrically connected to the frame reset terminal; the second reset terminal of the first-stage driving circuit is electrically connected to the frame reset terminal; the second reset terminal of the m-th stage driving circuit is electrically connected to the output terminal of the (m-1)-th control transmission gate, the input terminal of the (m-1)-th control transmission gate is electrically connected to the second node in the (m-1)-th stage driving circuit, the positive phase control terminal of the (m-1)-th control transmission gate is electrically connected to the first generation control clock signal terminal, and the inverting phase control terminal of the (m-1)-th control transmission gate is electrically connected to the second generation control clock signal terminal; m is an integer greater than 1. The drive module as described in claim 29, wherein, The first reset terminal of the multi-stage drive circuit is electrically connected to the frame reset terminal; the second reset terminal of the nth drive circuit is electrically connected to the nth control drive signal output terminal. The drive module as described in claim 29, wherein, The first reset terminal of the multi-stage drive circuit is electrically connected to the frame reset terminal; the second reset terminals of the a×n-a+1th stage drive circuit to the second reset terminals of the a×nth stage drive circuit are all electrically connected to the nth control drive signal output terminal; a is a positive integer. A display device comprising the driving module as described in any one of claims 29 to 35. The display device as claimed in claim 36, wherein, It also includes a control drive signal generation module; the control drive signal generation module includes a multi-level control drive signal generation circuit; the m-th level control drive signal generation circuit includes a first generation transmission gate, a second generation transmission gate, a NOR gate, a first generation inverter, a second generation inverter, and a third generation inverter. The input terminal of the m-th stage first generation transmission gate is electrically connected to the m-th stage generation input terminal, and the output terminal of the m-th stage first generation transmission gate is electrically connected to the first input terminal of the m-th stage generation NOR gate. The non-inverting control terminal of the m-th stage first generation transmission gate is electrically connected to the first driving control clock signal terminal, and the inverting control terminal of the m-th stage first generation transmission gate is electrically connected to the second driving control clock signal terminal. The input terminal of the m-th stage second generation transmission gate is electrically connected to the output terminal of the m-th stage first generation transmission gate, and the output terminal of the m-th stage second generation transmission gate is electrically connected to the output terminal of the m-th stage first generation inverter. The non-inverting control terminal of the m-th stage second generation transmission gate is electrically connected to the second driving control clock signal terminal, and the inverting control terminal of the m-th stage second generation transmission gate is electrically connected to the first driving control clock signal terminal. The second input terminal of the m-th stage generation NOR gate is electrically connected to the third reset terminal, and the output terminal of the m-th stage generation NOR gate is electrically connected to the input terminal of the m-th stage second generation inverter. The output terminal of the m-th stage second generator inverter is electrically connected to the input terminal of the m-th stage third generator inverter, and the output terminal of the m-th stage third generator inverter is electrically connected to the m-th control drive signal output terminal; m is a positive integer.

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