Pixel circuit, pixel driving method and display device

Abstract

The invention provides a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a light-emitting element, a driving circuit and a driving control circuit. The drive circuit controls the connection and disconnection between the first node and the second node under the control of the potential of the control node; the pixel circuit further comprises a first control circuit and / or a second control circuit; the first control circuit controls connection and disconnection between the power supply voltage end and the first node according to the first control signal; the second control circuit controls connection and disconnection between the second node and the first electrode of the light-emitting element according to the second control signal. According to the pixel circuit provided by the embodiment of the invention, the working mode of the first control circuit and / or the second control circuit is changed, so that the potential change of the control node is clear when the sub-frame state is switched, and large leakage current and power consumption are avoided.

Description

Pixel circuits, pixel driving methods, and display devices

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device.

[0002] In related technologies, LEDs (Light Emitting Diodes) offer higher brightness and reliability compared to OLEDs (Organic Light Emitting Diodes). For near-eye display products such as head-mounted displays, if OLEDs are used as pixels, their brightness is only in the thousands of nits, which is only suitable for use in enclosed, dark environments. LEDs, on the other hand, can provide much higher brightness, but correspondingly, they require a larger current. If analog circuits such as driver transistors are used to control the brightness of LEDs, the driver transistors typically need to operate in a constant current state, requiring a source-drain voltage difference of over 1V, which results in significant power consumption. However, if digital circuits such as MOS (Metal-Oxide-Semiconductor) switches are used to control the brightness of LEDs, the source-drain voltage difference of the MOS switches is 0.2V or less, which can greatly reduce power consumption.

[0003]

[0004] In one aspect, embodiments of this disclosure provide a pixel circuit, including a light-emitting element, a driving circuit, and a driving control circuit;

[0005] The control terminal of the drive circuit is electrically connected to the control node, the first terminal of the drive circuit is electrically connected to the first node, and the second terminal of the drive circuit is electrically connected to the second node. The drive circuit is used to control the on / off connection between the first node and the second node under the control of the potential of the control node.

[0006] The drive control circuit is electrically connected to the drive control terminal, the data line and the control node respectively, and is used to control the potential of the control node according to the data voltage provided by the data line under the control of the drive control signal provided by the drive control terminal.

[0007] The pixel circuit further includes a first control circuit and / or a second control circuit;

[0008] The first control circuit is electrically connected to the first control terminal, the power supply voltage terminal and the first node respectively, and is used to control the on / off connection between the power supply voltage terminal and the first node according to the first control signal provided by the first control terminal;

[0009] The second control circuit is electrically connected to the second control terminal, the second node, and the first electrode of the light-emitting element, respectively, and is used to control the on / off connection between the second node and the first electrode of the light-emitting element according to the second control signal provided by the second control terminal;

[0010] The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0011] In at least one embodiment of this disclosure, the drive control circuit includes a data writing circuit and a latching circuit; the drive control terminal includes a first scanning terminal, and the data line includes a first data line and a second data line;

[0012] The data writing circuit is electrically connected to the first scanning end, the first data line, the second data line, the first writing node, and the second writing node, respectively, and is used to write the first data voltage provided by the first data line to the first writing node and the second data voltage provided by the second data line to the second writing node under the control of the first scanning signal provided by the first scanning end; the second writing node is electrically connected to the control node;

[0013] The latching circuit is electrically connected to the first write node, the second write node, the second voltage terminal, and the third voltage terminal, respectively. It is used to control the writing of the second voltage signal provided by the second voltage terminal or the third voltage signal provided by the third voltage terminal to the second write node under the control of the potential of the first write node, and to write the third voltage signal or the second voltage signal to the first write node under the control of the potential of the second write node.

[0014] In at least one embodiment of this disclosure, the drive control circuit includes a data writing circuit, an inverter, and a storage circuit; the drive control terminal includes a first scanning terminal and a second scanning terminal, and the data line includes a first data line;

[0015] The data writing circuit is electrically connected to the first scanning end, the second scanning end, the first data line and the writing node, respectively, and is used to write the first data voltage provided by the first data line into the writing node under the control of the first scanning signal provided by the first scanning end and the second scanning signal provided by the second scanning end;

[0016] The storage circuit is electrically connected to the write node and is used to maintain the potential of the write node;

[0017] The inverter is electrically connected to both the write node and the control node, and is used to invert the potential of the write node to obtain the potential of the control node.

[0018] In at least one embodiment of this disclosure, the drive control circuit includes a data writing circuit and a storage circuit; the drive control terminal includes a first scanning terminal and a second scanning terminal, and the data line includes a first data line;

[0019] The data writing circuit is electrically connected to the first scanning end, the second scanning end, the first data line and the control node respectively, and is used to write the first data voltage provided by the first data line into the control node under the control of the first scanning signal provided by the first scanning end and the second scanning signal provided by the second scanning end;

[0020] The storage circuit is electrically connected to the control node and is used to maintain the potential of the control node.

[0021] In at least one embodiment of this disclosure, the data writing circuit includes a first transistor and a second transistor, and the latching circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0022] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the first write node.

[0023] The gate of the second transistor is electrically connected to the first scan terminal, the first terminal of the second transistor is electrically connected to the second data line, and the second terminal of the second transistor is electrically connected to the second write node.

[0024] The gate of the third transistor is electrically connected to the second write node, the first terminal of the third transistor is electrically connected to the second voltage terminal, and the second terminal of the third transistor is electrically connected to the first write node.

[0025] The gate of the fourth transistor is electrically connected to the second write node, the first terminal of the fourth transistor is electrically connected to the first write node, and the second terminal of the fourth transistor is electrically connected to the third voltage terminal.

[0026] The gate of the fifth transistor is electrically connected to the first write node, the first terminal of the fifth transistor is electrically connected to the second voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second write node.

[0027] The gate of the sixth transistor is electrically connected to the first write node, the first terminal of the sixth transistor is electrically connected to the second write node, and the second terminal of the sixth transistor is electrically connected to the third voltage terminal.

[0028] A pixel circuit provided in this disclosure includes a first control circuit;

[0029] The first control circuit includes a seventh transistor;

[0030] The gate of the seventh transistor is electrically connected to the first scanning terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first node.

[0031] In at least one embodiment of this disclosure, the first transistor is a P-type transistor, the second transistor is a P-type transistor, the third transistor and the fifth transistor are P-type transistors, and the fourth transistor and the sixth transistor are N-type transistors; the seventh transistor is an N-type transistor; the driving circuit includes a driving switch transistor that is an N-type transistor; or,

[0032] The first transistor is an N-type transistor, the second transistor is an N-type transistor, the third and fifth transistors are P-type transistors, the fourth and sixth transistors are N-type transistors, and the seventh transistor is a P-type transistor; the driving switch transistor is a P-type transistor.

[0033] In at least one embodiment of this disclosure, the data writing circuit includes a first transistor and a second transistor;

[0034] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the write node.

[0035] The gate of the second transistor is electrically connected to the second scan terminal, the first terminal of the second transistor is electrically connected to the first data line, and the second terminal of the second transistor is electrically connected to the write node.

[0036] A pixel circuit provided in this disclosure includes a first control circuit;

[0037] The first control circuit includes a seventh transistor;

[0038] The gate of the seventh transistor is electrically connected to the first scan terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first node.

[0039] In at least one embodiment of this disclosure, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the seventh transistor is an N-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor.

[0040] An embodiment of this disclosure provides a pixel circuit including a second control circuit;

[0041] The second control circuit includes an eighth transistor;

[0042] The gate of the eighth transistor is electrically connected to the second scanning terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0043] The first transistor is a P-type transistor, the second transistor is an N-type transistor, the eighth transistor is a P-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor.

[0044] In at least one embodiment of this disclosure, the data writing circuit includes a first transistor and a second transistor;

[0045] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the write node.

[0046] The gate of the second transistor is electrically connected to the second scan terminal, the first terminal of the second transistor is electrically connected to the first data line, and the second terminal of the second transistor is electrically connected to the write node.

[0047] The pixel circuit includes a first control circuit;

[0048] The first control circuit includes a seventh transistor;

[0049] The gate of the seventh transistor is electrically connected to the first scan terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first node.

[0050] In at least one embodiment of this disclosure, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the seventh transistor is an N-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor.

[0051] In at least one embodiment of this disclosure, the data writing circuit includes a first transistor and a second transistor;

[0052] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the write node.

[0053] The gate of the second transistor is electrically connected to the second scan terminal, the first terminal of the second transistor is electrically connected to the first data line, and the second terminal of the second transistor is electrically connected to the write node.

[0054] The pixel circuit includes a second control circuit;

[0055] The second control circuit includes an eighth transistor;

[0056] The gate of the eighth transistor is electrically connected to the second scanning terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0057] In at least one embodiment of this disclosure, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the eighth transistor is a P-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor.

[0058] In a second aspect, embodiments of this disclosure provide a pixel driving method applied to the aforementioned pixel circuit, the pixel driving method comprising:

[0059] Under the control of the drive control signal, the drive control circuit controls the potential of the control node according to the data voltage provided by the data line;

[0060] The first control circuit, under the control of the first control signal, controls the connection or disconnection between the power supply voltage terminal and the first node; and / or, the second control circuit, under the control of the second control signal, controls the connection or disconnection between the second node and the first electrode of the light-emitting element.

[0061] The drive circuit controls the connection and disconnection between the first node and the second node under the control of the potential of the control node.

[0062] In at least one embodiment of this disclosure, the display cycle includes N display stages, and the nth display stage includes the nth writing time period and the nth emission time period; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0063] During the nth write time period, the drive control circuit, under the control of the drive control signal, controls the potential of the control node according to the data voltage provided by the data line;

[0064] During the nth emission period, the driving control circuit maintains the potential of the control node, and under the control of the potential of the control node, the driving circuit controls the switching between the first node and the second node.

[0065] In at least one embodiment of this disclosure, the pixel circuit includes a first control circuit, and the pixel driving method further includes:

[0066] During the nth write time period, the first control circuit, under the control of the first control signal, controls the power supply voltage terminal to disconnect from the first node;

[0067] During the nth emission period, the first control circuit, under the control of the first control signal, controls the connection between the power supply voltage terminal and the first node.

[0068] In at least one embodiment of this disclosure, the pixel circuit includes a second control circuit, and the pixel driving method further includes:

[0069] During the nth writing time period, the second control circuit, under the control of the second control signal, controls the second node to disconnect from the first electrode of the light-emitting element;

[0070] During the nth emission period, the second control circuit, under the control of the second control signal, controls the connection between the second node and the first electrode of the light-emitting element.

[0071] In at least one embodiment of this disclosure, the durations of at least two of the said luminescence time periods are different from each other.

[0072] In at least one embodiment of this disclosure, the duration of the N light-emitting time periods included in the display cycle is different for each other.

[0073] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above.

[0074] Figure 1A is an equivalent circuit diagram of a digital circuit in the related technology;

[0075] Figure 1B is a structural diagram of a pixel circuit provided in an embodiment of this disclosure;

[0076] Figure 2 is a structural diagram of a pixel circuit provided in an embodiment of this disclosure;

[0077] Figure 3 is a structural diagram of a pixel circuit provided in an embodiment of this disclosure;

[0078] Figure 4 is a structural diagram of a pixel circuit provided in an embodiment of this disclosure;

[0079] Figure 5 is a structural diagram of a pixel circuit provided in an embodiment of this disclosure;

[0080] Figure 6 is a structural diagram of a pixel circuit provided in an embodiment of this disclosure;

[0081] Figure 7 is a structural diagram of a pixel circuit provided in an embodiment of this disclosure;

[0082] Figure 8 is a structural diagram of a pixel circuit provided in an embodiment of this disclosure;

[0083] Figure 9 is a structural diagram of a pixel circuit provided in an embodiment of this disclosure;

[0084] Figure 10 is a circuit diagram of a pixel circuit provided in an embodiment of this disclosure;

[0085] Figure 11 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 10;

[0086] Figure 12 is a circuit diagram of a pixel circuit provided in an embodiment of this disclosure;

[0087] Figure 13 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 12;

[0088] Figure 14 is a circuit diagram of a pixel circuit provided in an embodiment of this disclosure;

[0089] Figure 15 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 14;

[0090] Figure 16 is a circuit diagram of a pixel circuit provided in an embodiment of this disclosure;

[0091] Figure 17 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 16;

[0092] Figure 18 is a circuit diagram of a pixel circuit provided in an embodiment of this disclosure;

[0093] Figure 19 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 18;

[0094] Figure 20 is a circuit diagram of a pixel circuit provided in an embodiment of this disclosure;

[0095] Figure 21 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 20.

[0096] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0097] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0098] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0099] As shown in Figure 1A, a digital circuit in the related art includes a driving switching transistor M0, a memory cell, and a grayscale control transistor MS.

[0100] The storage unit includes a first control transistor MC1, a second control transistor MC2, a third control transistor MC3, a fourth control transistor MC4, a fifth control transistor MC5, and a sixth control transistor MC6. The storage unit stores and outputs grayscale signals to the drive switch transistor M0. The grayscale control transistor MS controls the switching of the drive switch transistor M0. MS, M0, MC2, and MC5 are P-type transistors; MC1, MC3, MC4, and MC6 are N-type transistors. The gate of MS is electrically connected to the grayscale control terminal RN. VSS represents the low-level terminal, VDDP represents the high-level terminal, BL represents the first data signal terminal, BL1 represents the second data signal terminal, and GND represents the ground terminal.

[0101] When RN is low, MS is turned on, and the high level provided by VDDD is transmitted to the gate VDR of M0. M0 is turned off, and the light-emitting diode L1 does not emit light. When RN is high, the grayscale control transistor MS is turned off, and the potential of VDR is controlled by the memory cell.

[0102] The pixel circuit shown in Figure 1A has the following problems: In a certain stage, the grayscale control terminal RN is at a high level, the potential of the storage cell control VDR is at a low voltage, and the light-emitting diode L1 emits light; in the next stage, it is desired that the light-emitting diode L1 does not emit light, so RN changes from a high level to a low level. Ideally, the grayscale control transistor MS should provide the high level provided by VDDD to the gate VDR of M0; however, in reality, since the potential of VDR is not pulled up in time, and the sixth control transistor MC6 is still conducting, the potential of VDR is reduced due to the voltage division between the sixth control transistor MC6 and the grayscale control transistor MS. This causes the circuit to generate a large instantaneous current flowing from the high-level terminal VDDD through the grayscale control transistor MS and the sixth control transistor MC6 to the ground terminal GND, thus generating additional power consumption; at the same time, M0 cannot be completely turned off, resulting in leakage current, which in turn generates additional power consumption.

[0103] Furthermore, in the circuit shown in Figure 1A, both the grayscale control transistor MS and the sixth control transistor MC6 affect the potential of the gate VDR of M0, causing uncertainty in the VDR potential. To ensure that the grayscale control transistor MS can successfully pull up the potential of VDR, the channel width-to-length ratio of MS needs to be increased. This will increase the area occupied by the grayscale control transistor MS, resulting in an increase in the space occupied by the circuit, which in turn affects the unit pixel density. Moreover, in this circuit, the grayscale control transistor MS is simultaneously controlled by the grayscale control terminal RN and the high-level terminal VDDD. The parasitic resistance and parasitic capacitance between multiple lines must be considered, which increases the redundancy of wiring space and timing design.

[0104] The pixel circuit described in this embodiment includes a light-emitting element, a driving circuit, and a driving control circuit;

[0105] The control terminal of the drive circuit is electrically connected to the control node, the first terminal of the drive circuit is electrically connected to the first node, and the second terminal of the drive circuit is electrically connected to the second node. The drive circuit is used to control the on / off connection between the first node and the second node under the control of the potential of the control node.

[0106] The drive control circuit is electrically connected to the drive control terminal, the data line and the control node respectively, and is used to control the potential of the control node according to the data voltage provided by the data line under the control of the drive control signal provided by the drive control terminal.

[0107] The pixel circuit further includes a first control circuit and / or a second control circuit;

[0108] The first control circuit is electrically connected to the first control terminal, the power supply voltage terminal and the first node respectively, and is used to control the connection and disconnection between the power supply voltage terminal and the first node under the control of the first control signal provided by the first control terminal;

[0109] The second control circuit is electrically connected to the second control terminal, the second node, and the first electrode of the light-emitting element, respectively, and is used to control the on / off connection between the second node and the first electrode of the light-emitting element under the control of the second control signal provided by the second control terminal;

[0110] The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0111] In the pixel circuit described in this embodiment, the first control circuit and / or the second control circuit are not used to control the potential of the node. The control node is only connected to the drive control circuit. The state switching of the control node is more stable, and there is no leakage current path and power consumption during state switching. By changing the operating mode of the first control circuit and / or the second control circuit, the pixel circuit described in this embodiment makes the potential change of the control node clear during subframe state switching, and there is no large leakage current and power consumption.

[0112] In the pixel circuit described in this embodiment, the first control circuit and / or the second control circuit are connected to the main light-emitting circuit. By controlling the control terminals of the corresponding control circuits through control signals, the main light-emitting circuit can be turned on / off. When the pixel circuit described in this embodiment is working, it first controls the main light-emitting circuit to turn off and controls the input data voltage. After the data voltage input is complete, the drive control circuit is turned off, thus storing the data voltage and turning on the control circuit. This structure eliminates control signal lines, saves the layout area of ​​the pixel circuit, and results in smaller pixel spacing and higher pixel density.

[0113] Optionally, the first voltage terminal can be a low voltage terminal or a ground terminal.

[0114] Optionally, the light-emitting element may be an LED (light-emitting diode), but is not limited thereto.

[0115] Based on the problems existing in the related pixel circuits, in a pixel circuit provided in this disclosure embodiment, the first control circuit and / or the second control circuit are not used to control the potential of the node, the control node is only connected to the drive control circuit, the state switching of the control node is more stable, and there is no leakage path and power consumption during state switching.

[0116] In a pixel circuit provided in this embodiment, the control node is controlled only by the drive control circuit, so that the potential of the control node will not be at an uncertain potential other than high level and low level. This allows the drive switching transistor (the gate of the drive switching transistor is electrically connected to the control node) included in the pixel circuit to operate in the linear region or the cutoff region, thereby improving circuit reliability and reducing power consumption.

[0117] In a pixel circuit provided in this embodiment, the first control circuit and / or the second control circuit are connected to the main light-emitting circuit. By controlling the control terminals of the corresponding control circuits through control signals, the main light-emitting circuit can be turned on / off. When the pixel circuit described in this embodiment is working, it first controls the main light-emitting circuit to turn off and controls the input data voltage. After the data voltage input is complete, the drive control circuit is turned off, thus storing the data voltage and turning on the control circuit. This structure eliminates control signal lines, saves the layout area of ​​the pixel circuit, and results in smaller pixel spacing and higher pixel density.

[0118] As shown in Figure 1B, a pixel circuit provided in this embodiment of the present disclosure includes a light-emitting element E1, a driving circuit 10, and a driving control circuit 11.

[0119] The control terminal of the drive circuit 10 is electrically connected to the control node G. The first terminal of the drive circuit 10 is electrically connected to the first node N1, and the second terminal of the drive circuit is electrically connected to the second node N2. The drive circuit 10 is used to control the on / off state between the first node N1 and the second node N2 under the control of the potential of the control node G.

[0120] The drive control circuit 11 is electrically connected to the drive control terminal GT, the data line DL and the control node G respectively, and is used to control the potential of the control node G according to the data voltage provided by the data line DL under the control of the drive control signal provided by the drive control terminal GT.

[0121] The pixel circuit also includes a first control circuit 21;

[0122] The first control circuit 21 is electrically connected to the first control terminal ST1, the power supply voltage terminal VDD, and the first node N1, respectively, and is used to control the on / off connection between the power supply voltage terminal VDD and the first node N1 under the control of the first control signal provided by the first control terminal ST1.

[0123] The second node N2 is electrically connected to the first electrode of the light-emitting element E1, and the second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0124] As shown in Figure 2, a pixel circuit provided in this embodiment includes a light-emitting element E1, a driving circuit 10, and a driving control circuit 11.

[0125] The control terminal of the drive circuit 10 is electrically connected to the control node G. The first terminal of the drive circuit 10 is electrically connected to the first node N1, and the second terminal of the drive circuit is electrically connected to the second node N2. The drive circuit 10 is used to control the on / off state between the first node N1 and the second node N2 under the control of the potential of the control node G.

[0126] The drive control circuit 11 is electrically connected to the drive control terminal GT, the data line DL and the control node G respectively, and is used to control the potential of the control node G according to the data voltage provided by the data line DL under the control of the drive control signal provided by the drive control terminal GT.

[0127] The pixel circuit also includes a second control circuit 22;

[0128] The second control circuit 22 is electrically connected to the second control terminal ST2, the second node N2 and the first pole of the light-emitting element E1, respectively, and is used to control the on / off connection between the second node N2 and the first pole of the light-emitting element E1 under the control of the second control signal provided by the second control terminal ST2;

[0129] The first node N1 is electrically connected to the power supply voltage terminal VDD; the second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0130] As shown in Figure 3, a pixel circuit provided in this embodiment includes a light-emitting element E1, a driving circuit 10, and a driving control circuit 11.

[0131] The control terminal of the drive circuit 10 is electrically connected to the control node G. The first terminal of the drive circuit 10 is electrically connected to the first node N1, and the second terminal of the drive circuit is electrically connected to the second node N2. The drive circuit 10 is used to control the on / off state between the first node N1 and the second node N2 under the control of the potential of the control node G.

[0132] The drive control circuit 11 is electrically connected to the drive control terminal GT, the data line DL and the control node G respectively, and is used to control the potential of the control node G according to the data voltage provided by the data line DL under the control of the drive control signal provided by the drive control terminal GT.

[0133] The pixel circuit also includes a first control circuit 21;

[0134] The first control circuit 21 is electrically connected to the first control terminal ST1, the power supply voltage terminal VDD, and the first node N1, respectively, and is used to control the on / off connection between the power supply voltage terminal VDD and the first node N1 under the control of the first control signal provided by the first control terminal ST1.

[0135] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1;

[0136] The pixel circuit also includes a second control circuit 22;

[0137] The second control circuit 22 is electrically connected to the second control terminal ST2, the second node N2 and the first pole of the light-emitting element E1, respectively, and is used to control the on / off connection between the second node N2 and the first pole of the light-emitting element E1 under the control of the second control signal provided by the second control terminal ST2.

[0138] In at least one embodiment of this disclosure, the drive control circuit includes a data writing circuit and a latching circuit; the drive control terminal includes a first scanning terminal, and the data line includes a first data line and a second data line;

[0139] The data writing circuit is electrically connected to the first scanning end, the first data line, the second data line, the first writing node, and the second writing node, respectively, and is used to write the first data voltage provided by the first data line to the first writing node and the second data voltage provided by the second data line to the second writing node under the control of the first scanning signal provided by the first scanning end; the second writing node is electrically connected to the control node;

[0140] The latching circuit is electrically connected to the first write node, the second write node, the second voltage terminal, and the third voltage terminal, respectively. It is used to control the writing of the second voltage signal provided by the second voltage terminal or the third voltage signal provided by the third voltage terminal to the second write node under the control of the potential of the first write node, and to write the third voltage signal or the second voltage signal to the first write node under the control of the potential of the second write node.

[0141] In a specific implementation, the drive control circuit may include a data writing circuit and a latching circuit. Under the control of the first scan signal, the data writing circuit writes a first data voltage to the first write node and writes a second data voltage to the second write node. The latching circuit stores the potential of the first write node and the potential of the second write node.

[0142] Optionally, the second voltage terminal can be a power supply voltage terminal, and the third voltage terminal can be a ground terminal or a low voltage terminal.

[0143] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 1B, the driving control circuit includes a data writing circuit 41 and a latching circuit 42; the driving control terminal includes a first scanning terminal G1, and the data lines include a first data line DL1 and a second data line DL2.

[0144] The data writing circuit 41 is electrically connected to the first scanning terminal G1, the first data line DL1, the second data line DL2, the first writing node A, and the second writing node B, respectively. Under the control of the first scanning signal provided by the first scanning terminal G1, it writes the first data voltage Vdata1 provided by the first data line DL1 to the first writing node A, and writes the second data voltage Vdata2 provided by the second data line DL2 to the second writing node B; the second writing node B is electrically connected to the control node G.

[0145] The latch circuit 42 is electrically connected to the first write node A, the second write node B, the second voltage terminal V2, and the third voltage terminal V3, respectively. It is used to control the writing of the second voltage signal provided by the second voltage terminal V2 or the third voltage signal provided by the third voltage terminal V3 to the second write node B under the control of the potential of the first write node A, and to write the third voltage signal or the second voltage signal to the first write node A under the control of the potential of the second write node B.

[0146] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 2, the driving control circuit includes a data writing circuit 41 and a latching circuit 42; the driving control terminal includes a first scanning terminal G1, and the data lines include a first data line DL1 and a second data line DL2.

[0147] The data writing circuit 41 is electrically connected to the first scanning terminal G1, the first data line DL1, the second data line DL2, the first writing node A, and the second writing node B, respectively. It is used to write the first data voltage Vdata1 provided by the first data line DL1 to the first writing node A and the second data voltage Vdata2 provided by the second data line DL2 to the second writing node B under the control of the first scanning signal provided by the first scanning terminal G1. The second writing node B is electrically connected to the control node G.

[0148] The latch circuit 42 is electrically connected to the first write node A, the second write node B, the second voltage terminal V2, and the third voltage terminal V3, respectively. It is used to control the writing of the second voltage signal provided by the second voltage terminal V2 or the third voltage signal provided by the third voltage terminal V3 to the second write node B under the control of the potential of the first write node A, and to write the third voltage signal or the second voltage signal to the first write node A under the control of the potential of the second write node B.

[0149] In at least one embodiment of this disclosure, the drive control circuit includes a data writing circuit, an inverter, and a storage circuit; the drive control terminal includes a first scanning terminal and a second scanning terminal, and the data line includes a first data line;

[0150] The data writing circuit is electrically connected to the first scanning end, the second scanning end, the first data line and the writing node, respectively, and is used to write the first data voltage provided by the first data line into the writing node under the control of the first scanning signal provided by the first scanning end and the second scanning signal provided by the second scanning end;

[0151] The storage circuit is electrically connected to the write node and is used to maintain the potential of the write node;

[0152] The inverter is electrically connected to both the write node and the control node, and is used to invert the potential of the write node to obtain the potential of the control node.

[0153] In a specific implementation, the drive control circuit may include a data writing circuit, an inverter, and a storage circuit; the data writing circuit, under the control of a first scan signal and a second scan signal, writes a first data voltage into the writing node; the storage circuit maintains the potential of the writing node; the inverter inverts the potential of the writing node to obtain the potential of the control node.

[0154] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 1B, the driving control circuit includes a data writing circuit 41, an inverter F1, and a storage circuit CH1; the driving control terminal includes a first scanning terminal G1 and a second scanning terminal G2, and the data line includes a first data line DL1.

[0155] The data writing circuit 41 is electrically connected to the first scanning terminal G1, the second scanning terminal G2, the first data line DL1 and the writing node X0, respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the writing node X0 under the control of the first scanning signal provided by the first scanning terminal G1 and the second scanning signal provided by the second scanning terminal G2.

[0156] The storage circuit CH1 is electrically connected to the write node X0 and is used to maintain the potential of the write node X0;

[0157] The inverter F1 is electrically connected to the write node X0 and the control node G respectively, and is used to invert the potential of the write node X0 to obtain the potential of the control node G.

[0158] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 2, the driving control circuit includes a data writing circuit 41, an inverter F1, and a storage circuit CH1; the driving control terminal includes a first scanning terminal G1 and a second scanning terminal G2, and the data line includes a first data line DL1.

[0159] The data writing circuit 41 is electrically connected to the first scanning terminal G1, the second scanning terminal G2, the first data line DL1 and the writing node X0, respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the writing node X0 under the control of the first scanning signal provided by the first scanning terminal G1 and the second scanning signal provided by the second scanning terminal G2.

[0160] The storage circuit CH1 is electrically connected to the write node X0 and is used to maintain the potential of the write node X0;

[0161] The inverter F1 is electrically connected to the write node X0 and the control node G respectively, and is used to invert the potential of the write node X0 to obtain the potential of the control node G.

[0162] In at least one embodiment of this disclosure, the drive control circuit includes a data writing circuit and a storage circuit; the drive control terminal includes a first scanning terminal and a second scanning terminal, and the data line includes a first data line;

[0163] The data writing circuit is electrically connected to the first scanning end, the second scanning end, the first data line and the control node respectively, and is used to write the first data voltage provided by the first data line into the control node under the control of the first scanning signal provided by the first scanning end and the second scanning signal provided by the second scanning end;

[0164] The storage circuit is electrically connected to the control node and is used to maintain the potential of the control node.

[0165] In a specific implementation, the drive control circuit may include a data writing circuit and a storage circuit. The data writing circuit writes a first data voltage to the control node under the control of a first scan signal and a second scan signal, and the storage circuit maintains the potential of the control node.

[0166] As shown in Figure 8, based on at least one embodiment of the pixel circuit shown in Figure 1B, the driving control circuit includes a data writing circuit 41 and a storage circuit CH1; the driving control terminal includes a first scanning terminal G1 and a second scanning terminal G2, and the data line includes a first data line DL1.

[0167] The data writing circuit 41 is electrically connected to the first scanning terminal G1, the second scanning terminal G2, the first data line DL1 and the control node G respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the control node G under the control of the first scanning signal provided by the first scanning terminal G1 and the second scanning signal provided by the second scanning terminal G2.

[0168] The storage circuit CH1 is electrically connected to the control node G and is used to maintain the potential of the control node G.

[0169] As shown in Figure 9, based on at least one embodiment of the pixel circuit shown in Figure 2, the driving control circuit includes a data writing circuit 41 and a storage circuit CH1; the driving control terminal includes a first scanning terminal G1 and a second scanning terminal G2, and the data line includes a first data line DL1.

[0170] The data writing circuit 41 is electrically connected to the first scanning terminal G1, the second scanning terminal G2, the first data line DL1 and the control node G respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the control node G under the control of the first scanning signal provided by the first scanning terminal G1 and the second scanning signal provided by the second scanning terminal G2.

[0171] The storage circuit CH1 is electrically connected to the control node G and is used to maintain the potential of the control node G.

[0172] Optionally, the data writing circuit includes a first transistor and a second transistor, and the latching circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0173] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the first write node.

[0174] The gate of the second transistor is electrically connected to the first scan terminal, the first terminal of the second transistor is electrically connected to the second data line, and the second terminal of the second transistor is electrically connected to the second write node.

[0175] The gate of the third transistor is electrically connected to the second write node, the first terminal of the third transistor is electrically connected to the second voltage terminal, and the second terminal of the third transistor is electrically connected to the first write node.

[0176] The gate of the fourth transistor is electrically connected to the second write node, the first terminal of the fourth transistor is electrically connected to the first write node, and the second terminal of the fourth transistor is electrically connected to the third voltage terminal.

[0177] The gate of the fifth transistor is electrically connected to the first write node, the first terminal of the fifth transistor is electrically connected to the second voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second write node.

[0178] The gate of the sixth transistor is electrically connected to the first write node, the first terminal of the sixth transistor is electrically connected to the second write node, and the second terminal of the sixth transistor is electrically connected to the third voltage terminal.

[0179] A pixel circuit provided in this disclosure includes a first control circuit;

[0180] The first control circuit includes a seventh transistor;

[0181] The gate of the seventh transistor is electrically connected to the first scanning terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first node.

[0182] In at least one embodiment of this disclosure, the first transistor is a P-type transistor, the second transistor is a P-type transistor, the third transistor and the fifth transistor are P-type transistors, and the fourth transistor and the sixth transistor are N-type transistors; the seventh transistor is an N-type transistor; the driving circuit includes a driving switch transistor that is an N-type transistor; or,

[0183] The first transistor is an N-type transistor, the second transistor is an N-type transistor, the third and fifth transistors are P-type transistors, the fourth and sixth transistors are N-type transistors, and the seventh transistor is a P-type transistor; the driving switch transistor is a P-type transistor.

[0184] As shown in Figure 10, based on at least one embodiment of the pixel circuit shown in Figure 4, the data writing circuit includes a first transistor M1 and a second transistor M2, the latching circuit includes a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6; the light-emitting element is a light-emitting diode L1.

[0185] The gate of the first transistor M1 is electrically connected to the first scan terminal G1, the drain of the first transistor M1 is electrically connected to the first data line DL1, and the source of the first transistor M1 is electrically connected to the first write node A.

[0186] The gate of the second transistor M2 is electrically connected to the first scan terminal G1, the drain of the second transistor M2 is electrically connected to the second data line DL2, and the source of the second transistor M2 is electrically connected to the second write node B.

[0187] The gate of the third transistor M3 is electrically connected to the second write node B, the source of the third transistor M3 is electrically connected to the high voltage terminal VDD, and the source of the third transistor M3 is electrically connected to the first write node A.

[0188] The gate of the fourth transistor M4 is electrically connected to the second write node B, the drain of the fourth transistor M4 is electrically connected to the first write node A, and the source of the fourth transistor M4 is electrically connected to ground GND.

[0189] The gate of the fifth transistor M5 is electrically connected to the first write node A, the source of the fifth transistor M5 is electrically connected to the high voltage terminal VDD, and the drain of the fifth transistor M5 is electrically connected to the second write node B.

[0190] The gate of the sixth transistor M6 is electrically connected to the first write node A, the drain of the sixth transistor M6 is electrically connected to the second write node B, and the source of the sixth transistor M6 is electrically connected to the ground terminal GND; the second write node B is electrically connected to the control node G.

[0191] The first control circuit includes a seventh transistor M7;

[0192] The gate of the seventh transistor M7 is electrically connected to the first scan terminal G1, the source of the seventh transistor M7 is electrically connected to the power supply voltage terminal VDD, and the drain of the seventh transistor T7 is electrically connected to the first node N1.

[0193] The drive circuit includes a drive switching transistor M0;

[0194] The gate of M0 is electrically connected to the control node G, the source of M0 is electrically connected to the first node N1, and the drain of M0 is electrically connected to the anode of L1.

[0195] The cathode of L1 is electrically connected to the low-voltage terminal VSS.

[0196] In at least one embodiment of the pixel circuit shown in Figure 10, M1 and M2 are N-type transistors, M3 and M5 are P-type transistors, M4 and M6 are N-type transistors, M7 is a P-type transistor, and M0 is a P-type transistor.

[0197] In at least one embodiment of this disclosure, a digital pixel driving circuit is used to control the light emission of the light-emitting diode L1. When the pixel circuit provided in this embodiment is working, the brightness of the light-emitting diode L1 is controlled by controlling the light emission time of the light-emitting diode L1. The gate of the driving switching transistor M0 is electrically connected to the second write node B. The potential of the second write node B only has two states, "0" and "1", that is, the potential of the second write node B is a low voltage or a high voltage, so as to control M0 to work in the linear region or the cutoff region and reduce the power consumption on M0.

[0198] In practical implementation, when the driving switching transistor M0 operates in the linear region, the source-drain voltage difference of M0 is small, so the power consumption of M0 is low; when the driving switching transistor M0 operates in the cutoff region, there is no current flowing through M0.

[0199] In a pixel circuit provided in an embodiment of this disclosure, all transistors can be switching transistors.

[0200] Figure 11 is a schematic diagram of the working timing of the pixel circuit shown in Figure 10 in one display cycle. The display cycle includes a first display stage S1, a second display stage S2, and a third display stage S3. The first display stage S1 includes a first write time period t11 and a first light emission time period t12. The second display stage S2 includes a second write time period t21 and a second light emission time period t22. The third display stage S3 includes a third write time period t31 and a third light emission time period t32.

[0201] The ratio of the duration of the first emission time period t12, the duration of the second emission time period t22, and the duration of the third emission time period t32 is 1:2:4.

[0202] During the first write time period t11, G1 is high, DL1 is high, DL2 is low, M1 and M2 are on, the potential of A is high, the potential of B is low, M6 and M3 are on, keeping the potential of A high and keeping the potential of B low.

[0203] During the first light-emitting period t12, G1 is at a low level, M1 and M2 are off, M7 is on, the potential of G is low, and M0 drives L1 to emit light.

[0204] During the second write time period t21, G1 is high, DL1 is low, DL2 is high, M1 and M2 are on, the potential of A is low, the potential of B is high, M5 and M4 are on, keeping the potential of A low, keeping the potential of B high, and keeping the potential of G high.

[0205] During the second light-emitting period t22, G1 is at a low level, M1 and M2 are off, M7 is on, the potential of G is high, M0 is off, and L1 does not emit light.

[0206] During the third write time period t31, G1 is high, DL1 is high, DL2 is low, M1 and M2 are on, the potential of A is high, the potential of B is low, M6 and M3 are on, keeping the potential of A high and keeping the potential of B low.

[0207] During the third light-emitting period t32, G1 is at a low level, M1 and M2 are off, M7 is on, the potential of G is low, and M0 drives L1 to emit light.

[0208] The pixel circuit disclosed in this embodiment divides one frame of time into three sub-frames during operation. Each sub-frame includes a sequentially set write time period and a light emission time period. The ratio between the length of the light emission time period of the first sub-frame and the length of the light emission time period of the second sub-frame is 1:2, and the ratio between the length of the light emission time period of the first sub-frame and the length of the light emission time period of the third sub-frame is 1:4. The LED can display eight different brightness gray levels. When more gray levels are needed, the number of sub-frames can be increased.

[0209] In a pixel circuit provided in this embodiment, the gate of M0 is only connected to a latch and operates separately from the seventh transistor included in the first control circuit. Its state switching is more stable and there is no leakage circuit during switching. When the pixel circuit provided in this embodiment is working, there is no situation where the potential of the gate of the driving switch transistor is controlled by voltage division of two transistors. The driving switch transistor can be controlled to work in the linear region or the cutoff region, so as to reduce the power consumption on the driving switch transistor.

[0210] Furthermore, the seventh transistor included in the first control circuit is connected to the main light-emitting circuit. By controlling the gate of the seventh transistor via G1, the main light-emitting circuit can be turned on / off. Through the external GOA module, the potential of the first scan signal provided by the first scan terminal is pulled up line by line, controlling the input data voltage and simultaneously turning off the main light-emitting circuit. When the data voltage input is complete, the potential of the first scan signal becomes low, disabling the latch circuit. This both stores the data voltage and turns on the seventh transistor included in the first control circuit. This structure eliminates control signal lines, saves the layout area of ​​the pixel circuit, and results in smaller pixel pitch and higher pixel density.

[0211] In an embodiment of this disclosure, a pixel circuit, when in operation, simultaneously shuts down the seventh transistor included in the first control circuit and opens the latch circuit with a first scan signal, thereby saving data writing time.

[0212] The differences between at least one embodiment of the pixel circuit shown in FIG12 of this disclosure and at least one embodiment of the pixel circuit shown in FIG10 of this disclosure are as follows:

[0213] M7 and M0 are NMOS (N-type metal-oxide-semiconductor) transistors;

[0214] M1 and M2 are PMOS (P-type metal-oxide-semiconductor) transistors.

[0215] Figure 13 is a schematic diagram of the working timing of the pixel circuit shown in Figure 12 in one display cycle. The display cycle includes a first display stage S1, a second display stage S2, and a third display stage S3. The first display stage S1 includes a first write time period t11 and a first light emission time period t12. The second display stage S2 includes a second write time period t21 and a second light emission time period t22. The third display stage S3 includes a third write time period t31 and a third light emission time period t32.

[0216] The ratio of the duration of the first emission time period t12, the duration of the second emission time period t22, and the duration of the third emission time period t32 is 1:2:4.

[0217] During the first write time period t11, G1 is low, DL1 is low, DL2 is high, M1 and M2 are on, the potential of A is low, the potential of B is high, M5 and M4 are on, keeping the potential of A low and the potential of B high.

[0218] During the first light-emitting time period t12, G1 is at a high level, M1 and M2 are off, M7 is on, the potential of G is high voltage, and M0 drives L1 to emit light;

[0219] During the second write time period t21, G1 is low, DL1 is high, DL2 is low, M1 and M2 are on, the potential of A is high, the potential of B is low, M5 and M4 are on, keeping the potential of A high, keeping the potential of B low, and keeping the potential of G low.

[0220] During the second light-emitting period t22, G1 is at a high level, M1 and M2 are off, M7 is on, the potential of G is low, M0 is off, and L1 does not emit light.

[0221] During the third write time period t31, G1 is low, DL1 is low, DL2 is high, M1 and M2 are on, the potential of A is low, the potential of B is high, M6 and M3 are on, keeping the potential of A low and keeping the potential of B high.

[0222] During the third light-emitting period t32, G1 is at a high level, M1 and M2 are off, M7 is on, the potential of G is high voltage, and M0 drives L1 to emit light.

[0223] In at least one embodiment of the pixel circuit shown in Figure 12, under the same process, the NMOS transistor has a higher carrier mobility, and when the MOS transistor size is the same and it is fully turned on, the NMOS transistor has a lower on-resistance, and the power consumption of the MOS transistor on the light-emitting main circuit will be lower.

[0224] Optionally, the data writing circuit includes a first transistor and a second transistor;

[0225] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the write node.

[0226] The gate of the second transistor is electrically connected to the second scan terminal, the first terminal of the second transistor is electrically connected to the first data line, and the second terminal of the second transistor is electrically connected to the write node.

[0227] A pixel circuit provided in this disclosure includes a first control circuit;

[0228] The first control circuit includes a seventh transistor;

[0229] The gate of the seventh transistor is electrically connected to the first scan terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first node.

[0230] In at least one embodiment of this disclosure, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the seventh transistor is an N-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor.

[0231] An embodiment of this disclosure provides a pixel circuit including a second control circuit;

[0232] The second control circuit includes an eighth transistor;

[0233] The gate of the eighth transistor is electrically connected to the second scanning terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0234] The first transistor is a P-type transistor, the second transistor is an N-type transistor, the eighth transistor is a P-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor.

[0235] As shown in Figure 14, based on at least one embodiment of the pixel circuit shown in Figure 6, the data writing circuit includes a first transistor M1 and a second transistor M2; the light-emitting element is a light-emitting diode L1.

[0236] The gate of the first transistor M1 is electrically connected to the first scan terminal G1, the source of the first transistor M1 is electrically connected to the first data line DL1, and the drain of the first transistor M1 is electrically connected to the write node X0.

[0237] The gate of the second transistor M2 is electrically connected to the second scan terminal G2, the drain of the second transistor M2 is electrically connected to the first data line DL1, and the source of the second transistor M2 is electrically connected to the write node X0.

[0238] The first control circuit includes a seventh transistor M7;

[0239] The gate of the seventh transistor M7 is electrically connected to the first scan terminal G1, the source of the seventh transistor M7 is electrically connected to the power supply voltage terminal VDD, and the drain of the seventh transistor M7 is electrically connected to the first node N1.

[0240] The storage circuit includes a first capacitor C1;

[0241] The first end of C1 is electrically connected to the write node X0, and the second end of C1 is electrically connected to the ground GND.

[0242] The input terminal of inverter F1 is electrically connected to the write node X0, and the output terminal of inverter F1 is electrically connected to the control node G.

[0243] The drive circuit includes a drive switching transistor M0;

[0244] The gate of M0 is electrically connected to the control node G, the source of M0 is electrically connected to the first node N1, and the drain of M0 is electrically connected to the anode of L1.

[0245] The cathode of L1 is electrically connected to the low-voltage terminal VSS.

[0246] Based on at least one embodiment of the pixel circuit shown in Figure 14, M1 is a P-type transistor, M2 is an N-type transistor, M7 is an N-type transistor, and M0 is a P-type transistor.

[0247] In at least one embodiment of this disclosure, the capacitor plus inverter structure provides a longer signal retention time and has better anti-interference and anti-fluctuation capabilities.

[0248] Figure 15 is a schematic diagram of the working timing of the pixel circuit shown in Figure 14 in one display cycle. The display cycle includes a first display stage S1, a second display stage S2, and a third display stage S3 set sequentially. The first display stage S1 includes a first write time period t11 and a first light emission time period t12. The second display stage S2 includes a second write time period t21 and a second light emission time period t22. The third display stage S3 includes a third write time period t31 and a third light emission time period t32.

[0249] The ratio of the duration of the first emission time period t12, the duration of the second emission time period t22, and the duration of the third emission time period t32 is 1:2:4.

[0250] During the first write time period t11, G1 is low, G2 is high, DL1 is high, M1 and M2 are open, and a high voltage signal is written to X0; F1 outputs a low voltage signal to G.

[0251] During the first light-emitting period t12, G1 is at a high level, G2 is at a low level, and M1 and M2 are off; M7 is on, the potential of G remains low, M0 is on, and M0 drives L1 to emit light.

[0252] During the second write time period t21, G1 is at a low level, G2 is at a high level, DL1 is at a low level, M1 and M2 are turned on, and a low voltage signal is written to X0; F1 outputs a high voltage signal to G.

[0253] During the second light-emitting period t22, G1 is at a high level, G2 is at a low level, M1 and M2 are off; M7 is on, the potential of G remains high, M0 is off, and L1 does not emit light.

[0254] During the third write time period t31, G1 is low, G2 is high, DL1 is high, M1 and M2 are turned on, and a high voltage signal is written to X0; F1 outputs a low voltage signal to G.

[0255] During the third light-emitting period t32, G1 is at a high level, G2 is at a low level, and M1 and M2 are turned off; M7 is turned on, the potential of G remains low, M0 is turned on, and M0 drives L1 to emit light.

[0256] As shown in Figure 16, based on at least one embodiment of the pixel circuit shown in Figure 7, the data writing circuit includes a first transistor M1 and a second transistor M2; the light-emitting element is a light-emitting diode L1.

[0257] The gate of the first transistor M1 is electrically connected to the first scan terminal G1, the source of the first transistor M1 is electrically connected to the first data line DL1, and the drain of the first transistor M1 is electrically connected to the write node X0.

[0258] The gate of the second transistor M2 is electrically connected to the second scan terminal G2, the drain of the second transistor M2 is electrically connected to the first data line DL1, and the source of the second transistor M2 is electrically connected to the write node X0.

[0259] The second control circuit includes an eighth transistor M8;

[0260] The gate of the eighth transistor M8 is electrically connected to the second scan terminal G2, the source of the eighth transistor M8 is electrically connected to the second node N2, and the eighth transistor M8 is electrically connected to the anode of L1.

[0261] The storage circuit includes a first capacitor C1;

[0262] The first end of C1 is electrically connected to the write node X0, and the second end of C1 is electrically connected to the ground GND.

[0263] The input terminal of inverter F1 is electrically connected to the write node X0, and the output terminal of inverter F1 is electrically connected to the control node G.

[0264] The drive circuit includes a drive switching transistor M0;

[0265] The gate of M0 is electrically connected to the control node G, the source of M0 is electrically connected to the power supply voltage terminal VDD, and the drain of M0 is electrically connected to the second node N2.

[0266] The cathode of L1 is electrically connected to the low-voltage terminal VSS.

[0267] Figure 17 is a schematic diagram of the working timing of the pixel circuit shown in Figure 16 in one display cycle. The display cycle includes a first display stage S1, a second display stage S2, and a third display stage S3 set sequentially. The first display stage S1 includes a first write time period t11 and a first light emission time period t12. The second display stage S2 includes a second write time period t21 and a second light emission time period t22. The third display stage S3 includes a third write time period t31 and a third light emission time period t32.

[0268] The ratio of the duration of the first emission time period t12, the duration of the second emission time period t22, and the duration of the third emission time period t32 is 1:2:4.

[0269] During the first write time period t11, G1 is low, G2 is high, M1 and M2 are on, DL is high to X0, F1 is low to G; M8 is off.

[0270] During the first light-emitting period t12, G1 is at a high level, G2 is at a low level, M1 and M2 are turned off, the potential of G remains at a low voltage, M8 is turned on, and M0 drives L1 to emit light.

[0271] During the second write time period t21, G1 is low, G2 is high, M1 and M2 are on, DL is low to X0, F1 is high to G; M8 is off.

[0272] During the second light-emitting period t22, G1 is at a high level, G2 is at a low level, M1 and M2 are turned off, the potential of G remains high, M8 is turned off, and L1 does not emit light.

[0273] During the third write time period t31, G1 is low, G2 is high, M1 and M2 are on, DL is high to X0, F1 is low to G; M8 is off.

[0274] During the third light-emitting period t32, G1 is at a high level, G2 is at a low level, M1 and M2 are turned off, the potential of G remains at a low voltage, M8 is turned on, and M0 drives L1 to emit light.

[0275] Optionally, the data writing circuit includes a first transistor and a second transistor;

[0276] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the write node.

[0277] The gate of the second transistor is electrically connected to the second scan terminal, the first terminal of the second transistor is electrically connected to the first data line, and the second terminal of the second transistor is electrically connected to the write node.

[0278] The pixel circuit includes a first control circuit;

[0279] The first control circuit includes a seventh transistor;

[0280] The gate of the seventh transistor is electrically connected to the first scan terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first node.

[0281] In at least one embodiment of this disclosure, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the seventh transistor is an N-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor.

[0282] Optionally, the data writing circuit includes a first transistor and a second transistor;

[0283] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the write node.

[0284] The gate of the second transistor is electrically connected to the second scan terminal, the first terminal of the second transistor is electrically connected to the first data line, and the second terminal of the second transistor is electrically connected to the write node.

[0285] The pixel circuit includes a second control circuit;

[0286] The second control circuit includes an eighth transistor;

[0287] The gate of the eighth transistor is electrically connected to the second scanning terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0288] In at least one embodiment of this disclosure, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the eighth transistor is a P-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor.

[0289] As shown in Figure 18, based on at least one embodiment of the pixel circuit shown in Figure 8, the data writing circuit includes a first transistor M1 and a second transistor M2; the light-emitting element is a light-emitting diode L1.

[0290] The gate of the first transistor M1 is electrically connected to the first scan terminal G1, the source of the first transistor M1 is electrically connected to the first data line DL1, and the drain of the first transistor M1 is electrically connected to the control node G.

[0291] The gate of the second transistor M2 is electrically connected to the second scan terminal G2, the source of the second transistor M2 is electrically connected to the first data line DL1, and the drain of the second transistor M2 is electrically connected to the control node G.

[0292] The first control circuit includes a seventh transistor M7;

[0293] The gate of the seventh transistor M7 is electrically connected to the first scan terminal G1, the drain of the seventh transistor M7 is electrically connected to the power supply voltage terminal VDD, and the source of the seventh transistor M7 is electrically connected to the first node N1.

[0294] The storage circuit includes a first capacitor C1;

[0295] The first terminal of C1 is electrically connected to the control node G; the second terminal of C1 is electrically connected to the ground terminal GND.

[0296] The drive circuit includes a drive switching transistor M0;

[0297] The gate of M0 is electrically connected to the control node G, the source of M0 is electrically connected to the first node N1, and the drain of M0 is electrically connected to the anode of L1.

[0298] The cathode of L1 is electrically connected to the low-voltage terminal VSS.

[0299] In at least one embodiment of the pixel circuit shown in Figure 18, M1 is a P-type transistor, M2 is an N-type transistor, M7 is an N-type transistor, and M0 is a P-type transistor.

[0300] Figure 19 is a schematic diagram of the working timing of the pixel circuit shown in Figure 18 in one display cycle. The display cycle includes a first display stage S1, a second display stage S2, and a third display stage S3 set sequentially. The first display stage S1 includes a first write time period t11 and a first light emission time period t12. The second display stage S2 includes a second write time period t21 and a second light emission time period t22. The third display stage S3 includes a third write time period t31 and a third light emission time period t32.

[0301] The ratio of the duration of the first emission time period t12, the duration of the second emission time period t22, and the duration of the third emission time period t32 is 1:2:4.

[0302] During the first write time period t11, G1 is low, G2 is high, DL1 is low, M1 and M2 are turned on, DL1 is low to G, and M7 is turned off.

[0303] During the first light-emitting time period t12, G1 is at a high level, G2 is at a low level, M1 and M2 are off, C1 maintains the potential of G at a low voltage, M0 is on, M7 is on, and M0 drives L1 to emit light.

[0304] During the second write time period t21, G1 is low, G2 is high, DL1 is high, M1 and M2 are turned on, DL1 is high to G, and M7 is turned off.

[0305] During the second light-emitting period t22, G1 is at a high level, G2 is at a low level, M1 and M2 are off, C1 maintains the potential of G at a high voltage, M0 is off, M7 is on, and L1 does not emit light.

[0306] During the third write time period t31, G1 is low, G2 is high, DL1 is low, M1 and M2 are on, DL1 is low to G, and M7 is off.

[0307] During the third light-emitting period t32, G1 is at a high level, G2 is at a low level, M1 and M2 are off, C1 maintains the potential of G at a low voltage, M0 is on, M7 is on, and M0 drives L1 to emit light.

[0308] In at least one embodiment of the pixel circuit shown in FIG18 of this disclosure, an inverter is not used, reducing the number of transistors used and thus reducing the layout size of the pixel circuit.

[0309] As shown in Figure 20, based on at least one embodiment of the pixel circuit shown in Figure 9, the data writing circuit includes a first transistor M1 and a second transistor M2; the light-emitting element is a light-emitting diode L1.

[0310] The gate of the first transistor M1 is electrically connected to the first scan terminal G1, the source of the first transistor M1 is electrically connected to the first data line DL1, and the drain of the first transistor M1 is electrically connected to the control node G.

[0311] The gate of the second transistor M2 is electrically connected to the second scan terminal G2, the source of the second transistor M2 is electrically connected to the first data line DL1, and the drain of the second transistor M2 is electrically connected to the control node G.

[0312] The second control circuit includes an eighth transistor M8;

[0313] The gate of the eighth transistor M8 is electrically connected to the second scan terminal G2, the source of the eighth transistor M8 is electrically connected to the second node N2, and the drain of the eighth transistor M8 is electrically connected to the anode of L1.

[0314] The storage circuit includes a first capacitor C1;

[0315] The first terminal of C1 is electrically connected to the control node G; the second terminal of C1 is electrically connected to the ground terminal GND.

[0316] The drive circuit includes a drive switching transistor M0;

[0317] The gate of M0 is electrically connected to the control node G, the source of M0 is electrically connected to the power supply voltage terminal VDD, and the drain of M0 is electrically connected to the second node N2.

[0318] The cathode of L1 is electrically connected to the low-voltage terminal VSS.

[0319] In at least one embodiment of the pixel circuit shown in FIG20, M1 is a P-type transistor, M2 is an N-type transistor, M0 is a P-type transistor, and M8 is a P-type transistor.

[0320] Figure 21 is a schematic diagram of the working timing of the pixel circuit shown in Figure 20 in one display cycle. The display cycle includes a first display stage S1, a second display stage S2, and a third display stage S3 set sequentially. The first display stage S1 includes a first write time period t11 and a first light emission time period t12. The second display stage S2 includes a second write time period t21 and a second light emission time period t22. The third display stage S3 includes a third write time period t31 and a third light emission time period t32.

[0321] The ratio of the duration of the first emission time period t12, the duration of the second emission time period t22, and the duration of the third emission time period t32 is 1:2:4.

[0322] During the first write time period t11, G1 is low, G2 is high, DL1 is low, M1 and M2 are on, DL1 is low to G, and M8 is off.

[0323] During the first light-emitting time period t12, G1 is at a high level, G2 is at a low level, M1 and M2 are off, C1 maintains the potential of G at a low voltage, M0 is on, M8 is on, and M0 drives L1 to emit light.

[0324] During the second write time period t21, G1 is low, G2 is high, DL1 is high, M1 and M2 are turned on, DL1 is high to G, and M8 is turned off.

[0325] During the second light-emitting period t22, G1 is at a high level, G2 is at a low level, M1 and M2 are turned off, C1 maintains the potential of G at a high voltage, M0 is turned off, M8 is turned on, and L1 does not emit light.

[0326] During the third write time period t31, G1 is low, G2 is high, DL1 is low, M1 and M2 are turned on, DL1 is low to G, and M8 is turned off.

[0327] During the third light-emitting period t32, G1 is at a high level, G2 is at a low level, M1 and M2 are off, C1 maintains the potential of G at a low voltage, M0 is on, M8 is on, and M0 drives L1 to emit light.

[0328] The pixel circuit provided in this disclosure can be fabricated on a silicon substrate. The silicon substrate has advantages such as high electron mobility and suitability for CMOS (Complementary Metal Oxide Semiconductor) processes, and is more suitable for use in panels for high PPI (Pixels Per Inch) AR (Augmented Reality) / VR (Virtual Reality) near-eye display scenarios.

[0329] The pixel driving method described in this disclosure is applied to the pixel circuit described above, and the pixel driving method includes:

[0330] Under the control of the drive control signal, the drive control circuit controls the potential of the control node according to the data voltage provided by the data line;

[0331] The first control circuit, under the control of the first control signal, controls the connection or disconnection between the power supply voltage terminal and the first node; and / or, the second control circuit, under the control of the second control signal, controls the connection or disconnection between the second node and the first electrode of the light-emitting element.

[0332] The drive circuit controls the connection and disconnection between the first node and the second node under the control of the potential of the control node.

[0333] In this embodiment, the first control circuit and / or the second control circuit are not used to control the potential of the control node. The gate of the control node is only connected to the drive control circuit. The state switching of the control node is more stable, and there is no leakage current path and power consumption during state switching. The pixel circuit described in this embodiment changes the operating mode of the first control circuit and / or the second control circuit, so that the potential change of the control node is clear during subframe state switching, without large leakage current and power consumption.

[0334] In at least one embodiment of this disclosure, the display cycle includes N display stages, and the nth display stage includes the nth writing time period and the nth emission time period; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0335] During the nth write time period, the drive control circuit, under the control of the drive control signal, controls the potential of the control node according to the data voltage provided by the data line;

[0336] During the nth emission period, the driving control circuit maintains the potential of the control node, and under the control of the potential of the control node, the driving circuit controls the switching between the first node and the second node.

[0337] In at least one embodiment of this disclosure, the pixel circuit includes a first control circuit, and the pixel driving method further includes:

[0338] During the nth write time period, the first control circuit, under the control of the first control signal, controls the power supply voltage terminal to disconnect from the first node;

[0339] During the nth emission period, the first control circuit, under the control of the first control signal, controls the connection between the power supply voltage terminal and the first node.

[0340] In at least one embodiment of this disclosure, the pixel circuit includes a second control circuit, and the pixel driving method further includes:

[0341] During the nth writing time period, the second control circuit, under the control of the second control signal, controls the second node to disconnect from the first electrode of the light-emitting element;

[0342] During the nth emission period, the second control circuit, under the control of the second control signal, controls the connection between the second node and the first electrode of the light-emitting element.

[0343] In at least one embodiment of this disclosure, the durations of at least two of the said luminescence time periods are different from each other.

[0344] In at least one embodiment of this disclosure, the duration of the N light-emitting time periods included in the display cycle is different for each other.

[0345] The display device described in this disclosure includes the pixel circuit described above.

[0346] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

A pixel circuit includes a light-emitting element, a driving circuit, and a driving control circuit; the control terminal of the driving circuit is electrically connected to a control node, the first terminal of the driving circuit is electrically connected to a first node, and the second terminal of the driving circuit is electrically connected to a second node; the driving circuit is used to control the on / off state between the first node and the second node under the control of the potential of the control node. The drive control circuit is electrically connected to the drive control terminal, the data line, and the control node, respectively, and is used to control the potential of the control node according to the data voltage provided by the data line under the control of the drive control signal provided by the drive control terminal; the pixel circuit further includes a first control circuit and / or a second control circuit; the first control circuit is electrically connected to the first control terminal, the power supply voltage terminal, and the first node, respectively, and is used to control the on / off connection between the power supply voltage terminal and the first node according to the first control signal provided by the first control terminal; The second control circuit is electrically connected to the second control terminal, the second node, and the first electrode of the light-emitting element, respectively, and is used to control the on / off connection between the second node and the first electrode of the light-emitting element according to the second control signal provided by the second control terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal. The pixel circuit as described in claim 1, wherein, The drive control circuit includes a data writing circuit and a latching circuit; the drive control terminal includes a first scanning terminal, and the data lines include a first data line and a second data line; the data writing circuit is electrically connected to the first scanning terminal, the first data line, the second data line, the first writing node, and the second writing node, respectively, and is used to write a first data voltage provided by the first data line to the first writing node and a second data voltage provided by the second data line to the second writing node under the control of a first scanning signal provided by the first scanning terminal; the second writing node is electrically connected to the control node; the latching circuit is electrically connected to the first writing node, the second writing node, a second voltage terminal, and a third voltage terminal, respectively, and is used to control the writing of a second voltage signal provided by the second voltage terminal or a third voltage signal provided by the third voltage terminal to the second writing node under the control of the potential of the first writing node, and to write the third voltage signal or the second voltage signal to the first writing node under the control of the potential of the second writing node. The pixel circuit as described in claim 1, wherein, The drive control circuit includes a data writing circuit, an inverter, and a storage circuit; the drive control terminal includes a first scanning terminal and a second scanning terminal, and the data line includes a first data line; the data writing circuit is electrically connected to the first scanning terminal, the second scanning terminal, the first data line, and the writing node, respectively, and is used to write the first data voltage provided by the first data line into the writing node under the control of the first scanning signal provided by the first scanning terminal and the second scanning signal provided by the second scanning terminal; The storage circuit is electrically connected to the write node and is used to maintain the potential of the write node; The inverter is electrically connected to both the write node and the control node, and is used to invert the potential of the write node to obtain the potential of the control node. The pixel circuit as described in claim 1, wherein, The drive control circuit includes a data writing circuit and a storage circuit; the drive control terminal includes a first scanning terminal and a second scanning terminal, and the data line includes a first data line; the data writing circuit is electrically connected to the first scanning terminal, the second scanning terminal, the first data line and the control node respectively, and is used to write the first data voltage provided by the first data line into the control node under the control of the first scanning signal provided by the first scanning terminal and the second scanning signal provided by the second scanning terminal; The storage circuit is electrically connected to the control node and is used to maintain the potential of the control node. The pixel circuit as described in claim 2, wherein, The data writing circuit includes a first transistor and a second transistor, and the latching circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the first write node. The gate of the second transistor is electrically connected to the first scan terminal, the first electrode of the second transistor is electrically connected to the second data line, and the second electrode of the second transistor is electrically connected to the second write node. The gate of the third transistor is electrically connected to the second write node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first write node. The gate of the fourth transistor is electrically connected to the second write node, the first electrode of the fourth transistor is electrically connected to the first write node, and the second electrode of the fourth transistor is electrically connected to the third voltage terminal. The gate of the fifth transistor is electrically connected to the first write node, the first electrode of the fifth transistor is electrically connected to the second voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second write node. The gate of the sixth transistor is electrically connected to the first write node, the first electrode of the sixth transistor is electrically connected to the second write node, and the second electrode of the sixth transistor is electrically connected to the third voltage terminal. The pixel circuit as described in claim 5, wherein, It includes a first control circuit; the first control circuit includes a seventh transistor; the gate of the seventh transistor is electrically connected to the first scanning terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first node. The pixel circuit as described in claim 6, wherein, The first transistor is a P-type transistor, the second transistor is a P-type transistor, the third transistor and the fifth transistor are P-type transistors, and the fourth transistor and the sixth transistor are N-type transistors; The seventh transistor is an N-type transistor; the driving circuit includes a driving switch transistor that is an N-type transistor; or, the first transistor is an N-type transistor, the second transistor is an N-type transistor, the third transistor and the fifth transistor are P-type transistors, the fourth transistor and the sixth transistor are N-type transistors, the seventh transistor is a P-type transistor, and the driving switch transistor is a P-type transistor. The pixel circuit as described in claim 3, wherein, The data writing circuit includes a first transistor and a second transistor; the gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the writing node; the gate of the second transistor is electrically connected to the second scan terminal, the first electrode of the second transistor is electrically connected to the first data line, and the second electrode of the second transistor is electrically connected to the writing node. The pixel circuit as described in claim 8, wherein, It includes a first control circuit; the first control circuit includes a seventh transistor; the gate of the seventh transistor is electrically connected to the first scanning terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first node. The pixel circuit as described in claim 9, wherein, The first transistor is a P-type transistor, the second transistor is an N-type transistor, the seventh transistor is an N-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor. The pixel circuit as described in claim 8, wherein, The system includes a second control circuit; the second control circuit includes an eighth transistor; the gate of the eighth transistor is electrically connected to the second scanning terminal, the first terminal of the eighth transistor is electrically connected to the second node, and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element; the first transistor is a P-type transistor, the second transistor is an N-type transistor, the eighth transistor is a P-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor. The pixel circuit as described in claim 4, wherein, The data writing circuit includes a first transistor and a second transistor; the gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the writing node; the gate of the second transistor is electrically connected to the second scan terminal, the first electrode of the second transistor is electrically connected to the first data line, and the second electrode of the second transistor is electrically connected to the writing node. The pixel circuit includes a first control circuit; the first control circuit includes a seventh transistor; the gate of the seventh transistor is electrically connected to the first scan terminal, the first electrode of the seventh transistor is electrically connected to the power supply voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first node. The pixel circuit as described in claim 12, wherein, The first transistor is a P-type transistor, the second transistor is an N-type transistor, the seventh transistor is an N-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor. The pixel circuit as described in claim 4, wherein, The data writing circuit includes a first transistor and a second transistor; the gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first data line, and the second electrode of the first transistor is electrically connected to the writing node; the gate of the second transistor is electrically connected to the second scan terminal, the first electrode of the second transistor is electrically connected to the first data line, and the second electrode of the second transistor is electrically connected to the writing node. The pixel circuit includes a second control circuit; the second control circuit includes an eighth transistor; the gate of the eighth transistor is electrically connected to the second scan terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element. The pixel circuit as described in claim 14, wherein, The first transistor is a P-type transistor, the second transistor is an N-type transistor, the eighth transistor is a P-type transistor, and the driving circuit includes a driving switch transistor that is a P-type transistor. A pixel driving method, applied to a pixel circuit as described in any one of claims 1 to 15, the pixel driving method comprising: Under the control of the drive control signal, the drive control circuit controls the potential of the control node according to the data voltage provided by the data line; The first control circuit, under the control of the first control signal, controls the connection or disconnection between the power supply voltage terminal and the first node; and / or, the second control circuit, under the control of the second control signal, controls the connection or disconnection between the second node and the first electrode of the light-emitting element; the driving circuit, under the control of the potential of the control node, controls the connection or disconnection between the first node and the second node. The pixel driving method as described in claim 16, wherein, The display cycle consists of N display stages, and the nth display stage includes the nth writing time period and the nth light emission time period; N is an integer greater than 1, and n is a positive integer less than or equal to N; During the nth write time period, the drive control circuit, under the control of the drive control signal, controls the potential of the control node according to the data voltage provided by the data line; During the nth emission period, the driving control circuit maintains the potential of the control node, and under the control of the potential of the control node, the driving circuit controls the switching between the first node and the second node. The pixel driving method as described in claim 17, wherein, The pixel circuit includes a first control circuit, and the pixel driving method further includes: during the nth writing time period, the first control circuit, under the control of a first control signal, controls the power supply voltage terminal to disconnect from the first node; during the nth light emission time period, the first control circuit, under the control of the first control signal, controls the power supply voltage terminal to connect with the first node. The pixel driving method as described in claim 17, wherein, The pixel circuit includes a second control circuit, and the pixel driving method further includes: during the nth writing time period, the second control circuit, under the control of a second control signal, controls the second node to disconnect from the first electrode of the light-emitting element; during the nth light-emitting time period, the second control circuit, under the control of a second control signal, controls the second node to connect with the first electrode of the light-emitting element. The pixel driving method according to any one of claims 17 to 19, wherein, The durations of at least two of the stated emission periods are different. The pixel driving method as described in claim 20, wherein, The display cycle includes N light-emitting time periods, each with a different duration. A display device comprising a pixel circuit as described in any one of claims 1 to 15.

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