Memory device including a wave drain selection level isolation

Abstract

A three-dimensional memory device includes: an alternating stack of insulating layers and conductive layers; a memory opening extending vertically through the alternating stack; a memory opening filling structure in the memory opening; and a drain select level isolation structure extending vertically through a subset of the layers within the alternating stack and extending generally laterally in a first horizontal direction with lateral undulations in a second horizontal direction, such that the first conductive layers within the alternating stack are divided into a set of at least two first drain selection level electrode strips. The drain select level isolation structure protrudes laterally into each memory opening fill structure in the first and second rows and does not protrude laterally into the first drain select level electrode strip within a gap between adjacent pairs of memory opening fill structures.

Description

Cross-references to related applications

[0001] This application claims the benefit and priority of U.S. Nonprovisional Patent Application Serial No. 18 / 666,018, filed May 16, 2024. Technical Field

[0002] This disclosure relates in general to the field of semiconductor devices, and more particularly to memory devices including a wavy drain-selective-level isolation structure and methods for forming the same. Background Technology

[0003] A three-dimensional vertical NAND string with one bit per cell was disclosed in an article by T. Endoh et al. entitled “Novel Ultra High Density Memory With AStacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proceedings (2001), pp. 33-36. Summary of the Invention

[0004] According to one aspect of this disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulating and conductive layers; a memory opening extending vertically through the alternating stack; memory opening filling structures located within the memory opening, wherein each memory opening filling structure includes a corresponding vertical semiconductor channel, a corresponding vertical stack of memory elements, and a corresponding drain region, wherein the memory opening filling structures are arranged in rows extending laterally along a first horizontal direction, and the rows are laterally spaced from each other along a second horizontal direction perpendicular to the first horizontal direction; and a drain selection hierarchical isolation structure extending vertically through the alternating stack. A subset of conductive layers, and generally extending laterally along a first horizontal direction, wherein there are lateral undulations along a second horizontal direction, such that the first conductive layers within the alternating stack are divided into a set of at least two first drain selection level electrode strips, wherein: the drain selection level isolation structure contacts the first row memory opening-fill structure and the second row memory opening-fill structure and is located between the first row memory opening-fill structure and the second row memory opening-fill structure; and the drain selection level isolation structure laterally protrudes into each memory opening-fill structure in the first row and the second row, and does not laterally protrude into the first drain selection level electrode strip within the gap between adjacent pairs of memory opening-fill structures laterally spaced along the first horizontal direction in the first row and the second row.

[0005] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming an alternating stack of an insulating layer and a spacer material layer over a substrate, wherein the spacer material layer is formed as a conductive layer or subsequently replaced by a conductive layer; forming a memory opening through the alternating stack; forming a memory opening filling structure in the memory opening, wherein each memory opening filling structure includes a corresponding memory film and a corresponding vertical semiconductor channel laterally surrounded by the corresponding memory film, wherein the memory opening filling structures are arranged in rows extending laterally along a first horizontal direction, and the rows are laterally spaced from each other along a second horizontal direction perpendicular to the first horizontal direction; forming a memory opening filling structure through the alternating stack of an insulating layer and a spacer material layer over a substrate, wherein the spacer material layer is formed as a conductive layer or subsequently replaced by a conductive layer; forming a memory opening opening through the alternating stack; forming a memory opening filling structure in the memory opening opening, wherein each memory opening filling structure includes a corresponding memory film and a corresponding vertical semiconductor channel laterally surrounded by the corresponding memory film; forming a memory opening filling structure through the alternating stack of an insulating layer and a spacer material layer over a substrate, wherein the memory opening filling structures are arranged in rows extending laterally along a first horizontal direction, and the rows are laterally spaced from each other along a second horizontal direction perpendicular to the first horizontal direction; forming a memory opening filling structure through the alternating stack of an insulating layer and a spacer material layer over a substrate, wherein the memory opening filling structure includes a corresponding memory opening filling structure; forming a memory opening filling structure through the alternating stack of an insulating layer and a spacer material layer ... A subset of the conductive layer of a conductive layer forms a drain select level isolation trench, such that the drain select level isolation trench divides the first conductive layer into a pair of first drain select level electrode strips, and includes a volume formed by removing portions of the first row memory opening fill structure and the second row memory opening fill structure; and a drain select level isolation structure is formed in the drain select level isolation trench, wherein the drain select level isolation structure laterally protrudes into each memory opening fill structure in the first row and the second row, and does not laterally protrude into the first drain select level electrode strips in the gap between adjacent pairs of memory opening fill structures laterally spaced along a first horizontal direction in the first row and the second row. Attached Figure Description

[0006] Figure 1 This is a schematic vertical cross-sectional view of a first exemplary structure following an alternating stacking of insulating and sacrificial material layers on a carrier substrate, according to a first embodiment of the present disclosure.

[0007] Figure 2 This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of a stepped surface and a stepped dielectric material portion, according to a first embodiment of the present disclosure.

[0008] Figure 3A This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of the memory opening and the support opening, according to a first embodiment of the present disclosure. Figure 3B yes Figure 3A The top view of the first exemplary structure. The hinged vertical cross-section A-A' is Figure 3A The vertical cross-sectional plane of the diagram.

[0009] Figure 4 This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of a sacrificial opening filling structure, according to a first embodiment of the present disclosure.

[0010] Figure 5 This is a vertical cross-sectional view of a first exemplary structure after the formation of the support column structure, according to a first embodiment of the present disclosure.

[0011] Figure 6 This is a schematic vertical cross-sectional view of a first exemplary structure after removing the sacrificial memory opening-filling structure according to a first embodiment of the present disclosure.

[0012] Figures 7A to 7F This is a vertical cross-sectional view of the memory opening sequence during the formation of the memory opening filling structure according to a first embodiment of the present disclosure.

[0013] Figure 8A This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of a memory opening filling structure, according to a first embodiment of the present disclosure. Figure 8B yes Figure 8A The top view of the first exemplary structure. Vertical plane AA is... Figure 8A The vertical cross-section of the section.

[0014] Figure 9A This is a vertical cross-sectional view of a first exemplary structure after the formation of a lateral isolation trench, according to a first embodiment of the present disclosure. Figure 9B yes Figure 9A The top view of the first exemplary structure. Vertical plane AA is... Figure 9A The vertical cross-sectional plane of the diagram.

[0015] Figure 10 This is a vertical cross-sectional view of a first exemplary structure after the formation of a lateral extension cavity, according to a first embodiment of the present disclosure.

[0016] Figure 11 This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of a conductive layer, according to a first embodiment of the present disclosure.

[0017] Figure 12 This is a vertical cross-sectional view of a first exemplary structure after the formation of the lateral isolation trench filling structure, the layer contact via structure, and the drain contact via structure, according to a first embodiment of the present disclosure.

[0018] Figure 13A This is a vertical cross-sectional view of a first exemplary structure after the formation of a drain selection hierarchical isolation trench according to a first embodiment of the present disclosure. Figure 13B , Figure 13C and Figure 13D They are along Figure 13A A horizontal cross-sectional view of the region of the first exemplary structure, taken from horizontal planes B-B', C-C', and D-D'. Figure 13E yes Figure 13A A top view of the first exemplary structure. Figure 13E The hinged vertical cross section A-A' in the middle is Figure 13AThe vertical cross-sectional plane of the diagram.

[0019] Figure 14 This is a vertical cross-sectional view of a first exemplary structure after the formation of a dielectric liner layer and an etched mask material layer, according to a first embodiment of the present disclosure.

[0020] Figure 15A This is a vertical cross-sectional view of a first exemplary structure after forming a drain selection hierarchical isolation trench according to a first embodiment of the present disclosure. Figure 15B , Figure 15C and Figure 15D They are along Figure 15A A horizontal cross-sectional view of the region of the first exemplary structure, taken from horizontal planes B-B', C-C', and D-D'.

[0021] Figure 16A This is a vertical cross-sectional view of a first exemplary structure after the removal of the etch mask material layer, according to a first embodiment of the present disclosure. Figure 16B It is along Figure 16A A horizontal cross-sectional view of the region of the first exemplary structure, taken from the horizontal plane B-B'.

[0022] Figure 17A , Figure 17B and Figure 17C This is a sequential horizontal cross-sectional view of a region of a first exemplary structure during various steps of an isotropic etching process according to a first embodiment of the present disclosure.

[0023] Figure 18A This is a vertical cross-sectional view of a first exemplary structure following a lateral extension drain selection hierarchical isolation trench, according to a first embodiment of the present disclosure. Figure 18B , Figure 18C and Figure 18D They are along Figure 18A A horizontal cross-sectional view of the region of the first exemplary structure, taken from horizontal planes B-B', C-C', and D-D'.

[0024] Figure 19A This is a vertical cross-sectional view of a first exemplary structure after forming a drain selection hierarchical isolation structure according to a first embodiment of the present disclosure. Figure 19B , Figure 19C and Figure 19D They are along Figure 19A A horizontal cross-sectional view of the region of the first exemplary structure, taken from horizontal planes B-B', C-C', and D-D'. Figure 19E yes Figure 19A A top view of the first exemplary structure. Figure 19E The hinged vertical cross section A-A' in the middle is Figure 19A The vertical cross-sectional plane of the diagram.

[0025] Figure 20A This is a vertical cross-sectional view of a first exemplary structure after various contact via structures have been formed, according to a first embodiment of the present disclosure. Figure 20B yes Figure 20A A top view of the first exemplary structure. Figure 20B The hinged vertical cross section A-A' in the middle is Figure 20A The vertical cross-sectional plane of the diagram.

[0026] Figure 21 This is a vertical cross-sectional view of a first exemplary structure after the formation of a memory die, according to a first embodiment of the present disclosure.

[0027] Figure 22 This is a vertical cross-sectional view of a logic die according to the first embodiment of this disclosure.

[0028] Figure 23 This is a vertical cross-sectional view of a first exemplary structure after attaching a logic die to a memory die, according to a first embodiment of the present disclosure.

[0029] Figure 24 This is a vertical cross-sectional view of a first exemplary structure after the removal of the carrier substrate, according to a first embodiment of the present disclosure.

[0030] Figure 25A This is a vertical cross-sectional view of a first exemplary structure after the formation of the source layer and the back-side contact structure, according to a first embodiment of the present disclosure. Figure 25B , Figure 25C and Figure 25D They are along Figure 25A A horizontal cross-sectional view of the region of the first exemplary structure, taken from horizontal planes B-B', C-C', and D-D'.

[0031] Figure 26A This is a vertical cross-sectional view of a second exemplary structure after forming a drain selection hierarchical isolation trench according to a second embodiment of the present disclosure. Figure 26B , Figure 26C and Figure 26D They are along Figure 26A A horizontal cross-sectional view of the region of the second exemplary structure, taken from horizontal planes B-B', C-C', and D-D'. Figure 26E yes Figure 26A A top view of the second exemplary structure. Figure 26E The hinged vertical cross section A-A' in the middle is Figure 26A The vertical cross-sectional plane of the diagram.

[0032] Figure 27A This is a vertical cross-sectional view of a second exemplary structure after forming a drain selection hierarchical isolation structure according to a second embodiment of the present disclosure. Figure 27B , Figure 27C and Figure 27D They are along Figure 27A A horizontal cross-sectional view of the region of the second exemplary structure, taken from horizontal planes B-B', C-C', and D-D'. Figure 27E yes Figure 27A A top view of the second exemplary structure. Figure 27E The hinged vertical cross section A-A' in the middle is Figure 27A The vertical cross-sectional plane of the diagram.

[0033] Figure 28 This is a vertical cross-sectional view of a second exemplary structure according to a second embodiment of the present disclosure after bonding the memory die and the memory die, removing the carrier substrate, and forming the source layer and the back contact structure. Detailed Implementation

[0034] Without being bound by a specific theory, it is believed that three-dimensional NAND memory devices may experience a downward drift of the threshold voltage due to damage to the external blocking dielectric during the formation of the drain select level isolation structure and / or due to contact between the external blocking dielectric and the drain select level isolation structure, such that any portion of the drain select gate electrode is not retained between the external blocking dielectric and the drain select level isolation structure. This downward drift is believed to be caused by electron decapture from the charge storage layer into the external blocking dielectric layer, resulting from damage and / or absence of the drain select gate electrode between the external blocking dielectric and the drain select level isolation structure (i.e., leaving ungated portions of the external blocking dielectric layer that accumulate decaptured electrons). This phenomenon reduces the reliability of the memory device performance. Embodiments of this disclosure relate to memory devices including wavy drain select level isolation structures and methods of forming them, various aspects of which are described below. Embodiments of this disclosure can be used to form various structures including multi-level memory structures, non-limiting examples of which include three-dimensional memory devices comprising multiple memory strings.

[0035] In some implementations, a wavy drain-select hierarchical isolation structure mitigates the threshold voltage shift. The drain-select hierarchical isolation structure is formed with a wavy horizontal cross-sectional profile, causing it to laterally protrude into the dielectric core of the memory aperture fill structure (i.e., through the memory film and channels of the vertical NAND string), while having no lateral protrusions in the gaps between adjacent memory aperture fill structures. Complete removal of the external blocking dielectric in the non-gated regions of the lateral protrusions is believed to reduce electron decapture into the external blocking dielectric layer, thus mitigating the threshold voltage shift. By stabilizing the threshold voltage of the NAND string at the level of the drain-select electrode, more uniform device operating characteristics and enhanced reliability are provided.

[0036] The accompanying drawings are not to scale. Multiple instances of an element may be reproduced where only a single instance is illustrated, unless otherwise explicitly described or clearly indicated that a reproduction of the element does not exist. Ordinal numbers such as “first,” “second,” and “third” are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0037] Like reference numerals denote the same or similar elements. Unless otherwise specified, elements with the same reference numerals are considered to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements providing an edge or surface shared by these elements. If two or more elements are not in direct contact with each other or are not in direct contact with each other, the two elements are “separated” from each other or “separated” from each other. As used herein, an element located “on” a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of an element and the surface of a second element, the element is “directly” located “on” the second element. As used herein, if there is a conductive path consisting of at least one conductive material between an element and a second element, the element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure whose shape or composition is subsequently modified.

[0038] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapering surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0039] Typically, a semiconductor die or semiconductor package can include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (typically one or two). Despite some limitations, the same, concurrent operations can be performed on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased in a single erase operation. Each block contains multiple pages, which are the smallest programmable units, i.e., the smallest units on which read operations can be performed.

[0040] As used in this article, "semiconductor material" refers to materials with an electrical conductivity of 1 x 10⁻⁶. -5 S / m to 1x10 5 Materials in the S / m range. As used herein, "semiconductor material" refers to a material in which the electrical conductivity is in the absence of electrical dopants and is 1 × 10⁻⁶. -5 Materials in the range of S / m to 1 S / m, and which, after appropriate doping with an electrical dopant, can produce conductivity in the range of 1 S / m to 1 × 10⁻⁶. 7 Doped materials in the S / m range. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, “conductive material” refers to a material with a conductivity greater than 1 x 10⁻⁶. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to materials with a conductivity of less than 1 x 10⁻⁶. -5 Materials with a S / m ratio. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a value greater than 1 x 10⁻⁶. 5 The conductivity is S / m. "Doped semiconductor material" can be a heavily doped semiconductor material, or it can be a semiconductor material comprising electrically dopants (i.e., p-type dopants and / or n-type dopants) at a concentration of 1 x 10⁻⁶. -5 S / m to 1x10 7 Conductivity in the S / m range. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrically conductive agent. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. A doped semiconductor material can be semiconductor or conductive, depending on the atomic concentration of the electrically conductive agent therein. As used herein, "metallic material" refers to a conductive material that includes at least one metallic element. All conductivity measurements were performed under standard conditions.

[0041] refer to Figure 1This illustrates a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a carrier substrate 9, which may be a semiconductor substrate or a conductive substrate. For example, the carrier substrate 9 may include a commercially available silicon wafer. Alternatively, the carrier substrate 9 may include any material that can be selectively removed relative to the material of the insulating layer 32 and the dielectric material to be subsequently formed.

[0042] Alternating stacks of a first material layer and a second material layer may be formed on a carrier substrate 9. The first material layer may be an insulating layer, and the second material layer may be a spacer material layer. In one embodiment, the spacer material layer may include a sacrificial material layer 42. In this case, alternating stacks (32, 42) of insulating layer 32 and sacrificial material layer 42 may be formed over the carrier substrate 9. Insulating layer 32 includes an insulating material such as undoped silicate glass or doped silicate glass, and sacrificial material layer 42 includes a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, insulating layer 32 (i.e., the first material layer) may include a silicon oxide layer, and sacrificial material layer 42 (i.e., the second material layer) may include a silicon nitride layer.

[0043] The alternating stacks (32, 42) may include multiple repetitions of a unit layer stack comprising an insulating layer 32 and a sacrificial material layer 42. The total number of repetitions of the unit layer stacks within the alternating stacks (32, 42) may be, for example, in the range of 8 to 1,024, such as 32 to 256, but smaller and larger repetitions may also be used. Hereinafter, the topmost insulating layer of the insulating layers 32 will be referred to as the topmost insulating layer 32T. The bottommost insulating layer of the insulating layers 32 is the insulating layer 32 closest to the carrier substrate 9, and this insulating layer is referred to herein as the bottommost insulating layer 32B.

[0044] Each insulating layer in the insulating layers 32, except for the topmost insulating layer 32T, may have a thickness ranging from 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses are also possible. Each sacrificial material layer in the sacrificial material layers 42 may have a thickness ranging from 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses are also possible. In one embodiment, the topmost insulating layer 32T may have a thickness approximately half that of the other insulating layers 32.

[0045] The first exemplary structure includes a memory array region 100 and a contact region 300, in which a three-dimensional array of memory elements will subsequently be formed, and in which a layered contact via structure for contact word lines will subsequently be formed.

[0046] While an embodiment in which the spacer material layer is formed as sacrificial material layer 42 is described, in an alternative embodiment, the spacer material layer may be formed as a conductive layer. Generally, the spacer material layer of this disclosure may be formed as a conductive layer, or may subsequently be at least partially replaced with a conductive layer.

[0047] refer to Figure 2 Optional stepped surfaces are formed in the contact area 300. As used herein, a “stepped surface” refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from an edge of the horizontal surface and to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume by removing portions of the alternatingly stacked (32, 42) from the stepped cavity by forming the stepped surfaces. A “stepped cavity” refers to a cavity having stepped surfaces.

[0048] The stepped cavity can have different stepped surfaces, such that the horizontal cross-sectional shape of the stepped cavity varies in a stepped manner with a vertical distance from the top surface of the supporting substrate 9. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. This set of processing steps may include, for example, a first type of etching process and a second type of etching process, wherein the first type of etching process vertically increases the depth of the cavity by one or more levels, and the second type of etching process laterally extends the area vertically etched in a subsequent first type of etching process. As used herein, a “hierarchy” comprising alternating plurality of structures is defined as the relative positions of a pair of first material layers and second material layers within the structure.

[0049] Each sacrificial material layer 42 within the alternating stacks (32, 42), except for the topmost sacrificial material layer 42, extends laterally further than any overlying sacrificial material layer 42 within the alternating stacks (32, 42) in the mezzanine area. The stepped surface of the alternating stacks (32, 42) extends continuously from the bottommost layer (such as the bottommost insulating layer 32B) within the alternating stacks (32, 42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stacks (32, 42).

[0050] A stepped dielectric material portion 65 (i.e., an insulating filler portion) can be formed in a stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed, for example, from the top surface of the topmost insulating layer 32T by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric material portion 65. As used herein, a “stepped” element refers to an element having a stepped surface and a horizontal cross-sectional region that increases or decreases in steps as a function of the vertical distance from the top surface of the substrate on which the element is situated. If silicon oxide is used for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 may or may not be doped with dopants such as B, P, and / or F.

[0051] refer to Figure 3A and Figure 3B An etch mask layer (such as a photoresist layer) may be formed over the alternating stacks (32, 42), and the etch mask layer may be photolithographically patterned to form openings in the memory array region 100 and in the contact region 300. An anisotropic etching process may be performed to transfer the pattern of the openings in the etch mask layer through the stepped dielectric material portion 65 and the alternating stacks (32, 42). Memory openings 49 are formed through the alternating stacks (32, 42) in the memory array region 100. Support openings 19 may optionally be formed through the stepped dielectric material portion 65 and the alternating stacks (32, 42) in the contact region 300.

[0052] Each of the memory opening 49 and the support opening 19 may extend vertically into the carrier substrate 9. In one embodiment, the bottom surfaces of the memory opening 49 and the support opening 19 may be formed at or below the top surface of the carrier substrate 9. The diameter of the memory opening 49 may range from 60 nm to 400 nm (e.g., 120 nm to 300 nm), but smaller and larger diameters are possible. The support opening 19 may have a diameter ranging from 60 nm to 400 nm (e.g., 120 nm to 300 nm), but smaller and larger diameters are possible.

[0053] Each cluster of memory openings 49 (corresponding to a region of a memory block) may include multiple rows of memory openings 49. Each row of memory openings 49 may include a plurality of memory openings 49 arranged at uniform spacing along a first horizontal direction hd1 (which may be a word line direction). The rows of memory openings 49 may be laterally spaced from each other along a second horizontal direction hd2 (which may be a bit line direction), which may be perpendicular to the first horizontal direction hd1. In one embodiment, each cluster of memory openings 49 may be formed as a two-dimensional periodic array of memory openings 49.

[0054] refer to Figure 4 Optional sacrificial liner layers (such as thin silicon oxide layers) and sacrificial filler materials can be deposited in the memory opening 49 and the support opening 19. The sacrificial filler materials may include carbon-based materials (such as amorphous carbon or diamond-like carbon), semiconductor materials (such as amorphous silicon or silicon-germanium alloys), polymeric materials, or dielectric materials (such as organosilicon glass or borosilicate glass). Excess sacrificial filler materials can be removed from a horizontal plane including the top surface of the top insulating layer 32T. The sacrificial filler materials filling each remaining portion of the memory opening 49 constitute a sacrificial memory opening filling structure 48. The sacrificial filler materials filling each remaining portion of the support opening 19 constitute a sacrificial support opening filling structure 18.

[0055] refer to Figure 5 A photoresist layer (not shown) may be applied over the first exemplary structure and may be photolithographically patterned to cover the sacrificial memory opening-fill structure 48 in the memory array region 100, but not the sacrificial support opening-fill structure 18 in the contact region 300. The sacrificial support opening-fill structure 18 is then selectively removed from the materials of the insulating layer 32, the sacrificial material layer 42, and the carrier substrate 9 by ashing or selective etching. A void is formed in the volume of the support opening 19 from which the sacrificial support opening-fill structure 18 is removed.

[0056] Dielectric filler material (such as silicon oxide) can be deposited in the support opening 19 using a conformal deposition process. Excess portions of the dielectric filler material can be removed, for example, from the top surface of the topmost insulating layer 32T using a recess etching process. Each portion of the dielectric filler material filling the corresponding support opening 19 constitutes a support pillar structure 20, which can be used to provide structural support to the insulating layer 32 and the stepped dielectric material portion 65 during the replacement of the sacrificial material layer 42 with a conductive layer. Alternatively, the support opening 19 can be formed simultaneously with the memory opening in a later step, and the support pillar structure 20 can be formed in the support opening 19 while the memory opening filling structure is formed in the memory opening, as will be described below.

[0057] refer to Figure 6 Subsequently, the sacrificial memory opening fill structure 48 is selectively removed from the materials of the insulating layer 32, the sacrificial material layer 42, and the carrier substrate 9. A void is formed in the volume of the memory opening 49 from which the sacrificial memory opening fill structure 48 is removed.

[0058] Figures 7A to 7F It is a continuous vertical cross-sectional view of the memory opening 49 during the formation of the memory opening filling structure 58 according to an embodiment of the present disclosure.

[0059] refer to Figure 7A Examples are shown in Figure 6 The memory opening 49 after the processing steps.

[0060] refer to Figure 7B A layer stack including a memory material layer 54 can be deposited conformally. In an exemplary example, the layer stack may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric pad 56. The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 may include a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing changes in resistivity, ferroelectric polarization, or any other measurable physical property. Where the memory material layer 54 includes a charge storage material, the optional dielectric pad 56 may include a tunneling dielectric layer.

[0061] refer to Figure 7C A semiconductor channel material layer 60L can be deposited over each memory film 50 by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, it can have doping of a first conductivity type, which can be p-type or n-type. The thickness of the semiconductor channel material layer 60L can be in the range of 5 nm to 50 nm (e.g., 10 nm to 30 nm), but smaller and larger thicknesses are also possible.

[0062] refer to Figure 7D A dielectric core layer 62L comprising a dielectric filler material (such as silicon oxide) can be deposited in the remaining volume of the memory opening 49. While conformal deposition processes (such as chemical vapor deposition) can be used to deposit the dielectric core layer 62L, the consistency of such conformal deposition processes may not be perfect. Therefore, the thickness of the bottom portion of the dielectric core layer 62L at the bottom of each memory opening 49 may be less than the thickness of the upper portion of the dielectric core layer 62L at the top of each memory opening 49.

[0063] refer to Figure 7E The dielectric core layer 62L can be vertically recessed such that each remaining portion of the dielectric core layer has a top surface at or near a horizontal plane including the bottom surface of the topmost insulating layer 32. Each remaining portion of the dielectric core layer constitutes the dielectric core 62.

[0064] refer to Figure 7FA doped semiconductor material having a second conductivity type can be deposited in each recessed region above the dielectric core 62. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be 5 × 10⁻⁶. 18 / cm 3 Up to 2×10 21 / cm 3 Within a certain range, but smaller or larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0065] Excess portions of the deposited semiconductor material doped with a second conductivity type and the horizontal portion of the semiconductor channel material layer 60L can be removed, for example, from the horizontal plane above the top surface, including the top insulating layer 32T, using chemical mechanical planarization (CMP) or recess etching processes. Each remaining portion of the doped semiconductor material with the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel material layer 60L (which has doping with a first conductivity type) constitutes a vertical semiconductor channel 60.

[0066] Each portion of the layer stack, including the memory material layer 54 retained in the respective memory opening 49, constitutes a memory film 50. In one embodiment, the memory film 50 may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric pad 56. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 includes a respective vertical stack of memory elements, which may include portions of the memory material layer 54 located at each level of the sacrificial material layer 42 (or generally, at each level of the spacer material layer that may be formed as a conductive layer or subsequently at least partially replaced by a conductive layer).

[0067] In an alternative embodiment, the support pillar structure 20 may be formed in the support opening 19 simultaneously with the memory opening filling structure 58 formed in the memory opening 49. In this case, the support pillar structure 20 comprises the same material as the memory opening filling structure 58.

[0068] An annealing process can be performed to activate the electrically dopants in the drain region 63 and the vertical semiconductor channel 60. In this case, any amorphous semiconductor material in the vertical semiconductor channel 60 is converted into a polycrystalline semiconductor material. In one embodiment, the grains within the vertical semiconductor channel 60 may extend primarily along a corresponding local direction perpendicular to a corresponding proximal portion of the inner sidewall of the vertical semiconductor channel 60 and perpendicular to a corresponding proximal portion of the outer sidewall of the vertical semiconductor channel 60. As used herein, if more than 50% of the drain extends along a particular direction, the grains extend primarily along that particular direction.

[0069] refer to Figure 8A and Figure 8B This illustrates a first exemplary structure after a memory aperture fill structure 58 is formed within a memory aperture 49. The memory aperture fill structure 58 is located within the memory aperture 49. Each memory aperture fill structure in the memory aperture fill structure 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60.

[0070] Therefore, an alternating stack (32, 42) of insulating layer 32 and sacrificial material layer 42 is formed on a substrate (such as carrier substrate 9). Spacer layers are formed as conductive layers or subsequently replaced by conductive layers. Memory openings 49 are formed through the alternating stacks (32, 42). Memory opening fill structures 58 are formed in the memory openings 49. Each memory opening fill structure in the memory opening fill structures 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60 laterally surrounded by the corresponding memory film 50. The memory opening fill structures 58 are arranged in rows extending laterally along a first horizontal direction hd1, and these rows are laterally spaced from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Each memory opening fill structure in the memory opening fill structures 58 includes a vertical stack of memory elements (which may include portions of the memory film 50 located at the level of the sacrificial material layer 42) and a corresponding drain region 63.

[0071] refer to Figure 9A and Figure 9B A dielectric material, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass, can be deposited over the alternating stacks (32, 42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 can be in the range of 100 nm to 600 nm, such as 200 nm to 400 nm, but smaller and larger thicknesses are also possible.

[0072] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be photolithographically patterned to form elongated openings extending laterally between adjacent clusters of the memory aperture-fill structure 58 along a first horizontal direction hd1. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stacks (32, 42), and the stepped dielectric material portions 65, and onto the top surface of the carrier substrate 9. Lateral isolation trenches 79 extending laterally along the first horizontal direction hd1 may be formed through the alternating stacks (32, 42), the stepped dielectric material portions 65, and the contact-level dielectric layer 80. Each lateral isolation trench 79 may include a pair of corresponding longitudinal sidewalls parallel to the first horizontal direction hd1 and extending vertically from the top surface of the contact-level dielectric layer 80 to the top surface of the carrier substrate 9. The surface of the carrier substrate 9 may be physically exposed beneath each lateral isolation trench 79. The photoresist layer can then be removed, for example, by ashing.

[0073] refer to Figure 10 For example, an isotropic etching process can be used to introduce an etchant into the lateral isolation trench 79, which selectively etches the material of the sacrificial material layer 42 relative to the material of the insulating layer 32. Lateral recesses 43 are formed in the volume where the sacrificial material layer 42 is removed. The sacrificial material layer 42 can be selectively removed with respect to the materials of the insulating layer 32, the stepped dielectric material portion 65, and the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer 42 may comprise silicon nitride, and the materials of the insulating layer 32 and the stepped dielectric material portion 65 may comprise silicon oxide.

[0074] The etching process for selectively removing the second material from the outermost layer of the first material and memory film 50 can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process in which an etchant is introduced in the vapor phase into the lateral isolation trench 79. For example, if the sacrificial material layer 42 comprises silicon nitride, the etching process can be a wet etching process in which the first exemplary structure is immersed in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride against silicon oxide, silicon, and various other materials used in this technology. The support pillar structure 20, the stepped dielectric material portion 65, and the memory stack structure 55 provide structural support, while the lateral recess 43 exists within the volume previously occupied by the sacrificial material layer 42.

[0075] Each lateral recess 43 may be a laterally extending cavity whose lateral dimension is greater than the vertical extent of the cavity. In other words, the lateral dimension of each lateral recess 43 may be greater than the height of the lateral recess 43. Multiple lateral recesses 43 may be formed in the volume from which the second material from which the sacrificial material layer 42 is removed. Compared to the lateral recesses 43, the memory opening in which the memory stack structure 55 is formed is referred to herein as a front opening or a front chamber.

[0076] Each of the plurality of lateral recesses 43 may extend substantially parallel to the top surface of the carrier substrate 9. The lateral recesses 43 may be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each lateral recess 43 may always have a consistent height.

[0077] refer to Figure 11 Optionally, an external barrier dielectric layer (not explicitly illustrated) may be formed. The external barrier dielectric layer (if present) comprises a dielectric material that acts as a control gate dielectric for a control gate subsequently formed in the lateral recess 43. The external barrier dielectric layer is optional if a barrier dielectric layer 52 is present within each memory opening. An external barrier dielectric layer is present if the barrier dielectric layer 52 is omitted.

[0078] At least one conductive material can be deposited in the lateral recess 43 by providing at least one reactive gas into the lateral recess 43 via a lateral isolation trench 79. A metal barrier layer can be deposited in the lateral recess 43. The metal barrier layer comprises a conductive metal material that can be used as a diffusion barrier layer and / or adhesion promoting layer for a subsequently deposited metal filler material. The metal barrier layer may comprise a conductive metal nitride material, such as TiN, TaN, WN, or a stack thereof, or may comprise a conductive metal carbide material, such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer can be deposited using a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer can range from 2 nm to 8 nm (e.g., 3 nm to 6 nm), but smaller and larger thicknesses are also possible. In one embodiment, the metal barrier layer may consist substantially of a conductive metal nitride such as TiN.

[0079] A metal filler material is deposited in a plurality of lateral recesses 43, on the sidewalls of at least one lateral isolation trench 79, and above the top surface of the contact layer dielectric layer 80 to form a metal filler material layer. The metal filler material can be deposited using conformal deposition methods, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or combinations thereof. In one embodiment, the metal filler material layer may consist substantially of at least one elemental metal. The at least one elemental metal of the metal filler material layer may be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal filler material layer may consist substantially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas (such as WF6) may be used to deposit the metal filler material layer. In one embodiment, the metal filler material layer may be a tungsten layer including residual levels of fluorine atoms as impurities. The metal filler material layer is separated from the insulating layer 32 and the memory stack structure 55 by a metal barrier layer, which is a metal barrier layer that prevents fluorine atoms from diffusing through it.

[0080] Multiple conductive layers 46 can be formed in multiple lateral recesses 43, and a continuous metal material layer can be formed on the sidewalls of each lateral isolation trench 79 and over the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of a metal barrier layer and a portion of a metal filler layer, these portions being located between a pair of vertically adjacent dielectric material layers (such as a pair of insulating layers 32). The continuous metal material layer includes continuous portions of the metal barrier layer and continuous portions of the metal filler layer, these continuous portions being located in the lateral isolation trench 79 or over the contact-level dielectric layer 80.

[0081] The deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each lateral isolation trench 79 and from above the contact-level dielectric layer 80 by performing an isotropic etching process of at least one conductive material in the lateral isolation trench 79. Each remaining portion of the metal material deposited in the lateral recess 43 constitutes a conductive layer 46. Each conductive layer 46 may be a wire structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46. Typically, the conductive layer 46 can be formed by providing a metal precursor gas into the lateral isolation trench 79 and the lateral recess 43.

[0082] At least one uppermost conductive layer 46 may include a drain-side select gate electrode. At least one bottommost conductive layer 46 may include a source-side select gate electrode. The remaining conductive layers 46 may include word lines. Each word line serves as a common control gate electrode for multiple vertical NAND strings (e.g., memory aperture-filled structure 58).

[0083] refer to Figure 12A dielectric filler material (such as silicon oxide) can be deposited in the lateral isolation trench 79. Excess portions of the dielectric filler material can be removed from above the contact-level dielectric layer 80. Each remaining portion of the dielectric filler material filling a corresponding lateral isolation trench 79 constitutes a lateral isolation trench fill structure 76, which may be a dielectric wall structure. In an alternative embodiment, insulating spacers with a tubular configuration can be formed in the peripheral portion of each lateral isolation trench 79, and through-stacked conductive via structures can be formed within a corresponding insulating spacer. In this case, each lateral isolation trench fill structure 76 may include a combination of a through-stacked conductive via structure and insulating spacers laterally surrounding the through-stacked conductive via structure.

[0084] Alternating stacks (32, 46) of insulating layer 32 and conductive layer 46 may be formed in the memory block region between each pair of adjacent lateral isolation trench fill structures 76. The alternating stacks (32, 46) may include at least one drain-select level conductive layer (i.e., drain-side select gate electrode) (46A, 46B) for activating or deactivating NAND strings extending vertically through the alternating stacks (32, 46) (e.g., adjacent portions of the memory aperture fill structure 58 and conductive layer 46). A subset of conductive layers 46 underlying the drain-select level conductive layers (46A, 46B) includes word lines that include control electrodes for the NAND strings. A subset of one or more bottommost conductive layers 46 underlying the word lines includes source-side select gate electrodes. The at least one drain select level conductive layer (46A, 46B) may include a single drain select level conductive layer 46A, or may include multiple drain select level conductive layers (46A, 46B). In one embodiment, the at least one drain select level conductive layer (46A, 46B) may include at least one first conductive layer 46A (e.g., one or more intermediate drain-side select gate electrodes SGD) and optionally at least one second conductive layer 46B (i.e., at least one top drain-side select gate electrode SGDT) overlying the at least one first conductive layer 46A. In one embodiment, the at least one first conductive layer 46A may include a single first conductive layer 46A or multiple first conductive layers 46A, such as two to six first conductive layers 46A. In one embodiment, the at least one second conductive layer 46B may include a single second conductive layer 46B or multiple second conductive layers 46B, such as two to three second conductive layers 46B. Although an embodiment comprising two first conductive layers 46A and one second conductive layer 46B is shown, alternative embodiments in which different numbers of first conductive layers 46A and / or different numbers of second conductive layers 46B are explicitly contemplated herein.

[0085] refer to Figures 13A to 13E A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80 and can be photolithographically patterned to form linear openings that extend laterally in the memory array region 100 along a first horizontal direction hd1. The linear openings may have an elongated rectangular horizontal cross-sectional shape that extends laterally between corresponding adjacent pairs of rows of the memory opening-fill structures 58 (i.e., between the first row of memory opening-fill structures 58 and the second row of memory opening-fill structures 58). Each conductive layer 46 may be embedded within a corresponding external barrier dielectric layer 44, which may comprise a dielectric metal oxide material, such as aluminum oxide or titanium oxide. Each external barrier dielectric layer 44 may have a pair of horizontally extending portions in contact with a corresponding insulating layer in the insulating layer 32, and a plurality of tubular portions laterally surrounding and connecting the pair of horizontally extending portions of the corresponding memory opening-fill structure in the memory opening-fill structure 58. The thickness of each external barrier dielectric layer 44 may range from 1 nm to 6 nm, but smaller and larger thicknesses are also possible.

[0086] A first anisotropic etching process can be performed to transfer a pattern of openings in the photoresist layer through the contact-level dielectric layer 80, through the topmost insulating layer 32T, and through the at least one second conductive layer 46B (if present). Trenches with an elongated rectangular horizontal cross-sectional shape can be formed through the contact-level dielectric layer 80, through the topmost insulating layer 32T, and through the at least one second conductive layer 46B (if present). These trenches cut through the at least one second conductive layer 46B (if present) and are subsequently modified in a later processing step (described below) to cut through the at least one first conductive layer 46A to provide electrical isolation between electrode strips formed at the drain select level. These trenches are referred to herein as in-process drain select level isolation trenches 71'. Each patterned portion of the at least one second conductive layer 46B is referred herein as a second drain select level electrode strip 462. Therefore, each second conductive layer 46B is divided into a corresponding plurality of second drain select level electrode strips 462, which are laterally spaced from each other along a second horizontal direction (e.g., bit line direction) hd2 through at least one drain select level isolation trench 71'.

[0087] In summary, the alternating stack (32, 46) includes a second conductive layer 46B overlying the first conductive layer 46A, and a drain selection level isolation trench 71' is formed during the process by performing a first anisotropic etching process through the second conductive layer 46B. In one embodiment, the sidewalls of the drain selection level isolation trench 71' may be straight and may optionally cut through portions of the memory opening fill structures 58 located in the first and second rows. In other words, the drain selection level isolation trench 71' may be formed between the first row memory opening fill structure 58 and the second row memory opening fill structure 58.

[0088] refer to Figure 14 The dielectric pad layer 73L is conformally deposited over the contact-level dielectric layer 80 and in the peripheral region of the process drain-selection-level isolation trench 71'. The dielectric pad layer 73L comprises a dielectric material different from the dielectric material of the insulating layer 32. The dielectric pad layer 73L may comprise silicon nitride, silicon carbonitride, or dielectric metal oxide and may be deposited by conformal deposition processes such as chemical vapor deposition or atomic layer deposition. The thickness of the dielectric pad layer 73L may be in the range of 1 nm to 15 nm, such as 2 nm to 8 nm, but smaller and larger thicknesses are also possible. The dielectric pad layer 73L is formed in the peripheral portion of each process drain-selection-level isolation trench 71'. The dielectric pad layer 73L may contact each of the second drain-selection-level electrode strips 462 and may be located over the at least one first conductive layer 46A.

[0089] An optional etch mask material layer 77 may be deposited over the dielectric pad layer 73L. Alternatively, the inner etch mask layer 77 may be omitted. If present, the etch mask material layer 77 comprises a material that can be used as an etch mask material during a subsequent second anisotropic etch process for vertically extending the drain selection level isolation trench 71'. In an illustrative example, the etch mask material layer 77 may comprise a carbon-based material, such as amorphous carbon, diamond-like carbon, or a commercially available patterned film, such as Advanced Patterned Film™ available from Applied Materials. In one embodiment, the etch mask material layer 77 may be deposited using a non-conformal deposition process, such as plasma-enhanced chemical vapor deposition. Due to the anisotropic nature of the deposition process used to deposit the etch mask material layer 77, the etch mask material layer 77 covers the top surface of the horizontally extended portion of the dielectric pad layer 73L and includes an elongated gap over the region of the drain selection level isolation trench 71' during the process. The thickness of the horizontally extended portion of the etched mask material layer 77 can range from 20 nm to 200 nm, but smaller and larger thicknesses are also possible.

[0090] refer to Figures 15A to 15D A second anisotropic etching process can be performed to etch the horizontal portion of the dielectric pad layer 73L. If the etching mask material layer 77 is omitted, the second anisotropic etching process includes sidewall spacer etching, such as reactive ion etching, which leaves the vertical sidewall spacer portion of the dielectric pad layer 73L on the sidewall of the drain selection level isolation trench 71' during the vertical level of the at least one second conductive layer 46B. If the etching mask material layer 77 is present, the second anisotropic etching process etches the bottom portion of the dielectric pad layer 73L not masked by the etching mask material layer 77 from the bottom of the drain selection level isolation trench 71' during the process.

[0091] The second anisotropic etching process then etches portions of the underlying material layer comprising each of the at least one first conductive layer 46A, without etching a subset of the conductive layers 46 used as word lines (which lie beneath the at least one first conductive layer 46A). The second anisotropic etching process may utilize a cavity pattern having a pair of straight sidewalls extending laterally along a first horizontal direction hd1 below a drain selection level isolation trench 71' in each process. The cavity pattern may have an elongated rectangular horizontal cross-sectional shape. Therefore, the second anisotropic etching process causes the drain selection level isolation trench 71' to extend vertically through the first conductive layer 46A during the process and transforms the drain selection level isolation trench 71' into a drain selection level isolation trench 71. Each first conductive layer 46A may be divided into a corresponding set of first drain selection level electrode strips 461. The upper portion of each drain select level isolation trench 71 may be filled with a corresponding portion of the dielectric liner layer 73L (e.g., a sidewall spacer portion). In one embodiment, the surface of the first drain select level electrode strip 461 exposed to the drain select level isolation trench 71 may include a flat surface segment parallel to the first horizontal direction hd1.

[0092] refer to Figure 16A and 16B The etching mask material layer 77 (if present) can be selectively removed from the dielectric pad layer 73L, the insulating layer 32, and the conductive layer 46. For example, the etching mask material layer 77 can be removed by ashing. Alternatively, if the etching mask material layer 77 is omitted, the removal step is omitted.

[0093] Figure 17A , Figure 17B and Figure 17C This is a sequential horizontal cross-sectional view of the region of the first exemplary structure during each step of the isotropic etching process used to laterally extend the lower portion of each drain selection level isolation trench 71.

[0094] refer to Figure 17AThe first etching step of an isotropic etching process can be performed, which may include an etching chemical that selectively etches the material of the conductive layer relative to the material of the dielectric pad layer 73L. For example, if the conductive layer 46 comprises a combination of a titanium nitride barrier pad and a tungsten filler material, a wet etching process using a mixture of hydrogen peroxide (H2O2) and ammonium hydroxide (NH4OH) or a mixture of hydrogen peroxide and sulfuric acid can be used as the first etching step of the isotropic etching process. The first etching step can etch the proximal portion of the insulating layer 32 and the memory film 50 in parallel at an etching rate lower than the etching rate of the material of the conductive layer 46.

[0095] For example, a drain select level isolation trench 71 may be formed between a first row of memory aperture fill structures 58 arranged along a first horizontal direction hd1 and a second row of memory aperture fill structures 58 arranged along the first horizontal direction hd1. The first row and the second row may be a pair of adjacent rows spaced apart from each other along a second horizontal direction hd2. In one embodiment, the memory aperture fill structures 58 in the first row may be laterally offset along the first horizontal direction hd1 from the memory aperture fill structures 58 in the second row by half the spacing of the memory aperture fill structures 58 in each row of memory aperture fill structures 58. The duration of the first etching step may be selected such that each memory aperture fill structure 58 located in a pair of adjacent rows of memory aperture fill structures 58 adjacent to each drain select level isolation trench 71 has a surface portion exposed to the corresponding drain select level isolation trench 71. In one embodiment, the physically exposed surface portion of the memory aperture fill structure 58 may be a laterally convex and vertically straight surface portion. As used herein, a laterally convex surface portion refers to a surface portion having a convex profile in a horizontal cross-sectional view. As used herein, a transverse concave surface segment refers to a surface segment that has a concave profile in a horizontal cross-sectional view. As used herein, a vertically straight surface segment refers to a surface segment that has a straight profile in a vertical cross-sectional view.

[0096] refer to Figure 17BA second etching step of an isotropic etching process can be performed to selectively etch the materials of the outer barrier dielectric layer 44 and the memory film 50 for the materials of the vertical semiconductor channel 60. In one embodiment, each memory film 50 may include a stack of layers of barrier dielectric layer 52, memory material layer 54, and tunneling dielectric layer 56. In an illustrative embodiment, the outer barrier dielectric layer 44 includes aluminum oxide, the barrier dielectric layer 52 includes silicon oxide, the memory material layer 54 includes silicon nitride as a charge trapping material, and the tunneling dielectric layer 56 includes an ONO stack. In this embodiment, the second step of the isotropic etching process may include a series of wet etching steps, such as a first wet etching step using a mixture of phosphoric acid, acetic acid, and nitric acid to etch aluminum oxide, a second wet etching step using dilute hydrofluoric acid to etch silicon oxide, a third wet etching step using phosphoric acid to etch silicon nitride, and a fourth wet etching step sequentially applying dilute hydrofluoric acid, phosphoric acid, and dilute hydrofluoric acid to etch the ONO stack. The portion of the external barrier dielectric layer 44 and memory film 50 near the drain select level isolation trench 71 can be removed at the level of the first drain select level electrode strip 461, while the dielectric pad layer 73L (or its remaining sidewall spacers) protects the second drain select level electrode strip 462 from etching.

[0097] refer to Figure 17C A third etching step of an isotropic etching process can be performed to etch the portion of the vertical semiconductor channel 60 exposed to the drain select level isolation trench 71. For example, a wet etching process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethyl ammonium hydroxide (TMAH) can be performed to etch the portion of the polycrystalline or amorphous silicon vertical semiconductor channel 60 exposed to the drain select level isolation trench 71.

[0098] refer to Figures 17A to 17C The isotropic etching process described, including a first etching step, a second etching step, and a third etching step, laterally extends each drain select level isolation trench 71 at the level of the first drain select level electrode strip 461, but does not extend each drain select level isolation trench at the level of the second drain select level electrode strip 462. Therefore, the wider second drain select level electrode strip 462 can be used in the gate-induced drain leakage (GIDL) current erasure step without degrading the erasure performance level.

[0099] refer to Figures 18A to 18DThe isotropic etching process may optionally include a fourth etching step, wherein the portion of the dielectric core 62 exposed to the drain select level isolation trench 71 is laterally recessed. In this case, a wet etching process using dilute hydrofluoric acid may be used in the fourth etching step to etch the silicon oxide dielectric core 62. The portion of the insulating layer 32 exposed to the drain select level isolation trench 71 may incidentally be recessed, while the dielectric pad layer 73L (or its sidewall spacers) protects the second drain select level electrode strip 462 and a subset of the insulating layer 32 overlying the first drain select level electrode strip 461.

[0100] As in Figure 16A and Figure 16B Each drain selection hierarchical isolation trench 71 provided at the processing step includes a corresponding volume of a cavity with a linear cavity pattern. (Refer to...) Figures 18A to 18D Following the described processing steps, each drain selection level isolation trench 71 includes a corresponding volume of cavity formed by extending the cavity pattern at a vertical level of the first drain selection level electrode strip 461, rather than at a vertical level overlying the second drain selection level electrode strip 462. Each drain selection level isolation trench 71 may be formed between a corresponding first row memory aperture fill structure 58 and a corresponding second row memory aperture fill structure 58. Gaps exist between the memory aperture fill structures 58 within each row of memory aperture fill structures 58 arranged along the first horizontal direction hd1. Figure 17C Processing steps and / or Figures 18A to 18D After the processing steps, each drain selection level isolation trench 71 protrudes laterally into each memory opening fill structure 58 in the first and second rows, and does not protrude laterally into the first drain selection level electrode strip 461 in the gap between adjacent pairs of memory opening fill structures 58 laterally spaced along the first horizontal direction hd1 in the first and second rows.

[0101] In one embodiment, each memory opening-fill structure in the memory opening-fill structure 58 includes a corresponding dielectric core 62 laterally surrounded by a corresponding vertical semiconductor channel 60, and each dielectric core 62 in the first and second rows is exposed to a drain select level isolation trench 71. In one embodiment, a surface portion of each inner sidewall of the vertical semiconductor channel 60 in the memory opening-fill structure 58 in the first and second rows is exposed to the drain select level isolation trench 71. In one embodiment, a horizontally convex and vertically straight surface portion of the dielectric core 62 in the first and second rows is exposed to the drain select level isolation trench 71. A surface portion of the sidewall of the first drain select level electrode strip 461 is physically exposed to a cavity formed within the volume of the memory opening 49 as the drain select level isolation trench 71 laterally expands. The portion of the first drain select level electrode strip 461 located within the gap between adjacent pairs of memory aperture fill structures 58 (these adjacent pairs of memory aperture fill structures are laterally spaced along the first horizontal direction hd1) may include a straight and flat sidewall section parallel to the first horizontal direction hd1 and exposed to the drain select level isolation trench 71. Therefore, by reducing or eliminating the non-gated portion of the external barrier dielectric layer 44, and by positioning all portions of the external barrier dielectric layer 44 adjacent to the corresponding first drain select level electrode strip 461 in the corresponding vertical level, it is believed that this reduces electron decapture from the memory material layer 54.

[0102] Generally, a drain-select-level isolation trench 71 is formed through a subset of the conductive layer 46, including the first conductive layer 46A, such that the drain-select-level isolation trench 71 divides the first conductive layer 46A into a pair of first drain-select-level electrode strips 461. The drain-select-level isolation trench 71 includes a volume formed by removing portions of the first row memory opening-fill structure 58 and the second row memory opening-fill structure 58. Each lateral protrusion of the horizontal cross-sectional shape of the drain-select-level isolation trench 71 cuts through the edge portion of a corresponding memory opening-fill structure in the memory opening-fill structure 58. Damage to the external barrier dielectric layer 44 and / or the formation of non-gated portions can be avoided or minimized to avoid or minimize electron decapture.

[0103] refer to Figures 19A to 19EOptionally, the dielectric liner layer 73L can be selectively removed from the contact-level dielectric layer 80 and the alternating stacks (32, 46). Dielectric filler material can be conformally deposited in the volume of voids within the drain-selection-level isolation trench 71. The dielectric filler material may include planarizable dielectric materials, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass. The portion of the dielectric filler material and the dielectric liner layer 73L overlying the top surface of the contact-level dielectric layer 80 can be removed by performing a planarization process employing chemical mechanical polishing. Each remaining portion of the dielectric filler material retained in the respective drain-selection-level isolation trench 71 constitutes a dielectric filler portion 72. Each remaining portion of the dielectric liner layer 73L retained in the respective drain-selection-level isolation trench 71 (if any) constitutes a dielectric liner 73 (i.e., a sidewall spacer).

[0104] Optionally, the dielectric filling material portion 72 may be embedded in the air gap 75, which contains no solid material, at the level of the first drain selection layer electrode strip 461. The collection of all structural elements filling the corresponding drain selection layer isolation trench 71 constitutes the drain selection layer isolation structure (72, optionally 73 and / or 75). Therefore, the drain selection layer isolation structure (72, optionally 73 and / or 75) may be formed in each drain selection layer isolation trench 71.

[0105] Drain-selection hierarchical isolation structures (72, optionally 73 and / or 75) may be formed between and in contact with the first row memory opening-fill structure 58 and the second row memory opening-fill structure 58. The drain-selection hierarchical isolation structures (72, optionally 73 and / or 75) extend vertically through a subset of layers within the alternating stack (32, 46) and generally extend laterally along a first horizontal direction hd1, wherein there are lateral undulations along a second horizontal direction hd2, such that the first conductive layer 46A within the alternating stack (32, 46) is divided into a group of at least two first drain-selection hierarchical electrode strips 461. The drain selection hierarchy isolation structure (72, optionally 73 and / or 75) protrudes laterally into each memory opening fill structure 58 in the first and second rows, and does not protrude laterally into the first drain selection hierarchy electrode strip (i.e., SGD electrode) 461 in the gap between adjacent pairs of memory opening fill structures 58 laterally spaced along the first horizontal direction hd1 in the first and second rows.

[0106] In one embodiment, each memory aperture fill structure 58 includes a corresponding dielectric core 62 laterally surrounded by a vertical semiconductor channel 60; and a drain selection hierarchical isolation structure (72, optionally 73 and / or 75) contacts each dielectric core 62 in the first and second rows. In one embodiment, for each memory aperture fill structure 58, the corresponding vertical semiconductor channel 60 includes an inner sidewall; and the drain selection hierarchical isolation structure (72, optionally 73 and / or 75) contacts a surface portion of the inner sidewall of the vertical semiconductor channel 60 of each memory aperture fill structure 58 in the first and second rows.

[0107] In one embodiment, the drain selection hierarchical isolation structure (72, optionally 73 and / or 75) includes horizontally concave and vertically straight surface segments that contact horizontally convex and vertically straight surface segments of the dielectric core 62 in the first and second rows.

[0108] In one embodiment, a portion of the drain selection hierarchy isolation structure (72, optionally 73 and / or 75) is located within a subset of the memory openings 49, which includes the first row of memory openings 49 and the second row of memory openings 49; and a portion of the drain selection hierarchy isolation structure (72, optionally 73 and / or 75) contacts a surface segment of the sidewall of the first drain selection hierarchy electrode strip 461.

[0109] In one embodiment, the portion of the drain selection hierarchy isolation structure (72, optionally 73 and / or 75) located within the gap between adjacent pairs of memory opening filling structures 58 laterally spaced along the first horizontal direction hd1 includes a straight sidewall segment parallel to the first horizontal direction hd1 and in contact with a corresponding first drain selection hierarchy electrode strip 461.

[0110] In one embodiment, the first conductive layer 46A lies beneath the second conductive layer 46B of the conductive layer 46. The second conductive layer 46B is closer to the drain region 63 of the memory aperture filling structure 58 than the first conductive layer 46A to the drain region 63. Drain selection layer isolation structures (72, optionally 73, and / or 75) divide the second conductive layer 46B into a pair of second drain selection layer electrode strips 462. In one embodiment, the drain selection layer isolation structures (72, optionally 73, and / or 75) are laterally wider at the vertical level of the first drain selection layer electrode strip 461 than the second drain selection layer electrode strips 462. In one embodiment, the interface between the drain selection layer isolation structures (72, optionally 73, and / or 75) and the pair of second drain selection layer electrode strips 462 consists of a flat surface segment parallel to the first horizontal direction hd1. In one embodiment, the interface between the drain selection hierarchical isolation structure (72, optionally 73 and / or 75) in the first and second rows and the memory opening filling structure 58 consists of a flat surface segment parallel to the first horizontal direction hd1.

[0111] In one embodiment, the drain select level isolation structure (72, optionally 73 and / or 75) includes: a dielectric liner layer 73L that contacts the pair of second drain select level electrode strips 462 but not the pair of first drain select level electrode strips 461; and a dielectric filler portion 72 comprising an upper portion laterally surrounded by the dielectric liner layer 73L and a lower portion lying beneath the dielectric liner layer 73L and contacting the pair of first drain select level electrode strips 461. In one embodiment, the upper portion of the dielectric filler portion 72 has a smaller width along a second horizontal direction hd2 than the lower portion of the dielectric filler portion 72; and the lower portion of the dielectric filler portion 72 includes an air gap 75 containing no solid phase material.

[0112] refer to Figure 20A and Figure 20B Contact via structures (88, 86) may be formed through the contact-level dielectric layer 80 and optionally through the stepped dielectric material portion 65. For example, a drain contact via structure 88 may be formed through the contact-level dielectric layer 80 on each drain region 63. A layer contact via structure 86 may be formed on the conductive layer 46 through the contact-level dielectric layer 80 and through the stepped dielectric material portion 65.

[0113] refer to Figure 21Additional dielectric material layers and additional metal interconnect structures may be formed above the contact-level dielectric layer 80. The additional dielectric material layer may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structures may include metal via structures, metal line structures, and / or integrated metal line and via structures. The additional dielectric material layer formed above the contact-level dielectric layer 80 is referred to herein as memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as memory-side metal interconnect structures 980. The memory-side dielectric material layer 960 includes bit-line level dielectric material layers with embedded bit lines, which are a subset of the memory-side metal interconnect structures 980.

[0114] Metal bonding pads (referred to herein as memory-side bonding pads 988) may be formed at the topmost layer of the memory-side dielectric material layer 960. The memory-side bonding pads 988 may be electrically connected to various nodes of the memory-side metal interconnect structure 980 and the three-dimensional memory array, including the conductive layer 46 and the memory opening fill structure 58. Thus, a memory die 900 may be provided.

[0115] A memory-side dielectric material layer 960 is formed over alternating stacks (32, 46). A memory-side metal interconnect structure 980 is embedded in the memory-side dielectric material layer 960. A memory-side bonding pad 988 may be embedded within the memory-side dielectric material layer 960, and specifically embedded in the topmost layer of the memory-side dielectric material layer 960. The memory-side bonding pad 988 may be electrically connected to the memory-side metal interconnect structure 980.

[0116] In one embodiment, the memory die 900 may include: a three-dimensional memory array underlying a first dielectric material layer 110 and comprising alternating stacks (32, 46) of insulating layer 32 and conductive layer 46; a two-dimensional array of memory openings 49 extending vertically through the alternating stacks (32, 46); a two-dimensional array of memory opening-filling structures 58 located within the two-dimensional array of memory openings 49 and comprising corresponding vertical stacks of memory elements and corresponding vertical semiconductor channels 60; and a two-dimensional array of contact via structures (such as drain contact via structure 88) overlying the three-dimensional memory array and electrically connected to a corresponding vertical semiconductor channel in the vertical semiconductor channel 60.

[0117] refer to Figure 22A logic die 700 may be provided. The logic die 700 includes a logic-side substrate 709, peripheral circuitry 720 located on the logic-side substrate 709 and including logic-side semiconductor devices (such as field-effect transistors), a logic-side metal interconnect structure 780 embedded within a logic-side dielectric material layer 760, and logic-side bonding pads 788. The peripheral circuitry 720 may be configured to control the operation of a memory array within the memory die 900. Specifically, the peripheral circuitry 720 may be configured to drive various electrical components within the memory array, including (but not limited to) a conductive layer 46, a drain region 63, and subsequently formed source contact structures. The peripheral circuitry 720 may be configured to control the vertical stacking of memory elements in the memory array within the memory die 900.

[0118] refer to Figure 23 The logic die 700 can be attached to the memory die 900, for example, by bonding logic-side bonding pads 788 to memory-side bonding pads 988 at a bonding interface. The bonding between the memory die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700), a die-to-die bonding process, or a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within the corresponding memory die 900.

[0119] refer to Figure 24 The substrate 9 can be removed, for example, by grinding, polishing, pyrolysis, isotropic etching, anisotropic etching, and / or combinations thereof. If a chemical mechanical polishing or etching process is used as the final step for removing the substrate 9, the bottom insulating layer 32B can be used as a polishing stop or an etching stop, respectively.

[0120] In one embodiment, at least one final step of the at least one removal process for removing the carrier substrate 9 may include a selective wet etching process that selectively etches the material of the carrier substrate 9 (such as the semiconductor material of the carrier substrate 9) relative to the dielectric material of the memory film 50. In an exemplary example, if the carrier substrate 9 comprises a semiconductor material, the final step of the at least one removal process may include a wet etching process using thermally heated trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH). The entire carrier substrate 9 can be removed by a selective wet etching process. The back-side end surface of the support pillar structure 20 may be physically exposed after the carrier substrate 9 has been removed.

[0121] A series of wet etching steps can be performed to sequentially remove portions of the memory films 50 exposed on the back side of the alternating stacks (32, 46). For example, the internal barrier dielectric layer 52, memory material layer 54, and optional dielectric pad 56 (e.g., which may be a tunneling dielectric layer) of each memory film 50 can be removed from a region farther from the bonding interface between the memory die 900 and the logic die 700 than from the flat surface physically exposed to the bonding interface of the bottom insulating layer 32B. For convenience, the geometry of the exemplary and other exemplary structures in this disclosure can be described by the orientation on which the logic die 700 overlies the memory die 900. Viewed in this orientation, the barrier dielectric layer 52, memory material layer 54, and optional dielectric pad 56 (e.g., which may be a tunneling dielectric layer) of each memory film 50 can be removed from below a horizontal plane including the bottom surface of the bottom insulating layer 32B.

[0122] refer to Figures 25A to 25D The source layer 2 may be formed to contact the exposed end of the vertical semiconductor channel 60 and the back surface of the bottom insulating layer 32B. The source layer 2 may include a doped semiconductor (e.g., polysilicon) layer and / or one or more metal layers (e.g., TiN / W). A back insulating layer 4 may be formed over the at least one source layer 2, and a back contact pad structure 6 may be formed through the back insulating layer 4.

[0123] refer to Figures 26A to 26E Drain selection level isolation trenches 71 can be formed by passing through the contact level dielectric layer 80 and each of the at least one second conductive layer 46B and the at least one first conductive layer 46A, as well as each insulating layer 32 covering the bottommost first conductive layer 46A. Figure 12 The first exemplary structure shown derives a second exemplary structure from the second embodiment. A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be photolithographically patterned to form a pattern of discrete openings having corresponding lateral zigzag shapes. An anisotropic etching process may be performed to transfer the pattern of discrete openings through the contact-level dielectric layer 80 and each of the at least one second conductive layer 46B and the at least one first conductive layer 46A, as well as each insulating layer 32 overlying the bottommost first conductive layer 46A. The photoresist layer may then be removed.

[0124] Each drain selection level isolation trench 71 may have a horizontal cross-sectional shape of a tortuous line extending generally along a first horizontal direction hd1, wherein the lateral protrusions extend along a second horizontal direction hd2. Each drain selection level isolation trench 71 may be formed between a corresponding first row memory opening fill structure 58 and a corresponding adjacent second row memory opening fill structure 58.

[0125] According to one aspect of this disclosure, the lateral undulation pattern of the horizontal cross-sectional shape of the drain selection hierarchical isolation trench 71 may have the same spacing as the spacing of each row of memory opening fill structures 58 along the first horizontal direction hd1. Furthermore, the location of the largest lateral protrusion of each undulation may be at a corresponding memory opening fill structure in the memory opening fill structure 58, such that each lateral protrusion of the horizontal cross-sectional shape of the drain selection hierarchical isolation trench 71 cuts through the edge portion of the corresponding memory opening fill structure in the memory opening fill structure 58. Damage to the external barrier dielectric layer 44 and / or the formation of non-gated portions can be avoided or minimized to avoid or minimize electron decapture.

[0126] The portion of the drain selection layer isolation trench 71 located within the gap between adjacent pairs of memory aperture filling structures 58 (these adjacent pairs of memory aperture filling structures are laterally spaced along a first horizontal direction hd1) within a row of memory aperture filling structures 58 includes a lateral recessed region, wherein the drain selection layer isolation trench 71 is laterally recessed away from the row of the memory aperture filling structure 58 along a second horizontal direction hd1. A portion of the first drain selection layer electrode strip 461 and a portion of the second drain selection layer electrode strip 462 laterally protrude into the lateral recessed region.

[0127] In one embodiment, the drain-select-level isolation trench 71 may cut through portions of the dielectric core 62 within the row of adjacent pairs of memory aperture fill structures. In one embodiment, each memory aperture fill structure 58 includes a corresponding dielectric core 62 laterally surrounded by a vertical semiconductor channel 60. Laterally convex and vertically straight surface portions of the dielectric core 62 within the row of adjacent pairs of memory aperture fill structures 58 may be exposed to the drain-select-level isolation trench 71.

[0128] refer to Figures 27A to 27E Dielectric filler material (such as undoped or doped silicate glass) may be deposited in the drain select level isolation trench 71. A portion of the dielectric filler material covering the horizontal plane including the top surface of the contact level dielectric layer 80 may be removed by a planarization process (such as chemical mechanical polishing). Each remaining portion of the dielectric filler material filling a corresponding drain select level isolation trench 71 constitutes a drain select level isolation structure 72 that is substantially composed of dielectric filler material portions.

[0129] The drain selection hierarchy isolation structure 72 extends vertically through a subset of layers within the alternating stack (32, 46) and extends laterally generally along a first horizontal direction hd1, wherein it has lateral undulations along a second horizontal direction hd2. Each first conductive layer 46A within the alternating stack (32, 46) is divided into a corresponding set of at least two first drain selection hierarchy electrode strips 461, and each second conductive layer 46B within the alternating stack (32, 46) is divided into a corresponding set of at least two second drain selection hierarchy electrode strips 462. Each drain selection hierarchy isolation structure 72 contacts and is located between a corresponding first row memory opening-fill structure 58 and a corresponding second row memory opening-fill structure 58. In this embodiment, the drain selection hierarchy isolation structure 72 has substantially the same lateral thickness at the hierarchy of the first and second drain selection hierarchy electrode strips.

[0130] In the second exemplary structure, the portion of the drain select layer isolation structure 72 located within the gap between adjacent pairs of memory aperture filling structures 58 (these adjacent pairs of memory aperture filling structures are laterally spaced along the first horizontal direction hd1) includes a lateral recessed region having a horizontally concave surface segment. A portion of the first drain select layer electrode strip 461 protrudes laterally into the lateral recessed region.

[0131] In one embodiment, each longitudinal sidewall of the drain selection hierarchy isolation structure 72 in the second exemplary structure includes laterally alternating laterally convex and vertically straight surface segments and laterally concave and vertically straight surface segments. These laterally convex and vertically straight surface segments contact a corresponding memory opening filling structure in the memory opening filling structures 58 of the first and second rows, and these laterally concave and vertically straight surface segments contact a corresponding laterally convex and vertically straight surface segment of the first drain selection hierarchy electrode strip 461.

[0132] In one embodiment, each memory opening fill structure in the memory opening fill structure 58 includes a corresponding dielectric core 62 laterally surrounded by a vertical semiconductor channel 60; a laterally convex and vertically straight surface segment of the drain selection hierarchy isolation structure 72 contacts the laterally convex and vertically straight surface segment of the dielectric core 62 in the first and second rows.

[0133] refer to Figure 28 Reference can be performed on the second exemplary structure. Figures 20A to 25D The described processing steps.

[0134] Referring to all the accompanying drawings and according to various embodiments of the present disclosure, a three-dimensional memory device includes: an alternating stack (32, 46) of insulating layer 32 on conductive layer 46; a memory opening 49 extending vertically through the alternating stack (32, 46); memory opening filling structures 58 located in the memory opening 49, wherein each memory opening filling structure in the memory opening filling structures 58 includes a corresponding vertical semiconductor channel 60, a corresponding vertical stack of memory elements (e.g., embodied as portions of memory film 50 located at the level of conductive layer 46), and a corresponding drain region 63, wherein the memory opening filling structures 58 are arranged in rows extending laterally along a first horizontal direction hd1, and these rows are laterally spaced from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1; and a drain selection hierarchical isolation structure (72, optionally 73 and / or 75) extending vertically through the alternating stack (32, 46) A subset of conductive layers (e.g., 46A, 46B) within 46), and generally extending laterally along a first horizontal direction hd1, wherein there are lateral undulations along a second horizontal direction hd2, such that the first conductive layer 46A within the alternating stacks (32, 46) is divided into a group of at least two first drain selection level electrode strips 461. Drain selection level isolation structures (72, optionally 73 and / or 75) contact the first row memory opening fill structure 58 and the second row memory opening fill structure 58 and are located between the first row memory opening fill structure and the second row memory opening fill structure; and the drain selection level isolation structures (72, optionally 73 and / or 75) laterally protrude into each memory opening fill structure 58 in the first row and the second row, and do not laterally protrude into the first drain selection level electrode strips 461 in the gap between adjacent pairs of memory opening fill structures 58 laterally spaced along the first horizontal direction hd1 in the first row and the second row.

[0135] In one embodiment, each memory aperture fill structure 58 further includes a corresponding dielectric core 62 laterally surrounded by a vertical semiconductor channel 60; and a drain selection hierarchical isolation structure (72, optionally 73 and / or 75) contacts each dielectric core 62 in the first and second rows. In one embodiment, for each memory aperture fill structure 58, the corresponding vertical semiconductor channel 60 includes an inner sidewall; and the drain selection hierarchical isolation structure (72, optionally 73 and / or 75) contacts a surface portion of the inner sidewall of the vertical semiconductor channel 60 of each memory aperture fill structure 58 in the first and second rows. In one embodiment, the drain selection hierarchical isolation structure (72, optionally 73 and / or 75) includes horizontally concave and vertically straight surface portions that contact horizontally convex and vertically straight surface portions of the dielectric cores 62 in the first and second rows.

[0136] In one embodiment, a portion of the drain selection hierarchy isolation structure (72, optionally 73 and / or 75) is located within a subset of the memory openings 49, which includes the first row of memory openings 49 and the second row of memory openings 49; and a portion of the drain selection hierarchy isolation structure (72, optionally 73 and / or 75) contacts a surface segment of the sidewall of the first drain selection hierarchy electrode strip 461.

[0137] In one embodiment, the portion of the drain selection hierarchy isolation structure (72, optionally 73 and / or 75) located within the gap between adjacent pairs of memory opening filling structures 58 laterally spaced along the first horizontal direction hd1 includes a straight sidewall segment parallel to the first horizontal direction hd1 and in contact with a corresponding first drain selection hierarchy electrode strip 461.

[0138] In one embodiment, the first conductive layer 46A lies beneath the second conductive layer 46B of the conductive layer 46, wherein the second conductive layer 46B is closer to the drain region 63 than the first conductive layer 46A to the drain region 63 of the memory opening-fill structure 58; and a drain selection hierarchy isolation structure (72, optionally 73 and / or 75) divides the second conductive layer 46B into a pair of second drain selection hierarchy electrode strips 462. In one embodiment, the drain selection hierarchy isolation structure is wider at the vertical level of the first drain selection hierarchy electrode strip 461 than at the vertical level of the second drain selection hierarchy electrode strip 462.

[0139] In one embodiment, the interface between the drain select layer isolation structure (72, optionally 73 and / or 75) and the pair of second drain select layer electrode strips 462 includes a flat surface segment parallel to the first horizontal direction hd1. In one embodiment, the interface between the drain select layer isolation structure (72, optionally 73 and / or 75) in the first and second rows and the memory opening fill structure 58 includes a flat surface segment parallel to the first horizontal direction hd1.

[0140] In one embodiment, the drain select layer isolation structure (72, optionally 73 and / or 75) includes: a dielectric liner layer 73L that contacts the pair of second drain select layer electrode strips 462 but not the pair of first drain select layer electrode strips 461; and a dielectric filler portion 72 comprising an upper portion laterally surrounded by the dielectric liner layer 73L and a lower portion lying beneath the dielectric liner layer 73L and contacting the pair of first drain select layer electrode strips 461. In one embodiment, the upper portion of the dielectric filler portion 72 has a smaller width along a second horizontal direction hd2 than the lower portion of the dielectric filler portion 72; and the lower portion of the dielectric filler portion 72 includes an air gap 75.

[0141] In one embodiment, a portion of the drain select hierarchy isolation structure 72 located within the gap between adjacent pairs of memory opening-fill structures 58 laterally spaced along a first horizontal direction hd1 includes a laterally recessed region having a horizontally concave surface segment, wherein a portion of the first drain select hierarchy electrode strip 461 laterally protrudes into the laterally recessed region. In one embodiment, each longitudinal sidewall of the drain select hierarchy isolation structure 72 includes laterally alternating laterally convex and vertically straight surface segments and laterally concave and vertically straight surface segments, the laterally convex and vertically straight surface segments contacting a corresponding memory opening-fill structure in the first and second rows of memory opening-fill structures 58, and the laterally concave and vertically straight surface segments contacting a corresponding laterally convex and vertically straight surface segment of the first drain select hierarchy electrode strip 461.

[0142] In one embodiment, each memory opening-fill structure in the memory opening-fill structure 58 further includes a memory film 50 comprising an inner barrier dielectric layer 52, a tunneling dielectric layer 56, and a memory material layer 54 comprising a vertically stacked memory element and located between the inner barrier dielectric layer and the tunneling dielectric layer. An outer barrier dielectric layer 44 having a convex outer surface is located between the memory film 50 and the first drain select level electrode strip 461. The first drain select level electrode strip 461 contacts the entire convex outer surface of the outer barrier dielectric layer 44 at a vertical level of the first drain select level electrode strip, and the convex outer surface of the outer barrier dielectric layer 44 does not contact the drain select level isolation structure (72, optionally 73, and / or 75). Thus, the non-gated portion of the outer barrier dielectric layer 44 is eliminated.

[0143] While the foregoing relates to specific preferred embodiments, it should be understood that this disclosure is not limited thereto. Those skilled in the art will envision various modifications that can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “consistently consisting of” or “comprises of” replace all embodiments for which the words “comprising” or “including” are used. Whenever two or more elements are listed as alternatives in the same paragraph or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb “capable” is used in this disclosure to describe the formation of an element or the execution of a processing step, it is also clearly envisioned that embodiments in which such element or such processing step is not performed are included, provided that the resulting apparatus or device is capable of providing equivalent results. Therefore, whenever omitting such an element or the formation of such a processing step can provide the same or equivalent result, the auxiliary verb "can" applied to the formation of an element or the execution of a processing step should also be interpreted as "can" or "may, or may not," with these equivalent results including slightly superior and slightly inferior results. In cases where embodiments employing specific structures and / or configurations are illustrated in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise known to be impossible for a person skilled in the art. If any publications, patent applications, and / or patents are cited herein, each of such documents is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: Alternating stacking of insulating and conductive layers; A memory opening that extends vertically through the alternating stack; A memory aperture filling structure, the memory aperture filling structure being located in the memory aperture, wherein each memory aperture filling structure includes a corresponding vertical semiconductor channel, a corresponding vertical stack of memory elements, and a corresponding drain region, wherein the memory aperture filling structures are arranged in rows extending laterally along a first horizontal direction, and the rows are laterally spaced from each other along a second horizontal direction perpendicular to the first horizontal direction. and A drain-selection hierarchical isolation structure extends vertically through a subset of the conductive layers within the alternating stack and extends laterally generally along a first horizontal direction, wherein it has lateral undulations along a second horizontal direction, such that the first conductive layers within the alternating stack are divided into a group of at least two first drain-selection hierarchical electrode strips. in: The drain selection hierarchical isolation structure is in contact with the first row memory opening filling structure and the second row memory opening filling structure and is located between the first row memory opening filling structure and the second row memory opening filling structure; and The drain selection hierarchy isolation structure protrudes laterally into each memory opening fill structure in the first and second rows, and does not protrude laterally into the first drain selection hierarchy electrode strip within the gap between adjacent pairs of memory opening fill structures laterally spaced along the first horizontal direction in the first and second rows.

2. The three-dimensional memory device according to claim 1, wherein: Each memory aperture filling structure in the memory aperture filling structure further includes a corresponding dielectric core laterally surrounded by the vertical semiconductor channel; and The drain selection hierarchical isolation structure contacts each dielectric core in the first and second rows.

3. The three-dimensional memory device according to claim 2, wherein: For each memory aperture filling structure, the corresponding vertical semiconductor channel includes an inner sidewall; and The drain selection hierarchical isolation structure contacts the surface segment of the inner sidewall of the vertical semiconductor channel of each memory opening filling structure in the first and second rows.

4. The three-dimensional memory device of claim 2, wherein the drain selection hierarchical isolation structure includes a horizontally concave and vertically straight surface segment, the horizontally concave and vertically straight surface segment contacting a horizontally convex and vertically straight surface segment of the dielectric core in the first row and the second row.

5. The three-dimensional memory device according to claim 1, wherein: A portion of the drain selection hierarchical isolation structure is located within a subset of the memory openings, and this subset includes the first row of memory openings and the second row of memory openings; and The portion of the drain selection layer isolation structure contacts the surface segment of the sidewall of the first drain selection layer electrode strip.

6. The three-dimensional memory device of claim 1, wherein the portion of the drain selection hierarchy isolation structure located within the gap between the adjacent pairs of memory opening filling structures laterally spaced along the first horizontal direction includes a straight sidewall segment parallel to the first horizontal direction and in contact with a corresponding first drain selection hierarchy electrode strip in the first drain selection hierarchy electrode strip.

7. The three-dimensional memory device according to claim 1, wherein: The first conductive layer lies beneath a second conductive layer within the first conductive layer, wherein the second conductive layer is closer to the drain region than the drain region of the memory aperture filling structure; and The drain selection layer isolation structure divides the second conductive layer into a pair of second drain selection layer electrode strips.

8. The three-dimensional memory device of claim 7, wherein the drain selection layer isolation structure is wider at the vertical level of the first drain selection layer electrode strip than at the vertical level of the second drain selection layer electrode strip.

9. The three-dimensional memory device according to claim 7, wherein: The interface between the drain selection layer isolation structure and the pair of second drain selection layer electrode strips includes a flat surface segment parallel to the first horizontal direction; and The interface between the drain selection hierarchical isolation structure in the first row and the memory aperture filling structure includes a flat surface segment parallel to the first horizontal direction.

10. The three-dimensional memory device of claim 7, wherein the drain selection hierarchical isolation structure comprises: A dielectric pad that contacts the pair of second drain select layer electrode strips but not the pair of first drain select layer electrode strips; and The dielectric filling material portion includes an upper portion laterally surrounded by the dielectric pad and a lower portion lying beneath the dielectric pad and in contact with the pair of first drain selection layer electrode strips.

11. The three-dimensional memory device according to claim 10, wherein: The upper portion of the dielectric filling material portion has a smaller width along the second horizontal direction than the lower portion of the dielectric filling material portion; and The lower portion of the dielectric filling material portion includes an air gap.

12. The three-dimensional memory device of claim 1, wherein the portion of the drain selection hierarchy isolation structure located within the gap between the adjacent pairs of memory opening filling structures laterally spaced along the first horizontal direction includes a lateral recessed region having a horizontally concave surface segment, wherein a portion of the first drain selection hierarchy electrode strip laterally protrudes into the lateral recessed region.

13. The three-dimensional memory device of claim 12, wherein each longitudinal sidewall of the drain selection hierarchy isolation structure comprises laterally alternating laterally convex and vertically straight surface segments and laterally concave and vertically straight surface segments, the laterally convex and vertically straight surface segments contacting a corresponding memory opening filling structure in the first row and the second row, and the laterally concave and vertically straight surface segments contacting a corresponding laterally convex and vertically straight surface segment of the first drain selection hierarchy electrode strip.

14. The three-dimensional memory device according to claim 1, wherein: Each memory opening filling structure in the memory opening filling structure further includes a memory film, the memory film including an inner barrier dielectric layer, a tunneling dielectric layer and a memory material layer, the memory material layer including a vertically stacked memory element and located between the inner barrier dielectric layer and the tunneling dielectric layer; An external barrier dielectric layer with a convex outer surface is located between the memory film and the first drain select layer electrode strip; The first drain selection layer electrode strip contacts the entire convex outer surface of the external barrier dielectric layer at the vertical level of the first drain selection layer electrode strip; and The convex outer surface of the external blocking dielectric layer does not contact the drain selection layer isolation structure.

15. A method for forming a semiconductor structure, the method comprising: An alternating stack of insulating and spacer material layers is formed over a substrate, wherein the spacer material layers are formed as conductive layers or are subsequently replaced by conductive layers. A memory opening is formed through the alternating stacks; A memory opening filling structure is formed in the memory opening, wherein each memory opening filling structure includes a corresponding memory film and a corresponding vertical semiconductor channel laterally surrounded by the corresponding memory film, wherein the memory opening filling structures are arranged in rows that extend laterally along a first horizontal direction, and the rows are laterally spaced apart from each other along a second horizontal direction perpendicular to the first horizontal direction. A drain selection level isolation trench is formed through a subset of the conductive layer including the first conductive layer, such that the drain selection level isolation trench divides the first conductive layer into a pair of first drain selection level electrode strips, and includes a volume formed by removing portions of the first row memory opening fill structure and the second row memory opening fill structure. as well as A drain selection layer isolation structure is formed in the drain selection layer isolation trench, wherein the drain selection layer isolation structure laterally protrudes into each memory opening fill structure in the first row and the second row, and does not laterally protrude into the first drain selection layer electrode strip within the gap between adjacent pairs of memory opening fill structures laterally spaced along the first horizontal direction in the first row and the second row.

16. The method of claim 15, wherein the drain selection hierarchical isolation trench is formed by: An anisotropic etching process is performed, wherein the anisotropic etching process utilizes a cavity pattern having a pair of straight sidewalls extending laterally along the first horizontal direction to etch the material of the first conductive layer and the material of the insulating layer; and An isotropic etching process is performed, wherein the isotropic etching process selectively etches the material of the memory opening-filling structure onto the material of the first conductive layer.

17. The method of claim 16, wherein the isotropic etching process comprises: An etching step, wherein the etching step etches the portions of the memory film in the first row and the second row that are exposed to the cavity pattern; and Another etching step, which etches a portion of the vertical semiconductor channel into the volume of the cavity formed by the expansion of the cavity pattern.

18. The method of claim 16, wherein: The alternating stack includes a second conductive layer overlying the first conductive layer; and The method further includes: forming a drain selection layer isolation trench that extends vertically through the second conductive layer by performing an additional anisotropic etching process, forming a dielectric pad in the peripheral portion of the drain selection layer isolation trench during the process, and making the drain selection layer isolation trench extend vertically through the first conductive layer during the process by performing the anisotropic etching process.

19. The method of claim 15, wherein: Each memory aperture filling structure in the memory aperture filling structure further includes a corresponding dielectric core laterally surrounded by the corresponding vertical semiconductor channel; and The drain selection hierarchical isolation structure includes a horizontally concave and vertically straight surface segment, which is directly formed on the horizontally convex and vertically straight surface segment of the dielectric core in the first and second rows.

20. The method of claim 15, wherein the portion of the drain selection layer isolation structure located within the gap between the adjacent pairs of memory opening filling structures laterally spaced along the first horizontal direction includes a lateral recessed region having a horizontally concave surface segment, wherein a portion of the first drain selection layer electrode strip laterally protrudes into the lateral recessed region.

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