Capacitance switching mechanism-based Dick type detector and detection method

Abstract

The invention discloses a Dicke type detector based on a capacitance switching mechanism and a detection method, and belongs to the field of microwave measurement and radio frequency signal detection. A Dick type detector based on a capacitor switching mechanism comprises a main circuit and a control circuit. The main circuit comprises a signal switching and conditioning network, a sampling and holding network and a differential output network; the control circuit is mainly composed of a clock generator and a logic driving circuit. According to the invention, the dual-path parallel capacitance sampling and holding network is constructed, the antenna signal and the reference load signal are respectively and completely stored and held, the problem of signal amplitude attenuation caused by duty ratio modulation of a traditional detector is solved, the responsivity is multiplied, and the sensitivity of weak signal detection is improved. Strict time sequence interlocking logic is implemented under clock control, it is ensured that charge transfer is carried out only after the sampling voltage is stable and the sampling voltage is disconnected from the input end, transient interference in the switching process of the radio frequency switch can be physically isolated and restrained, and the accuracy and reliability of measurement are improved.

Description

Technical Field

[0001] This invention belongs to the field of microwave measurement and radio frequency signal detection technology, and relates to a Dicke detector circuit based on a capacitor switching mechanism and its detection method. Background Technology

[0002] With the rapid development of microwave remote sensing, radio astronomy, and passive imaging technologies, the requirements for sensitivity and stability in weak signal detection are increasing. In these applications, receivers not only face the challenge of extremely low signal-to-noise ratios, but also the inherent gain fluctuations of the system itself and the flicker noise (1 / f noise) of low-frequency electronic devices can severely affect the identification and detection of the target signal. To address this issue, the Dicke radiometer system has been widely adopted. Traditional Dicke detectors introduce a temperature-controlled reference load and use a radio frequency switch to periodically modulate the signal from the antenna under test and the reference load signal, shifting the DC or low-frequency signal to the switching frequency. After detection, synchronous demodulation, and integration, the difference between the antenna temperature and the load temperature is obtained. This method effectively eliminates receiver gain fluctuations and background thermal noise, avoiding the low-frequency noise region.

[0003] However, traditional Dick detector designs have inherent drawbacks that cannot be ignored. The first is the problem of halved responsivity. Because the RF switch typically switches between the antenna and load with a 50% duty cycle, the subsequent synchronous detection circuit effectively slices the signal, resulting in the final integrated output voltage amplitude being only half the difference between the antenna signal and the load signal (i.e., ...). This means the system is in a non-full signal reception state half the time, directly limiting the detector's sensitivity and responsivity. Secondly, there's the issue of switching transient interference. During the high-speed switching of the RF switch, parasitic capacitance and non-ideal switching characteristics can generate charge injection effects or voltage spikes. If these transient responses enter the subsequent high-sensitivity detection circuit without isolation, they will introduce additional noise floor and measurement errors, especially in high-frequency broadband applications where the impact of such transient interference is particularly severe.

[0004] While existing improvement schemes attempt to compensate for insufficient responsivity by increasing preamplifier gain or employing digital correlation techniques, these often come at the cost of increased system complexity and power consumption, and fail to fundamentally eliminate transient disturbances caused by switching. Therefore, a novel detector circuit topology and control method is urgently needed that can simultaneously achieve full-cycle signal utilization, responsivity multiplication, and effective suppression of switching transient interference. Summary of the Invention

[0005] One of the objectives of this invention is to provide a Dicke detector based on a capacitor switching mechanism. This detector circuit has a topological structure and, by constructing a dual-parallel capacitor sampling and holding network, can completely store and hold the antenna signal and the reference load signal respectively. This overcomes the signal amplitude attenuation problem caused by duty cycle modulation in traditional Dicke detectors, thereby doubling the responsivity and improving the sensitivity of weak signal detection.

[0006] Based on the Dicke detector based on the capacitor switching mechanism, the second objective of this invention is to provide a detection method for the Dicke detector based on the capacitor switching mechanism. By implementing strict timing interlock logic under clock control, it ensures that charge transfer only occurs after the sampling voltage has stabilized and is disconnected from the input terminal. This can physically isolate and suppress transient interference during the RF switch switching process, thereby improving the accuracy and reliability of the measurement.

[0007] The objective of this invention is achieved through the following technical solution: This invention discloses a Dicke-type detector based on a capacitor switching mechanism, comprising a main circuit and a control circuit. The main circuit includes a signal switching and conditioning network, a sample-and-hold network, and a differential output network. The signal switching and conditioning network includes an RF SPDT (Radio Frequency Switching Module), a low-noise amplifier (LNA), a detector, and a baseband SPDT (Baseband Switching Module). The sample-and-hold network includes a first intermediate sampling capacitor. Second intermediate sampling capacitor First holding capacitor Second holding capacitor The system consists of a first charge transfer switch (SPST1) and a second charge transfer switch (SPST2). The differential output network is mainly composed of a differential amplifier (AMP).

[0008] In the main circuit, the first input terminal of the RF SPDT is connected to the antenna port for receiving the RF signal under test. The second input terminal of the RF SPDT is connected to the reference load port for receiving the reference thermal noise signal. The common output terminal of the RF SPDT is connected to the input terminal of the low-noise amplifier (LNA). The output terminal of the LNA is connected to the input terminal of the detector, and the output terminal of the detector is connected to the common input terminal of the baseband switch BB SPDT. The first output terminal of the baseband switch BB SPDT is connected to the first intermediate sampling capacitor. One end of the baseband switch BB SPDT is connected to the baseband switch BBSPDT, and the first output terminal of the baseband switch BBSPDT is also connected to the input terminal of the first charge transfer switch SPST1. The second output terminal of the baseband switch BBSPDT is connected to the second intermediate sampling capacitor. One end is connected, and the second output terminal of the baseband switch BB SPDT is also connected to the input terminal of the second charge transfer switch SPST2. First intermediate sampling capacitor. Second intermediate sampling capacitor The other end is connected to the ground wire. The output terminal of the first charge transfer switch SPST1 is connected to the first holding capacitor. One end of the first charge transfer switch SPST1 is connected to the non-inverting input of the differential amplifier AMP; the output of the second charge transfer switch SPST2 is connected to the second holding capacitor. One end is connected, and the output of the second charge transfer switch SPST2 is also connected to the inverting input of the differential amplifier AMP. The first holding capacitor... Second holding capacitor The other end of each is connected to ground. The output of the differential amplifier AMP serves as the final signal output of the Dicke detector.

[0009] The control circuit mainly consists of a clock generator and a logic drive circuit. Under the control of the clock module, the control circuit generates two non-overlapping complementary control signals with a predetermined dead time. The drive circuit converts the received logic signals and provides drive voltages to the RF switch RF SPDT, baseband switch BB SPDT, first charge transfer switch SPST1, and second charge transfer switch SPST2 in the main circuit. This controls each switching device to operate in strict accordance with the preset timing logic, ensuring the isolation between the sampling and holding processes in the time domain.

[0010] Furthermore, the sample-and-hold network and the subsequent circuit are matched to ensure that the noise equivalent temperature difference (NETD) of the Dicke detector reaches 0.25K when driven by a 1MHz clock frequency and 0.824K when driven by a 100kHz clock frequency, thereby ensuring high-sensitivity detection performance.

[0011] Furthermore, the impedance matching characteristics of the RF SPDT keep the average input VSWR below 1.67 in the passband; the baseband SPDT and the single-pole single-throw switch are configured to be compatible with dual power supply voltages of 1V and 1.8V, support the dynamic range of output voltage from 0V to 1.8V, and the single-channel operating power consumption is controlled at 41.8mW.

[0012] Furthermore, the differential amplifier AMP and its cascaded circuit have a wide dynamic range response characteristic, configured to cover an equivalent input brightness temperature range of 27.5K to 2188.4K, and set the static output voltage at room temperature to 0.374V ~ 0.4V, so as to achieve linear amplification and readout of signals with a wide temperature difference.

[0013] Furthermore, the Dicke detector's passband gain ripple is controlled within ±1.03dB in the 88GHz to 98GHz operating frequency band; the linear slope of the Dicke detector's response characteristics is 0.81 mV / K, and the temperature stability of the linear slope is maintained within ±0.051mV / K.

[0014] This invention also discloses a detection method for a Dicke detector based on a capacitor switching mechanism, implemented on the basis of a Dicke detector based on a capacitor switching mechanism. The detection method for a Dicke detector based on a capacitor switching mechanism includes the following steps: Step 1: When the clock is high, the control circuit confirms the second intermediate sampling capacitor. Disconnected from the front-end signal source and the first holding capacitor After the path is disconnected, the RF SPDT is driven to switch to the antenna channel and the baseband SPDT is driven to turn on the first output terminal, so that the antenna signal voltage is applied to the first intermediate sampling capacitor. Above; the control circuit forces the first charge transfer switch SPST1 to remain open to block sampling transient noise, and drives the second charge transfer switch SPST2 to close, thus closing the second intermediate sampling capacitor. The steady-state charge stored in the upper capacitor is transferred to the second holding capacitor. .

[0015] When the clock is high, the control circuit executes the sampling enable logic: given that the second intermediate sampling capacitor is at this time... It must be in an isolated state disconnected from the front end, and the first holding capacitor... The signal path must also be disconnected to avoid interference. After confirming that the above conditions are met, the control circuit drives the RF SPDT to switch to the antenna channel and simultaneously drives the baseband switch BB SPDT to connect the first output terminal. At this time, the signal link is connected, and the antenna signal voltage output by the detector... Directly applied to the first intermediate sampling capacitor superior, The system enters a sampling mode of charge accumulation and voltage establishment, where the voltage across its terminals varies with fluctuations in the front-end signal. At this time, the first intermediate sampling capacitor... The instantaneous voltage on is expressed as: in, for Instantaneous voltage at both ends, This is the RF signal voltage input to the antenna port. During this process, the control circuit executes global interlock protection logic for the dual channels: on the one hand, although the first intermediate sampling capacitor... The antenna signal voltage is being established, but due to the first intermediate sampling capacitor... At this point, the signal is directly connected to the front-end signal source and is significantly affected by charge injection during RF switch switching and transient noise during LNA setup. The signal has not yet reached a steady state. Furthermore, to meet the logic requirement that the sampling process must not overlap with the charge transfer process, the control circuit forcibly drives the first charge transfer switch SPST1 to remain open. The first intermediate sampling capacitor is then disconnected via an interlocking action. With the first holding capacitor of the subsequent stage The interlocking logic establishes a pathway between the two stages, effectively blocking non-stationary fluctuations during the sampling setup process from reaching the output stage. Simultaneously, the interlocking logic confirms the connection between the second intermediate sampling capacitor and the output stage. It is already in a physically isolated state from the front-end signal source. Regarding the first intermediate sampling capacitor... Dynamic blocking and The static isolation confirmation constitutes complementary logic, clearly defining that only at the current moment... It possesses the steady-state conditions for data transfer.

[0016] When the clock is high, the control circuit simultaneously executes the output update interlock logic for the load channel: the second intermediate sampling capacitor is detected. At this point, the signal source has been physically disconnected and is in a steady state, and the clock signal is confirmed to be high, meeting the prerequisites for safe charge transfer. The control circuit then drives the second charge transfer switch SPST2 to close. The second intermediate sampling capacitor... The steady-state charge stored on the capacitor is rapidly transferred to the second holding capacitor via SPST2. , so that the second holding capacitor The voltage across the terminals is updated to a clean load signal voltage. After the charge transfer is complete, the second holding capacitor... The voltage status is updated as follows: in, To maintain capacitance steady-state voltage, intermediate sampling capacitor The voltage maintained at the moment of disconnection. Since this transfer process occurs after the preceding stage disconnects, it ensures the voltage maintained by the output stage capacitor. Connect only after the front-end voltage has fully stabilized to avoid noise interference from the front-end circuit.

[0017] Step 2: When the clock flips to a low level, the control circuit confirms the first intermediate sampling capacitor. Disconnected from the front-end signal source and second holding capacitor After the path is disconnected, the RF SPDT is driven to switch to the reference load channel and the baseband SPDT is driven to turn on the second output terminal, so that the load signal voltage is applied to the second intermediate sampling capacitor. Above; the control circuit forces the second charge transfer switch SPST2 to remain open to isolate sampling fluctuations, and drives the first charge transfer switch SPST1 to close, thus closing the first intermediate sampling capacitor. The steady-state charge stored on the capacitor is transferred to the first holding capacitor. .

[0018] When the clock flips to a low level, the control circuit executes the load sampling enable logic: confirming the first intermediate sampling capacitor. It is now disconnected from the front-end signal source, and the second holding capacitor is simultaneously checked. The input path is in a disconnected protection state. Under the premise that the above isolation conditions are met, the control circuit drives the RF switch RF SPDT to switch to the reference load channel, and simultaneously drives the baseband switch BB SPDT to connect the second output terminal. At this time, the signal link switches, and the load signal voltage output by the detector... Directly applied to the second intermediate sampling capacitor Above, the second intermediate sampling capacitor The system enters a sampling mode of charge accumulation and voltage establishment, where the voltage across its terminals changes as the load thermal noise signal builds up. At this time, the second intermediate sampling capacitor... The instantaneous voltage on is expressed as: in, for Instantaneous voltage at both ends, The noise signal voltage is referenced to the load port input. During this process, the control circuit executes global interlock protection logic for both channels: on the one hand, considering... Currently in the dynamic sampling phase directly connected to the detector, the voltage is not yet stable and contains switching noise. To ensure that the sampling and transfer conditions do not overlap, the control circuit forces the second charge transfer switch SPST2 to remain open. This is achieved through an interlocking action. With the second holding capacitor of the subsequent stage The path between them ensures the second holding capacitor The voltage on the reference signal will not be affected by the current load sampling setup process, maintaining the stability of the reference signal; on the other hand, the interlock logic simultaneously confirms that the first intermediate sampling capacitor is at this time. It is now in a state of physical isolation from the front-end signal source. Dynamic blocking and The static isolation confirmation complements each other again, clearly defining that only at the current moment... It possesses the steady-state conditions for data transfer, providing a logically secure prerequisite for subsequent lossless signal transfer.

[0019] When the clock flips to a low level, the control circuit simultaneously executes the output update interlock logic for the antenna channel: utilizing the first intermediate sampling capacitor at this time. Having been disconnected from the front-end signal source and with its potential stabilized at the antenna signal amplitude, confirming that the "stabilize first, then transfer" timing requirement in full-cycle signal processing is met, the control circuit drives the first charge transfer switch SPST1 to close. At this time, the first intermediate sampling capacitor... The steady-state charge stored on the capacitor is transferred to the first holding capacitor via SPST1. , so that the first holding capacitor The voltage at both ends is updated to the antenna signal voltage. After the charge transfer is complete, the first holding capacitor... The voltage status is updated as follows: in, First holding capacitor steady-state voltage, The first intermediate sampling capacitor The voltage held at the moment of disconnection. This interlock logic ensures the voltage held by the first holding capacitor in the output stage. Only Data updates are only performed after the signal has completely stabilized away from the input terminal, thus achieving high-precision signal retention.

[0020] Step 3: First holding capacitor Second holding capacitor The differential amplifier in the main circuit continuously reads the steady-state voltages of the antenna signal and the load signal, respectively. and The potential difference at both ends directly outputs the difference between the antenna and the load signal, eliminating duty cycle modulation attenuation and doubling the responsivity, thereby improving the detection responsivity of the Dicke detector.

[0021] Through the alternating cycle of steps one and two described above, the Dicke detector strictly adheres to timing interlocks within each complete clock cycle: sampling occurs only during non-transfer periods, and transfer occurs only during the steady-state period after the signal source is disconnected. Under this mechanism, the first holding capacitor... Second holding capacitor All are in a continuously effective voltage holding state. Always maintain the latest antenna signal voltage. Always maintain the latest load signal voltage. The differential amplifier in the main circuit continuously reads... and The potential difference between the two ends, its output voltage Represented as: in, This represents the gain of the differential amplifier. The formula shows that the output signal can completely reproduce the difference between the antenna signal and the load signal, achieving full-cycle signal utilization. Since the output signal originates from the DC steady-state voltage of the holding capacitor after being purified by interlocking logic, rather than the clock-modulated pulse signal used in traditional techniques, there is no need for duty cycle averaging. The amplitude of the output signal remains at the full amplitude of the signal difference throughout the entire clock cycle, thereby doubling the responsivity of the Dicke detector.

[0022] Beneficial effects: 1. This invention discloses a Dicke detector and detection method based on a capacitor switching mechanism. Through a dual-channel parallel sampling and cross-hold circuit architecture, coupled with continuous reading by a differential amplifier, it completely changes the traditional Dicke detector's "half-time sampling, half-time idle" operating mode. This invention can directly output the complete difference between the antenna voltage and the load voltage. At the same system gain, the voltage responsivity of the detector is doubled, significantly enhancing the Dicke detector's ability to capture weak signals.

[0023] 2. The Dicke-type detector and detection method based on a capacitor switching mechanism disclosed in this invention deeply integrates the "stabilize first, then transfer" interlocking logic into the timing control of the circuit. By controlling the inter-stage charge transfer switch to close only after the intermediate sampling capacitor is physically disconnected from the input terminal, the temporal misalignment and spatial isolation between signal acquisition and signal output are achieved. The capacitor switching mechanism effectively blocks the propagation of charge injection spikes, switch jitter, and transient noise generated by the RF switch and baseband switch during high-speed switching to the subsequent holding capacitor, significantly reducing the noise floor of the output signal and improving the purity and accuracy of the detection results.

[0024] 3. The Dicke detector and detection method based on a capacitor switching mechanism disclosed in this invention retain the core advantage of the Dicke system—shifting the signal spectrum to higher frequencies to suppress 1 / f flicker noise—in its circuit structure. Simultaneously, thanks to the extremely small (nanosecond-level) time constant of capacitor charging and discharging in microwave circuits, combined with the timing interlock control of this invention, the detector can support extremely high clock switching frequencies. This invention not only facilitates further movement away from low-frequency noise regions but also has wide applicability in applications requiring high time resolution, such as high-speed broadband microwave radiometers, terahertz imaging, and radio astronomy observations. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the Dicke-type detector circuit structure based on the capacitor switching mechanism of the present invention.

[0026] Figure 2 This is the complete timing interlock logic diagram of the Dicke-type detector based on the capacitor switching mechanism of the present invention. Detailed Implementation

[0027] To better illustrate the purpose and advantages of the present invention, the invention will be further described below in conjunction with the accompanying drawings and examples.

[0028] Example 1: like Figure 1 As shown, this embodiment discloses a Dicke-type detector based on a capacitor switching mechanism, including a main circuit and a control circuit. The main circuit includes a signal switching and conditioning network, a sample-and-hold network, and a differential output network. The signal switching and conditioning network includes an RF SPDT (Radio Frequency Switching DT), a low-noise amplifier (LNA), a detector, and a baseband switch (BB SPDT). The sample-and-hold network includes a first intermediate sampling capacitor. Second intermediate sampling capacitor First holding capacitor Second holding capacitor The system consists of a first charge transfer switch (SPST1) and a second charge transfer switch (SPST2). The differential output network is mainly composed of a differential amplifier (AMP).

[0029] In the main circuit, the first input terminal of the RF SPDT is connected to the antenna port for receiving the RF signal under test. The second input terminal of the RF SPDT is connected to the reference load port for receiving the reference thermal noise signal. The common output terminal of the RF SPDT is connected to the input terminal of the low-noise amplifier (LNA). Within the operating frequency band of 88GHz to 98GHz, the impedance matching characteristics of the RF SPDT maintain the average input VSWR below 1.67 in the passband, and control the gain fluctuation within ±1.03dB. The output terminal of the LNA is connected to the input terminal of the detector, and the output terminal of the detector is connected to the common input terminal of the baseband switch BB SPDT. The first output terminal of the baseband switch BB SPDT is connected to the first intermediate sampling capacitor. One end of the baseband switch BB SPDT is connected to the first output terminal, which is also connected to the input terminal of the first charge transfer switch SPST1. The BB SPDT, along with the first charge transfer switch SPST1 and the second charge transfer switch SPST2, is compatible with dual power supplies of 1V and 1.8V, supporting a dynamic range of 0V to 1.8V. The second output terminal of the baseband switch BB SPDT is connected to the second intermediate sampling capacitor. One end is connected, and the second output terminal of the baseband switch BB SPDT is also connected to the input terminal of the second charge transfer switch SPST2. First intermediate sampling capacitor. Second intermediate sampling capacitor The other end is connected to the ground wire. The output terminal of the first charge transfer switch SPST1 is connected to the first holding capacitor. One end of the first charge transfer switch SPST1 is connected to the non-inverting input of the differential amplifier AMP; the output of the second charge transfer switch SPST2 is connected to the second holding capacitor. One end is connected, and the output of the second charge transfer switch SPST2 is also connected to the inverting input of the differential amplifier AMP. The first holding capacitor... Second holding capacitor The other end of each circuit is connected to ground. Through this dual-path parallel sample-and-hold mechanism, this embodiment achieves a noise equivalent temperature difference (NETD) of 0.25K under a 1MHz clock drive and 0.824K under a 100kHz clock drive, verifying the feasibility of the high-sensitivity objective. The output of the differential amplifier (AMP) serves as the final signal output of the Dicke-type detector. This embodiment can cover an equivalent input brightness temperature range of 27.5K to 2188.4K, and the static output voltage at room temperature is set to 0.374V~0.4V. The linear slope of the detector response characteristic is 0.81 mV / K, and the temperature stability of the linear slope is maintained within ±0.051 mV / K, with single-channel power consumption controlled at 41.8mW.

[0030] The control circuit mainly consists of a clock generator and a logic driver circuit. Figure 2 The timing logic control relationship shown is such that, under the control of the clock module, the control circuit generates two non-overlapping complementary control signals with a predetermined dead time. The drive circuit converts the received logic signals to provide drive voltages to the RF switch RF SPDT, baseband switch BB SPDT, first charge transfer switch SPST1, and second charge transfer switch SPST2 in the main circuit. This controls each switching device to operate in strict accordance with the preset timing logic, ensuring that the sampling process and the holding process are isolated in the time domain.

[0031] When the control signal is high, such as Figure 2 As shown in the high-level timing diagram, the driver circuit converts the logic signal to a higher level, driving the RF SPDT to switch to the antenna channel, and simultaneously controlling the baseband switch BB SPDT to connect the first intermediate sampling capacitor. This allows signals from the Dicke detector operating in the 88GHz to 98GHz frequency band to enter sampling mode. Figure 2 The interlock dead time setting between SPST1 and BB SPDT ensures that the first charge transfer switch SPST1 is strictly open during the sampling voltage establishment period, thereby effectively isolating transient noise at a switching frequency of 1MHz.

[0032] When the control signal is low, such as Figure 2 As shown in the low-level timing diagram, the driver circuit converts the logic signal to a higher level and then drives the RF SPDT to switch to the reference load channel. Simultaneously, it controls the baseband switch BB SPDT to connect the second intermediate sampling capacitor. This causes the system reference thermal noise signal to enter sampling mode. Corresponding to... Figure 2The interlock dead time setting between SPST2 and BB SPDT ensures that the second charge transfer switch SPST2 is strictly open during the sampling voltage establishment period, thereby effectively isolating transient noise at a switching frequency of 1MHz.

[0033] This embodiment also discloses a detection method for a Dicke detector based on a capacitor switching mechanism, implemented on the basis of a Dicke detector based on a capacitor switching mechanism. The specific implementation steps of the detection method for a Dicke detector based on a capacitor switching mechanism are as follows: Step 1: When the clock is high, the control circuit confirms the second intermediate sampling capacitor. Disconnected from the front-end signal source and the first holding capacitor After the path is disconnected, the RF SPDT is driven to switch to the antenna channel and the baseband SPDT is driven to turn on the first output terminal, so that the antenna signal voltage is applied to the first intermediate sampling capacitor. Above; the control circuit forces the first charge transfer switch SPST1 to remain open to block sampling transient noise, and drives the second charge transfer switch SPST2 to close, thus closing the second intermediate sampling capacitor. The steady-state charge stored in the upper part is transferred to the second holding capacitor. .

[0034] When the clock is high, the control circuit executes the sampling enable logic: given that the second intermediate sampling capacitor is at this time... It must be in an isolated state disconnected from the front end, and the first holding capacitor... The signal path must also be disconnected to avoid interference. After confirming that the above conditions are met, the control circuit drives the RF SPDT to switch to the antenna channel and simultaneously drives the baseband switch BB SPDT to connect the first output terminal. At this time, the signal link is connected, and the antenna signal voltage output by the detector... Directly applied to the first intermediate sampling capacitor superior, The system enters a sampling mode of charge accumulation and voltage establishment, where the voltage across its terminals changes with fluctuations in the front-end signal. At this time, the first intermediate sampling capacitor... The instantaneous voltage on is expressed as: in, for Instantaneous voltage at both ends, This is the RF signal voltage input to the antenna port. During this process, the control circuit executes global interlock protection logic for the dual channels: on the one hand, although the first intermediate sampling capacitor... The antenna signal voltage is being established, but due to the first intermediate sampling capacitor... At this point, the signal is directly connected to the front-end signal source and is significantly affected by charge injection during RF switch switching and transient noise during LNA setup. The signal has not yet reached a steady state. Furthermore, to meet the logic requirement that the sampling process must not overlap with the charge transfer process, the control circuit forcibly drives the first charge transfer switch SPST1 to remain open. The first intermediate sampling capacitor is then disconnected via an interlocking action. With the first holding capacitor of the subsequent stage The interlocking logic establishes a pathway between the two stages, effectively blocking non-stationary fluctuations during the sampling setup process from reaching the output stage. Simultaneously, the interlocking logic confirms the connection between the second intermediate sampling capacitor and the output stage. It is already in a physically isolated state from the front-end signal source. Regarding the first intermediate sampling capacitor... Dynamic blocking and The static isolation confirmation constitutes complementary logic, clearly defining that only at the current moment... It possesses the steady-state conditions for data transfer.

[0035] When the clock is high, the control circuit simultaneously executes the output update interlock logic for the load channel: the second intermediate sampling capacitor is detected. At this point, the signal source has been physically disconnected and is in a steady state, and the clock signal is confirmed to be high, meeting the prerequisites for safe charge transfer. The control circuit then drives the second charge transfer switch SPST2 to close. The second intermediate sampling capacitor... The steady-state charge stored on the capacitor is rapidly transferred to the second holding capacitor via SPST2. , so that the second holding capacitor The voltage across the terminals is updated to a clean load signal voltage. After the charge transfer is complete, the second holding capacitor... The voltage status is updated as follows: in, To maintain capacitance steady-state voltage, intermediate sampling capacitor The voltage maintained at the moment of disconnection. Since this transfer process occurs after the preceding stage disconnects, it ensures the voltage maintained by the output stage capacitor. Connect only after the front-end voltage has fully stabilized to avoid noise interference from the front-end circuit.

[0036] Step 2: When the system clock flips to a low level, the control circuit confirms the first intermediate sampling capacitor. Disconnected from the front-end signal source and second holding capacitor After the path is disconnected, the RF SPDT is driven to switch to the reference load channel and the baseband SPDT is driven to turn on the second output terminal, so that the load signal voltage is applied to the second intermediate sampling capacitor. Above; the control circuit forces the second charge transfer switch SPST2 to remain open to isolate sampling fluctuations, and drives the first charge transfer switch SPST1 to close, thus closing the first intermediate sampling capacitor. The steady-state charge stored on the capacitor is transferred to the first holding capacitor. .

[0037] When the clock flips to a low level, the control circuit executes the load sampling enable logic: confirming the first intermediate sampling capacitor. It is now disconnected from the front-end signal source, and the second holding capacitor is being checked simultaneously. The input path is in a disconnected protection state. Under the premise that the above isolation conditions are met, the control circuit drives the RF switch RF SPDT to switch to the reference load channel, and simultaneously drives the baseband switch BB SPDT to connect the second output terminal. At this time, the signal link switches, and the load signal voltage output by the detector... Directly applied to the second intermediate sampling capacitor Above, the second intermediate sampling capacitor The system enters a sampling mode of charge accumulation and voltage establishment, where the voltage across its terminals changes as the load thermal noise signal builds up. At this time, the second intermediate sampling capacitor... The instantaneous voltage on is expressed as: in, for Instantaneous voltage at both ends, The noise signal voltage is referenced to the load port input. During this process, the control circuit executes global interlock protection logic for both channels: on the one hand, considering... Currently in the dynamic sampling phase directly connected to the detector, the voltage is not yet stable and contains switching noise. To ensure that the sampling and transfer conditions do not overlap, the control circuit forces the second charge transfer switch SPST2 to remain open. This is achieved through an interlocking action. With the second holding capacitor of the subsequent stage The path between them ensures the second holding capacitor The voltage on the reference signal will not be affected by the current load sampling setup process, maintaining the stability of the reference signal; on the other hand, the interlock logic simultaneously confirms that the first intermediate sampling capacitor is at this time. It is now in a state of physical isolation from the front-end signal source. Dynamic blocking and The static isolation confirmation complements each other again, clearly defining that only at the current moment... It possesses the steady-state conditions for data transfer, providing a logically secure prerequisite for subsequent lossless signal transfer.

[0038] When the clock flips to a low level, the control circuit simultaneously executes the output update interlock logic for the antenna channel: utilizing the first intermediate sampling capacitor at this time. Having been disconnected from the front-end signal source and with its potential stabilized at the antenna signal amplitude, confirming that the "stabilize first, then transfer" timing requirement in full-cycle signal processing is met, the control circuit drives the first charge transfer switch SPST1 to close. At this time, the first intermediate sampling capacitor... The steady-state charge stored on the capacitor is transferred to the first holding capacitor via SPST1. , so that the first holding capacitor The voltage at both ends is updated to the antenna signal voltage. After the charge transfer is complete, the first holding capacitor... The voltage status is updated as follows: in, First holding capacitor steady-state voltage, The first intermediate sampling capacitor The voltage held at the moment of disconnection. This interlock logic ensures the voltage held by the first holding capacitor in the output stage. Only Data updates are only performed after the signal has completely stabilized away from the input terminal, thus achieving high-precision signal holding.

[0039] Step 3: First holding capacitor Second holding capacitor The differential amplifier in the main circuit continuously reads the steady-state voltages of the antenna signal and the load signal, respectively. and The potential difference at both ends directly outputs the difference between the antenna and the load signal, eliminating duty cycle modulation attenuation and doubling the responsivity, thereby improving the detection responsivity of the Dicke detector.

[0040] Through the alternating cycle of steps one and two described above, the Dicke detector strictly adheres to timing interlocks within each complete clock cycle: sampling occurs only during non-transfer periods, and transfer occurs only during the steady-state period after the signal source is disconnected. Under this mechanism, the first holding capacitor... Second holding capacitor All are in a continuously effective voltage holding state. Always maintain the latest antenna signal voltage. Always maintain the latest load signal voltage. The differential amplifier in the main circuit continuously reads... and The potential difference between the two ends, its output voltage Represented as: in, This represents the gain of the differential amplifier. The formula shows that the output signal can completely reproduce the difference between the antenna signal and the load signal, achieving full-cycle signal utilization. Since the output signal originates from the DC steady-state voltage of the holding capacitor after being purified by interlocking logic, rather than the clock-modulated pulse signal used in traditional techniques, there is no need for duty cycle averaging. The amplitude of the output signal remains at the full amplitude of the signal difference throughout the entire clock cycle, thereby doubling the responsivity of the Dicke detector.

[0041] The above detailed description further illustrates the purpose, technical solution, and beneficial effects of the invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A Dicke-type detector based on a capacitor switching mechanism, characterized in that: It includes a main circuit and a control circuit; the main circuit includes a signal switching and conditioning network, a sample-and-hold network, and a differential output network; the signal switching and conditioning network includes an RF SPDT, a low-noise amplifier (LNA), a detector, and a baseband switch (BB SPDT); the sample-and-hold network includes a first intermediate sampling capacitor. Second intermediate sampling capacitor First holding capacitor Second holding capacitor The system consists of a first charge transfer switch SPST1, a second charge transfer switch SPST2, and a differential output network mainly composed of a differential amplifier AMP. In the main circuit, the first input terminal of the RF SPDT is connected to the antenna port for receiving the RF signal under test; the second input terminal of the RF SPDT is connected to the reference load port for receiving the reference thermal noise signal; the common output terminal of the RF SPDT is connected to the input terminal of the low-noise amplifier (LNA); the output terminal of the LNA is connected to the input terminal of the detector; the output terminal of the detector is connected to the common input terminal of the baseband switch BB SPDT; and the first output terminal of the baseband switch BB SPDT is connected to the first intermediate sampling capacitor. One end of the baseband switch BB SPDT is connected to the first output terminal, which is also connected to the input terminal of the first charge transfer switch SPST1; the second output terminal of the baseband switch BB SPDT is connected to the second intermediate sampling capacitor. One end is connected, and the second output terminal of the baseband switch BB SPDT is also connected to the input terminal of the second charge transfer switch SPST2; the first intermediate sampling capacitor Second intermediate sampling capacitor The other end is connected to the ground wire; the output terminal of the first charge transfer switch SPST1 is connected to the first holding capacitor. One end of the first charge transfer switch SPST1 is connected to the non-inverting input of the differential amplifier AMP; the output of the second charge transfer switch SPST2 is connected to the second holding capacitor. One end is connected, and the output of the second charge transfer switch SPST2 is also connected to the inverting input of the differential amplifier AMP; the first holding capacitor Second holding capacitor The other end of each is connected to the ground wire; the output of the differential amplifier AMP serves as the final signal output of the Dicke detector; The control circuit mainly consists of a clock generator and a logic drive circuit.

2. The Dicke detector based on a capacitor switching mechanism as described in claim 1, characterized in that: Under the control of the clock module, the control circuit generates two non-overlapping complementary control signals with a predetermined dead time. The drive circuit converts the received logic signals to provide drive voltages to the RF switch RF SPDT, baseband switch BB SPDT, first charge transfer switch SPST1, and second charge transfer switch SPST2 in the main circuit. This controls each switching device to operate in strict accordance with the preset timing logic, ensuring that the sampling process and the holding process are isolated in the time domain.

3. The Dicke detector based on a capacitor switching mechanism as described in claim 2, characterized in that: The sample-and-hold network and subsequent circuitry are matched to achieve a noise equivalent temperature difference (NETD) of 0.25K for the Dicke detector driven at a 1MHz clock frequency and 0.824K for the detector driven at a 100kHz clock frequency.

4. The Dicke detector based on a capacitor switching mechanism as described in claim 2, characterized in that: The impedance matching characteristics of the RF SPDT switch keep the average input VSWR below 1.67 in the passband; the baseband switch BBSPDT and single-pole single-throw switch are configured to be compatible with dual power supply voltages of 1V and 1.8V, support the dynamic range of output voltage from 0V to 1.8V, and the single-channel operating power consumption is controlled at 41.8mW.

5. The Dicke detector based on a capacitor switching mechanism as described in claim 2, characterized in that: The differential amplifier AMP and its cascaded circuit are configured to cover an equivalent input brightness temperature range of 27.5K to 2188.4K, and the static output voltage under normal temperature conditions is set to 0.374V ~ 0.4V to achieve linear amplification and readout of signals with a wide temperature difference.

6. The Dicke detector based on a capacitor switching mechanism as described in claim 2, characterized in that: The Dicke detector operates within the 88 GHz to 98 GHz frequency band, with passband gain ripple controlled within ±1.03 dB. The linear slope of the Dicke detector response is 0.81 mV / K, and the temperature stability of the linear slope is maintained within ±0.051 mV / K.

7. A detection method for a Dicke detector based on a capacitor switching mechanism, implemented using a Dicke detector based on a capacitor switching mechanism as described in claim 1 or 2, characterized in that: Includes the following steps: Step 1: When the clock is high, the control circuit confirms the second intermediate sampling capacitor. Disconnected from the front-end signal source and the first holding capacitor After the path is disconnected, the RF SPDT is driven to switch to the antenna channel and the baseband SPDT is driven to turn on the first output terminal, so that the antenna signal voltage is applied to the first intermediate sampling capacitor. Above; the control circuit forces the first charge transfer switch SPST1 to remain open to block sampling transient noise, and drives the second charge transfer switch SPST2 to close, thus closing the second intermediate sampling capacitor. The steady-state charge stored in the upper part is transferred to the second holding capacitor. ; Step 2: When the clock flips to a low level, the control circuit confirms the first intermediate sampling capacitor. Disconnected from the front-end signal source and second holding capacitor After the path is disconnected, the RF SPDT is driven to switch to the reference load channel and the baseband SPDT is driven to turn on the second output terminal, so that the load signal voltage is applied to the second intermediate sampling capacitor. Above; the control circuit forces the second charge transfer switch SPST2 to remain open to isolate sampling fluctuations, and drives the first charge transfer switch SPST1 to close, thus closing the first intermediate sampling capacitor. The steady-state charge stored on the capacitor is transferred to the first holding capacitor. ; Step 3: First holding capacitor Second holding capacitor The differential amplifier in the main circuit continuously reads the steady-state voltages of the antenna signal and the load signal, respectively. and The potential difference at both ends directly outputs the difference between the antenna and the load signal, eliminating duty cycle modulation attenuation and doubling the responsivity, thereby improving the detection responsivity of the Dicke detector.

8. The detection method of the Dicke detector based on the capacitor switching mechanism as described in claim 7, characterized in that: The implementation method for step one is as follows: When the clock is high, the control circuit executes the sampling enable logic: given that the second intermediate sampling capacitor is at this time... It must be in an isolated state disconnected from the front end, and the first holding capacitor... The signal path must also be disconnected to avoid interference. After confirming that the above conditions are met, the control circuit drives the RF SPDT to switch to the antenna channel and simultaneously drives the baseband switch BB SPDT to connect the first output terminal. At this time, the signal link is connected, and the antenna signal voltage output by the detector is... Directly applied to the first intermediate sampling capacitor superior, The system enters a sampling mode of charge accumulation and voltage establishment, where the voltage across its terminals changes with fluctuations in the front-end signal; at this time, the first intermediate sampling capacitor... The instantaneous voltage on is expressed as: in, for Instantaneous voltage at both ends, The RF signal voltage input to the antenna port; during this process, the control circuit executes global interlock protection logic for the dual channels: the first intermediate sampling capacitor. The antenna signal voltage is being established, but due to the first intermediate sampling capacitor... At this point, the circuit is directly connected to the front-end signal source. To meet the logic requirement that the sampling process must not overlap with the charge transfer process, the control circuit forcibly drives the first charge transfer switch SPST1 to remain open; and disconnects the first intermediate sampling capacitor through an interlocking action. With the first holding capacitor of the subsequent stage The interlock logic establishes a pathway between the two stages, thus preventing non-stationary fluctuations during the sampling setup process from reaching the output stage; the interlock logic simultaneously confirms the connection of the second intermediate sampling capacitor at this time. It is already in a physically isolated state from the front-end signal source; regarding the first intermediate sampling capacitor Dynamic blocking and The static isolation confirmation constitutes complementary logic, clearly defining that only at the current moment... It possesses the steady-state conditions for data transfer; When the clock is high, the control circuit simultaneously executes the output update interlock logic for the load channel: the second intermediate sampling capacitor is detected. At this point, the signal source has been physically disconnected and is in a steady state, and the clock signal is confirmed to be high, meeting the prerequisites for safe charge transfer. The control circuit then drives the second charge transfer switch SPST2 to close; the second intermediate sampling capacitor... The steady-state charge stored on the capacitor is rapidly transferred to the second holding capacitor via SPST2. , so that the second holding capacitor The voltage across the terminals is updated to a clean load signal voltage. After the charge transfer is completed, the second holding capacitor... The voltage status is updated as follows: in, To maintain capacitance steady-state voltage, intermediate sampling capacitor The voltage maintained at the moment of disconnection; since this transfer process occurs after the previous stage disconnects, it ensures the output stage capacitor... Connect only after the front-end voltage has fully stabilized to avoid noise interference from the front-end circuit.

9. The detection method of the Dicke detector based on the capacitor switching mechanism as described in claim 8, characterized in that: The second step is implemented as follows: When the clock flips to a low level, the control circuit executes the load sampling enable logic: confirming the first intermediate sampling capacitor. It is now disconnected from the front-end signal source, and the second holding capacitor is simultaneously checked. The input path is in a disconnected protection state; provided the above isolation conditions are met, the control circuit drives the RF SPDT to switch to the reference load channel, and simultaneously drives the baseband switch BB SPDT to connect the second output terminal; at this time, the signal link switches, and the load signal voltage output by the detector... Directly applied to the second intermediate sampling capacitor Above, the second intermediate sampling capacitor The sampling mode, which involves charge accumulation and voltage establishment, is entered, and the voltage across its terminals changes as the load thermal noise signal is established; at this time, the second intermediate sampling capacitor... The instantaneous voltage on is expressed as: in, for Instantaneous voltage at both ends, The noise signal voltage is referenced to the load port input; during this process, the control circuit executes global interlock protection logic for both channels: considering... Currently in the dynamic sampling phase directly connected to the detector, the voltage is not yet stable and contains switching noise. To ensure that the sampling and transfer conditions do not overlap, the control circuit forces the second charge transfer switch SPST2 to remain open; and cuts off the circuit through an interlocking action. With the second holding capacitor of the subsequent stage The path between them ensures the second holding capacitor The voltage on the reference signal will not be affected by the current load sampling setup process, maintaining the stability of the reference signal; the interlock logic simultaneously confirms the first intermediate sampling capacitor at this time. It is already in a physically isolated state from the front-end signal source; Dynamic blocking and The static isolation confirmation complements each other again, clearly defining that only at the current moment... It possesses the steady-state conditions for data transfer; When the clock flips to a low level, the control circuit simultaneously executes the output update interlock logic for the antenna channel: utilizing the first intermediate sampling capacitor at this time. Having been disconnected from the front-end signal source and with its potential stabilized at the antenna signal amplitude, confirming that the "stabilize first, then transfer" timing requirement in full-cycle signal processing is met, the control circuit drives the first charge transfer switch SPST1 to close; at this time, the first intermediate sampling capacitor... The steady-state charge stored on the capacitor is transferred to the first holding capacitor via SPST1. , so that the first holding capacitor The voltage at both ends is updated to the antenna signal voltage. After the charge transfer is completed, the first holding capacitor The voltage status is updated as follows: in, First holding capacitor steady-state voltage, The first intermediate sampling capacitor The voltage held at the moment of disconnection; this interlock logic ensures the voltage held by the first holding capacitor in the output stage. Only Data updates are only performed after the signal has completely stabilized away from the input terminal, thus achieving high-precision signal retention.

10. The detection method of the Dicke detector based on the capacitor switching mechanism as described in claim 9, characterized in that: The method for implementing step three is as follows: Through the alternating cycle of steps one and two described above, the Dicke detector strictly adheres to timing interlocks within each complete clock cycle: sampling occurs only during non-transfer periods, and transfer occurs only during the steady-state period after the signal source is disconnected; under this mechanism, the first holding capacitor... Second holding capacitor All are in a continuously effective voltage holding state; among them Always maintain the latest antenna signal voltage. Always maintain the latest load signal voltage; the differential amplifier in the main circuit continuously reads... and The potential difference between the two ends, its output voltage Represented as: in, The gain of the differential amplifier is used to fully reproduce the difference between the antenna signal and the load signal, achieving full-cycle signal utilization. Since the output signal originates from the DC steady-state voltage of the holding capacitor after being purified by interlocking logic, there is no need for duty cycle averaging. The amplitude of the output signal remains at the full amplitude of the signal difference throughout the entire clock cycle, thereby doubling the responsivity of the Dicke detector.

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