Intelligent switching method and system based on chip low-power-consumption mode

Abstract

The invention relates to the technical field of integrated circuit low-power-consumption management, in particular to an intelligent switching method and system based on a chip low-power-consumption mode, and the method comprises the steps: obtaining an original electric signal and an environment signal during the operation of a chip; stripping a kernel steady state component and a peripheral transient state component from the electric signal, and constructing a composite electric signal spectrum; performing characteristic decomposition on the environment signal, and extracting a trend component and a disturbance component; fusing and aligning the electric signal atlas and the environment components in time to generate a chip-environment unified state model; the model is analyzed, and a key state node indicating power consumption mode transition is identified; and generating a pre-execution control sequence of voltage and frequency regulation based on the node attributes and relationships. By constructing the internal and external state coupling model, more accurate prediction and active control of the switching opportunity of the low-power-consumption mode of the chip are realized.

Description

Technical Field

[0001] This invention relates to the field of low-power management technology for integrated circuits, and in particular to a method and system for intelligent switching of low-power modes based on chips. Background Technology

[0002] Existing low-power management technologies for chips primarily rely on monitoring single aggregated signals such as overall power consumption, current, or temperature, and making mode-switching decisions based on preset fixed thresholds. This approach overlays the electrical activity characteristics of different functional units within the chip, making it impossible to distinguish between steady-state current generated by the computing core and transient current caused by peripheral circuit activity. Due to the lack of fine-grained identification of power consumption sources and behavioral patterns, the system can only provide a delayed and coarse response to changes in overall power consumption, making it difficult to achieve precise power consumption control.

[0003] Existing solutions typically treat environmental factors as parallel decision conditions independent of the chip's internal state or as simple linear correction factors. This approach severs the intrinsic connection between dynamic environmental changes and the chip's internal electrical activity, failing to consider the differentiated impacts of gradual changes in environmental parameters and rapid disturbances on different circuit modules. Therefore, current technologies cannot capture and utilize the complex spatiotemporal coupling between the chip's operating state and the environmental state, resulting in insufficient predictability of power mode switching timing and often missing the optimal energy efficiency point. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a method and system for intelligent switching of low-power modes based on chips.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a method for intelligent switching of low-power modes based on chips, comprising:

[0006] Acquire the raw electrical signals and raw environmental signals during chip operation;

[0007] The steady-state electrical signal component generated by the operation of the chip core and the transient electrical signal component generated by the activity of the peripheral circuit are extracted from the original electrical signal, and a composite electrical signal spectrum is constructed based on the dynamic range of the steady-state electrical signal component and the transient electrical signal component respectively.

[0008] The original environmental signal is subjected to signal feature decomposition to extract the trend component that changes slowly over time and the disturbance component that fluctuates rapidly over time.

[0009] The composite electrical signal spectrum is fused and aligned with the trend component and the disturbance component in the time dimension to generate a unified state model that reflects the coupling relationship between the chip's operating state and the environment state.

[0010] The unified state model is analyzed to identify key state nodes in the model that correspond to the chip about to enter the high power consumption region or about to leave the low power consumption region.

[0011] Based on the attributes of the key state nodes and the relationships between the nodes, a set of pre-execution control sequences containing voltage regulation commands and frequency regulation commands is generated.

[0012] As a further aspect of the present invention, the method further includes:

[0013] The pre-execution control sequence is sent to the chip's power management interface, and the actual power consumption trajectory fed back by the chip is collected synchronously during the execution process;

[0014] The actual power consumption trajectory is compared with the expected power consumption trajectory in the pre-execution control sequence to calculate the execution error of power consumption adjustment;

[0015] Based on the execution error, the parameters of subsequent instructions in the pre-execution control sequence are fine-tuned to generate a corrected control sequence;

[0016] The corrected control sequence, the actual power consumption trajectory, and the execution error are encapsulated into a status report and sent to an external collaborative management node via a short-range wireless communication link.

[0017] As a further aspect of the present invention, the step of extracting the steady-state electrical signal component generated by the operation of the chip core and the transient electrical signal component generated by the activity of the peripheral circuit from the original electrical signal, and constructing a composite electrical signal spectrum based on the dynamic range of the steady-state electrical signal component and the transient electrical signal component, specifically involves:

[0018] The original electrical signal is segmented to obtain time-continuous signal segments;

[0019] For each of the signal segments, the low-frequency energy concentration band located near the fundamental frequency and the discrete energy spectral lines distributed in the high-frequency region are separated;

[0020] The low-frequency energy concentration band is reconstructed into a steady-state electrical signal component characterizing the continuous computing load of the chip core;

[0021] The time-domain signals corresponding to the discrete energy spectral lines are superimposed to reconstruct transient electrical signal components characterizing the sudden access operation of the peripheral circuit;

[0022] The characteristic parameters of the steady-state electrical signal component and the transient electrical signal component within a preset observation window are extracted respectively.

[0023] The elements in the steady-state electrical signal component and the transient electrical signal component are mapped to feature points on a two-dimensional plane;

[0024] Connect the steady-state feature points and transient feature points at the same timestamp to form multiple feature line segments;

[0025] The feature line segments are arranged in chronological order, and the ratio of steady-state to transient energy is marked to form the composite electrical signal spectrum.

[0026] As a further aspect of the present invention, the step of performing signal feature decomposition on the original environmental signal to extract the trend component that changes slowly over time and the disturbance component that fluctuates rapidly over time specifically involves:

[0027] Receive raw environmental signals from multiple physical location sensors, the raw environmental signals including temperature signals and air pressure signals;

[0028] Temperature and air pressure signals from sensors at the same physical location are time-stamped and their amplitudes are normalized to obtain a synchronized environmental signal pair.

[0029] For each of the synchronous environmental signal pairs, the temperature signal is trend-fitted, and a polynomial curve reflecting the slow rise and fall of the ambient background temperature is extracted as the temperature trend component.

[0030] Subtract the corresponding temperature trend component from the temperature signal in each of the synchronous environmental signal pairs to obtain the temperature disturbance component mainly caused by local heat sources or air flow;

[0031] The pressure signal in each of the synchronous environmental signal pairs is subjected to moving average filtering to obtain a pressure baseline that reflects the macroscopic changes in atmospheric pressure, which is used as the pressure trend component.

[0032] The original air pressure signal in each of the synchronous environmental signal pairs is subtracted from the corresponding air pressure baseline to obtain the air pressure disturbance component caused by the start and stop of equipment fans or the opening and closing of doors and windows;

[0033] Spatially interpolate the temperature trend components, temperature disturbance components, air pressure trend components, and air pressure disturbance components from all physical location sensors to form corresponding temperature trend surfaces, temperature disturbance fields, air pressure trend surfaces, and air pressure disturbance fields.

[0034] As a further aspect of the present invention, the step of fusing and aligning the composite electrical signal spectrum with the trend component and the disturbance component in the time dimension to generate a unified state model reflecting the coupling relationship between the chip's operating state and the environment state specifically involves:

[0035] Establish a unified time baseline and map the time axes of the composite electrical signal spectrum, the trend component, and the disturbance component onto the unified time baseline.

[0036] Sampling points are set at fixed time intervals on the unified time reference line;

[0037] At each sampling point, the steady-state description vector value and transient description vector value at the corresponding time are read from the composite electrical signal spectrum, the temperature trend value corresponding to the chip location is read from the temperature trend surface, and the corresponding temperature disturbance value is read from the temperature disturbance field, the air pressure trend value corresponding to the chip location is read from the air pressure trend surface, and the corresponding air pressure disturbance value is read from the air pressure disturbance field.

[0038] The steady-state description vector value, transient description vector value, temperature trend value, temperature disturbance value, air pressure trend value, and air pressure disturbance value read from each sampling point are combined into a multi-dimensional state feature vector in a preset order.

[0039] Arrange the multidimensional state feature vectors corresponding to all sampling points in chronological order to form a sequence of state feature vectors that evolves over time.

[0040] The state feature vector sequence is input into the network structure, and the network structure outputs a dynamic model that can characterize the chip's operating state and the environment state at the current moment, and can predict short-term state changes in the future, which serves as the unified state model.

[0041] As a further aspect of the present invention, the step of parsing the unified state model and identifying key state nodes in the model corresponding to the chip about to enter the high-power region or about to leave the low-power region specifically involves:

[0042] In the state space defined by the unified state model, low-power state regions and high-power state regions are delineated based on historical data clustering.

[0043] Real-time monitoring of the trajectory of the current state point output by the unified state model in the state space;

[0044] When the trajectory shows that the current state point is moving from the inside of the low-power state region to the boundary, calculate the estimated time for the current state point to reach the boundary of the low-power state region;

[0045] If the estimated time is less than the preset warning threshold, the current state point is marked as a candidate critical state node that is about to leave the low power consumption zone.

[0046] When the trajectory shows that the current state point is moving from outside the high-power state region to the boundary, calculate the estimated time for the current state point to reach the boundary of the high-power state region;

[0047] If the estimated time is greater than the preset warning threshold, the current state point is marked as a candidate critical state node that is about to enter the high power consumption zone.

[0048] For each candidate key state node, calculate the curvature and direction consistency of the state evolution path;

[0049] If the curvature is below a threshold and the directional consistency is above a threshold, then the state evolution of the candidate key state node is determined to have a deterministic trend, and it is ultimately identified as the key state node.

[0050] As a further aspect of the present invention, the generation of a pre-execution control sequence containing voltage adjustment instructions and frequency adjustment instructions based on the attributes of the key state nodes and the relationships between the nodes specifically includes:

[0051] Based on the type of the key state node, retrieve the corresponding voltage frequency adjustment mode from the policy library;

[0052] Based on the specific coordinates of the key state nodes in the state space, the initial voltage and initial frequency values ​​used in the state in history are obtained.

[0053] Obtain the current chip's heatsink performance rating and the maximum instantaneous current supply capacity of the power supply unit;

[0054] Starting with the initial voltage and frequency values, and combining the radiator performance rating and the maximum instantaneous current supply capacity, a series of feasible voltage and frequency adjustment paths under electrical and thermal safety constraints are calculated.

[0055] From the feasible voltage and frequency adjustment paths, the path with the smallest energy consumption increment is selected as the optimal adjustment path;

[0056] The optimal adjustment path is discretized into a series of voltage setpoints and frequency setpoints arranged in time sequence;

[0057] Each voltage setpoint is encapsulated as an independent voltage adjustment command, and each frequency setpoint is encapsulated as an independent frequency adjustment command.

[0058] According to the time sequence of the optimal adjustment path, the voltage adjustment command and the frequency adjustment command are interleaved to form the pre-execution control sequence with execution timestamps.

[0059] As a further aspect of the present invention, the step of sending the pre-execution control sequence to the chip's power management interface and synchronously collecting the actual power consumption trajectory fed back by the chip during execution specifically includes:

[0060] Establish a command channel with the chip power management interface, and send each instruction in the pre-execution control sequence sequentially through the command channel;

[0061] When sending each instruction, record the time of transmission and the content of the instruction;

[0062] A data channel is established with the chip's internal power consumption monitoring unit. Through this data channel, the real-time current and voltage values ​​fed back by the chip during instruction execution are continuously collected at a rate higher than the instruction sending frequency.

[0063] Multiply the real-time current value and the real-time voltage value collected at each sampling moment to obtain the instantaneous power consumption value at the sampling moment;

[0064] Connect all instantaneous power consumption values ​​from the start of instruction transmission to the current moment, form a power consumption curve in chronological order, and mark the position point corresponding to the time of each instruction transmission as the actual power consumption trajectory.

[0065] As a further aspect of the present invention, the step of comparing the actual power consumption trajectory with the expected power consumption trajectory in the pre-execution control sequence to calculate the execution error of power consumption adjustment specifically involves:

[0066] Based on the expected voltage and frequency values ​​of each instruction in the pre-execution control sequence, and combined with the chip's nominal power consumption model under the voltage and frequency combination, the expected steady-state power consumption value after the execution of each instruction is calculated.

[0067] Using the execution timestamps of the instructions in the pre-execution control sequence as nodes, the calculated steady-state power consumption values ​​are connected to form a stepped expected power consumption trajectory.

[0068] On the timeline, align the actual power consumption trajectory with the expected power consumption trajectory;

[0069] For each instruction in the pre-execution control sequence, a stable time period is found on the actual power consumption trajectory after the instruction transmission time;

[0070] Calculate the average power consumption value of the actual power consumption trajectory during the stable time period, and use it as the actual steady-state power consumption value after the instruction is executed;

[0071] The single-step execution error of the instruction is obtained by subtracting the actual steady-state power consumption value corresponding to the instruction from the expected steady-state power consumption value.

[0072] The average and standard deviation of the single-step execution error of all instructions in the pre-execution control sequence are statistically analyzed and used as the average execution error and execution dispersion of the overall adjustment, respectively.

[0073] As a further aspect of the present invention, the present invention also includes a chip-based low-power mode intelligent switching system, the system including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the computer program, it implements the steps of the chip-based low-power mode intelligent switching method described above.

[0074] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0075] This approach separates and distinguishes the steady-state components of the chip core from the transient components of the peripheral circuits from the original electrical signal, thereby constructing a composite electrical signal spectrum based on the dynamic range of both. This enables independent characterization and quantification of the power consumption characteristics of different functional modules within the chip, allowing the system to acquire more detailed and interpretable state information than the overall power consumption signal. This provides a data foundation for accurately determining the chip's actual workload and activity mode, avoiding the information aliasing and source ambiguity inherent in traditional single-signal monitoring, thus improving the accuracy of state perception.

[0076] The aforementioned composite electrical signal spectrum is rigorously fused and aligned with the decomposed environmental trend and disturbance components in the time dimension to generate a unified chip-environment coupled state model. This scheme establishes an explicit correlation between internal electrical activity modes and dynamic changes in the external environment, enabling the system to analyze state transitions from a holistic, collaborative evolution perspective. By analyzing this model to identify key state nodes, the decision-making process can comprehensively reflect the combined effects of internal activities and external conditions, achieving forward-looking prediction of power mode transition critical points, thus changing the traditional passive response method based on independent threshold comparisons.

[0077] Based on the key node attributes and their interrelationships derived from the unified model, a pre-execution control sequence containing specific voltage and frequency adjustment instructions is dynamically generated. The generation logic of this control sequence is directly derived from an in-depth analysis of the coupled states, ensuring a high degree of matching between the control instructions and the complex real-world scenario in which the chip operates. The pre-execution mechanism enables the switching of power consumption modes to be precisely synchronized with the predicted state changes in timing, reducing uncertainties and resource waste during state transitions and achieving smoother and more timely low-power state transitions. Attached Figure Description

[0078] Figure 1 This is a flowchart of the intelligent switching method for low-power modes based on chips as described in this invention;

[0079] Figure 2 A flowchart for the pre-execution control sequence issuance and feedback correction;

[0080] Figure 3A flowchart for constructing a composite electrical signal spectrum;

[0081] Figure 4 A feature decomposition diagram of the chip's operating environment temperature signal;

[0082] Figure 5 This is a timing monitoring diagram of the chip's operating state feature vector. Detailed Implementation

[0083] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0084] In the description of this invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, in the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0085] See Figure 1 The process involves acquiring raw electrical signals and environmental signals during chip operation. Raw electrical signals typically include current and voltage waveforms, while environmental signals may include temperature and pressure data from sensors. Steady-state electrical signals generated by the chip core's operation and transient electrical signals generated by peripheral circuitry are extracted from the raw electrical signals. Based on the dynamic range of each component, steady-state and transient description vectors are constructed and mapped and connected in a two-dimensional plane to form a composite electrical signal spectrum. Signal feature decomposition is performed on the environmental signals to extract slowly changing trend components and rapidly fluctuating disturbance components. The composite electrical signal spectrum is fused and aligned with the trend and disturbance components in the time dimension. By establishing a unified time reference, sampling, combining multi-dimensional feature vectors, and inputting them into a time-series network, a unified state model reflecting the coupling relationship between the chip's operating state and the environmental state is generated. This unified state model is analyzed to identify key state nodes corresponding to the chip entering a high-power region or leaving a low-power region. Based on the attributes of key state nodes and the relationships between nodes, the corresponding adjustment mode is retrieved from the policy library. The optimal adjustment path is calculated by combining historical records and hardware constraints, and then discretized into an instruction sequence to generate a set of pre-execution control sequences containing voltage adjustment instructions and frequency adjustment instructions.

[0086] In one embodiment of the present invention, see [reference] Figure 2 The pre-execution control sequence is sent to the chip's power management interface through an established command channel, which is implemented using an integrated circuit bus or serial peripheral interface protocol. When sending each instruction in the pre-execution control sequence, the system records the transmission time of the instruction and the specific voltage or frequency value contained within it. During instruction execution, the system synchronously acquires real-time current and voltage values ​​fed back by the chip's internal power consumption monitoring unit through an independent data channel. The sampling frequency of the data channel is set to a fixed multiple higher than the instruction transmission frequency. The real-time current and voltage values ​​acquired at each sampling time are multiplied to obtain the instantaneous power consumption value at that sampling time. Using time as the x-axis and the instantaneous power consumption value as the y-axis, all instantaneous power consumption data points from the instruction transmission start time to the current time are sequentially connected to form a power consumption change curve extending from the start time to the current time. This curve is defined as the actual power consumption trajectory. On the actual power consumption trajectory, the system marks the specific position point on the curve corresponding to each instruction transmission time based on the recorded instruction transmission time.

[0087] Comparing the actual power consumption trajectory with the expected power consumption trajectory in the pre-execution control sequence requires pre-constructing the expected power consumption trajectory. Based on the expected voltage and frequency values ​​for each instruction in the pre-execution control sequence, and combined with the nominal power consumption model provided by the chip manufacturer describing the relationship between voltage / frequency combinations and power consumption, the expected steady-state power consumption value after each instruction's execution is calculated. Using the execution timestamp associated with each instruction in the pre-execution control sequence as a time node, these calculated steady-state power consumption values ​​are connected chronologically to form a stepped expected power consumption trajectory. The actual power consumption trajectory and the expected power consumption trajectory are strictly aligned on the time axis. For each instruction in the pre-execution control sequence, the system locates a stable time period after the instruction's transmission time on the actual power consumption trajectory, calculates the arithmetic mean of all instantaneous power consumption values ​​within this stable time period, and uses this average as the actual steady-state power consumption value after the instruction's execution. The difference between the actual steady-state power consumption value corresponding to the instruction and the expected steady-state power consumption value of the instruction is the single-step execution error of that instruction. The single-step execution error of all instructions in the pre-execution control sequence is statistically analyzed. The arithmetic mean of all single-step execution errors is calculated as the average execution error of the overall adjustment. At the same time, the standard deviation of all single-step execution errors is calculated as the execution dispersion of the overall adjustment. The average execution error and the execution dispersion together constitute the execution error of power consumption adjustment.

[0088] In some embodiments, when fine-tuning the parameters of subsequent instructions in the pre-execution control sequence based on the execution error, the system quantitatively adjusts the voltage and frequency values ​​of subsequent instructions based on the calculated average execution error and execution dispersion. If the average execution error is positive and the execution dispersion is small, indicating that the actual power consumption is consistently higher than expected, the system will proportionally reduce the voltage setpoint in subsequent instructions. The adjustment amount of the voltage setpoint... Through the formula:

[0089]

[0090] in: It is the predetermined compensation gain coefficient. This is the statistically obtained average execution error. The fine-tuning process applies the commands in the pre-execution control sequence that have not yet been executed, generating a corrected control sequence with updated parameters.

[0091] As can be understood, after generating the corrected control sequence, the system encapsulates the corrected control sequence, the actual power consumption trajectory, and the execution error into a status report. The status report is encoded in a predefined binary format, containing a sequence identifier, timestamp, corrected instruction list, power consumption sampling point array, and error statistics structure. The encapsulated status report is sent to an external collaborative management node via a short-range wireless communication link. This short-range wireless communication link operates in a specific frequency band and uses the Bluetooth Low Energy protocol for data transmission. In specific implementations, after receiving the status report, the collaborative management node parses the report content and stores the corrected control sequence, actual power consumption trajectory, and execution error into a historical database. This historical database provides data records for subsequent analysis of power adjustment strategies under similar workloads.

[0092] In one embodiment of the present invention, see [reference] Figure 3 The raw electrical signals generated during chip operation are segmented using a window function. The Hanning window, with a window length of 1024 sampling points and a 512-sampling-point overlap between adjacent windows, yields a series of time-continuous and partially overlapping signal segments. A Fast Fourier Transform (FFT) is performed on each signal segment to perform spectral analysis. In the resulting spectrum, frequency bands below 10kHz with continuous energy are identified as low-frequency energy bands, while spectral lines above 10kHz exhibiting isolated peaks are identified as discrete energy lines. An inverse Fourier transform is performed on the low-frequency energy bands to reconstruct the steady-state electrical signal components representing the continuous computational load of the chip core. An inverse Fourier transform is then performed on each discrete energy line, and the time-domain signals obtained from all inverse transforms are superimposed and summed to reconstruct the transient electrical signal components representing sudden access operations of peripheral circuits.

[0093] Calculate the mean and variance of the steady-state electrical signal components within a preset observation window. The preset observation window length is 1 millisecond. With variance The calculation covers all sampling points within the window, forming a steady-state description vector containing two elements. S ⃗ =[ μ s , σ s 2 ] Count the number of times transient electrical signal components appear within the same preset observation window. Average amplitude and cumulative duration This forms a transient description vector containing three elements. T ⃗ =[N, A avg , T sum ] Plotting time on the horizontal axis and signal amplitude on the vertical axis, the mean value in the steady-state description vector is... Mapped to steady-state feature points in a two-dimensional plane, the ordinate position is determined by... The value of determines the average magnitude in the transient description vector. Mapped to transient feature points at the same timestamp. Connecting the corresponding steady-state and transient feature points at the same timestamp forms a feature line segment pointing from the steady-state feature point to the transient feature point. The length of the feature line segment is equal to the average amplitude of the transient component. Proportional. Arrange all feature segments generated by timestamps from left to right in chronological order, and label each segment with a ratio label. The ratio label represents the ratio between steady-state and transient energy, thus forming a composite electrical signal spectrum.

[0094] In some embodiments, the system receives raw environmental signals from sensors deployed at three different physical locations within the cabinet: directly above the chip, at the left air duct inlet of the chip, and at the back of the cabinet. The raw environmental signals include at least temperature signals from temperature sensors at each location and air pressure signals from air pressure sensors. The temperature and air pressure signals from sensors at the same physical location are time-stamped and normalized. Time-stamping is performed using interpolation to synchronize the system clock, and signal amplitude normalization maps the raw voltage readings to a range of 0 to 1, resulting in three pairs of synchronized environmental signals. The temperature signal in each synchronized environmental signal pair is fitted using the least squares method to extract a quadratic polynomial curve reflecting the slow rise and fall of the ambient background temperature on a timescale of several minutes, serving as the temperature trend component for that location. The corresponding temperature trend component is subtracted from the raw temperature signal in each synchronized environmental signal pair to obtain the temperature disturbance component, primarily caused by the chip's own heating or the airflow from the cooling fan, with a change period of less than a second.

[0095] Optionally, a moving average filter is applied to the air pressure signal in each synchronization environment signal pair, with a moving window length of 100 sampling points, to obtain a smooth air pressure baseline as the air pressure trend component. The difference between the original air pressure signal in each synchronization environment signal pair and the corresponding air pressure baseline is calculated to obtain the air pressure disturbance component caused by the periodic start and stop of the equipment fan or the opening and closing of the cabinet door. The temperature trend components from the three physical location sensors are spatially interpolated using a bilinear interpolation algorithm to generate a two-dimensional temperature trend surface covering the area where the chips are located within the cabinet. The temperature disturbance components from the three physical location sensors are interpolated using the same method to generate a two-dimensional temperature disturbance field.

[0096] It can be understood that spatial interpolation is performed on the pressure trend components from all physical location sensors to generate a two-dimensional pressure trend surface. Similarly, spatial interpolation is performed on the pressure disturbance components from all physical location sensors to generate a two-dimensional pressure disturbance field. In practice, the two-dimensional trend surface and disturbance field are stored as grid data, with each grid node containing numerical and coordinate information. It can be understood that through these steps, the environmental signal is decomposed into slowly changing background trend components and rapidly fluctuating local disturbance components, forming spatial distribution information and providing multi-dimensional environmental state input for subsequent fusion with electrical signals.

[0097] In one embodiment of the present invention, a unified time baseline is established, with the initial power-on time of the system as the origin and incrementing in milliseconds. The time axes of the composite electrical signal spectrum, the temperature trend surface, the temperature disturbance field, the pressure trend surface, and the pressure disturbance field are mapped and aligned with the unified time baseline using their respective timestamps. Sampling points are set at fixed time intervals on the unified time baseline, with the sampling interval set to 100 microseconds. At each sampling point, the steady-state description vector value and transient description vector value for the corresponding time moment are read from the composite electrical signal spectrum. The steady-state description vector value includes the mean. With variance The transient description vector value includes the number of occurrences. Average amplitude and cumulative duration .

[0098] In practice, at each sampling point, the temperature trend value corresponding to that coordinate point is read from the two-dimensional temperature trend surface through bilinear interpolation, based on the chip's physical coordinates within the cabinet. And read the corresponding temperature perturbation value from the two-dimensional temperature perturbation field. At the same sampling point, based on the same physical coordinates, the corresponding pressure trend value is read from the two-dimensional pressure trend surface. And read the corresponding pressure disturbance value from the two-dimensional pressure disturbance field. The six feature values ​​read from each sampling point are combined into a nine-dimensional multidimensional state feature vector according to a preset order: steady-state mean, steady-state variance, number of transients, transient amplitude, transient duration, temperature trend, temperature disturbance, air pressure trend, and air pressure disturbance. Its expression is:

[0099] V ⃗ state =[ μ s , σ s 2 , N t , A t , D t , Θ trend , Θ perturb , P trend , P perturb ]

[0100] in: and From the steady-state description vector, From the transient description vector, and These represent the temperature trend value and the temperature disturbance value, respectively. and These represent the pressure trend value and the pressure disturbance value, respectively. The multidimensional state feature vectors corresponding to all sampling points are arranged in chronological order along the time baseline, forming a sequence of state feature vectors that evolves continuously over time.

[0101] In some embodiments, the state feature vector sequence is input into a network structure with temporal memory capability. The network structure employs a Long Short-Term Memory (LSTM) recurrent neural network (RNN). The LSM RNN has 9 input layer nodes, corresponding to the dimension of the multidimensional state feature vector, and 9 output layer nodes. The hidden layer contains 64 memory units. The LSM RNN uses the multidimensional state feature vector from the previous time step and the network's internal memory states as input to learn the dependencies and transition rules between previous and subsequent states in the state feature vector sequence, and predicts the multidimensional state feature vector for the next time step. The predicted vector output by the network structure, together with the historical state sequence at the current moment, constitutes a dynamic model that characterizes the chip's operating state and environmental state at the current moment, and can iteratively predict future short-term state changes. This dynamic model is defined as a unified state model.

[0102] It is understandable that establishing a unified time baseline ensures strict synchronization of signals from different sources in the time dimension, and the construction of multi-dimensional state feature vectors realizes standardized encapsulation of multi-source heterogeneous data. In some embodiments, the sampling interval can be adjusted according to specific application scenarios. For example, in scenarios with drastic load changes, the sampling interval can be set to 50 microseconds, while in scenarios with stable loads, the sampling interval can be set to 500 microseconds. It is also understandable that by modeling the state sequence through a long short-term memory recurrent neural network, the unified state model not only captures instantaneous snapshots of the states but also embeds the dynamic laws of state evolution, giving the model short-term predictive capabilities. In specific implementations, the unified state model is stored in memory in the form of network parameters and the current memory state, and is updated in real time with the arrival of new sampling points.

[0103] In one embodiment of the present invention, in the state space defined by the unified state model, low-power state regions and high-power state regions are delineated based on the analysis of historical chip operating data. The system extracts a set of multi-dimensional state feature vectors corresponding to all low-power operating segments from the stored historical operating data. These vectors are processed using a K-means clustering algorithm, and the space enclosed by the cluster centers and the boundary range containing the vast majority of low-power samples is defined as the low-power state region. Similarly, the system extracts a set of multi-dimensional state feature vectors corresponding to all high-power operating segments and performs cluster analysis, defining the space enclosed by the cluster centers and the boundary range containing high-power samples as the high-power state region. The system monitors in real time the trajectory of the current state point output by the unified state model in the state space; the trajectory is formed by connecting consecutive state point positions within a recent period.

[0104] In some embodiments, when the trajectory shows that the current state point is moving from the interior of the low-power state region towards the boundary, and the direction of movement is pointing towards the high-power state region, the system calculates the estimated time for the current state point to reach the boundary of the low-power state region along the current moving speed vector. Estimated time By calculating the shortest Euclidean distance from the current state point to the region boundary. Divide by the instantaneous rate at the current state point Received. If the calculated estimated time If the current state point is below the preset warning threshold, it is marked as a candidate critical state node that is "about to leave the low-power region". When the trajectory shows that the current state point is moving from outside the high-power state region towards the boundary, and the direction of movement is pointing towards the inside of the high-power state region, the estimated time for the current state point to reach the boundary of the high-power state region is also calculated. If this estimated time... If the value exceeds the preset warning threshold, the current state point will be marked as a candidate critical state node that is about to enter the high power consumption zone.

[0105] For each candidate critical state node, the system traces its state evolution path over the previous few time steps; this path consists of a continuous sequence of state points. The curvature of the state evolution path is calculated. Consistency with direction curvature Reflects the degree of path curvature and directional consistency The stability of the direction of movement is quantified by calculating the average of the dot product of continuous displacement vectors along the path. If the curvature... Below the preset curvature threshold and with consistent direction If the state evolution of this candidate critical state node exceeds a preset consistency threshold, it is determined that the state evolution has a deterministic trend, and it is ultimately identified as a critical state node. The system obtains the type attribute of the critical state node, which includes "about to leave the low-power region" or "about to enter the high-power region".

[0106] In practical implementation, if the critical state node is "about to leave the low-power region," then a voltage and frequency regulation pattern related to smooth performance improvement is retrieved from the pre-built policy library. This pattern may contain a sequence where voltage increases before frequency increases. If the critical state node is "about to enter the high-power region," then a voltage and frequency regulation pattern related to preventing performance overheating is retrieved from the policy library. This pattern may contain rules for frequency-limited increases. Based on the specific coordinates of the critical state node in the state space, historical successful regulation records are queried from the historical database to obtain the initial voltage values ​​used in the same or similar coordinate states in the past. Compared with the initial frequency value See Table 1, a historical record lookup table.

[0107] Table 1: Historical Successful Adjustment Records

[0108]

[0109] Get the heatsink performance rating of the current chip Maximum instantaneous current supply capability of the power supply unit With the initial voltage value Compared with the initial frequency value Starting with radiator performance ratings With maximum instantaneous current supply capability As a constraint, a series of feasible voltage-frequency adjustment paths are calculated on the voltage-frequency two-dimensional plane. Each path is composed of multiple discrete voltage-frequency points connected sequentially. From all feasible voltage-frequency adjustment paths, the path that enables the chip to operate stably at the target performance level and minimizes the overall energy consumption increment is selected as the optimal adjustment path.

[0110] Optionally, the optimal adjustment path is discretized into a series of voltage and frequency setpoints arranged in chronological order, with the time interval between setpoints determined based on the urgency of load changes. Each voltage setpoint is encapsulated as an independent voltage adjustment instruction containing the target voltage value; each frequency setpoint is encapsulated as an independent frequency adjustment instruction containing the target frequency value. Following the chronological order of the optimal adjustment path, the voltage and frequency adjustment instructions are interleaved to form a pre-execution control sequence, and each instruction in the pre-execution control sequence is appended with an execution timestamp accurate to microseconds. It can be understood that the interleaved arrangement of instructions is to avoid electrical stress caused by simultaneous abrupt changes in voltage and frequency. In some embodiments, the pre-execution control sequence is cached in memory using a linked list data structure, awaiting issuance.

[0111] See Figure 4 This is a feature decomposition diagram of the chip's operating environment temperature signal. By performing trend fitting and perturbation extraction on the original temperature signal, it clearly shows the long-term trend and short-term fluctuation characteristics of the ambient temperature. This is the core analysis result of the "environmental signal processing" stage in the chip's low-power mode intelligent switching system. Changes in ambient temperature are driven by both slow trends and rapid perturbations. The trend component reflects macroscopic environmental changes and is an important input for chip power consumption prediction; the perturbation component reflects local thermal events and is a key basis for triggering dynamic power consumption regulation. After 120 steps, the amplitude and frequency of temperature perturbation significantly increase, which highly coincides with the key node (140 steps) in the chip's state trajectory indicating "approaching the high-power region," suggesting that chip heating has become one of the main sources of ambient temperature perturbations. This correlation is the core basis for constructing the "chip operating state and environmental state coupling model."

[0112] In one embodiment of the present invention, a command channel is established with the chip's power management interface. The command channel employs a system management bus protocol, and the system sequentially sends each instruction in the pre-execution control sequence through the command channel. When sending each instruction, the system records the sending time and instruction content, which includes the target voltage value for a voltage adjustment instruction or the target frequency value for a frequency adjustment instruction. A data channel is established with the chip's internal power consumption monitoring unit. The data channel employs an integrated circuit bus protocol, and the system continuously collects real-time current and voltage values ​​fed back by the chip during instruction execution at a rate higher than the instruction sending frequency. The instruction sending frequency is 100 instructions per second, and the data acquisition frequency is 10,000 times per second. The real-time current value collected at each sampling time is... With real-time voltage value Multiply by the product to obtain the instantaneous power consumption value at that sampling moment. Using time as the horizontal axis and instantaneous power consumption as the vertical axis, all instantaneous power consumption data points from the start of instruction transmission to the current time are connected in chronological order to form a continuous power consumption curve extending from the start time to the current time. This curve is defined as the actual power consumption trajectory. On the actual power consumption trajectory, the system marks corresponding position points on the curve according to the recorded transmission time of each instruction. These position points segment the trajectory to correspond to different instruction execution stages.

[0113] In some embodiments, constructing the expected power consumption trajectory requires relying on the instruction parameters in the pre-executed control sequence and the chip's nominal power consumption model. Based on the expected voltage and frequency values ​​for each instruction in the pre-executed control sequence, and combined with the nominal power consumption model provided by the chip manufacturer describing the relationship between voltage / frequency combinations and steady-state power consumption, the expected steady-state power consumption value after each instruction's execution is calculated. The nominal power consumption model can be a lookup table or a polynomial function. Using the execution timestamp associated with each instruction in the pre-executed control sequence as a time node, these calculated expected steady-state power consumption values ​​are connected chronologically to form a stepped expected power consumption trajectory. On the time axis, the actual power consumption trajectory and the expected power consumption trajectory are strictly aligned; the alignment operation is based on the common start timestamp and the same time scale of the two trajectories.

[0114] For each instruction in the pre-execution control sequence, the system locates a stable time period after the instruction's transmission time on the actual power consumption trajectory. The starting point of this stable time period is a preset stabilization delay (e.g., 200 microseconds) after the instruction transmission, and the duration is fixed at 500 microseconds. The average power consumption value within this stable time period on the actual power consumption trajectory is calculated. This average value is used as the actual steady-state power consumption value after the instruction is executed. The calculation formula is:

[0115]

[0116] in: It is the total number of sampling points within a stable time period. It is the first The instantaneous power consumption value at each sampling point. The actual steady-state power consumption value corresponding to the instruction. Compared with the expected steady-state power consumption value The difference is calculated, and the resulting value is the single-step execution error of this instruction. The single-step execution error of all instructions in the pre-execution control sequence is statistically analyzed, and the arithmetic mean of all single-step execution errors is calculated as the average execution error of the overall adjustment. Simultaneously, the standard deviation of all single-step execution errors is calculated as the execution dispersion of the overall adjustment. .

[0117] See Figure 5 This is a timing monitoring diagram of the chip's operating state feature vector. By comparing it with the boundary thresholds of the low-power and high-power regions, it reflects the dynamic switching process of the chip between different power states in real time. It is the core basis for the "state monitoring and key node identification" stage in the low-power mode intelligent switching system. The high-frequency fluctuation of the state feature value indicates that the chip load changes rapidly. The system needs to have millisecond-level monitoring and control response capabilities to avoid performance jitter caused by frequent switching. The boundary between the low-power region (40) and the high-power region (70) can be further optimized based on the chip's historical operating data. For example, the state region can be redefined to better fit the actual situation through K-means clustering to improve the accuracy of key node identification.

[0118] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for intelligent switching of low-power modes based on chips, characterized in that, Includes the following steps: Acquire the raw electrical signals and raw environmental signals during chip operation; The steady-state electrical signal component generated by the operation of the chip core and the transient electrical signal component generated by the activity of the peripheral circuit are extracted from the original electrical signal, and a composite electrical signal spectrum is constructed based on the dynamic range of the steady-state electrical signal component and the transient electrical signal component respectively. The original environmental signal is subjected to signal feature decomposition to extract the trend component that changes slowly over time and the disturbance component that fluctuates rapidly over time. The composite electrical signal spectrum is fused and aligned with the trend component and the disturbance component in the time dimension to generate a unified state model that reflects the coupling relationship between the chip's operating state and the environment state. The unified state model is analyzed to identify key state nodes in the model that correspond to the chip about to enter the high power consumption region or about to leave the low power consumption region. Based on the attributes of the key state nodes and the relationships between the nodes, a set of pre-execution control sequences containing voltage regulation commands and frequency regulation commands is generated.

2. The method for intelligent switching of low-power modes based on chips according to claim 1, characterized in that, The method further includes: The pre-execution control sequence is sent to the chip's power management interface, and the actual power consumption trajectory fed back by the chip is collected synchronously during the execution process; The actual power consumption trajectory is compared with the expected power consumption trajectory in the pre-execution control sequence to calculate the execution error of power consumption adjustment; Based on the execution error, the parameters of subsequent instructions in the pre-execution control sequence are fine-tuned to generate a corrected control sequence; The corrected control sequence, the actual power consumption trajectory, and the execution error are encapsulated into a status report and sent to an external collaborative management node via a short-range wireless communication link.

3. The method for intelligent switching of low-power modes based on chips according to claim 1, characterized in that, The process involves extracting the steady-state electrical signal component generated by the chip core's operation and the transient electrical signal component generated by the peripheral circuitry from the original electrical signal, and constructing a composite electrical signal spectrum based on the dynamic ranges of the steady-state and transient electrical signal components. Specifically: The original electrical signal is segmented to obtain time-continuous signal segments; Spectral analysis is performed on each signal segment to separate the low-frequency energy concentration band located near the fundamental frequency and the discrete energy spectral lines distributed in the high-frequency region; The low-frequency energy concentration band is reconstructed into a steady-state electrical signal component characterizing the continuous computing load of the chip core; The time-domain signals corresponding to the discrete energy spectral lines are superimposed to reconstruct transient electrical signal components characterizing the sudden access operation of the peripheral circuit; The characteristic parameters of the steady-state electrical signal component and the transient electrical signal component within a preset observation window are extracted respectively. The elements in the steady-state electrical signal component and the transient electrical signal component are mapped to feature points on a two-dimensional plane; Connect the steady-state feature points and transient feature points at the same timestamp to form multiple feature line segments; The feature line segments are arranged in chronological order, and the ratio of steady-state to transient energy is marked to form the composite electrical signal spectrum.

4. The method for intelligent switching of low-power modes based on chips according to claim 1, characterized in that, The step of performing signal feature decomposition on the original environmental signal to extract the trend components that change slowly over time and the disturbance components that fluctuate rapidly over time specifically involves: Receive raw environmental signals from multiple physical location sensors, the raw environmental signals including temperature signals and air pressure signals; Temperature and air pressure signals from sensors at the same physical location are time-stamped and their amplitudes are normalized to obtain a synchronized environmental signal pair. For each of the synchronous environmental signal pairs, the temperature signal is trend-fitted, and a polynomial curve reflecting the slow rise and fall of the ambient background temperature is extracted as the temperature trend component. Subtract the corresponding temperature trend component from the temperature signal in each of the synchronous environmental signal pairs to obtain the temperature disturbance component mainly caused by local heat sources or air flow; The pressure signal in each of the synchronous environmental signal pairs is subjected to moving average filtering to obtain a pressure baseline that reflects the macroscopic changes in atmospheric pressure, which is used as the pressure trend component. The original air pressure signal in each of the synchronous environmental signal pairs is subtracted from the corresponding air pressure baseline to obtain the air pressure disturbance component caused by the start and stop of equipment fans or the opening and closing of doors and windows; Spatially interpolate the temperature trend components, temperature disturbance components, air pressure trend components, and air pressure disturbance components from all physical location sensors to form corresponding temperature trend surfaces, temperature disturbance fields, air pressure trend surfaces, and air pressure disturbance fields.

5. The method for intelligent switching of low-power modes based on chips according to claim 4, characterized in that, The step of fusing and aligning the composite electrical signal spectrum with the trend component and the disturbance component in the time dimension to generate a unified state model reflecting the coupling relationship between the chip's operating state and the environment state specifically involves: Establish a unified time baseline and map the time axes of the composite electrical signal spectrum, the trend component, and the disturbance component onto the unified time baseline. Sampling points are set at fixed time intervals on the unified time reference line; At each sampling point, the steady-state description vector value and transient description vector value at the corresponding time are read from the composite electrical signal spectrum, the temperature trend value corresponding to the chip location is read from the temperature trend surface, and the corresponding temperature disturbance value is read from the temperature disturbance field, the air pressure trend value corresponding to the chip location is read from the air pressure trend surface, and the corresponding air pressure disturbance value is read from the air pressure disturbance field. The steady-state description vector value, transient description vector value, temperature trend value, temperature disturbance value, air pressure trend value, and air pressure disturbance value read from each sampling point are combined into a multi-dimensional state feature vector in a preset order. Arrange the multidimensional state feature vectors corresponding to all sampling points in chronological order to form a sequence of state feature vectors that evolves over time. The state feature vector sequence is input into the network structure, and the network structure outputs a dynamic model that can characterize the chip's operating state and the environment state at the current moment, and can predict short-term state changes in the future, which serves as the unified state model.

6. The method for intelligent switching of low-power modes based on chips according to claim 5, characterized in that, The process of analyzing the unified state model identifies key state nodes in the model that correspond to the chip about to enter the high-power region or about to leave the low-power region. Specifically: In the state space defined by the unified state model, low-power state regions and high-power state regions are delineated based on historical data clustering. Real-time monitoring of the trajectory of the current state point output by the unified state model in the state space; When the trajectory shows that the current state point is moving from the inside of the low-power state region to the boundary, calculate the estimated time for the current state point to reach the boundary of the low-power state region; If the estimated time is less than the preset warning threshold, the current state point is marked as a candidate critical state node that is about to leave the low power consumption zone. When the trajectory shows that the current state point is moving from outside the high-power state region to the boundary, calculate the estimated time for the current state point to reach the boundary of the high-power state region; If the estimated time is greater than the preset warning threshold, the current state point is marked as a candidate critical state node that is about to enter the high power consumption zone. For each candidate key state node, calculate the curvature and direction consistency of the state evolution path; If the curvature is below a threshold and the directional consistency is above a threshold, then the state evolution of the candidate key state node is determined to have a deterministic trend, and it is ultimately identified as the key state node.

7. The method for intelligent switching of low-power modes based on chips according to claim 6, characterized in that, Based on the attributes of the key state nodes and the relationships between the nodes, a set of pre-execution control sequences containing voltage adjustment commands and frequency adjustment commands is generated, specifically as follows: Based on the type of the key state node, retrieve the corresponding voltage frequency adjustment mode from the policy library; Based on the specific coordinates of the key state nodes in the state space, the initial voltage and initial frequency values ​​used in the state in history are obtained. Obtain the current chip's heatsink performance rating and the maximum instantaneous current supply capacity of the power supply unit; Starting with the initial voltage and frequency values, and combining the radiator performance rating and the maximum instantaneous current supply capacity, a series of feasible voltage and frequency adjustment paths under electrical and thermal safety constraints are calculated. From the feasible voltage and frequency adjustment paths, the path with the smallest energy consumption increment is selected as the optimal adjustment path; The optimal adjustment path is discretized into a series of voltage setpoints and frequency setpoints arranged in time sequence; Each voltage setpoint is encapsulated as an independent voltage adjustment command, and each frequency setpoint is encapsulated as an independent frequency adjustment command. According to the time sequence of the optimal adjustment path, the voltage adjustment command and the frequency adjustment command are interleaved to form the pre-execution control sequence with execution timestamps.

8. The method for intelligent switching of low-power modes based on chips according to claim 2, characterized in that, The step of sending the pre-execution control sequence to the chip's power management interface and synchronously collecting the actual power consumption trajectory fed back by the chip during execution is as follows: Establish a command channel with the chip power management interface, and send each instruction in the pre-execution control sequence sequentially through the command channel; When sending each instruction, record the time of transmission and the content of the instruction; A data channel is established with the chip's internal power consumption monitoring unit. Through this data channel, the real-time current and voltage values ​​fed back by the chip during instruction execution are continuously collected at a rate higher than the instruction sending frequency. Multiply the real-time current value and the real-time voltage value collected at each sampling moment to obtain the instantaneous power consumption value at the sampling moment; Connect all instantaneous power consumption values ​​from the start of instruction transmission to the current moment, form a power consumption curve in chronological order, and mark the position point corresponding to the time of each instruction transmission as the actual power consumption trajectory.

9. The method for intelligent switching of low-power modes based on chips according to claim 2, characterized in that, The step of comparing the actual power consumption trajectory with the expected power consumption trajectory in the pre-execution control sequence to calculate the execution error of power consumption adjustment specifically involves: Based on the expected voltage and frequency values ​​of each instruction in the pre-execution control sequence, and combined with the chip's nominal power consumption model under the voltage and frequency combination, the expected steady-state power consumption value is calculated. The calculated steady-state power consumption values ​​are connected together to form the expected power consumption trajectory. For each instruction in the pre-execution control sequence, a stable time period is found on the actual power consumption trajectory after the instruction transmission time; Calculate the average power consumption value of the actual power consumption trajectory during the stable time period, and use it as the actual steady-state power consumption value corresponding to the instruction; The single-step execution error of the instruction is obtained by subtracting the actual steady-state power consumption value corresponding to the instruction from the expected steady-state power consumption value. The average and standard deviation of the single-step execution error of all instructions in the pre-execution control sequence are statistically analyzed and used as the average execution error and execution dispersion of the overall adjustment, respectively.

10. A chip-based low-power mode intelligent switching system, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the chip low-power mode intelligent switching method described in any one of claims 1 to 9.

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