Training method for high-bandwidth memory, computer equipment and medium

Abstract

The invention relates to the technical field of digital signal processing and provides a training method for a high-bandwidth memory, computer equipment and a medium. The training method includes utilizing a loopback mode of a high-bandwidth memory device, and performing de-bias training through cooperation between a high-bandwidth memory physical layer and the high-bandwidth memory device. Therefore, data alignment in the physical layer of the high-bandwidth memory is realized, the deviation between the signal groups is reduced, the variation range of the deviation between the signals is controlled, simplified design is realized in the aspects of hardware implementation and algorithm details, the eye pattern margin is improved, and the performance of the high-bandwidth memory is improved.

Description

Technical Field

[0001] This application relates to the field of digital signal processing technology, and in particular to a training method, computer device and medium for high-bandwidth memory. Background Technology

[0002] High-bandwidth memory (HBM) is widely used in applications such as large-scale artificial intelligence models, data centers, and high-performance servers, and generally supports the Double Data Rate Memory Physical Layer Interface (DFI) protocol. Due to factors such as circuit delay characteristics, path differences, and process voltage temperature (PVT) variations, skew may exist between the multiple signals received by the parallel interface of HBM. This can affect the accuracy of data sampling and hinder performance improvement. To address this, HBM provides high-performance parallel interface solutions and offers a series of training schemes through firmware training to achieve data alignment and improve data sampling accuracy. However, existing HBM training schemes generally focus on detection and adjustment at the parallel interface of the HBM, such as obtaining timing information between signals through pins and providing training schemes. Even with data alignment at the parallel interface, after entering the internal physical layer of the HBM, skew may still exist between the internal signals due to delay differences during signal transmission. Because it is located inside the physical layer of high-bandwidth memory, it is difficult to accurately obtain the timing information between signals using probes or external instruments. Furthermore, the number and composition of the signals to be transmitted may vary, which means that the signal deviations inside the physical layer of high-bandwidth memory may also vary. Therefore, it is necessary to perform detection and training from time to time to reduce signal deviations inside the physical layer of high-bandwidth memory. This requires simplification in both hardware implementation and algorithm details.

[0003] Therefore, this application provides a training method, computer device, and medium for high-bandwidth memory to solve the technical problems in the prior art. Summary of the Invention

[0004] In a first aspect, this application provides a training method for a high-bandwidth memory. The training method includes utilizing a loopback mode of the high-bandwidth memory device to perform debiasing training through cooperation between the high-bandwidth memory physical layer and the high-bandwidth memory device. The method includes: gradually increasing the delay of a data gating signal starting from zero delay, and after each adjustment of the data gating signal, comparing data based on the sampling results of multiple signal groups until the sampling results of each of the multiple signal groups are correct, thereby determining the left boundary and delay value of the data gating signal relative to the signal width. The high-bandwidth memory physical layer is used to receive the multiple signal groups, each of the multiple signal groups including at least one signal, the sum of the data widths of the signals included in each of the multiple signal groups does not exceed the signal width, and the signals included in each of the multiple signal groups satisfy inter-signal deviation constraints. The digital delay chain of the data strobe signal is configured using the delay value of the data strobe signal relative to the signal width. Then, the delay of each of the multiple signal groups is gradually increased from zero delay through their respective independent digital delay chains, thereby obtaining data comparison results for each of the multiple signal groups within a configurable delay range. Based on the data comparison results of the multiple signal groups, the distance between the left boundary of each of the multiple signal groups and the left boundary of the data strobe signal relative to the signal width is determined, thereby determining the delay value of each of the multiple signal groups relative to the signal width. The digital delay chain of each of the multiple signal groups is configured using the delay values ​​of each of the multiple signal groups relative to the signal width, thereby reducing the deviation between the multiple signal groups.

[0005] Through the first aspect of this application, not only is data alignment achieved within the physical layer of the high-bandwidth memory, reducing the deviation between signal groups and controlling the range of variation of the deviation between signals, but also the hardware implementation and algorithm details are simplified, improving the eye diagram margin and thus improving the performance of the high-bandwidth memory.

[0006] In one possible implementation of the first aspect of this application, the debiasing training is used for receiving direction debiasing training, the data gating signal is a receiving direction data gating signal, the high-bandwidth memory physical layer generates reference data, and the high-bandwidth memory physical layer compares the reference data with the sampled data returned by the high-bandwidth memory device to determine whether the sampling results of each of the plurality of signal groups are correct.

[0007] In one possible implementation of the first aspect of this application, the debiasing training is used for transmission direction debiasing training, the data gating signal is a transmission direction data gating signal, the high-bandwidth memory physical layer generates reference data and sends the reference data to the high-bandwidth memory device, the high-bandwidth memory device performs data comparison and sends the data comparison result to the high-bandwidth memory physical layer, and then the high-bandwidth memory physical layer determines whether the sampling results of each of the plurality of signal groups are correct based on the data comparison result.

[0008] In one possible implementation of the first aspect of this application, the debiasing training includes receiving direction debiasing training and the data gating signal in the receiving direction debiasing training is a receiving direction data gating signal, and the debiasing training also includes transmitting direction debiasing training and the data gating signal in the transmitting direction debiasing training is a transmitting direction data gating signal.

[0009] In one possible implementation of the first aspect of this application, the debiasing training includes receive direction debiasing training and transmit direction debiasing training, and the training method includes sequentially executing: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing receive direction debiasing training, performing read training, performing transmit direction debiasing training, and performing write training.

[0010] In one possible implementation of the first aspect of this application, the debiasing training includes receive direction debiasing training, and the training method includes sequentially executing: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing receive direction debiasing training, performing read training, and performing write training.

[0011] In one possible implementation of the first aspect of this application, the debiasing training includes transmission direction debiasing training, and the training method includes sequentially executing: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing read training, performing transmission direction debiasing training, and performing write training.

[0012] In one possible implementation of the first aspect of this application, the training method further includes re-performing the debiasing training when the high-bandwidth memory applies a different parallel interface protocol, or when the routing between the high-bandwidth memory physical layer and the high-bandwidth memory device changes, or when the circuit layout of the high-bandwidth memory changes, or when the signal width changes.

[0013] In one possible implementation of the first aspect of this application, the signal width-associated common digital delay chain is used to control the delay of all signals in the plurality of signal groups, and the programmable step size of the digital delay chain of each of the plurality of signal groups is smaller than the fixed step size of the common digital delay chain.

[0014] In one possible implementation of the first aspect of this application, the debiasing training is used to reduce input timing skew and output timing skew between the high-bandwidth memory physical layer and the high-bandwidth memory device.

[0015] In one possible implementation of the first aspect of this application, the method further includes controlling the high-bandwidth memory device to exit the loopback mode after obtaining the data comparison results of each of the plurality of signal groups.

[0016] In one possible implementation of the first aspect of this application, the eye diagram margin associated with the signal width of the parallel interface of the high-bandwidth memory is determined based on the length of the maximum parallel time period between the plurality of signal groups, and the debiasing training is used to increase the eye diagram margin associated with the signal width of the parallel interface of the high-bandwidth memory.

[0017] In one possible implementation of the first aspect of this application, the signal width is 32 bits, and the signals included in the plurality of signal groups include the data strobe signal, the data signal, and the data bus toggle signal.

[0018] Secondly, embodiments of this application also provide a computer device, the computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a method according to any of the above-mentioned implementations.

[0019] Thirdly, embodiments of this application also provide a computer-readable storage medium storing computer instructions that, when executed on a computer device, cause the computer device to perform a method according to any of the above-described implementations.

[0020] Fourthly, embodiments of this application also provide a computer program product, the computer program product including instructions stored on a computer-readable storage medium, which, when executed on a computer device, cause the computer device to perform a method according to any of the above-described aspects. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a high-bandwidth memory provided in an embodiment of this application. The high-bandwidth memory includes a high-bandwidth memory controller, a high-bandwidth memory physical layer, and a high-bandwidth memory device. Figure 2 A schematic diagram of a bias-free training process provided in an embodiment of this application; Figure 3 A schematic diagram of a training method for a high-bandwidth memory according to a first embodiment of this application; Figure 4 A schematic diagram of a training method for a high-bandwidth memory according to a second embodiment of this application; Figure 5 A schematic diagram of a training method for a high-bandwidth memory according to a third embodiment of this application; Figure 6 This application provides a timing diagram of the data gating signal relative to multiple signal groups before debiasing training; Figure 7 This application provides a timing diagram of a data strobe signal relative to multiple signal groups after determining the left boundary of the data strobe signal relative to the signal width. Figure 8 A schematic diagram illustrating the data comparison results of multiple signal groups provided in an embodiment of this application; Figure 9 A timing diagram of a data gating signal relative to multiple signal groups after bias-free training is provided in an embodiment of this application. Figure 10 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0023] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0024] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0025] Figure 1 This is a schematic diagram of a high-bandwidth memory provided in an embodiment of this application. The high-bandwidth memory includes a high-bandwidth memory controller, a high-bandwidth memory physical layer, and a high-bandwidth memory device. Figure 1 As shown, the high-bandwidth memory 101 includes a high-bandwidth memory controller 110, a high-bandwidth memory physical layer 120, and a high-bandwidth memory device 130. The high-bandwidth memory controller 110 is interconnected with the high-bandwidth memory physical layer 120, and the high-bandwidth memory physical layer 120 is interconnected with the high-bandwidth memory device 130. Therefore, even if signal alignment is performed at the physical interface of the high-bandwidth memory physical layer 120, after entering the interior of the high-bandwidth memory physical layer, there may still be deviations between the internal signals due to delay differences during signal transmission, etc.

[0026] Figure 2 This is a schematic diagram of a deskew training process provided in an embodiment of this application. The training method for high-bandwidth memory includes deskew training (deskew) through cooperation between the high-bandwidth memory physical layer and the high-bandwidth memory device, utilizing the loopback mode of the high-bandwidth memory device. Specifically, the deskew training includes the following steps.

[0027] Step S201: Gradually increase the delay of the data strobe signal starting from zero delay, and after each adjustment of the data strobe signal, compare the data based on the sampling results of each of the multiple signal groups until the sampling results of each of the multiple signal groups are correct, thereby determining the left boundary and delay value of the data strobe signal relative to the signal width. The high-bandwidth memory physical layer is used to receive the multiple signal groups, each of the multiple signal groups includes at least one signal, the sum of the data widths of the signals included in each of the multiple signal groups does not exceed the signal width, and the signals included in each of the multiple signal groups satisfy the signal deviation constraint.

[0028] Step S203: Configure the digital delay chain of the data strobe signal using the delay value of the data strobe signal relative to the signal width. Then, through the digital delay chains of the multiple signal groups that are independent of each other, gradually increase the delay of each of the multiple signal groups starting from zero delay, thereby obtaining the data comparison results of the multiple signal groups within the configurable delay range.

[0029] Step S205: Based on the data comparison results of the plurality of signal groups, determine the distance between the left boundary of each of the plurality of signal groups and the left boundary of the data strobe signal relative to the signal width, thereby determining the delay value of each of the plurality of signal groups relative to the signal width.

[0030] Step S207: Configure the digital delay chain of each of the plurality of signal groups using the delay value of each of the plurality of signal groups relative to the signal width, thereby reducing the deviation between the plurality of signal groups.

[0031] Figure 2 The debiasing training illustrated can be used for training high-bandwidth memories. Utilizing the loopback mode of the high-bandwidth memory device, randomly generated reference data, such as pseudo-random binary sequences (PRBS) or other random generation algorithms, can effectively reduce the bias between different signal groups. At the physical interface of the high-bandwidth memory, such as pins, the timing relationship of each signal line can be measured using probes or external instruments to implement various training schemes. However, once the signals enter the physical layer, biases may still exist between different signal groups due to factors such as circuit delay, path differences, and PVT. Although bias constraints can be used to keep the bias within a single signal group within a controllable range, the biases between different signal groups need to be adjusted individually to achieve signal alignment. Furthermore, because the signal groups are divided according to a certain data width (DWORD), such as 32 bits, each signal group may contain a certain number of signals, such as 6 to 8 signals. This means that different signal groups may differ in signal composition and number, making it difficult to predict the deviation between signal groups in advance, thus requiring real-time detection and adjustment.

[0032] to this end, Figure 2The debiasing training shown first determines the left boundary and delay value of the data gating signal relative to the signal width. In step S201, the delay of the data gating signal is gradually increased starting from zero delay. After each adjustment of the data gating signal, data comparison is performed based on the sampling results of multiple signal groups until the sampling results of each of the multiple signal groups are correct, thereby determining the left boundary and delay value of the data gating signal relative to the signal width. The high-bandwidth memory physical layer is used to receive the multiple signal groups, each of which includes at least one signal. The sum of the data widths of the signals included in each of the multiple signal groups does not exceed the signal width, and the signals included in each of the multiple signal groups satisfy the signal deviation constraint. Thus, by repeatedly adjusting the delay of the data gating signal and performing data comparison, until all signal groups have sampled correct data, it means that by adjusting the position of the rising edge of the data gating signal, the left boundary of the data gating signal relative to the signal width is found, and the currently set delay of the data gating signal corresponds to the delay value of the data gating signal relative to the signal width.

[0033] After determining the left boundary and delay value of the data strobe signal relative to the signal width, in step S203, the digital delay chain of the data strobe signal is configured using the delay value of the data strobe signal relative to the signal width. Then, through the independent digital delay chains of the multiple signal groups, the delay of each of the multiple signal groups is gradually increased from zero delay to obtain the data comparison results of each of the multiple signal groups within the configurable delay range. Therefore, the delay value corresponding to the left boundary of the data strobe signal relative to the signal width can be configured into the digital delay chain used to adjust the delay of the data strobe signal, which means that the position of the rising edge of the data strobe signal is adjusted to the left boundary of the corresponding data strobe signal relative to the signal width. Then, by configuring the registers of the digital delay chains of the multiple signal groups, the adjustment of the delay of each of the multiple signal groups and the data comparison are repeatedly performed within the configurable range, thus recording the data comparison results of each signal group under different delays.

[0034] By comparing the data of each signal group under different delays, signal alignment between signal groups can be achieved through analysis. In step S205, based on the data comparison results of each of the multiple signal groups, the distance between the left boundary of each of the multiple signal groups and the left boundary of the data strobe signal relative to the signal width is determined, thereby determining the delay value of each of the multiple signal groups relative to the signal width. Then, in step S207, the digital delay chains of each of the multiple signal groups are configured using the delay values ​​of each of the multiple signal groups relative to the signal width, thereby reducing the deviation between the multiple signal groups.

[0035] Thus, by utilizing the loopback mode of the high-bandwidth memory device, and through the collaboration between the high-bandwidth memory physical layer and the high-bandwidth memory device, test data can be randomly generated and compared using the loopback mode. This allows for the traversal of different delay values ​​of the data gating signal until all signal groups return correct sampling results, thereby determining the left boundary and delay value of the data gating signal relative to the signal width. Then, the digital delay chain of the data gating signal is configured using the delay value of the data gating signal relative to the signal width. This means that the rising edge of the data gating signal aligns with the left boundary or start position of the latest-starting specific signal group among all signal groups. This implies that other signal groups will inevitably begin signal transmission before the rising edge of the data gating signal. Therefore, due to the data gating effect of the data gating signal, subsequent data comparison results will differ.

[0036] Multiple rounds of operation are performed using the independent digital delay chains of each of the multiple signal groups. Starting from zero delay, the delay of each signal group is gradually increased, for example, from 0 to 15, increasing by 1 each round. After each round, the data comparison result of each signal group is recorded; for example, a correct result is recorded as 1, and an incorrect result as 0. This yields the data comparison results for each signal group. Based on these results, it is easy to determine which signal group is the specific signal group mentioned above, that is, the specific signal group that started latest among all the signal groups. This is because after the rising edge of the data strobe signal aligns with the left boundary of the specific signal group (or the start position of the specific signal group), other signal groups will inevitably begin signal transmission before the rising edge of the data strobe signal. Therefore, by gradually increasing the delay of each signal group starting from zero delay, those signal groups that began signal transmission before the rising edge of the data strobe signal will gradually also have their left boundaries aligned with the rising edge of the data strobe signal. Therefore, by recording correct results as 1 and incorrect results as 0, the data comparison results of each of the multiple signal groups are presented as a change from one or more consecutive 0s to consecutive 1s, that is, a change from incorrect sampling to correct sampling. Furthermore, the distance between the left boundary of each of the multiple signal groups and the left boundary of the data strobe signal relative to the signal width can be determined by determining the position of the boundary line from 0 to 1. The farther the boundary line is from the start of the signal group, the further the start of the signal group is from the left boundary of the data strobe signal relative to the signal width, resulting in a greater number of consecutive 0s in the sequence of 0s and 1s. Conversely, the closer the boundary line is to the start of the signal group, the closer the start of the signal group is to the left boundary of the data strobe signal relative to the signal width, resulting in a smaller number of consecutive 0s in the sequence of 0s and 1s.

[0037] Therefore, the signal group with the fewest zeros in the data comparison results of each of the multiple signal groups is the specific signal group mentioned above, that is, the latest starting signal group among all the signal groups. Then, by determining the number of consecutive zeros, the distance between the left boundary of each of the multiple signal groups and the left boundary of the data strobe signal relative to the signal width can be calculated. For example, one extra zero represents an adjustable delay of one digital delay chain, and two extra zeros represent an adjustable delay of two digital delay chains. In this way, the delay value of each of the multiple signal groups relative to the signal width can be determined, and after these delay values ​​are configured into the registers of the digital delay chains of the corresponding signal groups, the left boundaries of each of the multiple signal groups are aligned with the left boundary of the data strobe signal relative to the signal width.

[0038] Furthermore, the high-bandwidth memory divides the signal into multiple signal groups according to the signal width, and the signals included in each of these signal groups satisfy the inter-signal deviation constraint. Therefore, the eye diagram margin is affected by the deviation between the multiple signal groups. The eye diagram margin associated with the signal width of the parallel interface of the high-bandwidth memory is determined based on the length of the maximum parallel time period between the multiple signal groups, that is, the time period from the start of parallel operation of all signal groups to the end of parallel operation of all signal groups. Therefore, by determining the left boundary and delay value of the data gating signal relative to the signal width, and subsequently aligning the left boundaries of each of the multiple signal groups with the left boundary of the data gating signal relative to the signal width, even if different signal groups may differ in signal composition and signal quantity, it is difficult to predict the deviation between signal groups in advance. Through deviation correction training, signal alignment between multiple signal groups is achieved and the rising edge of the data gating signal is matched, which is beneficial to improving the accuracy of data sampling and improving the eye diagram margin.

[0039] It should be noted that by utilizing the loopback mode of the high-bandwidth memory device, and through cooperation between the high-bandwidth memory physical layer and the high-bandwidth memory device, timing information of the signals is not obtained through probes or external instruments. Instead, through optimized hardware and software implementation details, the left boundary and delay value of the data strobe signal relative to the signal width are first determined. Then, the distance between the left boundary of each of the multiple signal groups and the left boundary of the data strobe signal relative to the signal width is determined, thereby determining the delay value of each of the multiple signal groups relative to the signal width. This not only achieves data alignment within the high-bandwidth memory physical layer, reducing deviations between signal groups and controlling the range of deviation variation, but also simplifies the design in terms of hardware implementation and algorithm details, improves eye diagram margin, and is beneficial to improving the performance of the high-bandwidth memory.

[0040] Figure 3 This is a schematic diagram of a training method for a high-bandwidth memory according to a first embodiment of this application. Above. Figure 2 The debiasing training process is illustrated. Training methods for high-bandwidth memories can include a series of training schemes to form a complete training process. Debiasing training can be used to optimize the eye diagram size in either the transmit or receive direction throughout the training process, or it can be used simultaneously to optimize the eye diagram size in both the transmit and receive directions. Figure 3 As shown, the debiasing training includes receive-direction debiasing training and transmit-direction debiasing training. After startup, the training method includes executing the following sequentially: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing receive-direction debiasing training, performing read training, performing transmit-direction debiasing training, and performing write training. Finally, other training can be performed or the process can be terminated as needed.

[0041] Thus, by training to correct bias in the receiving direction, the eye diagram margin in the receiving direction can be improved. The improved eye diagram scan results are then used to adjust the digital delay chain of the receiving direction data gating signal, thereby enhancing the training effect in the receiving direction. Conversely, by training to correct bias in the transmitting direction, the eye diagram margin in the transmitting direction can be improved. The improved eye diagram scan results are then used to adjust the digital delay chain of the transmitting direction data gating signal, thereby enhancing the training effect in the transmitting direction.

[0042] Figure 4 This is a schematic diagram of a training method for a high-bandwidth memory according to a second embodiment of this application. Above. Figure 2The debiasing training process is illustrated. Training methods for high-bandwidth memories can include a series of training schemes to form a complete training process. Debiasing training can be used to optimize the eye diagram size in either the transmit or receive direction throughout the training process, or it can be used simultaneously to optimize the eye diagram size in both the transmit and receive directions. Figure 4 As shown, the bias correction training includes receive direction bias correction training. After startup, the training method includes executing the following sequentially: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing receive direction bias correction training, performing read training, and performing write training. Finally, other training can be performed or the process can be terminated as needed.

[0043] Thus, by training to correct the bias in the receiving direction, the eye diagram margin in the receiving direction can be improved. The improved eye diagram scanning results are then used to adjust the digital delay chain of the receiving direction data gating signal, thereby improving the training effect in the receiving direction.

[0044] Figure 5 This is a schematic diagram of a training method for a high-bandwidth memory according to a third embodiment of this application. Above. Figure 2 The debiasing training process is illustrated. Training methods for high-bandwidth memories can include a series of training schemes to form a complete training process. Debiasing training can be used to optimize the eye diagram size in either the transmit or receive direction throughout the training process, or it can be used simultaneously to optimize the eye diagram size in both the transmit and receive directions. Figure 5 As shown, the deviation correction training includes transmission direction deviation correction training. After startup, the training method includes executing the following sequentially: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing read training, performing transmission direction deviation correction training, and performing write training. Finally, other training can be performed or the process can be terminated as needed.

[0045] Thus, by training to correct the bias in the transmission direction, the eye diagram margin in the transmission direction can be improved. By using the improved eye diagram scan results to adjust the digital delay chain of the transmission direction data gating signal, the training effect in the transmission direction is improved.

[0046] See Figure 1 , Figure 2 , Figure 3 , Figure 4 as well as Figure 5 It can be seen that Figure 2The debiasing training process shown can be used to optimize the eye diagram size in the transmit direction only, or only in the receive direction only, or simultaneously in both directions. If read training or write training is performed directly without debiasing training, the data transmission performance of the parallel interface may be affected by the deviation between signal groups. Therefore, debiasing training can be performed only as described above. Figure 4 The received direction correction training shown can be performed, or, alternatively, only the following can be performed: Figure 5 The transmission direction correction training shown can be performed, or alternatively, it can be performed as follows: Figure 3 The received direction debiasing training and the transmitted direction debiasing training are shown.

[0047] Figure 6 This application provides a timing diagram of the data gating signal relative to multiple signal groups before bias correction training. Taking bias correction training in the receiving direction as an example, the data gating signal is the receiving direction data gating signal. Figure 6 The diagram schematically illustrates the first valid rising edge of the receive direction data strobe signal. Multiple signal groups are schematically represented as TG0, TG1, TG2, TG3, TG4, and TG5. It can be seen that the boxes corresponding to TG0, TG1, TG2, TG3, TG4, and TG5 represent the start and end positions of each signal group in a timing sense. By comparing the position of the first valid rising edge of the receive direction data strobe signal with the start positions of each signal group, it can be seen that, without signal alignment, the length of the maximum parallel time period between these signal groups can be expressed as follows: Figure 6 The middle area defined by the two dashed lines is the margin. Due to the deviation between multiple signal groups, such as the start position of signal group TG2 leading the start position of signal group TG3, and the end position of signal group TG2 also leading the end position of signal group TG3, the eye diagram size is affected.

[0048] Figure 7 This application provides a timing diagram of a data strobe signal relative to multiple signal groups after determining the left boundary of the data strobe signal relative to the signal width, as provided in an embodiment of the present application. (Reference) Figure 2In step S201 of the debiasing training process shown, the delay of the data gating signal is gradually increased starting from zero delay. After each adjustment of the data gating signal, data comparison is performed based on the sampling results of multiple signal groups until the sampling results of each of the multiple signal groups are correct, thereby determining the left boundary of the data gating signal relative to the signal width and the delay value. Thus, after determining the left boundary of the data gating signal relative to the signal width, it means that the rising edge of the data gating signal is aligned with the left boundary of the latest-starting specific signal group among all the signal groups, or the start position of a specific signal group. This means that other signal groups must have started signal transmission before the rising edge of the data gating signal. Because of the data gating function of the data gating signal, it will cause differences in subsequent data comparison results, which is helpful in determining the distance between the left boundaries of each of the multiple signal groups and the left boundary of the data gating signal relative to the signal width. Figure 7 As shown, the latest starting signal group is TG3, and the position of the first valid rising edge of the receive direction data strobe signal is aligned with the left boundary, i.e., the starting position, of the latest starting signal group TG3.

[0049] Figure 8 This is a schematic diagram illustrating the data comparison results of multiple signal groups provided in an embodiment of this application. After determining the left boundary and delay value of the data gating signal relative to the signal width, reference is made to... Figure 2In step S203 of the debiasing training process shown, the digital delay chain of the data gating signal is configured using the delay value of the data gating signal relative to the signal width. Then, through the independent digital delay chains of the multiple signal groups, the delay of each signal group is gradually increased from zero, thereby obtaining the data comparison results of each signal group within the configurable delay range. Therefore, the delay value corresponding to the left boundary of the data gating signal relative to the signal width can be configured into the digital delay chain used to adjust the delay of the data gating signal, meaning that the rising edge position of the data gating signal is adjusted to the left boundary of the corresponding data gating signal relative to the signal width. Then, by configuring the registers of the digital delay chains of the multiple signal groups, the adjustment of the delay of each signal group and data comparison are repeatedly performed within the configurable range, thus recording the data comparison results of each signal group under different delays. Multiple rounds of operation are performed using the independent digital delay chains of each of the multiple signal groups. Starting from zero delay, the delay of each signal group is gradually increased, for example, from 0 to 15, increasing by 1 each round. After each round, the data comparison result of each signal group is recorded; for example, a correct result is recorded as 1, and an incorrect result as 0. This yields the data comparison results for each signal group. Based on these results, it is easy to determine which signal group is the specific signal group mentioned above, that is, the specific signal group that started latest among all the signal groups. This is because after the rising edge of the data strobe signal aligns with the left boundary of the specific signal group (or the start position of the specific signal group), other signal groups will inevitably begin signal transmission before the rising edge of the data strobe signal. Therefore, by gradually increasing the delay of each signal group starting from zero delay, those signal groups that began signal transmission before the rising edge of the data strobe signal will gradually also have their left boundaries aligned with the rising edge of the data strobe signal.

[0050] like Figure 8As shown, multiple signal groups are schematically represented as TG0, TG1, TG2, TG3, TG4, and TG5. Based on the data comparison results of each of these signal groups, it is easy to determine which signal group is the specific signal group mentioned above, that is, the specific signal group that started latest among all the signal groups. This is because after the rising edge of the data strobe signal aligns with the left boundary of the specific signal group (or the start position of the specific signal group), other signal groups will inevitably start signal transmission before the rising edge of the data strobe signal. Therefore, as the delay of each of the multiple signal groups is gradually increased from zero delay, those signal groups that started signal transmission before the rising edge of the data strobe signal will gradually have their left boundaries aligned with the rising edge of the data strobe signal. Therefore, by recording correct results as 1 and incorrect results as 0, the data comparison results of each of the multiple signal groups are presented as changing from one or more consecutive 0s to consecutive 1s, that is, from incorrect sampling to correct sampling. Furthermore, the distance between the left boundary of each of the plurality of signal groups and the left boundary of the data strobe signal relative to the signal width can be determined by determining the position of the dividing line from 0 to 1. The farther the dividing line is from the start of the signal group, the further the start of the signal group is from the left boundary of the data strobe signal relative to the signal width, which results in a greater number of consecutive 0s in the sequence of 0s and 1s. Conversely, the closer the dividing line is to the start of the signal group, the closer the start of the signal group is to the left boundary of the data strobe signal relative to the signal width, which results in a smaller number of consecutive 0s in the sequence of 0s and 1s.

[0051] exist Figure 8 In the example shown, signal group TG3 has one 0, which is the smallest number of 0s among all signal groups. Therefore, it can be easily determined that signal group TG3 is the specific signal group mentioned above, that is, the latest starting specific signal group among all signal groups. Combined with... Figure 6 , Figure 7 as well as Figure 8As can be seen, by utilizing the loopback mode of the high-bandwidth memory device, and through the collaboration between the high-bandwidth memory physical layer and the high-bandwidth memory device, timing information of the signal is not obtained through probes or external instruments. Instead, through optimized hardware and software implementation details, the left boundary and delay value of the data strobe signal relative to the signal width are first determined, and then the data comparison results of each of the multiple signal groups are determined. This helps to quickly determine the distance between the left boundary of each of the multiple signal groups and the left boundary of the data strobe signal relative to the signal width. The signal group with the smallest number of 0s in the data comparison results of the multiple signal groups is the specific signal group mentioned above, that is, the latest starting signal group among all the signal groups. Then, by determining the number of consecutive 0s, the distance between the left boundary of each of the multiple signal groups and the left boundary of the data strobe signal relative to the signal width can be calculated. For example, one extra 0 represents an adjustable delay of one digital delay chain, and two extra 0s represent an adjustable delay of two digital delay chains. Figure 8 In this context, TG3 is the latest starting signal group and has one 0. Signal group TG1 has two 0s, resulting in one extra 0, and signal group TG5 has four 0s, resulting in three extra 0s. The number of these extra 0s, or the number of extra 0s relative to the number of 0s in the latest starting signal group, represents the distance between the starting position of each of these signal groups and the starting position of the latest starting signal group. This also represents the distance between the left boundary of each of the signal groups and the left boundary of the data strobe signal relative to the signal width. Thus, the delay value of each of the signal groups relative to the signal width can be determined. After these delay values ​​are configured into the registers of the digital delay chains of the corresponding signal groups, the left boundaries of each of the signal groups are aligned with the left boundary of the data strobe signal relative to the signal width.

[0052] Figure 9 This application provides a timing diagram of the data gating signal relative to multiple signal groups after bias-free training, as illustrated in an embodiment of the present application. Figure 9 In the above-described debiasing training, the timing relationship of the data gating signal relative to the multiple signal groups TG0, TG1, TG2, TG3, TG4, and TG5 changes. It can be seen that the boxes corresponding to TG0, TG1, TG2, TG3, TG4, and TG5 represent the start and end positions of each signal group in a temporal sense. By comparing the position of the first valid rising edge of the receiving direction data gating signal with the start positions of each signal group, it can be seen that signal alignment is achieved after debiasing training. The length of the maximum parallel time period between the multiple signal groups can be expressed as... Figure 9 The middle region defined by the two dashed lines represents the margin. This is achieved through comparison. Figure 6 and Figure 9 As can be seen, the deviation between multiple signal groups has been significantly reduced. For example, in Figure 2 In the diagram, the start position of signal group TG2 precedes the start position of signal group TG3, and the end position of signal group TG2 also precedes the end position of signal group TG3, thus affecting the eye diagram size. Conversely, in... Figure 9 In this context, the left boundaries, i.e., the starting positions, of all signal groups TG0, TG1, TG2, TG3, TG4, and TG5 are aligned with the first valid rising edge of the receive direction data strobe signal. Therefore, Figure 9 The area defined by the dashed line represents the eye diagram margin, and it should be significantly larger than... Figure 6 The area defined by the dashed line represents the eye diagram margin. This means that by determining the left boundary and delay value of the data gating signal relative to the signal width, and subsequently aligning the left boundaries of each of the multiple signal groups with the left boundary of the data gating signal relative to the signal width, even if different signal groups may differ in signal composition and number, it is difficult to predict the deviation between signal groups in advance. Through deviation correction training, signal alignment between multiple signal groups is achieved and the rising edge of the data gating signal is matched, which helps to improve the accuracy of data sampling and increase the eye diagram margin.

[0053] See Figures 1 to 9 In some embodiments, the debiasing training is used for receiving direction debiasing training, the data gating signal is a receiving direction data gating signal, the high-bandwidth memory physical layer generates reference data, and the high-bandwidth memory physical layer compares the reference data with the sampled data returned by the high-bandwidth memory device to determine whether the sampling results of each of the plurality of signal groups are correct.

[0054] Thus, by training to correct bias in the receiving direction, the eye diagram margin in the receiving direction can be improved. The improved eye diagram scan results are then used to adjust the digital delay chain of the receiving direction data gating signal, thereby enhancing the training effect in the receiving direction. Using the loopback mode of a high-bandwidth memory device, training is performed on receiving direction command operations such as read commands. Reference data, such as PRBS, is generated by the high-bandwidth memory physical layer, but is only generated and not transmitted. The high-bandwidth memory device generates and feeds back sampled data for comparison with the reference data, thereby determining whether the sampling results of each of the multiple signal groups are correct.

[0055] See Figures 1 to 9In some embodiments, the debiasing training is used for transmission direction debiasing training, the data gating signal is a transmission direction data gating signal, the high-bandwidth memory physical layer generates reference data and sends the reference data to the high-bandwidth memory device, the high-bandwidth memory device performs data comparison and sends the data comparison result to the high-bandwidth memory physical layer, and then the high-bandwidth memory physical layer determines whether the sampling results of each of the multiple signal groups are correct based on the data comparison result.

[0056] Thus, training to correct bias in the transmission direction can improve the eye diagram margin of the transmission direction. The improved eye diagram scan results are then used to adjust the digital delay chain of the transmission direction data gating signal, improving the training effect of the transmission direction. Using the loopback mode of the high-bandwidth memory device, training is performed on transmission direction command operations such as write commands. Reference data, such as PRBS, is generated by the high-bandwidth memory physical layer and sent to the high-bandwidth memory device. Feedback is generated by the high-bandwidth memory device, which then performs data comparison and sends the comparison result to the high-bandwidth memory physical layer. Finally, the high-bandwidth memory physical layer performs the subsequent left boundary search.

[0057] See Figures 1 to 9 In some embodiments, the debiasing training includes receiving direction debiasing training and the data gating signal in the receiving direction debiasing training is a receiving direction data gating signal. The debiasing training also includes transmitting direction debiasing training and the data gating signal in the transmitting direction debiasing training is a transmitting direction data gating signal.

[0058] Thus, by training to correct bias in the receiving direction, the eye diagram margin in the receiving direction can be improved. The improved eye diagram scan results are then used to adjust the digital delay chain of the receiving direction data gating signal, thereby enhancing the training effect in the receiving direction. Conversely, by training to correct bias in the transmitting direction, the eye diagram margin in the transmitting direction can be improved. The improved eye diagram scan results are then used to adjust the digital delay chain of the transmitting direction data gating signal, thereby enhancing the training effect in the transmitting direction.

[0059] See Figures 1 to 9 In some embodiments, the debiasing training includes receive direction debiasing training and transmit direction debiasing training. The training method includes performing the following sequentially: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing receive direction debiasing training, performing read training, performing transmit direction debiasing training, and performing write training.

[0060] Thus, by training to correct bias in the receiving direction, the eye diagram margin in the receiving direction can be improved. The improved eye diagram scan results are then used to adjust the digital delay chain of the receiving direction data gating signal, thereby enhancing the training effect in the receiving direction. Conversely, by training to correct bias in the transmitting direction, the eye diagram margin in the transmitting direction can be improved. The improved eye diagram scan results are then used to adjust the digital delay chain of the transmitting direction data gating signal, thereby enhancing the training effect in the transmitting direction.

[0061] See Figures 1 to 9 In some embodiments, the debiasing training includes receive direction debiasing training, and the training method includes performing the following sequentially: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing receive direction debiasing training, performing read training, and performing write training.

[0062] Thus, by training to correct the bias in the receiving direction, the eye diagram margin in the receiving direction can be improved. The improved eye diagram scanning results are then used to adjust the digital delay chain of the receiving direction data gating signal, thereby improving the training effect in the receiving direction.

[0063] See Figures 1 to 9 In some embodiments, the debiasing training includes transmission direction debiasing training, and the training method includes performing the following sequentially: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing read training, performing transmission direction debiasing training, and performing write training.

[0064] Thus, by training to correct the bias in the transmission direction, the eye diagram margin in the transmission direction can be improved. By using the improved eye diagram scan results to adjust the digital delay chain of the transmission direction data gating signal, the training effect in the transmission direction is improved.

[0065] See Figures 1 to 9 In some embodiments, the training method further includes re-performing the debiasing training when the high-bandwidth memory applies a different parallel interface protocol, or when the routing between the high-bandwidth memory physical layer and the high-bandwidth memory device changes, or when the circuit layout of the high-bandwidth memory changes, or when the signal width changes.

[0066] Different protocols, routing methods, and circuit layouts can all lead to variations in the deviation between signal groups. Furthermore, high-bandwidth memories divide signals into multiple groups based on signal width, and the signals within each group satisfy inter-signal deviation constraints. Therefore, the eye diagram margin is affected by the deviation between these signal groups. The eye diagram margin associated with the signal width of the high-bandwidth memory's parallel interface is determined based on the length of the maximum parallel time period between the multiple signal groups—that is, the time period from the start to the end of parallel operation for all signal groups. Therefore, if the signal width changes, for example from 32 bits to 48 bits, re-training to correct the deviation is necessary to align the signals between multiple signal groups and match the rising edge of the data strobe signal, thereby improving data sampling accuracy and eye diagram margin.

[0067] See Figures 1 to 9 In some embodiments, the signal width-associated common digital delay chain is used to control the delay of all signals in the plurality of signal groups, and the programmable step size of the digital delay chain of each of the plurality of signal groups is smaller than the fixed step size of the common digital delay chain.

[0068] Thus, by providing more refined and independently programmable digital delay chains for each of the multiple signal groups, fine-tuning is provided within a configurable range, which is beneficial for compensating for deviations between signal groups.

[0069] See Figures 1 to 9 In some embodiments, the debiasing training is used to reduce input timing skew and output timing skew between the high-bandwidth memory physical layer and the high-bandwidth memory device.

[0070] Thus, by utilizing the loopback mode of the high-bandwidth memory device, and through the cooperation between the high-bandwidth memory physical layer and the high-bandwidth memory device, timing information of the signals is obtained without probes or external instruments. Instead, through optimized hardware and software implementation details, the left boundary and delay value of the data strobe signal relative to the signal width are first determined. Then, the distance between the left boundary of each of the multiple signal groups and the left boundary of the data strobe signal relative to the signal width is determined, thereby determining the delay value of each of the multiple signal groups relative to the signal width. This not only achieves data alignment within the high-bandwidth memory physical layer, reducing deviations between signal groups and controlling the range of deviation variation, but also simplifies the design in terms of hardware implementation and algorithm details, improves eye diagram margin, and is beneficial to improving the performance of the high-bandwidth memory.

[0071] See Figures 1 to 9In some embodiments, the method further includes controlling the high-bandwidth memory device to exit the loopback mode after obtaining the data comparison results of each of the plurality of signal groups.

[0072] In this way, by introducing the loopback mode, system overhead is saved.

[0073] See Figures 1 to 9 In some embodiments, the eye diagram margin associated with the signal width of the parallel interface of the high-bandwidth memory is determined based on the length of the maximum parallel time period between the plurality of signal groups, and the debiasing training is used to increase the eye diagram margin associated with the signal width of the parallel interface of the high-bandwidth memory.

[0074] Thus, comparison Figure 6 and Figure 9 As can be seen, the deviation between multiple signal groups has been significantly reduced. For example, in Figure 2 In the diagram, the start position of signal group TG2 precedes the start position of signal group TG3, and the end position of signal group TG2 also precedes the end position of signal group TG3, thus affecting the eye diagram size. Conversely, in... Figure 9 In this context, the left boundaries, i.e., the starting positions, of all signal groups TG0, TG1, TG2, TG3, TG4, and TG5 are aligned with the first valid rising edge of the receive direction data strobe signal. Therefore, Figure 9 The area defined by the dashed line represents the eye diagram margin, and it should be significantly larger than... Figure 6 The area defined by the dashed line represents the eye diagram margin. This means that by determining the left boundary and delay value of the data gating signal relative to the signal width, and subsequently aligning the left boundaries of each of the multiple signal groups with the left boundary of the data gating signal relative to the signal width, even if different signal groups may differ in signal composition and number, it is difficult to predict the deviation between signal groups in advance. Through deviation correction training, signal alignment between multiple signal groups is achieved and the rising edge of the data gating signal is matched, which helps to improve the accuracy of data sampling and increase the eye diagram margin.

[0075] See Figures 1 to 9 In some embodiments, the signal width is 32 bits, and the signals included in the plurality of signal groups include the data strobe signal, the data signal, and the data bus toggle signal.

[0076] In this way, it is possible to adapt to various signal widths, as well as the composition and quantity of various signals.

[0077] Figure 10This is a schematic diagram of the structure of a computer device 1000 provided in an embodiment of this application. The computer device 1000 includes one or more processors 1010, a communication interface 1020, and a memory 1030. The processors 1010, the communication interface 1020, and the memory 1030 are interconnected via a bus 1040. Optionally, the computer device 1000 may further include an input / output interface 1050, which is connected to input / output devices for receiving user-set parameters, etc. The computer device 1000 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-described embodiments of this application; the processor 1010 can also be used to implement some or all of the operation steps of the method embodiment in the above-described embodiments of this application. For example, the specific implementation of various operations performed by the computer device 1000 can be referred to the specific details in the above embodiments, such as the processor 1010 being used to execute some or all of the steps or operations in the above-described method embodiments. For example, in the embodiments of this application, the computer device 1000 can be used to implement some or all of the functions of one or more components in the above-described device embodiments. In addition, the communication interface 1020 can be used for communication functions necessary to implement the functions of these devices and components, and the processor 1010 can be used for processing functions necessary to implement the functions of these devices and components.

[0078] It should be understood that, Figure 10 The computer device 1000 may include one or more processors 1010, and the multiple processors 1010 may cooperate to provide processing power in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or an arbitrary connection mode; or the multiple processors 1010 may form a processor sequence or a processor array; or the multiple processors 1010 may be divided into a main processor and an auxiliary processor; or the multiple processors 1010 may have different architectures, such as adopting a heterogeneous computing architecture. Furthermore, Figure 10 The structural and functional descriptions of the computer device 1000 shown are exemplary and non-limiting. In some exemplary embodiments, the computer device 1000 may include... Figure 10 The diagram shows more or fewer components, or combinations of some components, or splitting of some components, or different arrangements of components.

[0079] The processor 1010 can have various specific implementations. For example, it may include one or more combinations of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a tensor processing unit (TPU), or a data processing unit (DPU). This application does not impose specific limitations on these embodiments. The processor 1010 can also be a single-core or multi-core processor. The processor 1010 can be a combination of a CPU and hardware chips. These hardware chips can be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The PLDs can be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof. The processor 1010 can also be implemented using logic devices with built-in processing logic, such as FPGAs or digital signal processors (DSPs). The communication interface 1020 can be a wired interface or a wireless interface, used to communicate with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless LAN interface, etc.

[0080] Memory 1030 may be non-volatile memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Memory 1030 may also be volatile memory, which may be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 1030 can also be used to store program code and data, so that the processor 1010 can call the program code stored in the memory 1030 to execute some or all of the operation steps in the above method embodiments, or to execute the corresponding functions in the above device embodiments. Furthermore, the computer device 1000 may include, compared to... Figure 10 The number of components displayed may be more or less, or there may be different component configurations.

[0081] The 1040 bus can be a Peripheral Component Interconnect Express (PCIe) bus, or an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. The 1040 bus can be divided into an address bus, a data bus, and a control bus. In addition to the data bus, the 1040 bus can also include a power bus, a control bus, and a status signal bus. However, for clarity, Figure 10 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0082] The methods and devices provided in this application are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, the embodiments, implementation methods, examples, or methods of implementation of the methods and devices can be referred to each other, and repeated details will not be repeated. This application also provides a system comprising multiple computer devices, the structure of each computer device of which can refer to the structure of the computer devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0083] This application also provides a computer-readable storage medium storing computer instructions. When these computer instructions are executed on a computer device (such as one or more processors), they can implement the method steps described in the above method embodiments. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0084] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this application can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless network communication, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0085] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0086] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A training method for a high-bandwidth memory, characterized in that, The training method includes utilizing the loopback mode of a high-bandwidth memory device to perform bias correction training through cooperation between the high-bandwidth memory physical layer and the high-bandwidth memory device, including: Starting from zero delay, the delay of the data gating signal is gradually increased. After each adjustment of the data gating signal, data comparison is performed based on the sampling results of multiple signal groups until the sampling results of multiple signal groups are all correct. This determines the left boundary and delay value of the data gating signal relative to the signal width. The high-bandwidth memory physical layer is used to receive the multiple signal groups, each of which includes at least one signal. The sum of the data widths of the signals included in each of the multiple signal groups does not exceed the signal width, and the signals included in each of the multiple signal groups satisfy the signal deviation constraint. The digital delay chain of the data strobe signal is configured using the delay value of the data strobe signal relative to the signal width. Then, the delay of each of the multiple signal groups is gradually increased from zero delay through their respective digital delay chains, thereby obtaining the data comparison results of each of the multiple signal groups within the configurable delay range. Based on the data comparison results of each of the multiple signal groups, the distance between the left boundary of each of the multiple signal groups and the left boundary of the data strobe signal relative to the signal width is determined, thereby determining the delay value of each of the multiple signal groups relative to the signal width; The digital delay chains of the multiple signal groups are configured using their respective delay values ​​relative to the signal width, thereby reducing the deviation between the multiple signal groups.

2. The method according to claim 1, characterized in that, The debiasing training is used for receiving direction debiasing training. The data gating signal is the receiving direction data gating signal. The high-bandwidth memory physical layer generates reference data. The high-bandwidth memory physical layer compares the reference data with the sampled data returned by the high-bandwidth memory device to determine whether the sampling results of each of the multiple signal groups are correct.

3. The method according to claim 1, characterized in that, The debiasing training is used for transmission direction debiasing training. The data gating signal is a transmission direction data gating signal. The high-bandwidth memory physical layer generates reference data and sends the reference data to the high-bandwidth memory device. After the high-bandwidth memory device performs data comparison, it sends the data comparison result to the high-bandwidth memory physical layer. Then, the high-bandwidth memory physical layer determines whether the sampling results of each of the multiple signal groups are correct based on the data comparison result.

4. The method according to claim 1, characterized in that, The debiasing training includes receiving direction debiasing training, and the data gating signal in the receiving direction debiasing training is a receiving direction data gating signal. The debiasing training also includes transmitting direction debiasing training, and the data gating signal in the transmitting direction debiasing training is a transmitting direction data gating signal.

5. The method according to claim 1, characterized in that, The debiasing training includes receive direction debiasing training and transmit direction debiasing training. The training method includes performing the following sequentially: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing receive direction debiasing training, performing read training, performing transmit direction debiasing training, and performing write training.

6. The method according to claim 1, characterized in that, The debiasing training includes receive direction debiasing training, and the training method includes sequentially executing: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing receive direction debiasing training, performing read training, and performing write training.

7. The method according to claim 1, characterized in that, The debiasing training includes transmission direction debiasing training, and the training method includes performing the following sequentially: initializing the high-bandwidth memory physical layer, initializing the high-bandwidth memory device, performing command address bus training, performing read gating training, performing read training, performing transmission direction debiasing training, and performing write training.

8. The method according to claim 1, characterized in that, The training method further includes re-performing the debiasing training when the high-bandwidth memory applies a different parallel interface protocol, or when the routing between the high-bandwidth memory physical layer and the high-bandwidth memory device changes, or when the circuit layout of the high-bandwidth memory changes, or when the signal width changes.

9. The method according to claim 1, characterized in that, The shared digital delay chain associated with the signal width is used to control the delay of all signals in the plurality of signal groups, and the programmable step size of the digital delay chain of each of the plurality of signal groups is smaller than the fixed step size of the shared digital delay chain.

10. The method according to claim 1, characterized in that, The debiasing training is used to reduce the input timing deviation and output timing deviation between the high-bandwidth memory physical layer and the high-bandwidth memory device.

11. The method according to claim 1, characterized in that, The method further includes controlling the high-bandwidth memory device to exit the loopback mode after obtaining the data comparison results of each of the plurality of signal groups.

12. The method according to claim 1, characterized in that, The eye diagram margin associated with the signal width of the parallel interface of the high-bandwidth memory is determined based on the length of the maximum parallel time period between the plurality of signal groups, and the debiasing training is used to increase the eye diagram margin associated with the signal width of the parallel interface of the high-bandwidth memory.

13. The method according to claim 1, characterized in that, The signal width is 32 bits, and the signals included in the multiple signal groups include the data strobe signal, the data signal, and the data bus toggle signal.

14. A computer device, characterized in that, The computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method according to any one of claims 1 to 13.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 13.

Images