Programmable logic device configuration method and hardware board card

Abstract

The invention provides a programmable logic device configuration method and a hardware board card, and relates to the technical field of electronic hardware design and logic control. The method is applied to a hardware board card comprising a CPLD and comprises the steps that when the CPLD is powered on and started, configuration information is read from a user flash memory in the CPLD, and the configuration information at least comprises a hardware version identifier and a function configuration identifier; analyzing the read configuration information, and dynamically selecting and starting a specific logic function module matched with the hardware board card from the same set of logic codes solidified in the CPLD based on the hardware version identifier and the function configuration identifier obtained through analysis, therefore, on the hardware logic control level, traditional normal form conversion of'multiple sets of codes and multiple BOMs' is replaced with'one set of codes and multiple configurations', repeated logic code development and testing for hardware board cards with similar functions are effectively reduced, and then related manpower and time cost is remarkably reduced.

Description

Technical Field

[0001] This application relates to the field of electronic hardware design and logic control technology, and in particular to a method for configuring a programmable logic device and a hardware board. Background Technology

[0002] With the rapid development of data centers, cloud computing, and communication networks, core hardware devices such as switches and servers are evolving towards higher integration, more complex functions, and faster iteration speeds. Among these devices, Complex Programmable Logic Devices (CPLDs) are widely used for critical logic functions such as system power-on timing management, signal monitoring, interface expansion, and status indicator control due to their high reliability, flexible reconfigurability, and powerful interface control capabilities. A typical hardware system is usually composed of multiple functionally similar but slightly different printed circuit boards (PCBs). The CPLD on each board needs to perform slightly different logic tasks based on its specific hardware layout and pin definitions.

[0003] In related technologies, a "one-to-one" customized development and configuration model is typically adopted. Specifically, for each PCB board with different hardware configurations or pin definitions, engineers need to write and compile a corresponding set of CPLD logic code, generate a unique binary image file, and burn it into the corresponding board's CPLD. In the production and management stages, each unique set of CPLD code is identified as an independent material, corresponding to an independent bill of materials (BOM) entry. When there are multiple hardware versions or derivative models in the product line, multiple highly similar sets of code and BOMs need to be maintained, forming a discrete configuration management system driven by hardware differences. However, this approach suffers from high development and maintenance costs. Summary of the Invention

[0004] This application provides a method for configuring a programmable logic device and a hardware board to solve the problem of high development and maintenance costs in related technologies.

[0005] In a first aspect, this application provides a method for configuring a programmable logic device, applied to a hardware board containing a CPLD, the method comprising:

[0006] When the CPLD is powered on, configuration information is read from the user flash memory (UFM) inside the CPLD. The configuration information includes at least the hardware version identifier and the function configuration identifier.

[0007] Parse the read configuration information to obtain the hardware version identifier and function configuration identifier;

[0008] Based on the hardware version identifier and function configuration identifier obtained from the parsing, a specific logic function module that matches the hardware board is dynamically selected and enabled from the same set of logic code embedded in the CPLD.

[0009] In one possible implementation, based on the parsed hardware version identifier and function configuration identifier, a specific logical function module matching the hardware board is dynamically selected and enabled from the same set of logic code embedded within the CPLD. This includes: determining a logic code framework compatible with the hardware version identifier based on the hardware version identifier; and dynamically selecting and enabling a specific logical function module matching the hardware board within the compatible logic code framework based on the function configuration identifier.

[0010] In one possible implementation, the configuration information is a multi-bit command word, which includes: a validity identifier field for identifying the validity of the multi-bit command word itself; a hardware version identifier field for indicating the hardware version identifier; and a function configuration identifier field for indicating the function configuration identifier.

[0011] In one possible implementation, the programmable logic device configuration method further includes: determining whether the configuration information is valid based on the validity flag bit field; if the configuration information is determined to be invalid, controlling the CPLD to execute the preset default configuration logic and generating an alarm signal.

[0012] In one possible implementation, dynamically selecting and enabling specific logic function modules includes configuring the functional definition, electrical characteristics, or signal mapping relationship of at least one input / output pin of the CPLD based on a function configuration identifier.

[0013] In one possible implementation, determining a logic code framework compatible with the hardware version identifier based on the hardware version identifier includes comparing the hardware version identifier with a list of compatible versions pre-stored in the CPLD to determine whether a compatible framework exists.

[0014] In one possible implementation, the programmable logic device configuration method further includes: if the comparison result indicates that no compatible framework exists, then controlling the CPLD to execute a preset default configuration logic.

[0015] In one possible implementation, the programmable logic device configuration method further includes: in response to a configuration update instruction received through the communication interface of the CPLD, updating configuration information stored in the user flash memory based on the configuration update instruction.

[0016] In one possible implementation, before updating the configuration information stored in the user flash memory, the programmable logic device configuration method further includes: backing up the current configuration information in the user flash memory to a preset storage area; if the operation of updating the user flash memory according to the configuration update instruction fails, restoring the backed-up configuration information in the preset storage area to the user flash memory.

[0017] Secondly, this application provides a programmable logic device configuration apparatus, applied to a hardware board including a CPLD, the programmable logic device configuration apparatus comprising:

[0018] The configuration information reading module is used to read configuration information from the user flash memory inside the CPLD when the CPLD is powered on and started. The configuration information includes at least the hardware version identifier and the function configuration identifier.

[0019] The parsing module is used to parse the read configuration information to obtain the hardware version identifier and function configuration identifier;

[0020] The logic selection module is used to dynamically select and enable a specific logic function module that matches the hardware board from the same set of logic code embedded in the CPLD, based on the parsed hardware version identifier and function configuration identifier.

[0021] Thirdly, this application provides a hardware board including a CPLD configured to perform the methods described in any of the first aspects.

[0022] Fourthly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0023] Memory is used to store instructions executed by the computer;

[0024] A processor for executing computer-executable instructions stored in memory to implement any of the methods of the first aspect.

[0025] Fifthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed, are used to implement the method of any one of the first aspects.

[0026] Sixthly, this application provides a computer program product, including a computer program that, when executed, implements the method of any one of the first aspects.

[0027] The programmable logic device configuration method and hardware board provided in this application are applied to a hardware board containing a CPLD. The method includes: when the CPLD is powered on, reading configuration information from the user flash memory inside the CPLD, the configuration information including at least a hardware version identifier and a function configuration identifier; parsing the read configuration information to obtain the hardware version identifier and the function configuration identifier; and dynamically selecting and enabling a specific logic function module matching the hardware board from the same set of logic code embedded inside the CPLD based on the parsed hardware version identifier and function configuration identifier.

[0028] In this process, by reading and parsing the hardware version identifier and function configuration identifier pre-set in the user flash memory of the CPLD when it is powered on, and dynamically selecting and enabling the corresponding specific function modules from the same set of fixed logic code based on the hardware version identifier and function configuration identifier, a paradigm shift is achieved at the hardware logic control level, replacing the traditional "multiple sets of code, multiple BOMs" with "one set of code, multiple configurations". This effectively reduces the repetitive logic code development and testing for hardware boards with similar functions, thereby significantly reducing the related manpower and time costs. In addition, by transforming the "configuration information" required to distinguish hardware into software-definable data stored inside the CPLD, the BOM level is unified and simplified, allowing hardware boards with different configurations to share the same BOM in the production process. This fundamentally reduces the large-scale production errors caused by numerous BOM versions and incorrect selection, and significantly reduces the risk of returns for repair. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0030] Figure 1 A flowchart illustrating a programmable logic device configuration method provided as an exemplary embodiment of this application;

[0031] Figure 2 Another schematic flowchart illustrating a programmable logic device configuration method provided for an exemplary embodiment of this application;

[0032] Figure 3 A schematic diagram of a programmable logic device configuration apparatus provided as an exemplary embodiment of this application;

[0033] Figure 4 A schematic diagram of the structure of a hardware board provided for an exemplary embodiment of this application;

[0034] Figure 5 A schematic diagram of the structure of an electronic device provided as an exemplary embodiment of this application.

[0035] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0037] The terms “first,” “second,” etc., used in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, products, or apparatus.

[0038] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with relevant laws, regulations and standards, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0039] In related technologies, when adopting a "one-to-one" customized development and configuration model, for logical requirements with more than 90% functional similarity, almost repetitive design, coding, simulation, and board-level testing are still required, resulting in a significant waste of human resources and project time. Secondly, numerous BOM entries with similar names are prone to confusion or entry errors during procurement, production assembly, and material picking, leading to a surge in BOM management complexity and low fault tolerance. Once incorrect CPLD code is burned onto an incompatible hardware board, it will directly cause the entire machine to malfunction and make on-site maintenance and recovery difficult. Such failures caused by BOM mismatch cannot be repaired through remote software updates in the traditional model. Usually, the equipment must be returned to the factory for hardware replacement or re-burning, resulting in high rework costs, long maintenance cycles, and poor customer experience.

[0040] To address the aforementioned issues, this application provides a programmable logic device (PLD) configuration scheme. This scheme pre-integrates all the functions required by the CPLD into a unified set of logic code and embeds it within the chip. Simultaneously, a hardware version identifier (for identifying the hardware board type) and a function configuration identifier (for selecting specific functions) are stored as programmable configuration information in the CPLD's non-volatile user flash memory. When the CPLD powers on, it reads and parses this internally stored configuration information. Based on the parsing results, it dynamically selects, combines, and activates specific logic function modules that precisely match the current hardware board from the same set of embedded logic code resources. This transforms the management of hardware differences from a "hard-binding" model relying on multiple independent firmware and BOM entries. Based on a unified hardware platform and using software-configurable data for "soft adaptation," the hardware logic control layer has achieved a paradigm shift from the traditional "multiple sets of code, multiple BOMs" to "one set of code, multiple configurations." This effectively reduces the repetitive logic code development and testing for functionally similar hardware boards, thereby significantly reducing related manpower and time costs. In addition, by transforming the "configuration information" required to differentiate hardware into software-defined data stored within the CPLD, the BOM level has been unified and simplified. This allows hardware boards with different configurations to share the same BOM during the production process, thereby fundamentally reducing mass production errors caused by numerous BOM versions and incorrect selections, and significantly reducing the risk of returns for repairs.

[0041] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0042] Figure 1This is a flowchart illustrating a programmable logic device configuration method provided in an exemplary embodiment of this application. The programmable logic device configuration method provided in this embodiment is applied to a hardware board including a CPLD. Figure 1 As shown, the programmable logic device configuration method includes the following steps:

[0043] S101. When the CPLD is powered on, read the configuration information from the user flash memory inside the CPLD. The configuration information includes at least the hardware version identifier and the function configuration identifier.

[0044] Among them, CPLD is an integrated circuit that can be programmed and configured by users according to their own needs. It has the characteristics of high flexibility and good integration and is often used to implement various digital logic functions. User flash memory refers to a non-volatile memory integrated inside the CPLD, which is used to store user-defined data and configuration information. Even if the CPLD is powered off, the data in it will not be lost.

[0045] For example, taking a CPLD application in the field of industrial control as an example, when the device containing the CPLD is powered on, the CPLD starts up. During the startup process, the internal hardware circuit of the CPLD sends read commands to its internal user flash memory according to a preset process. After receiving the commands, the user flash memory transmits the configuration information stored therein to the CPLD's control unit through the internal data bus. This configuration information is pre-written into the user flash memory using a specific programming tool. It explicitly includes hardware version identifiers, such as using specific binary codes to indicate whether the hardware board is a first-generation, second-generation, or other different versions. It also includes functional configuration identifiers, such as using different codes to indicate whether the hardware board has specific communication functions, data processing functions, etc.

[0046] S102. Parse the read configuration information to obtain the hardware version identifier and function configuration identifier.

[0047] Here, parsing refers to identifying, converting, and extracting the raw configuration information read from the user's flash memory, transforming it into data in a specific format that the CPLD can understand and process, thereby obtaining the hardware version identifier and function configuration identifier contained therein.

[0048] For example, after the CPLD's control unit receives the configuration information transmitted from the user's flash memory, it activates its internal parsing module. This parsing module processes the configuration information according to pre-set rules and algorithms. For instance, for the hardware version identifier, the parsing module converts the binary code into the corresponding hardware version number according to specific encoding rules, such as identifying "0001" as the first-generation hardware version. For the function configuration identifier, the parsing module checks the code bit by bit, determining the various functions of the hardware board based on the meaning of each bit; for example, a bit of "1" indicates the presence of a specific encryption function, while "0" indicates the absence of one. Through this parsing process, the CPLD successfully obtains the hardware version identifier and the function configuration identifier.

[0049] S103. Based on the hardware version identifier and function configuration identifier obtained from the parsing, dynamically select and enable a specific logic function module that matches the hardware board from the same set of logic code embedded in the CPLD.

[0050] Dynamic selection refers to the CPLD flexibly deciding which logic function modules to enable during operation based on the real-time acquired hardware version identifier and function configuration identifier, rather than using a fixed set of function modules. Logic function modules are different parts of the CPLD's internal logic code divided according to function. Each module implements a specific digital logic function, such as data buffering, signal encoding and decoding, and logic operations.

[0051] For example, after obtaining the hardware version identifier and function configuration identifier, the CPLD's internal logic selection module begins operation. For instance, if the parsed hardware version identifier indicates that the hardware board is a newer version with higher processing speed and more interfaces, the logic selection module will select a code framework adapted to the new hardware version from the fixed logic code based on this information. This framework may contain more efficient data processing algorithms and more interface control logic. Simultaneously, based on the function configuration identifier, if the identifier indicates that the hardware board requires specific communication protocol processing capabilities, the logic selection module will find and activate the logic function module responsible for processing that communication protocol within the determined code framework, such as an Ethernet communication module or a serial communication module. In this way, the CPLD can dynamically activate the most suitable logic function module according to the actual situation of the hardware board, achieving precise matching between hardware and software, thereby significantly improving the overall performance and flexibility of the system.

[0052] The programmable logic device configuration method provided in this application reads and parses the hardware version identifier and function configuration identifier pre-set in the user flash memory of the CPLD when it is powered on. Based on the hardware version identifier and function configuration identifier, it dynamically selects and enables the corresponding specific function module from the same set of fixed logic code. This realizes a paradigm shift at the hardware logic control level, replacing the traditional "multiple sets of code, multiple BOMs" with "one set of code, multiple configurations". This effectively reduces the repetitive logic code development and testing for hardware boards with similar functions, thereby significantly reducing the related manpower and time costs. In addition, by transforming the "configuration information" required to distinguish hardware into software-definable data stored inside the CPLD, it achieves the unification and simplification of the BOM level. This allows hardware boards with different configurations to share the same BOM in the production process, thereby fundamentally reducing the large-scale production errors caused by numerous BOM versions and incorrect selection, and significantly reducing the risk of return for repair.

[0053] In some embodiments, based on the parsed hardware version identifier and function configuration identifier, a specific logical function module matching the hardware board is dynamically selected and enabled from the same set of logic code embedded in the CPLD. This includes: determining a logic code framework compatible with the hardware version identifier based on the hardware version identifier; and dynamically selecting and enabling a specific logical function module matching the hardware board within the compatible logic code framework based on the function configuration identifier.

[0054] For example, in actual hardware system development and application, taking a hardware board in a communication device as an example, during the device startup initialization phase, the system first reads and parses the hardware version identifier and function configuration identifier from a specific storage area on the hardware board. The CPLD has a pre-installed set of logic code, which has the potential to implement multiple logic function modules. Based on the read hardware version identifier, the system first performs matching analysis in the CPLD's logic code to determine a logic code framework compatible with the hardware version identifier. For example, if the hardware version identifier indicates a new model hardware board, then a code framework containing more high-speed interface processing logic is selected. Then, based on the read function configuration identifier, within the determined compatible logic code framework, the system further dynamically selects and enables specific logic function modules that match the actual functional requirements of the hardware board. For example, if the function configuration identifier indicates that the hardware board needs specific encryption and decryption functions, then the corresponding encryption and decryption logic function module is enabled from the code framework, thereby achieving precise adaptation between the hardware board and the logic functions.

[0055] In some embodiments, the configuration information is a multi-bit command word, which includes: a validity identifier field for identifying the validity of the multi-bit command word itself; a hardware version identifier field for indicating the hardware version identifier; and a function configuration identifier field for indicating the function configuration identifier.

[0056] For example, Table 1 provides an example of a multi-bit command word provided in an exemplary embodiment of this application.

[0057]

[0058] As shown in Table 1, for 8-bit data, the first bit is used to identify the validity of the multi-bit command word itself. When this bit is set to a specific value (e.g., "1"), it indicates that the multi-bit command word is valid, and the CPLD can perform corresponding operations based on the subsequent bit field information. If it is set to other values ​​(e.g., "0"), it indicates that the multi-bit command word is invalid and will be ignored in subsequent processing to reduce system anomalies caused by error information. The second to fourth bits are used to identify the hardware version. These three bits represent different hardware versions through different binary combinations. For example, "000" can represent the first-generation hardware version, "001" can represent the second-generation hardware version, and so on. Different hardware versions may have differences in hardware design, interface type, performance parameters, etc. Through this bit field identification, the current hardware version can be accurately identified, providing a basis for subsequent selection of the appropriate logic function module. The last four bits are used to define the functional configuration of the hardware in detail. Each bit can correspond to a specific function option. For example, setting the third bit to "1" indicates that it has high-speed communication function, and setting it to "0" indicates that it does not; the second bit can control whether to enable encryption function, etc. With this flexible bit setting method, users can personalize the hardware functions according to actual application scenarios and needs, and realize the flexible application of a single code on CPLDs with different functional requirements.

[0059] Accordingly, referring to the detailed definition of multi-bit command words in Table 1, users can flexibly modify the value of the hardware version identifier field according to their actual needs to adapt to different hardware versions; at the same time, by adjusting the value of the function configuration identifier field, the required functions of the hardware can also be flexibly configured. Correspondingly, upon receiving the multi-bit command word, the hardware version information and function configuration information can be accurately parsed, and then the specific logical function module matching the current hardware board can be dynamically selected and activated from the same internally fixed set of logic code, significantly improving the system's versatility and flexibility, and further reducing development costs and maintenance difficulty.

[0060] It should be noted that the 8-bit command word shown in Table 1 above is merely an example, intended to clearly illustrate the basic structure and functional division logic of multi-bit command words. In practical applications, multi-bit command words offer extremely high flexibility and scalability. The number of bits is not fixed at 8; it can be flexibly adjusted based on factors such as the complexity of the specific hardware system, functional requirements, and the precision requirements of information transmission. For example, it can also be 16-bit, 32-bit, or even more bits. The allocation and functional definition of each bit can be replanned and customized according to actual needs to better adapt to diverse hardware designs and functional configurations, meeting the personalized needs of different industries and application fields for hardware control and functional implementation.

[0061] Based on the above embodiments, in some embodiments, the programmable logic device configuration method further includes: determining whether the configuration information is valid based on the validity flag bit field; if the configuration information is determined to be invalid, controlling the CPLD to execute the preset default configuration logic and generating an alarm signal.

[0062] For example, Table 2 provides examples of functional configurations corresponding to different multi-bit command words provided in the exemplary embodiments of this application.

[0063]

[0064] As shown in Table 2, when the highest bit is defined as "1", the 8-bit command word is considered valid data, and the hardware will be configured accordingly based on the subsequent bit information. Conversely, when the highest bit is "0", the 8-bit command word is considered invalid data. For example, if the received 8-bit command word is "0_101_0101", since its highest bit is "0", it is considered invalid configuration information. In this case, the CPLD will automatically execute the preset default configuration logic. This default configuration logic is a pre-set basic configuration scheme that ensures the hardware can still operate in a basic and stable state even without valid configuration information. Simultaneously, an alarm signal is generated. This alarm signal can be connected to the corresponding indicator light via hardware circuitry or sent to the host computer software to remind the user that there is a problem with the current configuration information and that valid configuration information needs to be re-entered, thereby ensuring the normal operation of the hardware system and the accuracy of the configuration.

[0065] In some embodiments, dynamically selecting and enabling specific logic function modules includes configuring the functional definition, electrical characteristics, or signal mapping relationship of at least one input / output pin of the CPLD based on a function configuration identifier.

[0066] For example, referring to the example in Table 2, when a valid 8-bit command word is received, a specific logic function module will be dynamically selected and enabled based on the value of the function configuration identifier field (i.e., bits [3:0]), including the configuration of the CPLD input / output pins. For example, when the received 8-bit command word is "1_000_0001", since the value of the [3:0]th bit is "0001", according to the preset rules, "0001" means that the CPLD needs to add some pin functions or modify some pin functions according to the board configuration corresponding to "0001" on the basis of the default configuration. Specifically, assuming that under the default configuration, a certain input pin of the CPLD is only used to receive ordinary digital signals, while under the "0001" configuration, the function definition of the input pin is modified to receive signals of a specific encoding format, and its electrical characteristics may also be adjusted accordingly, such as setting the input impedance to a specific value to better match the signal source; for the output pin, it may originally only output simple high and low level signals, but under the "0001" configuration, its signal mapping relationship may be changed so that it outputs signals related to the calculation results of a specific algorithm, so as to realize the added function, such as the specific communication protocol encoding output function. Accordingly, when the received 8-bit command word is "1_000_0010", bits [3:0] are "0010". Based on the board configuration corresponding to "0010", the relevant pins of the CPLD will be configured with different functions, electrical characteristics, or signal mapping relationships. For example, a pin originally used for data transmission can be changed to an enable pin for controlling external devices under the "0010" configuration, while its driving capability and other electrical characteristics are adjusted to meet different functional requirements. In this way, the input / output pins of the CPLD can be flexibly configured in all aspects according to the function configuration identifier, thereby achieving the goal of adapting to different hardware boards and functional requirements.

[0067] In this embodiment, by finely configuring the functional definitions, electrical characteristics, or signal mapping relationships of one or more input / output pins of the CPLD according to the functional configuration identifier, a high degree of flexible decoupling and dynamic reconfiguration of hardware logic and physical interface is achieved. This allows the same CPLD to adapt to the interface requirements of different hardware boards through software configuration without changing the hardware design and external interconnections. This not only effectively simplifies the complexity of hardware design and reduces the need to design multiple PCB versions for different interface requirements, but also significantly improves the reusability and maintainability of the hardware. Product line expansion and field function upgrades can be achieved through configuration updates without hardware modifications, thereby greatly reducing development costs and shortening the product iteration cycle.

[0068] In some embodiments, determining a logic code framework compatible with the hardware version identifier based on the hardware version identifier includes comparing the hardware version identifier with a list of compatible versions pre-stored in the CPLD to determine whether a compatible framework exists.

[0069] For example, a compatible version list is pre-stored within the CPLD. This list exists in the form of a specific data structure, such as an array or a linked list. This compatible version list records in detail the hardware version identifiers compatible with the current CPLD logic code. Taking the multi-bit command word structure defined in Table 1 as an example, the hardware version identifier field is bits [6:4]. Different combinations of these 3 binary bits represent different hardware versions. Accordingly, in this compatible version list, the 3 binary values ​​corresponding to all compatible hardware versions are stored sequentially. For example, assuming the initial hardware version identifier is "000", and subsequent upgraded version identifiers are "001" and "010", etc., if the current CPLD logic code is compatible with the initial version and version "001", then the compatible version list stores the binary values ​​"000" and "001". Correspondingly, assuming that when the CPLD is powered on and started, the configuration information read from the user flash memory inside the CPLD is "1_001_0101", and the value of its [6:4]th bit is "001", which is the current hardware version identifier.

[0070] Furthermore, the parsed hardware version identifier "001" is compared with a pre-stored list of compatible versions. This comparison can be achieved by traversing each element in the list. Specifically, starting from the first element of the list, each element is compared sequentially with the parsed hardware version identifier "001". If a match is found, such as in the example above where "001" is stored in the list, it means that the parsed hardware version identifier "001" is compatible with the CPLD's internal logic code framework. Then, according to preset rules, the logic code framework corresponding to the hardware version can be selected for subsequent operations, such as configuring input / output pins or executing specific functional logic.

[0071] In this embodiment, a hardware compatibility pre-verification mechanism is established by comparing the hardware version identifier with the list of compatible versions pre-stored in the CPLD. This effectively ensures that the CPLD activates the corresponding function only on hardware platforms explicitly supported by its logic code. This reduces the risk of logical errors, electrical conflicts, or system instability caused by code-hardware incompatibility from the source, effectively improving the robustness and security of the system. At the same time, it provides a clear software compatibility boundary for the iteration and management of hardware versions in the product line, simplifying the unified maintenance and technical support of multiple hardware versions.

[0072] In some embodiments, the programmable logic device configuration method further includes: if the comparison result shows that there is no compatible framework, then controlling the CPLD to execute a preset default configuration logic.

[0073] Correspondingly, if after traversing the entire compatible version list, no element matching the parsed hardware version identifier is found, for example, if the parsed hardware version identifier is "011", but the compatible version list only contains "000" and "001", it indicates that the current hardware version identifier is incompatible with the pre-stored logic code framework inside the CPLD. In this case, the CPLD is controlled to execute the preset default configuration logic, and at the same time, the CPLD is controlled to take corresponding error handling measures, such as generating an error prompt signal, connecting it to an indicator light through a hardware circuit for flashing, or sending the error information to the host computer software, to remind the user that the current hardware version is incompatible with the CPLD logic code and that compatible hardware needs to be replaced or the CPLD logic code needs to be updated to ensure the normal operation of the system.

[0074] In this embodiment, when the hardware version identifier fails to match the pre-stored compatibility list, it can automatically revert to the preset default configuration logic. This fault-tolerance mechanism effectively ensures the system's basic operational capabilities and security status in unknown or incompatible hardware environments, effectively reducing the spread of system lock-up, hardware damage, or functional abnormalities caused by configuration errors. Simultaneously, this mechanism provides a safety baseline for production debugging, equipment compatibility testing, and unexpected hardware replacement in the field, significantly improving the product's robustness, maintainability, and user experience.

[0075] In some embodiments, the programmable logic device configuration method further includes: in response to a configuration update instruction received through the communication interface of the CPLD, updating the configuration information stored in the user flash memory based on the configuration update instruction.

[0076] For example, the CPLD receives configuration update instructions from an external management unit (such as the system main processor or remote management controller) through its integrated communication interface, such as a Universal Asynchronous Receiver / Transmitter (UART) or an Inter-Integrated Circuit (I2C). These instructions contain new configuration data and the target write address. After parsing and verifying the instruction format and integrity, the CPLD's internal state machine initiates a flash programming sequence. Specifically, it performs an erase operation on the target address range of the user's flash memory, and then writes the new configuration data in byte or page mode. After the update is complete, an optional read-back check is performed to ensure data consistency. Correspondingly, when the CPLD undergoes its next power-on reset or receives a software-triggered reconfiguration command, it reads the updated configuration information and dynamically reconstructs the logical functions accordingly, thereby achieving remote, online updates of system functions.

[0077] This application embodiment achieves remote, online, and non-intrusive reconfiguration of hardware logic functions by updating configuration information in the CPLD's internal user flash memory in response to external commands. This allows for functional upgrades, problem fixing, or configuration adaptation without physical contact or hardware replacement after product deployment, significantly reducing the cost, time, and complexity of on-site maintenance and upgrades. Simultaneously, it provides the product with robust full lifecycle maintainability and rapid market response capabilities, flexibly addressing changes in demand, hardware compatibility adjustments, or potential defect repairs, significantly enhancing the product's market competitiveness and user satisfaction.

[0078] In some embodiments, before updating the configuration information stored in the user flash memory, the programmable logic device configuration method further includes: backing up the current configuration information in the user flash memory to a preset storage area; if the operation of updating the user flash memory according to the configuration update instruction fails, restoring the backed-up configuration information in the preset storage area to the user flash memory.

[0079] For example, to ensure the security and reliability of the configuration update process, before performing a write operation on the user's flash memory according to the configuration update instruction, the complete configuration information currently stored in the user's flash memory is read and backed up to a reserved, non-volatile, preset storage area (e.g., another independent physical sector within the user's flash memory). Afterward, the system performs a regular erase and programmable procedure to attempt to update the configuration. If the update process fails due to unexpected power outages, communication interruptions, or data verification errors, a recovery process will be automatically triggered upon detecting the failure or upon discovering an invalid configuration during a subsequent power-on self-test: the previously backed-up configuration information will be read from the preset storage area and written back completely to the original storage area of ​​the user's flash memory. This backup mechanism ensures that even in the event of an update failure, the system can revert to a known valid configuration version, guaranteeing the basic functional availability of the device and effectively reducing the risk of functional loss due to configuration corruption.

[0080] Figure 2 Another schematic flowchart illustrating a programmable logic device configuration method provided for an exemplary embodiment of this application. For example... Figure 2 As shown, the programmable logic device configuration method includes the following steps:

[0081] S201. When the CPLD is powered on and started, read the configuration information from the user flash memory inside the CPLD.

[0082] S202. Parse the read configuration information to obtain the validity identifier, hardware version identifier, and function configuration identifier.

[0083] S203. Determine whether the read configuration information is valid based on the validity identifier.

[0084] For example, as shown in Table 1, for 8-bit data, the first bit is set to identify the validity of the multi-bit command word itself. When the bit is set to a specific value (e.g., "1"), it indicates that the multi-bit command word is valid, and the CPLD can perform corresponding operations based on the subsequent bit field information; if it is set to other values ​​(e.g., "0"), it indicates that the multi-bit command word is invalid.

[0085] If so, execute S204;

[0086] If not, proceed with S207.

[0087] S204. Based on the hardware version identifier, determine the logical code framework that is compatible with the hardware version identifier.

[0088] S205. Based on the function configuration identifier, select the specific logic function module that matches the hardware board within the compatible logic code framework.

[0089] S206. Enable the selected specific logical function module.

[0090] S207. Control the CPLD to execute the preset default configuration logic and generate alarm signals.

[0091] For example, the CPLD is automatically controlled to execute a preset default configuration logic. This default configuration logic is a pre-defined basic configuration scheme that ensures the hardware can still operate in a basic and stable state even without valid configuration information. Simultaneously, an alarm signal is generated. This alarm signal can be connected to a corresponding indicator light via hardware circuitry or sent to the host computer software to remind the user that there is a problem with the current configuration information and that valid configuration information needs to be re-entered, thereby ensuring the normal operation of the hardware system and the accuracy of the configuration.

[0092] In summary, this application has at least the following advantages:

[0093] First, by pre-storing identification information containing hardware version and functional configuration in the user flash memory inside the CPLD, and dynamically selecting and enabling specific functional modules in the solidified logic code upon power-up, the innovation of "one set of code, multiple configurations" is achieved. At the hardware logic level, the management of hardware differences is transformed from the traditional, BOM-bound multiple independent firmware mode to a software programmable configuration mode based on a unified hardware platform. This achieves CPLD firmware compatibility under different hardware configurations, thereby eliminating the repetitive logic code development, compilation, and burning work for functionally similar hardware boards from the root. This significantly reduces the cost of repetitive development and testing, and reserves valuable buffer time for the overall design, verification, and production process of hardware projects, significantly accelerating the product's progress from design to mass production.

[0094] Second, by transforming key hardware information from physical BOM entries into software-configurable data stored within the CPLD, a high degree of uniformity and simplification at the BOM level is achieved. This allows boards with different configurations to share the same CPLD material code and basic BOM, effectively reducing the risks of incorrect material procurement and incorrect chip placement caused by numerous BOM versions and similar entries, and significantly improving the operational efficiency of the supply chain and the first-pass yield.

[0095] Third, the solution proposed in this application also significantly enhances the maintainability, adaptability, and lifecycle value of the product. On the one hand, configuration information can be remotely updated via a communication interface, allowing on-site problem repair, function upgrades, or compatibility adjustments to be completed solely through software updates without requiring hardware return to the factory, thus reducing related maintenance costs and downtime by several times. On the other hand, this architecture possesses excellent versatility and scalability, enabling it to flexibly adapt to future hardware version iterations and the introduction of new features.

[0096] Figure 3This is a schematic diagram of a programmable logic device configuration apparatus provided as an exemplary embodiment of this application. The programmable logic device configuration apparatus provided in this embodiment is applied to a hardware board containing a CPLD. Figure 3 As shown, the programmable logic device configuration device 30 includes a configuration information reading module 31, a parsing module 32, and a logic selection module 33, wherein:

[0097] The configuration information reading module 31 is used to read configuration information from the user flash memory inside the CPLD when the CPLD is powered on and started. The configuration information includes at least the hardware version identifier and the function configuration identifier.

[0098] Parsing module 32 is used to parse the read configuration information to obtain the hardware version identifier and function configuration identifier;

[0099] The logic selection module 33 is used to dynamically select and enable a specific logic function module that matches the hardware board from the same set of logic code embedded in the CPLD, based on the parsed hardware version identifier and function configuration identifier.

[0100] In one possible implementation, the logic selection module 33 can be specifically used to: determine a logic code framework compatible with the hardware version identifier based on the hardware version identifier; and dynamically select and enable a specific logic function module that matches the hardware board within the compatible logic code framework according to the function configuration identifier.

[0101] In one possible implementation, the configuration information is a multi-bit command word, which includes: a validity identifier field for identifying the validity of the multi-bit command word itself; a hardware version identifier field for indicating the hardware version identifier; and a function configuration identifier field for indicating the function configuration identifier.

[0102] In one possible implementation, the logic selection module 33 can also be used to: determine whether the configuration information is valid based on the validity flag bit field; if the configuration information is determined to be invalid, control the CPLD to execute the preset default configuration logic and generate an alarm signal.

[0103] In one possible implementation, the logic selection module 33 can also be used to configure the functional definition, electrical characteristics, or signal mapping relationship of at least one input / output pin of the CPLD according to the function configuration identifier.

[0104] In one possible implementation, the logic selection module 33 can also be used to compare the hardware version identifier with a list of compatible versions pre-stored in the CPLD to determine whether a compatible framework exists.

[0105] In one possible implementation, the logic selection module 33 can also be used to: control the CPLD to execute preset default configuration logic when the comparison result indicates that no compatible framework exists.

[0106] In one possible implementation, the programmable logic device configuration method further includes: in response to a configuration update instruction received through the communication interface of the CPLD, updating the configuration information stored in the user flash memory based on the configuration update instruction.

[0107] In one possible implementation, before updating the configuration information stored in the user flash memory, the logic selection module 33 can also be used to: back up the current configuration information in the user flash memory to a preset storage area; if the operation of updating the user flash memory according to the configuration update instruction fails, restore the configuration information backed up in the preset storage area to the user flash memory.

[0108] The programmable logic device configuration apparatus provided in this application embodiment can execute the technical solution shown in the above-described programmable logic device configuration method embodiment. Its implementation principle and beneficial effects are similar, and will not be repeated here.

[0109] It should be noted that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. For example, the logic selection module can be a separate processing element, or it can be integrated into a chip in the above device. Alternatively, it can be stored as program code in the memory of the above device, and its function can be called and executed by a processing element. The implementation of other modules is similar. Moreover, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0110] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more Digital Signal Processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a System-On-a-Chip (SOC).

[0111] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., Digital Video Discs, DVDs), or semiconductor media (e.g., solid-state disks (SSDs)).

[0112] Figure 4 A schematic diagram of the structure of a hardware board provided for an exemplary embodiment of this application. (See diagram below.) Figure 4As shown, the hardware board 40 includes a CPLD 41, which is configured to perform the method as described in any of the above embodiments.

[0113] Figure 5 A schematic diagram of the structure of an electronic device provided as an exemplary embodiment of this application. For example... Figure 5 As shown, the electronic device 50 in this embodiment includes:

[0114] At least one processor 51; and a memory 52 communicatively connected to the at least one processor;

[0115] The memory 52 stores instructions that can be executed by at least one processor 51 to cause the electronic device to perform the method as described in any of the above embodiments.

[0116] Alternatively, the memory 52 can be either standalone or integrated with the processor 51.

[0117] The memory 52 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device.

[0118] The processor 51 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. Specifically, when implementing the programmable logic device configuration method described in the foregoing method embodiments, the electronic device may be, for example, an electronic device with processing capabilities such as a server.

[0119] Optionally, the electronic device may also include a communication interface 53. In specific implementations, if the communication interface 53, memory 52, and processor 51 are implemented independently, they can be interconnected via a bus to complete communication. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not imply that there is only one bus or one type of bus.

[0120] Optionally, in a specific implementation, if the communication interface 53, memory 52 and processor 51 are integrated on a single chip, then the communication interface 53, memory 52 and processor 51 can communicate through an internal interface.

[0121] The implementation principle and technical effects of the electronic device provided in this embodiment can be found in the foregoing embodiments, and will not be repeated here.

[0122] This application also provides a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are executed, they are used to implement the method steps as described in the above method embodiments. The specific implementation methods and technical effects are similar and will not be repeated here.

[0123] The aforementioned computer-readable storage media can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0124] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in a programmable logic device configuration device.

[0125] This application also provides a computer program product, including a computer program, which, when executed, implements the method steps as described in the above method embodiments. The specific implementation and technical effects are similar and will not be repeated here.

[0126] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0127] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for configuring a programmable logic device, applied to a hardware board containing a complex programmable logic device (CPLD), characterized in that, The method includes: When the CPLD is powered on, configuration information is read from the user flash memory inside the CPLD. The configuration information includes at least a hardware version identifier and a function configuration identifier. Parse the read configuration information to obtain the hardware version identifier and the function configuration identifier; Based on the hardware version identifier and the function configuration identifier obtained from the parsing, a specific logical function module that matches the hardware board is dynamically selected and enabled from the same set of logic code embedded in the CPLD.

2. The programmable logic device configuration method according to claim 1, characterized in that, The step of dynamically selecting and enabling a specific logical function module matching the hardware board from the same set of logic code embedded within the CPLD, based on the parsed hardware version identifier and the function configuration identifier, includes: Based on the hardware version identifier, determine a logical code framework that is compatible with the hardware version identifier; Based on the function configuration identifier, within the compatible logic code framework, a specific logic function module that matches the hardware board is dynamically selected and enabled.

3. The programmable logic device configuration method according to claim 1 or 2, characterized in that, The configuration information is a multi-bit command word, which includes: The validity flag field is used to identify the validity of the multi-bit command word itself; The hardware version identifier field is used to represent the hardware version identifier; The function configuration identifier field is used to represent the function configuration identifier.

4. The programmable logic device configuration method according to claim 3, characterized in that, The method further includes: The validity of the configuration information is determined based on the validity flag field. If the configuration information is determined to be invalid, the CPLD is controlled to execute the preset default configuration logic and generate an alarm signal.

5. The method for configuring a programmable logic device according to claim 1 or 2, characterized in that, The dynamic selection and activation of specific logical function modules includes: Based on the function configuration identifier, the function definition, electrical characteristics, or signal mapping relationship of at least one input / output pin of the CPLD is configured.

6. The programmable logic device configuration method according to claim 2, characterized in that, The step of determining a logical code framework compatible with the hardware version identifier based on the hardware version identifier includes: The hardware version identifier is compared with the list of compatible versions pre-stored in the CPLD to determine whether a compatible framework exists.

7. The programmable logic device configuration method according to claim 6, characterized in that, Also includes: If the comparison result indicates that no compatible framework exists, the CPLD is controlled to execute the preset default configuration logic.

8. The method for configuring a programmable logic device according to claim 1 or 2, characterized in that, The method further includes: In response to a configuration update command received through the communication interface of the CPLD, the configuration information stored in the user flash memory is updated based on the configuration update command.

9. The programmable logic device configuration method according to claim 8, characterized in that, Before updating the configuration information stored in the user's flash memory, the method further includes: Back up the current configuration information in the user's flash memory to a preset storage area; If the operation of updating the user flash memory according to the configuration update instruction fails, the configuration information backed up in the preset storage area will be restored to the user flash memory.

10. A hardware board, characterized in that, Includes a complex programmable logic device (CPLD) configured to perform the method as described in any one of claims 1 to 9.

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