UFS chip management method, terminal equipment and computer readable storage medium

Abstract

The invention discloses a UFS chip management method, terminal equipment and a computer readable storage medium, and relates to the technical field of storage. The UFS chip management method is applied to a storage system, and the UFS chip management method comprises the following steps: collecting data of a UFS chip to obtain basic data; performing feature extraction on the basic data to obtain feature values; inputting the characteristic value into a hybrid artificial intelligence model to obtain an execution decision; and executing an action according to the execution decision, according to the management method of the UFS chip, dynamic adjustment of hardware parameters is realized through the hybrid artificial intelligence model, and balanced management of power consumption and performance of the UFS chip is realized.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a management method for a UFS chip, a terminal device, and a computer-readable storage medium. Background Technology

[0002] In UFS (Universal Flash Storage) chip storage devices, the static DVFS (Dynamic Voltage and Frequency Scaling) solution cannot adapt to sudden loads: Static DVFS relies on historical loads or fixed thresholds to trigger frequency scaling, but mobile device loads are sudden. For example, if a user suddenly opens the camera to take continuous shots, the UFS chip needs to switch from PWM-Gear1 low-power mode to HS-Gear4 high-performance mode. Static DVFS needs time to detect the load and switch, resulting in delays in writing the first few photos and a sluggish user experience. On the other hand, rule-based heuristic scheduling (such as fixed queue depth, priority strategies, caching strategies, etc.) cannot learn user behavior: different users have vastly different usage patterns, but the rules are fixed. For gamers, a high queue depth is needed to process a large number of small file loadings in parallel; for document editors, a low queue depth is sufficient to meet the need for sequential writing of large files; for social app users, the loading of videos and images requires burst processing. Current resource management solutions for UFS chip storage devices are unable to quickly respond to sudden load demands from mobile devices, nor can they adapt to personalized user habits. This results in a disconnect between storage resource allocation and actual needs, failing to achieve a precise balance between performance and power consumption. Therefore, how to quickly adjust the hardware resource configuration of UFS flash memory chips based on different user habits and achieve effective UFS chip management has become an urgent problem to be solved. Summary of the Invention

[0003] The purpose of this application is to provide a management method for UFS chips, a terminal device, and a computer-readable storage medium, which achieves dynamic adjustment of hardware parameters through a hybrid artificial intelligence model, thereby realizing balanced management of UFS chip power consumption and performance.

[0004] This application discloses a management method for a UFS chip, applied to a storage system, including the following steps: Collect data from the UFS chip to obtain basic data; Feature extraction is performed on the basic data to obtain feature values; The feature values ​​are input into a hybrid artificial intelligence model to obtain the execution decision; and Based on the decision to be implemented, take action.

[0005] Optionally, the step of acquiring data from the UFS chip to obtain basic data includes: Collect data from the UFS chip; Obtain basic data; Create timestamps corresponding to the base data; Align the underlying data according to the timestamp to form a data snapshot.

[0006] Optionally, the step of extracting features from the basic data to obtain feature values ​​includes: Feature extraction is performed on the basic data to obtain feature values; According to the type of feature, the feature vectors are concatenated to obtain the feature vectors corresponding to each type; The dimensionality of the feature vectors is reduced to obtain the dimensionality-reduced feature vectors.

[0007] Optionally, the step of concatenating feature vectors according to the type of features to obtain feature vectors includes: The feature values ​​are classified into statistical features, temporal features, and semantic features; Based on statistical features, temporal features, and semantic features, statistical feature vectors, temporal feature vectors, and semantic feature vectors are concatenated respectively to obtain statistical feature vectors, temporal feature vectors, and semantic feature vectors.

[0008] Optionally, the step of performing dimensionality reduction processing on the feature vector to obtain the dimensionality-reduced feature vector includes: Standardize the statistical feature vector, temporal feature vector, and semantic feature vector; Calculate the covariance matrix of the standardized statistical feature vector, temporal feature vector, and semantic feature vector to obtain the corresponding feature vector; Choose the number of principal components to generate a dimensionality-reduced feature vector; Based on the selected number of principal components, a projection matrix is ​​formed, and the projection matrix is ​​used to generate dimensionality-reduced feature vectors.

[0009] Optionally, the step of inputting feature values ​​into a hybrid artificial intelligence model to obtain an execution decision includes: Calling a hybrid artificial intelligence model; Input the dimensionality-reduced feature vectors into the hybrid artificial intelligence model; Hybrid AI models output execution decisions; The output execution decision includes execution actions in m dimensions, where m is greater than or equal to 4.

[0010] Optionally, the steps of executing the action based on the execution decision include: Analyze the execution decision to obtain the decision vector; Query the strategy mapping table and obtain the corresponding hardware parameter combination based on the value of the decision vector; Instructions are issued based on the combination of hardware parameters to execute actions.

[0011] Optionally, the hybrid artificial intelligence model is formed by combining at least two artificial intelligence models.

[0012] This application also discloses a terminal device, including a storage system, a processor, and a computer program stored in the storage system and executable on the processor, wherein the processor executes the computer program to implement the steps of the UFS chip management method described above.

[0013] This application also discloses a computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the UFS chip management method described above.

[0014] The UFS chip management method of this application collects data from the UFS chip to obtain basic data, extracts features from the basic data to obtain feature values, inputs the feature values ​​into a hybrid artificial intelligence model to generate execution decisions, and executes actions based on the execution decisions to realize resource adjustment management of the UFS chip. Through the analysis of feature values ​​by the hybrid artificial intelligence model, the current and short-term load of the UFS chip is predicted in real time, and the hardware parameters are dynamically adjusted according to the load prediction results to achieve balanced management of power consumption and performance. Attached Figure Description

[0015] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without creative effort. In the drawings: Figure 1 This is a flowchart illustrating the steps of a UFS chip management method according to the first embodiment of this application; Figure 2 This is a flowchart illustrating the specific steps of step S1 in the first embodiment of this application; Figure 3 This is a flowchart illustrating the specific steps of step S2 in the first embodiment of this application; Figure 4 This is a flowchart illustrating the specific steps of step S22 in the first embodiment of this application; Figure 5 This is a flowchart illustrating the specific steps of step S3 in the first embodiment of this application; Figure 6This is a flowchart illustrating the specific steps of step S4 in the first embodiment of this application; Figure 7 This is a schematic diagram of the structure of a terminal device according to the second embodiment of this application.

[0016] Among them, 100 is the terminal device; 110 is the storage system; 120 is the processor; and 130 is the computer program. Detailed Implementation

[0017] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0018] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0019] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0021] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0022] Figure 1This is a flowchart illustrating the steps of a UFS chip management method according to the first embodiment of this application, as follows: Figure 1 As shown, as a first embodiment of this application, a UFS chip management method is disclosed, the UFS chip management method including the following steps: S1: Collect data from the UFS chip to obtain basic data; Specifically, key data affecting performance and power consumption in the UFS chip are collected as basic data. The key data can include the following three types of data: host-side data, UFS protocol layer data, and UFS physical layer data. S2: Extract features from the basic data to obtain feature values; Specifically, feature extraction is performed on the collected basic data to convert the basic data into features containing information, thereby obtaining feature values; S3: Input the feature values ​​into the hybrid artificial intelligence model to obtain the execution decision; Specifically, the feature values ​​obtained from the above steps will be input into the calibrated or trained hybrid artificial intelligence model. The hybrid artificial intelligence model will then comprehensively consider the feature values ​​to generate an execution decision. S4: Execute actions based on the execution decision; Specifically, the hybrid AI model generates execution decisions based on feature values, which are then translated into specific actions by the UFS hardware. These actions are executed from different dimensions to achieve resource adjustments in the storage system.

[0023] The UFS chip management method of this application collects data from the UFS chip to obtain basic data, extracts features from the basic data to obtain feature values, inputs the feature values ​​into a hybrid artificial intelligence model to generate execution decisions, and executes actions based on the execution decisions to achieve resource adjustment management of the UFS chip. Through the analysis of feature values ​​by the hybrid artificial intelligence model, the current and short-term load of the UFS chip is predicted in real time, and the hardware parameters are dynamically adjusted according to the load prediction results to achieve balanced management of power consumption and performance of the UFS chip.

[0024] Figure 2 This is a flowchart illustrating the specific steps of step S1 in the first embodiment of this application, as follows: Figure 2 As shown, the steps for acquiring data from the UFS chip to obtain basic data include: S10: Collect data from the UFS chip; S11: Obtain basic data; S12: Create a timestamp corresponding to the base data; Specifically, timestamps corresponding to the basic data are created to align all the basic data to a unified time grid according to the timestamps. For example, CPU load, IOPS and M-PHY data at t=1.0ms are aligned. S13: Align the basic data according to the timestamp to form a data snapshot; Specifically, based on the timestamps created in the previous step, align all the basic data to a unified time grid to form a unified data snapshot for easier subsequent work; The basic data in this embodiment includes three types: host-side data, UFS protocol layer data, and UFS physical layer data. Host-side data can collect the current foreground application name / type, power status, and CPU load. UFS protocol layer data can collect SCSI queue depth, throughput (IOPS), and command type. UFS physical layer data can collect the current M-PHY speed (Mode / Gear), number of active channels, and flash memory temperature. Furthermore, to ensure the integrity and reliability of the basic data, the following handling mechanism is adopted for abnormal situations during data acquisition: if there are missing sampling points in the basic data, the previous valid value or linear interpolation is used to fill them; if there are data with large instantaneous fluctuations in the basic data, a moving average filter is used to smooth the data, filtering out noise interference while preserving the data's inherent trend.

[0025] In this embodiment, the collected basic data is placed into a high-speed circular buffer, and a timestamp corresponding to the basic data is created. All basic data are stamped with high-precision timestamps and aligned to a unified time grid according to the timestamps to form a unified data snapshot, which facilitates subsequent feature extraction of the basic data to obtain feature values.

[0026] Figure 3 This is a flowchart illustrating the specific steps of step S2 in the first embodiment of this application, as follows: Figure 3 As shown, the steps for extracting features from the basic data to obtain feature values ​​include: S20: Extract features from the basic data to obtain feature values; Specifically, by constructing different features, basic data can be transformed into feature values ​​that contain rich information. These can be broadly categorized into three types: statistical features, temporal features, and semantic features. Statistical characteristics may include average (average load level), standard deviation (load volatility), maximum / minimum (peak demand), and request type ratio (read / write request ratio, sequential / random request ratio). Time-series features can include rate of change and trend (calculating the slope of IOPS within a window to predict whether IOPS will rise or fall), frequency domain features (performing a fast Fourier transform on the IO request sequence to analyze its periodic components; for example, finding an I / O pulse every 16.67ms can predict the load related to UI rendering), and autocorrelation (detecting the degree of correlation between the current load and the past load to determine whether it is a predictable periodic load or a random load). Semantic features can be combined with prior knowledge such as user behavior and system status to give features contextual labels. For example, if the foreground application is a camera and the system call is the camera API, it is labeled as "prelude to taking a picture". If the continuous write rate exceeds 1000MB / s and the write block size is 128KB, it is labeled as "video recording". If the GPU load is greater than 80% and the frame rate is less than 30, it is labeled as "game is lagging and needs acceleration".

[0027] The above-mentioned feature value types are merely examples. This application does not impose a unique limitation on the specific type of feature value, and feature types can be expanded according to actual application scenarios. S21: Concatenate the eigenvectors according to the type of eigenvalues ​​to obtain the eigenvectors of each type; Specifically, all processed feature values ​​(statistical features, temporal features, and semantic features) are concatenated into a long feature vector, integrating heterogeneous feature values ​​from different sources and of different natures into a unified language, allowing the hybrid artificial intelligence model to simultaneously see the macro-level situation (semantic features), micro-level dynamics (temporal features), and overall summary (statistical features). For example: The statistical feature vector V_stat = [mean (IOPS), standard deviation (IOPS), mean (write ratio), maximum (queue depth), mean (latency), current temperature, temperature slope, command type entropy] (dimension 8); The time-series feature vector V_time [IOPS change rate, FFT main frequency amplitude of the load sequence, autocorrelation coefficient, current load trend (rising / falling)] (dimension 4); Semantic feature vector V_sem [foreground application type, CPU load level, battery level, charging status, screen status, expert scene expression (e.g., pre-photo capture signal = 0.9)] (dimensional 6); Feature vector concatenation first aligns the dimensions. For example, the statistical feature vector has a dimension of 8, the temporal feature vector has a dimension of 4, and the semantic feature vector has a dimension of 6. Then, the first and last parts of the multiple feature vectors are concatenated to obtain the concatenated feature vector. V_combine = [Mean (IOPS), Standard Deviation (IOPS), Mean (Write Ratio), Maximum (Queue Depth), Mean (Latency), Current Temperature, Temperature Slope, Command Type Entropy, IOPS Change Rate, FFT Frequency Amplitude of Load Sequence, Autocorrelation Coefficient, Current Load Trend (Increasing / Decreasing), Foreground Application Type, CPU Load Level, Battery Level, Charging Status, Screen Status, Expert Scene Tags] This forms a complete 19-dimensional feature vector. In practice, more dimensional feature values ​​can be extracted to form a longer feature vector. The 19-dimensional complete feature vector here is only for illustrative purposes and is not limited to 19 dimensions.

[0028] S22: The dimensionality of the feature vectors is reduced to obtain the dimensionality-reduced feature vectors; Specifically, multidimensional feature vectors may contain redundant information, and the computational load may still be too large for microcontrollers. Therefore, dimensionality reduction of multidimensional feature vectors can improve the computational efficiency of hybrid artificial intelligence models and speed up inference time. It should be noted that dimensionality reduction of multidimensional feature vectors can be performed by using principal component analysis (PCA). In this application, after concatenating the feature vectors into a multi-dimensional feature vector (e.g., 150-dimensional, as illustrated below using a 150-dimensional feature vector as an example), dimensionality reduction processing is then used to compress the multi-dimensional feature vector into a 20-30 dimensionality reduced feature vector. This process can retain more than 90% of the original information. The eigenvalues ​​in the multi-dimensional feature vector are highly correlated, and the 150 collected eigenvalues ​​are not completely independent. For example: There is a strong correlation between “average IOPS over the past 1ms”, “average IOPS over the past 5ms”, and “instantaneous IOPS”. There is an inherent relationship between "CPU load", "current foreground application type" and "system call frequency"; NAND temperature and controller power consumption are closely related; Dimensionality reduction techniques like PCA work by identifying the correlations between these eigenvalues ​​and merging multiple correlated eigenvalues ​​into a new, uncorrelated eigenvalue (principal component). Furthermore, multidimensional eigenvectors have low intrinsic dimensionality; although a multidimensional eigenvector may have 150 dimensions, its variation patterns are likely primarily controlled by a few underlying driving factors, such as: User behavior factors (stillness, swiping, taking photos, playing games); System status factors (high load, low load); Hardware limitations (power, temperature, etc.); There may only be 10 to 20 of these core driving factors. Therefore, by keeping the dimensionality-reduced feature vector in a 20 to 30-dimensional space, most of the information can be captured.

[0029] Figure 4 This is a flowchart illustrating the specific steps of step S22 in the first embodiment of this application. The step of reducing the dimensionality of the feature vector to obtain the dimensionality-reduced feature vector includes: S220: Standardize the statistical feature vector, temporal feature vector, and semantic feature vector; Specifically, since the dimensions and numerical ranges of feature values ​​in different dimensions of the feature vector differ significantly (e.g., IOPS values ​​may reach thousands, while flash memory temperature values ​​are usually tens), directly inputting these feature values ​​into the artificial intelligence model will lead to the large feature values ​​dominating the results. Therefore, it is necessary to standardize the feature values ​​of each dimension so that the mean of each feature value is 0 and the standard deviation is 1, to avoid the difference in numerical range affecting the dimensionality reduction effect. In this embodiment, Z-Score normalization or Min-Max normalization can be used to standardize the feature values. Min-Max normalization can scale the feature values ​​to the [0,1] interval, while Z-Score normalization has no fixed interval but can preserve the distribution trend of the feature values. The specific choice can be made according to the actual type of feature values. S221: Calculate the covariance matrix of the standardized statistical feature vector, temporal feature vector, and semantic feature vector to obtain the corresponding feature vector; Specifically, the covariance matrix of the standardized eigenvectors is calculated. The covariance matrix describes the linear relationship between the eigenvectors (the covariance matrix measures the degree to which multiple eigenvalues ​​change together; a positive value indicates that two eigenvalues ​​are positively correlated, meaning that when one eigenvalue increases, the other tends to increase as well; a negative value indicates that two eigenvalues ​​are negatively correlated, meaning that when one eigenvalue increases, the other tends to decrease; a zero value indicates that the eigenvalues ​​are linearly independent). By solving the covariance matrix, the calculated eigenvalues ​​and corresponding eigenvectors are obtained. The magnitude of the eigenvalues ​​reflects the variance of the original data carried by the corresponding principal component direction (the larger the variance, the richer the information contained), and the eigenvectors define the spatial direction of the new coordinate axes (principal components). S222: Select the number of principal components to generate dimensionality-reduced feature vectors; Specifically, with k principal components, the eigenvalues ​​obtained after calculating the covariance matrix are sorted in descending order. Then, the cumulative variance ratio is calculated (cumulative variance = sum of the first k eigenvalues ​​[principal component count] / sum of all eigenvalues). The smallest value of k is selected such that the cumulative variance is ≥90%. By discarding no more than 10% of the original information, the dimensionality of the eigenvalues ​​is significantly reduced. In this embodiment, the number of principal components k can be a value between 20 and 30. Setting the number of principal components k within this range can retain more than 90% to 95% of the original information, allowing the dimensionality of the eigenvalues ​​to be significantly reduced while retaining most of the data, achieving a balance between dimensionality reduction and information preservation. S223: Based on the number of principal components selected, form a projection matrix and use the projection matrix to generate dimensionality-reduced feature vectors; Specifically, based on the number of principal components k obtained in the above steps, a projection matrix W is formed using the first k eigenvectors. The standardized eigenvectors are then mapped onto a k-dimensional space (a new linear subspace formed by the first k eigenvectors) through the projection matrix W, resulting in a dimensionality-reduced eigenvector V_final = V_combine * W. The management method in this embodiment concatenates multiple feature values ​​into a long feature vector (e.g., 150-dimensional; the following explanation uses a 150-dimensional feature vector as an example). Then, through dimensionality reduction processing, the long feature vector is compressed into a 20-30 dimensional feature vector. This can retain more than 90% of the original information. Dimensionality reduction of the feature vector not only improves the computational efficiency of the artificial intelligence model but also reduces overfitting caused by redundant features, improving the performance of the artificial intelligence model on unseen user behaviors. At the same time, the dimensions of the dimensionality-reduced feature vector are independent and have uniform dimensions, which can accelerate the convergence speed of the optimization algorithm of the artificial intelligence model and find the optimal solution more quickly and stably.

[0030] Figure 5 This is a flowchart illustrating the specific steps of step S3 in the first embodiment of this application, as follows: Figure 5 As shown, the step of inputting feature values ​​into a hybrid artificial intelligence model to obtain an execution decision includes: S30: Invoke the hybrid artificial intelligence model; Specifically, the hybrid artificial intelligence model is formed by combining at least two artificial intelligence models, which can be a hybrid model of 1D-CNN (one-dimensional neural convolutional network) and LSTM (long short-term memory network) or GRU (gated recurrent unit); One-dimensional neural convolutional networks are used to extract local spatial features of I / O request sequences over a short period of time, such as the burstiness and continuity of the requests. The input data consists of 6-dimensional feature values ​​from the most recent 20 sampling times (each time interval is 100 microseconds), as shown below:

[0031] Long Short-Term Memory (LSTM) networks, or gated recurrent units, are used to learn over long periods of time, such as the amount of time a user frequently plays games, to predict future load trends. The input data consists of feature values ​​from a single point in time, as shown below:

[0032] S31: Input the dimensionality-reduced feature vectors into the hybrid artificial intelligence model; S32: Hybrid AI model outputs execution decisions; Specifically, after receiving the required dimensionality-reduced feature vectors, the hybrid artificial intelligence model performs calculations based on the dimensionality-reduced feature vectors to generate an execution decision. The output execution decision includes m-dimensional execution actions, where m is greater than or equal to 4. That is, the execution decision can output a 4-dimensional execution action, where each dimension represents a specific prediction or suggestion, and the value range is between [0, 1].

[0033] Figure 6 This is a flowchart illustrating the specific steps of step S4 in the first embodiment of this application, as follows: Figure 6 As shown, the steps for executing an action based on an execution decision include: S40: Analyze the execution decision to obtain the decision vector; Specifically, the execution decisions output by the hybrid artificial intelligence model are analyzed, the execution actions in the execution decisions are read, and the decision vector is obtained; S41: Query the policy mapping table and obtain the corresponding hardware parameter combination based on the value of the decision vector; Specifically, based on the value of the decision vector, the corresponding hardware parameter combination is searched in a predefined strategy mapping table to obtain the hardware parameter combination of the decision vector. The predefined strategy mapping table stores the correspondence between "decision vector interval - hardware parameter combination". Based on the weight values ​​of each dimension of the decision vector, the optimal matching hardware parameter combination is searched in the table. The strategy mapping table can be dynamically updated according to the actual application scenario. S42: Issues instructions and commands based on hardware parameter combinations to execute actions; Specifically, based on the combination of hardware parameters, specific control commands are issued through the UFS controller; or SCSI commands (such as Mode Select) are sent, or registers are directly configured (such as M-PHY speed) to achieve dynamic adjustment of multi-dimensional hardware parameters. An example adjustment scheme is as follows:

[0034] The UFS chip management method of this embodiment collects data from the UFS chip to obtain basic data, extracts features from the basic data to obtain feature values, concatenates the feature values ​​into feature vectors, and then performs dimensionality reduction processing to obtain dimensionality-reduced feature vectors. These vectors are then input into an artificial intelligence model to generate execution decisions. Based on the execution decisions, actions are executed to achieve resource adjustment and management of the UFS chip. Through the analysis of feature values ​​by the artificial intelligence model, the current and short-term load of the UFS chip is predicted in real time. On the other hand, based on the load prediction results, hardware parameters are dynamically adjusted to achieve a balance between power consumption and performance management. Furthermore, this embodiment concatenates feature values ​​into feature vectors and then performs dimensionality reduction processing, compressing multi-dimensional feature vectors into fewer-dimensional dimensionality-reduced feature vectors while retaining more than 90% of the original information. This improves the computational efficiency of the artificial intelligence model and ensures the accuracy of the decisions. This allows the UFS chip management method of this application to quickly generate execution decisions based on feature values, so as to quickly and stably find the optimal operating parameters of the UFS chip for different user behaviors and achieve resource adjustment of the UFS chip.

[0035] Figure 7 This is a schematic diagram of the structure of a terminal device according to the second embodiment of this application, as shown below. Figure 7 As shown, as a second embodiment of this application, a terminal device is disclosed, including a storage system, a processor, and a computer program stored in the storage system and executable on the processor. When the processor executes the computer program, it implements the steps of the UFS chip management method described in the above embodiment.

[0036] As a third embodiment of this application, a computer-readable storage medium is disclosed, which stores a computer program that, when executed by a processor, implements the steps of the UFS chip management method described in the above embodiments.

[0037] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0038] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0039] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0040] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A management method for a UFS chip, applied to a storage system, characterized in that, Including the following steps: Data is collected from the UFS chip to obtain basic data; Feature extraction is performed on the basic data to obtain feature values; The feature values ​​are input into the hybrid artificial intelligence model to obtain the execution decision; as well as Based on the decision to be implemented, take action.

2. The management method for a UFS chip according to claim 1, characterized in that, The steps for acquiring data from the UFS chip to obtain basic data include: Collect data from the UFS chip; Obtain basic data; Create timestamps corresponding to the base data; Align the underlying data according to the timestamp to form a data snapshot.

3. The management method for a UFS chip according to claim 1, characterized in that, The steps for extracting features from the basic data to obtain feature values ​​include: Feature extraction is performed on the basic data to obtain feature values; According to the type of feature, the feature vectors are concatenated to obtain the feature vectors corresponding to each type; The dimensionality of the feature vectors is reduced to obtain the dimensionality-reduced feature vectors.

4. The UFS chip management method according to claim 3, characterized in that, The step of concatenating feature vectors according to their types to obtain feature vectors includes: The feature values ​​are classified into statistical features, temporal features, and semantic features; Based on statistical features, temporal features, and semantic features, statistical feature vectors, temporal feature vectors, and semantic feature vectors are concatenated respectively to obtain statistical feature vectors, temporal feature vectors, and semantic feature vectors.

5. The UFS chip management method according to claim 4, characterized in that, The steps for dimensionality reduction of the feature vector to obtain the dimensionality-reduced feature vector include: Standardize the statistical feature vector, temporal feature vector, and semantic feature vector; Calculate the covariance matrix of the standardized statistical feature vector, temporal feature vector, and semantic feature vector to obtain the corresponding feature vector; Choose the number of principal components to generate a dimensionality-reduced feature vector; Based on the selected number of principal components, a projection matrix is ​​formed, and the projection matrix is ​​used to generate dimensionality-reduced feature vectors.

6. The management method for a UFS chip according to claim 3, characterized in that, The step of inputting feature values ​​into the hybrid artificial intelligence model to obtain the execution decision includes: Calling a hybrid artificial intelligence model; Input the dimensionality-reduced feature vectors into the hybrid artificial intelligence model; Hybrid AI models output execution decisions; The output execution decision includes execution actions in m dimensions, where m is greater than or equal to 4.

7. The UFS chip management method according to claim 1, characterized in that, The steps for executing actions based on the execution decision include: Analyze the execution decision to obtain the decision vector; Query the strategy mapping table and obtain the corresponding hardware parameter combination based on the value of the decision vector; Instructions are issued based on the combination of hardware parameters to execute actions.

8. The management method for a UFS chip according to claim 1, characterized in that, The hybrid artificial intelligence model is formed by combining at least two artificial intelligence models.

9. A terminal device, characterized in that, The device includes a storage system, a processor, and a computer program stored in the storage system and executable on the processor, wherein the processor executes the computer program to implement the steps of the UFS chip management method as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the UFS chip management method as described in any one of claims 1 to 8.

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