Reconfigurable hardware suite control method, equipment, medium and product

Abstract

The invention discloses a reconfigurable hardware suite control method and device, a medium and a product, and relates to the field of artificial intelligence hardware. The method comprises the following steps: in response to an access event, reading and analyzing module archive information in a storage unit through a golden finger interface unit to obtain hardware resource requirements and operating system adaptation information; allocating hardware resources to the extended function module through the resource control unit based on hardware resource requirements; in response to the module hot plug event, performing initialization and drive loading on the extended function module based on the operating system adaptation information; in response to the task chain, decomposing the task chain into an atomic operator sequence through the dynamic reconfigurable computing unit, and configuring a reconfigurable interconnection network in the dynamic reconfigurable computing unit; and generating system load prediction information based on calculation characteristics of various atomic operators and real-time task queue depth, and dynamically configuring the reconfigurable hardware suite through a hardware management unit. The control efficiency of the reconfigurable hardware suite can be improved.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence hardware technology, and in particular to a method, device, medium and product for controlling a reconfigurable hardware kit. Background Technology

[0002] With the widespread application of artificial intelligence technology in edge computing scenarios, reconfigurable hardware kits have become key to achieving high-performance edge intelligent computing due to their ability to adapt to different computing tasks through dynamic configuration. Traditional control methods suffer from poor coordination between computing units when dealing with dynamic and varied task flows and heterogeneous computing resources. This leads to a significant compression of the effective computing time of hardware resources, and the overall system throughput and energy efficiency are far below the theoretical peak. While existing Dynamic Voltage and Frequency Scaling (DVFS) technology can adjust the processor's operating voltage and frequency according to the load, its adjustment granularity is usually based on the entire processor or a fixed computing cluster. It cannot provide fine-grained differentiated control for heterogeneous computing units in neural network processors, nor can it predictively allocate computing resources based on task type characteristics and task queue depth before task execution. Furthermore, existing dynamic adjustment schemes only manage power consumption for a single hardware module, lacking the ability to predict the overall load and coordinate cross-module resources, thus reducing the control efficiency of reconfigurable hardware kits. Summary of the Invention

[0003] This application provides a method, device, medium, and product for controlling a reconfigurable hardware kit, which addresses the technical problem of how to improve the control efficiency of a reconfigurable hardware kit.

[0004] In a first aspect, embodiments of this application provide a reconfigurable hardware kit control method, applied to a reconfigurable hardware kit, wherein the reconfigurable hardware kit includes a main computing module and at least one extended functional module, the main computing module includes a dynamically reconfigurable computing unit, a hardware management unit, and a resource control unit, and the extended functional module includes a gold finger interface unit and a storage unit, the method comprising: In response to the access event of the extended function module, the main computing module reads and parses the module file information in the storage unit through the gold finger interface unit to obtain hardware resource requirements and operating system adaptation information. The module file information is used to store the configuration data of the extended function module. Based on the hardware resource requirements, hardware resources are allocated to the extended function module through the resource control unit. In response to a module hot-plug event, the extended function module is initialized and its driver is loaded based on the operating system adaptation information, so that the extended function module can be put into a usable state. In response to the task chain issued by the artificial intelligence application, the task chain is decomposed into a sequence of atomic operators by the dynamically reconfigurable computing unit, and the sequence of atomic operators includes multiple different types of atomic operators; Based on the computational characteristics of the various atomic operators, a reconfigurable interconnection network is configured in the dynamically reconfigurable computing unit; Based on the computational characteristics of various atomic operators and the real-time task queue depth, system load prediction information is generated. Based on the system load prediction information, the reconfigurable hardware suite is dynamically configured through the hardware management unit.

[0005] Optionally, the gold finger interface unit includes a first configuration pin. In response to the access event of the extended function module, the main computing module reads and parses the module file information in the storage unit through the gold finger interface unit to obtain hardware resource requirements and operating system adaptation information. This includes: in response to the access event, the main computing module accesses the module file information of the storage unit through the first configuration pin. The module file information includes at least a module identifier, power consumption requirement information, the required number of high-speed input / output channels, an interrupt mapping scheme, and driver configuration scripts for different operating systems. The power consumption requirement information and the required number of high-speed input / output channels are used as the hardware resource requirements, and each of the driver configuration scripts is used as the operating system adaptation information.

[0006] Optionally, the gold finger interface unit further includes a second configuration pin. After the main computing module reads and parses the module file information in the storage unit through the gold finger interface unit to obtain hardware resource requirements and operating system adaptation information in response to the access event of the extended function module, the method further includes: the main computing module communicating bidirectionally with the extended function module through the second configuration pin to obtain electrical parameter sets corresponding to the various operating modes supported by the extended function module, the electrical parameter sets including a reference power supply requirement and a reference signal rate; obtaining the real-time power supply requirement and real-time signal rate monitored by the main computing module; matching the real-time power supply requirement and the real-time signal rate with each of the electrical parameter sets to determine a target level operating mode, the target level operating mode being used to characterize the highest level operating mode where the reference power supply requirement does not exceed the real-time power supply requirement and the reference signal rate does not exceed the real-time signal rate; and updating the power consumption requirement information and the required number of high-speed input / output channels of the hardware resource requirements based on the reference power supply requirement and the reference signal rate of the target level operating mode.

[0007] Optionally, the dynamically reconfigurable computing unit includes a neural network processing component (NPU) and a hardware task chain parsing component. The task chain, responding to a task chain issued by an artificial intelligence application, is decomposed into a sequence of atomic operators by the dynamically reconfigurable computing unit. This includes: parsing the task chain using the hardware task chain parsing component to obtain a dependency analysis result of the task chain. The dependency analysis result is used to characterize the data dependencies in the task chain, and the data dependencies include at least parallel branch relationships and serial dependencies. Based on the dependency analysis result, the task chain is decomposed into multiple atomic operators, including an execution order, to obtain the atomic operator sequence.

[0008] Optionally, the NPU includes multiple scalar processing units (SPUs), tensor processing units (TPUs), and vector processing units (VPUs). The step of configuring a reconfigurable interconnect network in the dynamically reconfigurable computing unit based on the computational characteristics of the various atomic operators includes: determining a set of target processing elements for the atomic operator sequence based on the computational characteristics; the set of target processing elements includes multiple target processing elements, with one type of atomic operator corresponding to one or more target processing elements; the target processing elements are used to characterize any one of the SPUs, TPUs, and VPUs; establishing data paths for each target processing element through the reconfigurable interconnect network based on the set of target processing elements; and connecting atomic operators with data dependencies based on the data paths to configure the reconfigurable interconnect network.

[0009] Optionally, generating system load prediction information based on the computational characteristics of various atomic operators and the real-time task queue depth includes: obtaining the baseline power consumption values ​​of various atomic operators at standard voltage and frequency, and the historical memory access frequencies of various atomic operators during historical execution, based on the computational characteristics of various atomic operators; identifying the type and number of atomic operators to be executed based on the real-time task queue depth, and calculating the total baseline power consumption value of the current queue based on each baseline power consumption value and a preset weight set; predicting the memory controller bandwidth configuration and interface data throughput in a preset future time window using a preset linear regression algorithm based on the historical memory access frequency and the type and number of atomic operators to be executed; calculating the power consumption increment value using a preset power consumption model based on the memory controller bandwidth configuration and the interface data throughput; calculating the sum of the total baseline power consumption value and the power consumption increment value to obtain the predicted power consumption value in the preset future time window; and using the memory controller bandwidth configuration, the interface data throughput, and the predicted power consumption value together as the system load prediction information.

[0010] Optionally, the dynamic configuration of the reconfigurable hardware suite based on the system load prediction information via the hardware management unit includes: adjusting the bandwidth, operating mode, and clock frequency of the memory controller of the main computing module based on the memory controller bandwidth configuration; adjusting the link rate and power management status of the high-speed input / output interface between the main computing module and the extended function module via the resource control unit based on the interface data throughput; if the predicted power consumption value is greater than a preset power consumption threshold, searching in the preset frequency and voltage configuration table for a first frequency and voltage combination whose power consumption value does not exceed the preset power consumption threshold, and reducing the operating voltage and operating frequency of the dynamic reconfigurable computing unit to the value corresponding to the first frequency and voltage combination; if the predicted power consumption value is less than or equal to the preset power consumption threshold, calculating the difference between the preset power consumption threshold and the predicted power consumption value to obtain a power consumption margin, searching in the frequency and voltage configuration table for a second frequency and voltage combination whose power consumption increase value does not exceed the power consumption margin, and increasing the operating voltage and operating frequency of the dynamic reconfigurable computing unit to the value corresponding to the second frequency and voltage combination.

[0011] In a second aspect, embodiments of this application provide a reconfigurable hardware suite control device, which includes: one or more processors and a memory; the memory is coupled to the one or more processors, and the memory is used to store computer program code, which includes computer instructions, and the one or more processors call the computer instructions to cause the reconfigurable hardware suite control device to perform the method described in the first aspect and any possible implementation thereof.

[0012] Thirdly, embodiments of this application provide a computer program product containing instructions that, when the computer program product is run on a reconfigurable hardware kit control device, cause the reconfigurable hardware kit control device to perform the method described in the first aspect and any possible implementation thereof.

[0013] Fourthly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a reconfigurable hardware kit control device, cause the reconfigurable hardware kit control device to perform the method described in the first aspect and any possible implementation thereof.

[0014] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages: 1. By adopting module archive information to achieve self-description and automatic configuration of extended functional modules, and combining dynamic parsing of task chains, computing power reconfiguration, and predictive energy efficiency management, a complete control closed loop is formed. This enables the reconfigurable hardware kit to achieve synergistic optimization in terms of scalability, computing efficiency, and global energy efficiency, allowing the hardware kit to intelligently adapt to dynamically changing AI tasks and external expansion needs. This fundamentally improves the overall performance and energy efficiency ratio of the edge intelligent computing system and enhances the control efficiency of the reconfigurable hardware kit.

[0015] 2. By reading module file information through the first configuration pin and performing dynamic electrical negotiation of the working mode in conjunction with the second configuration pin, not only is the cumbersome manual jumper and BIOS settings in the traditional method eliminated, but also the optimal working mode and hardware resources can be dynamically matched and configured for the expansion module according to the real-time system supply capacity. Thus, while ensuring electrical stability and signal integrity, the performance potential of each expansion module is maximized.

[0016] 3. By using a hardware task chain parsing component to perform dependency analysis and atomization decomposition of AI task chains, and based on the computational characteristics of atomic operators, the optimal data path is dynamically configured among heterogeneous computing units such as SPU, TPU, and VPU. This achieves "precise matching" and "dynamic stitching" of computing hardware resources to software tasks, effectively eliminating the data transport and scheduling overhead of fixed-architecture NPUs when processing complex task chains, significantly reducing task processing latency, and greatly improving the utilization rate of computing units and the overall energy efficiency of the system.

[0017] 4. By combining the static computation characteristics of atomic operators with the real-time task queue depth, fine-grained and forward-looking system load prediction is performed. Based on this, the voltage, frequency and power consumption of computing units, memory and I / O interfaces are adjusted in a coordinated manner. This achieves a leap in energy efficiency management from "local passive response" to "global active optimization". Under strict power consumption constraints, the system can avoid performance bottlenecks and thermal throttling in advance, thereby providing continuous and stable high-performance computing power output and successfully breaking through the "power consumption wall" limitation of edge devices. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the reconfigurable hardware kit provided in the embodiments of this application; Figure 2 This is a flowchart illustrating a reconfigurable hardware kit control method provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a reconfigurable hardware kit control device provided in an embodiment of this application.

[0019] Explanation of reference numerals in the attached drawings: 301, Central Processing Unit; 302, Read-Only Memory; 303, Random Access Memory; 304, Bus; 305, Input / Output Interface; 306, Input Section; 307, Output Section; 308, Storage Section; 309, Communication Section; 310, Driver; 311, Removable Media. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the description of the embodiments of this application, words such as "illustrative," "for example," or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "illustrative," "for example," or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of words such as "illustrative," "for example," or "for example" is intended to present the relevant concepts in a specific manner.

[0022] In the description of the embodiments of this application, the terms "first" and "second" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first" and "second" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0023] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0024] In the implementation of this application, the collection and processing of relevant data should strictly comply with the requirements of relevant national laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.

[0025] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0026] In related technologies, adjusting the processor's operating voltage and frequency according to the load lacks the ability to predict the overall load and coordinate cross-module resources, which reduces the control efficiency of reconfigurable hardware kits. To address the above problems, embodiments of this application provide a reconfigurable hardware kit control method, device, medium, and product that can effectively improve the control efficiency of reconfigurable hardware kits.

[0027] Figure 1 This is a schematic diagram of the reconfigurable hardware kit provided in the embodiments of this application.

[0028] This invention discloses a control method for a reconfigurable hardware suite, applicable to reconfigurable hardware suites, such as... Figure 1 As shown, the reconfigurable hardware kit includes a main computing module and at least one extended functional module. The main computing module includes a dynamically reconfigurable computing unit, a hardware management unit, and a resource control unit. The extended functional module includes a gold finger interface unit and a storage unit.

[0029] See Figure 2 , Figure 2 This is a flowchart illustrating a reconfigurable hardware kit control method provided in an embodiment of this application. The reconfigurable hardware kit control method disclosed in this embodiment of the invention includes the following steps.

[0030] S101. In response to the access event of the extended function module, the main computing module reads and parses the module file information in the storage unit through the gold finger interface unit to obtain the hardware resource requirements and operating system adaptation information. The module file information is used to store the configuration data of the extended function module.

[0031] Specifically, when the extended function module physically connects to the reconfigurable hardware kit, the connection action is detected and identified by the system as an access event. The main computing module is then triggered and actively accesses the module file information pre-stored in the storage unit on the extended function module through its gold finger interface unit that interfaces with the extended module. First, it reads the raw data of the information, and then parses it according to a predefined format and protocol. Two key parts are extracted from the structured data: one is the hardware resource requirements for the normal operation of the extended module, and the other is the operating system adaptation information required by it in different operating system environments.

[0032] In this context, extended function modules refer to pluggable hardware units that provide additional specific functions to the device, such as camera modules, GPS modules, 4G / 5G communication modules, or dedicated AI acceleration modules. Access events represent the act of an extended function module establishing a physical and electrical connection with the main device, which triggers system-level interrupts or state change detection. The main computing module refers to the device's core processor unit (such as a CPU or SoC), responsible for the entire system's computation, control, and decision-making. The gold finger interface unit is a row of electroplated copper contacts and its corresponding controller used to connect the motherboard and the extended function module, providing a channel for mechanical connection, power supply, and high-speed data exchange. Storage units refer to non-volatile memory chips located on the extended function module, such as EEPROM (Electrically Erasable Programmable Read-Only Memory), specifically used to store the module's critical information. Module file information represents a file or data set recording all the module's configuration data, serving as the module's digital identity. Hardware resource requirements represent the system resources that the extended function module needs to allocate from the main computing module for normal operation, specifically including but not limited to the number of PCIe lanes, interrupt request lines, a specific memory address space range, and power budget. Operating system adaptation information represents the software-level information required to drive and manage the module, such as driver filenames, version compatibility lists, and device class identifiers, to ensure that the operating system can correctly identify and load the appropriate driver. Configuration data refers to the set of parameters and settings used to define and initialize a hardware or software component.

[0033] For example, suppose an AI accelerator card supporting PCIe 4.0 x4 is inserted into the slot of an edge computing device carrying this embodiment of the invention. After detecting the access event, the main computing module accesses an EEPROM chip (storage unit) on the accelerator card through the I2C pin on the gold finger interface (which is part of the gold finger interface unit). It reads the pre-stored module profile information and, after parsing, learns that its hardware resource requirements are: four PCIe 4.0 lanes and a peak power consumption of 25 watts. Simultaneously, its operating system adaptation information includes a driver loading script for Linux systems, which specifies the register addresses and parameter values ​​that need to be initialized.

[0034] Based on the above embodiments, as an optional embodiment, the gold finger interface unit includes a first configuration pin, for... Figure 2 The step S101 shown can be implemented through steps S1011-S1012, which will be explained in detail below.

[0035] S1011 In response to the access event, the main computing module accesses the module file information of the storage unit through the first configuration pin. The module file information includes at least the module identifier, power consumption requirements, the number of required high-speed input / output channels, the interrupt mapping scheme, and the driver configuration scripts for different operating systems.

[0036] Specifically, when the physical connection of the extended function module is detected and identified as an access event by the system, the main computing module initiates an access request to the storage unit of the extended function module through the first configuration pin, which is predefined on the gold finger interface unit and dedicated to transmitting configuration information. The purpose is to obtain the module file information stored therein. After the main computing module reads the raw data of this information from the storage unit, it does not simply receive it, but parses it and precisely extracts several key predefined data fields. These fields include at least a module identifier that uniquely identifies the module, power consumption requirement information describing its power consumption characteristics, the number of high-speed input / output channels required to declare its data transmission bandwidth requirements, an interrupt mapping scheme that specifies how it communicates with the host via interrupts, and a driver configuration script containing customized software configurations for different operating systems. This parsed structured data is output, providing a direct basis for subsequent resource allocation and driver loading.

[0037] The first configuration pin refers to a specific set of pins on the gold finger interface that are physically and electrically defined specifically for transmitting low-speed, low-power configuration communication signals (such as I2C or SMBus). This is separate from the pins used for high-speed data services, ensuring the independence and reliability of the configuration channel. The module identifier is a globally unique code that identifies the type of the extended function module. It typically includes the manufacturer ID, device ID, and version number, which the system uses to determine the module type and load the corresponding support. Power consumption requirements describe the current or power consumption of the extended function module under different operating states, such as standby power consumption, average operating power consumption, and peak power consumption. This information guides the main computing module in making reasonable power allocation and management. The required number of high-speed input / output channels indicates the number of high-speed serial computer expansion bus channels that the main computing module needs to allocate to the module to achieve its nominal performance, such as four PCIe channels (x4). The interrupt mapping scheme refers to the allocation and mapping rules of the interrupt request lines used when the module requests the main computing module to process its asynchronous events, such as using MSI-X interrupts and their corresponding memory addresses. A driver configuration script is a piece of data or code that contains a series of hardware initialization commands and parameters. For a specific operating system kernel, it guides the system on how to correctly set the registers of the module so that it can enter a working state.

[0038] S1012. The power consumption requirement information and the required number of high-speed input / output channels are used as hardware resource requirements, and the configuration scripts of each driver are used as operating system adaptation information.

[0039] Specifically, the power consumption requirements and the number of required high-speed input / output channels are combined into a set called "hardware resource requirements." This set clearly defines the extension module's requirements for the underlying physical resources of the system. Simultaneously, the main computing module merges all the parsed driver configuration scripts (typically one script per target operating system) into another set called "operating system adaptation information." This set defines the configuration required for the module to function correctly at the software level. Through this step, the original, mixed module file information is refined and reorganized into two targeted, purpose-specific data sets for use in different subsequent system processes.

[0040] Based on the above embodiments, as an optional embodiment, the gold finger interface unit further includes a second configuration pin. Figure 2 Following step S101, the reconfigurable hardware kit control method further includes steps S201-S204, which will be described in detail below.

[0041] S201, the main computing module communicates bidirectionally with the extended function module through the second configuration pin to obtain the electrical parameter set corresponding to the various operating modes supported by the extended function module. The electrical parameter set includes the reference power supply requirement and the reference signal rate.

[0042] Specifically, after the main computing module recognizes the static identity and basic requirements of the module through the first configuration pin, the configuration process enters a more in-depth dynamic negotiation stage. The main computing module will activate another set of independent second configuration pins on the gold finger interface unit to establish a bidirectional communication link with the extended function module through this dedicated channel. On this link, the main computing module initiates a query request to the extended function module, and the extended function module responds to this request by returning the various levels of working modes it supports and their corresponding detailed electrical parameter sets to the main computing module. This allows the main computing module to fully obtain the range of optional working capabilities of the extended function module beyond its basic requirements, providing key data support for subsequently determining the optimal working mode.

[0043] The second configuration pin refers to a separate set of pins on the gold finger interface, distinct from the first configuration pin. This pair is physically and electrically defined as being dedicated to high-speed, differential signal negotiation communication (e.g., based on LVDS technology). It is independent of both the first configuration pin and the high-speed data pin, and is specifically used for transmitting negotiation messages with high real-time requirements and small data volumes. Bidirectional communication indicates an interactive dialogue between the main computing module and the extended function module, enabling question-and-answer or continuous information exchange, rather than a one-way read operation. This is implemented based on a lightweight, low-level point-to-point communication protocol. Multiple operating modes represent several discrete operating states preset by the extended function module to adapt to different performance, power consumption, and application scenarios. For example, a 5G communication module may support different levels such as energy-saving mode, standard performance mode, and extreme throughput mode; a vision processing module may include different levels such as high-precision real-time analysis mode and event-triggered detection mode; and a positioning module may include different levels such as multi-frequency multi-satellite high-precision mode, standard navigation mode, and periodic positioning mode. The electrical parameter set refers to a group of parameters closely tied to each specific operating mode, describing its core electrical characteristics. It serves as the direct basis for determining whether a mode can operate stably in the current system environment. The reference power supply requirement precisely indicates the typical voltage and current (or power) values ​​required for the extended functional module to operate normally under the corresponding specific operating mode, such as 1.8V and 2.5A. The reference signal rate is another key item in the electrical parameter set, precisely indicating the signal transmission rate that the physical link (such as a PCIe link) needs to achieve and maintain during high-speed data communication between the module and the host under the corresponding specific operating mode, such as 8.0GT / s.

[0044] S202. Obtain the real-time power supply requirements and real-time signal rate monitored by the main computing module.

[0045] Specifically, the main computing module continuously monitors and updates two key real-time system parameters. The first is the real-time power demand, which reflects the remaining power or current capacity that the power management subsystem can safely and stably provide to the new expansion module under the current total system load. The second is the real-time signal rate, which characterizes the highest data transmission rate that the target high-speed I / O link (such as the PCIe channel) can reliably establish and maintain under the current physical channel quality and system interference background. These two real-time data together constitute a profile of the system's resource supply capability.

[0046] The real-time power demand characterizes the current real-time power supply capability available on the main computing module side. It is a dynamically changing value, reflecting the remaining power / current margin that the power subsystem has after meeting the power consumption of existing modules, which can be allocated to new modules. For example, if the total system power rating is 200W and 150W has been consumed so far, then the real-time power supply capability is 50W. The real-time signal rate refers to the real-time signal rate that the current link on the main computing module side can support. It is not a fixed value, but rather a maximum stable rate that can be achieved under the current environment, determined through link training or signal integrity analysis, and is subject to physical characteristics such as channel loss, reflection, and crosstalk. For example, a PCIe 5.0 physical layer may only be able to negotiate a stable PCIe 4.0 rate (16GT / s) due to poor channel conditions.

[0047] S203. Based on real-time power supply demand and real-time signal rate, and matched with various electrical parameter sets, determine the target level operating mode. The target level operating mode is used to characterize the highest level operating mode where the reference power supply demand does not exceed the real-time power supply demand and the reference signal rate does not exceed the real-time signal rate.

[0048] Specifically, the real-time power supply requirements and real-time signal rates of the system are used as constraints. These are compared one by one with the baseline power supply requirements and baseline signal rates in the electrical parameter set corresponding to each operating mode obtained from the module side. The purpose of this comparison is to filter out all feasible operating modes, namely those whose baseline power supply requirements do not exceed the system's real-time power supply capacity and whose baseline signal rates do not exceed the system's real-time signal capacity. From all feasible modes, based on a predefined strategy (usually optimal performance), the highest-level mode is determined as the target-level operating mode. This mode is the best choice that maximizes the performance of the expansion module while ensuring system stability.

[0049] Among them, the target-level working mode is used to represent the actual working state of the extended function module that has been selected after rigorous system evaluation and is about to be configured, serving as a bridge between connectivity negotiation and hardware resource configuration.

[0050] Through the above embodiments, by sensing the system status in real time and accurately matching it with the module capabilities, the system dynamically allocates appropriate and optimal working levels to the expansion modules within the system stability boundary, ensuring that the system always maximizes the performance potential of each hardware component under the premise of safety and reliability, achieving a balance between stability and high performance, and improving the overall efficiency of the entire system.

[0051] S204. Based on the reference power supply requirements and reference signal rate of the target-level operating mode, update the power consumption requirements of hardware resources and the required number of high-speed input / output channels.

[0052] Specifically, based on the selected target-level operating mode, the main computing module extracts two core parameters from its corresponding electrical parameter set: the reference power supply requirement and the reference signal rate. Using these two precise parameter values, the relatively broad or maximum-capacity hardware resource requirements obtained in the initial analysis phase are updated. The reference power supply requirement is used to cover or replace the original power consumption requirement information. At the same time, based on the bandwidth requirement implied by the reference signal rate, the required number of high-speed input / output channels is derived and updated. This ensures that the requirement information used in subsequent resource allocation steps is a precise resource request that is completely matched with the current effective operating mode.

[0053] S102. Based on hardware resource requirements, allocate hardware resources to the extended function modules through the resource control unit.

[0054] Specifically, based on the updated and confirmed hardware resource requirements, the main computing module issues explicit resource allocation instructions to its internal resource control unit. As the unified manager of system hardware resources, the resource control unit receives these instructions and executes specific allocation operations, which involve allocating and binding specific physical resource fragments in the system's global resource pool to newly connected extended function modules, ensuring that the module obtains the exclusive or guaranteed hardware environment necessary for its normal operation.

[0055] The resource control unit is a hardware logic subsystem integrated into the main computing module. It is responsible for managing the topology and connectivity of all allocable high-speed I / O resources (such as PCIe lanes and SATA ports). It can receive software or firmware instructions and dynamically configure physical links. Hardware resources specifically refer to system-level physical resources that need to be dynamically allocated through the resource control unit. Its core is the high-speed input / output channel (such as PCIe Lanes), and it also includes the power and interrupt resources that are allocated in conjunction with it.

[0056] For example, the resource control unit receives an instruction to allocate hardware resources to a network card, with the following requirements: power consumption requirement of 10W and a requirement of 2 PCIe 3.0 high-speed input / output channels. The resource control unit first checks the system's PCIe resource pool, finds two free PCIe 3.0 channels, and electrically connects them to the slot where the network card is located via a switch array. Simultaneously, it instructs the power management unit to provide a power budget of up to 10W for the slot. After allocation, the network card can then exchange data at high speed with the system CPU through these two dedicated PCIe channels.

[0057] S103. In response to the module hot-plug event, based on the operating system adaptation information, initialize and load the driver for the extended function module so that the extended function module can be put into a usable state.

[0058] Specifically, when the system detects the insertion or removal of an extended function module during operation, a module hot-plug event is generated. In response, the operating system kernel or underlying firmware typically initializes and loads the extended function module based on operating system adaptation information obtained and stored in the module file beforehand. Initialization focuses on the hardware level, that is, configuring the module's specific registers according to the instructions in the driver configuration script, so that it exits the reset state and enters a basic working state that can be operated by software. Driver loading focuses on the software level, that is, loading the device driver kernel module that matches the current operating system into the system kernel space and binding the driver instance to the initialized hardware module. At this time, the extended function module enters the available state, which means that the hardware function of the module has been fully activated, and the operating system can now recognize, manage and use it through its driver.

[0059] Among them, module hot-plug events represent interrupt signals or system notifications generated when an extended function module is physically inserted or removed while the system is powered on and running. These are software signals that trigger the dynamic configuration and unloading process. Initialization refers to the most basic configuration of the programmable logic or controller on the extended function module, usually accomplished by reading and writing its memory-mapped registers. The purpose is to bring the hardware to a known and stable basic state, such as setting the operating mode, enabling the clock, and clearing interrupt flags. Driver loading refers to reading a piece of software code (device driver) specifically used to manage and control this particular hardware module from the storage device into memory and integrating it into the operating system kernel, making it part of the kernel and enabling it to directly operate the hardware. The available state represents the final target state of the extended function module after all software and hardware configurations are completed. In this state, the module is a functional device that has been successfully recognized by the operating system, resources have been allocated, and the driver is ready, and it can be discovered and invoked by upper-layer applications.

[0060] For example, on a running Linux server, a user inserts a dedicated encryption / decryption accelerator card. The system generates a hot-plug event. The kernel's udev mechanism is triggered, retrieving the card's operating system compatibility information, which includes a Linux-specific driver configuration script. The script's initialization commands are executed, configuring the accelerator card's DMA engine and interrupts via the PCIe configuration space. The corresponding kernel driver module is loaded using the insmod command. After successful driver binding, the accelerator card becomes visible in the system's device list, and applications can access its functions; at this point, the card is considered usable.

[0061] Through the above embodiments, users can add and configure new hardware without restarting the system, which greatly improves the maintainability, scalability and service continuity of the system. This automated process based on pre-stored configuration information eliminates errors and compatibility issues that may be caused by manually installing drivers and configuring system parameters, and ensures the consistency of hardware behavior across different instances, providing key software support for building highly dynamic and highly reliable edge computing and data center environments.

[0062] S104. In response to the task chain issued by the artificial intelligence application, the task chain is decomposed into a sequence of atomic operators through a dynamically reconfigurable computing unit. The sequence of atomic operators includes multiple different types of atomic operators.

[0063] Specifically, when upper-layer AI applications (such as object detection and speech recognition) need to execute a complex computational process, a complete task chain is sent to the underlying reconfigurable hardware suite. In response to this request, the dynamic reconfigurable computing unit receives the complete task chain description and, through its internal dedicated processing logic (such as a hardware task chain parser), performs in-depth analysis of the task chain, breaking down a large and complex task chain into a series of small, computationally indivisible basic computing units, i.e., atomic operators. All these atomic operators are organized according to their logical dependencies and execution order in the original task chain, forming an ordered list, i.e., an atomic operator sequence. Due to the complexity of the original task chain, this sequence naturally includes various types of atomic operators such as convolution, pooling, matrix multiplication, and activation functions.

[0064] In this context, the task chain issued by an AI application refers to a directed acyclic graph (DAG) generated by a software framework (such as TensorFlow or PyTorch) that describes a complete AI model or its continuous computational components. Nodes represent computational operations, and edges represent data flow. A dynamically reconfigurable computational unit (RMU) specifies the physical carrier performing the decomposition actions. It includes dedicated hardware optimized for efficient parsing of the computation graph, rather than relying on general-purpose CPUs for software parsing, thus achieving lower parsing latency. It is a system-on-a-chip (SoC) or IP core. An atomic operator sequence is an ordered list obtained after decomposition, representing the intermediate hardware representation of the task chain. Each item in the sequence is an atomic operator and its associated parameters and tensor information. Atomic operators represent computational operations considered the smallest scheduling and execution unit under a given hardware architecture. For example, for an NPU, its atomic operators might include 2D convolution, matrix multiplication, and ReLU activation.

[0065] Based on the above embodiments, as an optional embodiment, the dynamically reconfigurable computing unit includes a neural network processing component (NPU) and a hardware task chain parsing component, targeting... Figure 2The step S104 shown can be implemented through steps S1041-S1042, which will be explained in detail below.

[0066] S1041. The task chain is parsed by the hardware task chain parsing component to obtain the dependency analysis results of the task chain. The dependency analysis results are used to characterize the data dependency relationships in the task chain. The data dependency relationships include at least parallel branch relationships and serial dependency relationships.

[0067] Specifically, within the dynamically reconfigurable computing unit, its hardware architecture integrates two core sub-components: a neural network processing unit (NPU) responsible for performing computations and a hardware task chain parsing component responsible for understanding the task. When a task chain is fed into the unit, the hardware task chain parsing component is activated, acting as dedicated hardware logic for computation graph analysis. It performs high-speed parsing of the input task chain. This parsing process is not a simple instruction decoding, but rather analyzes the data flow between various operators in the task chain to obtain an intermediate representation called dependency analysis result. This representation characterizes the complex data dependencies within the entire task chain, explicitly indicating which operators' execution depends on the output data of other operators. This data dependency is subdivided into at least two basic modes: parallel branching, where multiple operators can execute simultaneously because there is no direct data dependency between them; and serial dependency, where an operator must wait for its predecessor operator to complete and output data before it can begin execution.

[0068] The Neural Processing Unit (NPU) refers to a collection of heterogeneous computing engines within a dynamically reconfigurable computing unit responsible for executing various neural network atomic operators (such as convolution and matrix multiplication). It typically includes scalar, vector, and tensor processing units. The hardware task chain parsing component refers to a parser implemented in the form of dedicated hardware circuits (such as state machines or custom processors). Its design goal is to analyze the computation graph structure with extremely low latency, significantly reducing task scheduling overhead compared to software parsing. Dependency analysis results are the direct output of the parsing process; they are metadata that does not contain actual computational data but precisely describes the flow order and constraints of computational data between operators. Data dependencies refer to the constraints on the execution order of operators determined by data flow; they are truth-value dependencies and determine the potential execution sequence of operators on the timeline. Parallel branch relationships are used to represent the relationships between operators on different branch paths in the computation graph that are independent of each other. Identifying these relationships is key to unlocking task-level parallelism and improving hardware utilization. Serial dependency is used to represent the relationship between operators in a computation graph that have direct data transfer. It defines the strict order in which computations must be performed and is the basis for ensuring the correctness of the computation results.

[0069] S1042. Based on the dependency analysis results, the task chain is decomposed into multiple atomic operators including the execution order, resulting in an atomic operator sequence.

[0070] Specifically, based on the strict sequential constraints (serial dependency) and the potential for simultaneous execution (parallel branching) between operators revealed by the analysis results, all atomic operators in the task chain are topologically sorted and scheduled. The task chain, which originally represented a graph structure, is decomposed and transformed into a linear list of multiple atomic operators with a clear execution order. This scheduling process ensures that in the final atomic operator sequence, no atomic operator is scheduled to be executed before its dependent predecessor operator, thus strictly adhering to the data dependency relationship. Finally, an atomic operator sequence that combines correctness and potential parallelism is obtained and can be directly consumed by the hardware execution engine.

[0071] The execution order refers to assigning a clear, logical execution position number or timestamp to each atomic operator in the sequence. This order is the key to ensuring the correctness of the calculation results and is the soul of the sequence. It defines the starting order of atomic operators. For operators with parallel branching relationships, the order in the sequence may be the same (indicating that they can be started in parallel), while for operators with serial dependencies, the order has a clear priority.

[0072] S105. Based on the computational characteristics of various atomic operators, configure a reconfigurable interconnection network in the dynamically reconfigurable computing unit.

[0073] Specifically, the computational characteristics of each atomic operator are extracted and modeled in detail. This mainly includes data dependencies (i.e., which operator's result is the input of another operator), parallelism (which operators can be executed simultaneously), and data flow (the source and destination of data). This analysis process is actually constructing a precise computational dataflow graph, where nodes represent atomic operators and directed edges represent data flow paths and dependencies between operators. Based on this constructed dataflow graph, the physical resources of a dynamically reconfigurable computing unit are configured. This computing unit contains a large number of processing elements (PEs) capable of performing different operations and a flexible reconfigurable interconnection network composed of switch matrices and multiplexers. Each atomic operator node in the dataflow graph is assigned to a specific processing element (PE) in the computing unit that can perform the corresponding function, and the state of the reconfigurable interconnection network is set according to the edges in the dataflow graph. For example, for each data dependency edge in the graph pointing from operator A to operator B, a series of... The control signals are sent to the corresponding switches and routing resources in the interconnection network. By opening specific data paths and closing other irrelevant paths, a physical data link is precisely established from the output port of the PE of layout operator A to the input port of the PE of layout operator B. When all edges in the data flow graph are transformed into physical connections in the interconnection network, the entire configuration process is completed. A highly efficient dedicated data processing circuit customized for a specific computing task is formed inside the dynamically reconfigurable computing unit. Data can flow directly and at high speed between various functional units according to the preset path without going through a general bus and complex addressing process, thereby greatly improving computing efficiency and energy efficiency.

[0074] The computational characteristics of various atomic operators refer to the key attributes used to describe the computational behavior of atomic operators, such as computational density (the ratio of computational operations to memory accesses), data parallelism (the number of data elements that can be processed simultaneously), data precision, and instruction type (multiplication-accumulation, logical operations, etc.). These characteristics determine which type of computing unit the operator is best suited to execute on. A reconfigurable interconnect network refers to a programmable interconnect architecture (such as Network-on-Chip, Crossbar) located inside the chip, connecting multiple computing units and data buffers. It is the physical basis for dynamically stitching together computing resources.

[0075] The above embodiments completely break through the limitations of traditional fixed pipeline architecture, enabling hardware resources to be dynamically reorganized according to rapidly changing computing tasks. By establishing optimal data paths for different types of operators, unnecessary data movement and global memory access are greatly reduced, thereby significantly reducing data access latency and power consumption.

[0076] Based on the above embodiments, as an optional embodiment, the NPU includes multiple scalar processing units (SPUs), tensor processing units (TPUs), and vector processing units (VPUs), targeting... Figure 2 The step S105 shown can be implemented through steps S1051-S1053, which will be explained in detail below.

[0077] S1051. Based on computational characteristics, determine the target processing element set of the atomic operator sequence. The target processing element set includes multiple target processing elements. One type of atomic operator corresponds to one or more target processing elements. The target processing elements are used to characterize any one of the processing elements in SPU, TPU and VPU.

[0078] Specifically, the NPU includes three heterogeneous processing elements: a scalar processing element (SPU) responsible for control flow and complex logic, a tensor processing element (TPU) responsible for large-scale matrix and convolution operations, and a vector processing element (VPU) responsible for data-parallel element-level operations. Based on the computational characteristics of each atomic operator (such as operation type, data parallelism, and precision requirements), the most suitable physical unit for execution is determined for a type of atomic operator in the sequence (such as all convolution operators). The set of all these selected units constitutes the target processing element set, which includes multiple target processing elements. This means that an atomic operator may be mapped to only one type of element (such as convolution being mapped to a TPU), or it may be mapped to one or more different types of elements working together (such as a complex activation function being completed jointly by a VPU and an SPU). The target processing element, as a higher-level functional unit, is used to characterize that it can be any of the processing elements among the SPU, TPU, and VPU physically.

[0079] Scalar Processing Units (SPUs) are processor cores specifically designed to process single data elements and complex control logic (such as loops and branches), typically performing task scheduling, data dependency management, and irregular computations. Tensor Processing Units (TPUs) are computational units highly optimized for multidimensional array (tensor) operations; they are arrays of multiply-accumulators running in parallel, specifically designed for computationally intensive operations such as convolution and matrix multiplication. Vector Processing Units (VPUs) are processing units employing a single-instruction-multiple-data architecture, capable of performing the same operation on a set of data (vectors), and adept at performing element-level transformations such as activation functions, pooling, and normalization.

[0080] For example, the system needs to process a sequence of atomic operators that includes matrix multiplication and the GELU activation function. Based on the computational characteristics: matrix multiplication is identified as a high-density tensor operation, so its target processing element is determined to be a TPU; the GELU function contains polynomial computations and is identified as a complex element-level transformation, so it is determined that it is jointly completed by a VPU (responsible for the core element computation) and an SPU (responsible for auxiliary coefficient computation and flow control).

[0081] S1052. Based on the target processing element set, establish the data path of each target processing element through a reconfigurable interconnection network.

[0082] Specifically, based on the defined set of target processing elements, connection configuration instructions are sent to the reconfigurable interconnect network. By programming and controlling the switching switches and routing paths within this network, dedicated data paths are established to connect each target processing element. These paths ensure that when performing computational tasks, data can flow directly and efficiently from the output port of one target processing element to the input port of another, or be transferred between the target processing element and external memory, thus forming an on-chip micronetwork optimized for the current specific task.

[0083] Establishing a data path refers to the specific actions of configuring the interconnection network, including but not limited to: setting the connectivity of crossbar switches, configuring the network-on-chip (NoC) routing table, and establishing bus-based time-division multiplexing channels to physically or logically form point-to-point communication links. A data path is a communication link established for transmitting data; it defines the data flow path and may have specific bit width, delay, and bandwidth characteristics; it is the lifeblood connecting computing nodes.

[0084] Through the above embodiments, isolated computing islands are connected into an organic whole through programmable bridges (data paths), forming a temporary virtual computing engine that is optimal for the current task. This reduces the number of times data is moved and the latency in various levels of cache or global memory, and avoids the bandwidth contention and bottleneck problems that may be caused by traditional shared bus architecture, thereby greatly improving data throughput and computing energy efficiency.

[0085] S1053. Based on data paths, connect atomic operators with data dependencies for configuring reconfigurable interconnected networks.

[0086] Specifically, based on these established physical data paths, a key connection operation is performed. This connection does not refer to the re-laying of physical lines, but rather to the explicit binding of atomic operators with data dependencies in the task chain to the corresponding physical data paths at the system scheduler or configuration management level. In essence, it is to allocate the corresponding physical transmission link (data path) to each edge (dependency) in the logical data flow graph, in order to finally complete the runtime configuration of the reconfigurable interconnection network. This enables the hardware to not only have physical connectivity, but also to be given a clear data flow semantic that is completely consistent with the logic of the computing task. Only at this point is the entire configuration process declared complete, and the hardware enters the standby execution state.

[0087] For example, suppose there is a data dependency between the atomic operator convolution (executed on TPU-1) and the atomic operator ReLU (executed on VPU-5) in the task chain (i.e., the output of convolution is the input of ReLU). A physical data path (e.g., path ID Path_7) is established between the output of TPU-1 and the input of VPU-5. The output data stream of the convolution operator is specified to be transmitted to the ReLU operator through Path_7 for the final network configuration to complete this task. Now, the hardware not only knows that TPU-1 and VPU-5 are connected, but also knows more clearly which specific data stream this path serves.

[0088] S106. Based on the computational characteristics of various atomic operators and the real-time task queue depth, generate system load prediction information.

[0089] Specifically, a comprehensive analysis is conducted based on two dimensions of information: firstly, the static computational characteristics of various atomic operators, reflecting the essence of computation; and secondly, the dynamic real-time task queue depth, reflecting the real-time system load. Key parameters related to power consumption and resource consumption (such as the theoretical number of execution cycles, memory access intensity, and typical power consumption values) are extracted from the computational characteristics. The real-time task queue depth is analyzed to identify the types, quantities, and order of operators to be executed in the queue. Through a built-in prediction model or algorithm, these two types of information are fused and calculated to dynamically generate a quantitative description of the load on key system components within a short future time window (e.g., hundreds of microseconds), i.e., system load prediction information. This information provides crucial decision-making basis for subsequent dynamic configuration.

[0090] The real-time task queue depth refers to the length and content of the sequence of atomic operators to be processed before the dynamically reconfigurable computing unit. It is a dynamic signal that changes over time and directly reflects the computational pressure the system will face. The system load prediction information is a structured dataset that includes at least: the expected power consumption curve of the NPU, the expected bandwidth utilization of the memory controller, and the expected data throughput of the high-speed I / O interface.

[0091] Based on the above embodiments, as an optional embodiment, for Figure 2 The step S106 shown can be implemented through steps S1061-S1066, which will be explained in detail below.

[0092] S1061. Based on the computational characteristics of various atomic operators, obtain the reference power consumption value of various atomic operators under standard voltage and frequency, as well as the historical memory access frequency of various atomic operators during historical execution.

[0093] Specifically, based on the computational characteristics of various atomic operators obtained through pre-analysis, two key basic parameters are obtained from a static, predefined configuration database or performance model. The first type of parameter is the baseline power consumption value of various atomic operators at standard voltage and frequency. This is a calibration value determined during chip design or rigorous calibration, characterizing the energy consumption of the operator's computational core itself under ideal conditions. The second type of parameter is the historical memory access frequency of various atomic operators during historical execution. This is an empirical indicator characterizing the frequency of the operator's access to the memory system, obtained through performance analysis tools during the model compilation stage or through past running statistics. Together, they constitute the static input baseline for load prediction.

[0094] The baseline power consumption value refers to a normalized value that characterizes the inherent power consumption characteristics of the atomic operator's computational logic after removing the effects of voltage and frequency scaling. It is typically measured or simulated at a fixed, standard voltage and frequency point and serves as a baseline for power consumption prediction. The standard voltage and frequency refer to a predefined reference operating point used for performance and power consumption calibration. The baseline power consumption values ​​of all operators are measured under this unified condition to ensure data comparability and consistency. Historical memory access frequency represents the average number of times a specific atomic operator initiates access requests to off-chip memory per unit time during past executions, or the total number of bytes accessed per execution, reflecting the operator's memory access intensity. Historical execution process refers to the background from which these memory access statistics are derived, typically obtained through performance profiling of the operator under different network models and input data.

[0095] S1062. Based on the real-time task queue depth, identify the type and number of atomic operators to be executed, and calculate the total baseline power consumption value of the current queue based on each baseline power consumption value and the preset weight set.

[0096] Specifically, based on the dynamic information of the real-time task queue depth, the system analyzes all atomic operators waiting to be executed in the task queue, identifies the type and number of atomic operators to be executed. For example, if there are 3 convolution operators, 5 ReLU operators, and 2 pooling operators in the queue, a weighted calculation is performed based on the baseline power consumption values ​​(i.e., the unit power consumption of each type of operator) obtained in the first step and a preset weight set. This calculation multiplies the number of each type of operator in the queue by its corresponding baseline power consumption value, and then considers its preset weight in the current system context (such as fine-tuning due to different data shapes). Finally, the power consumption contribution of all types of operators is summed to calculate the total baseline power consumption value of the current queue. This total value represents the theoretical total energy required to process all tasks in the current queue and compute the core part under standard voltage and frequency.

[0097] The preset weight set refers to a set of coefficients used to fine-tune the baseline power consumption value. These weights may take into account the impact of specific runtime parameters of the atomic operators (such as the specific size of the input / output tensors and the batch size) on the actual power consumption, making the estimation more accurate. For example, a large-size convolution operator has a higher weight than a small-size convolution operator. Calculating the total baseline power consumption value of the current queue is the final output action of this step, achieved through a weighted summation formula: Total baseline power consumption value = Σ(Number of operators of type i × Baseline power consumption value of operators of type i × Preset weights of operators of type i).

[0098] S1063. Based on historical memory access frequency and the type and number of atomic operators to be executed, predict the memory controller bandwidth configuration and interface data throughput in a preset future time window using a preset linear regression algorithm.

[0099] Specifically, based on previously acquired historical memory access frequencies and the types and quantities of atomic operators to be executed that have just been identified, these are used as core input features. These features are then fed into a pre-defined linear regression algorithm model. This model, trained using a large amount of performance profiling data during the system development phase, is able to establish a linear mapping relationship from operator type and quantity to memory and I / O load. After the algorithm runs, it predicts the bandwidth configuration required by the memory controller and the data throughput required by the interface (such as PCIe) in order to meet the data needs of all operators in the queue within a pre-defined future time window (e.g., the next few hundred microseconds). This set of predicted values ​​quantifies the pressure that the system interconnect and storage subsystems will face.

[0100] Among them, the preset linear regression algorithm is a statistical model that predicts output values ​​by linearly weighting and combining input features. Its model parameters (weights and biases) are obtained by training with performance data of different types of atomic operators under various input scales collected offline, and can be adjusted online based on actual performance feedback during runtime. The preset future time window refers to the length of the future time period covered by the prediction. This is an important hyperparameter, and its setting matches the system's control cycle and the execution granularity of the task. Memory controller bandwidth configuration refers to the predicted data transfer rate (e.g., XX GB / s) that the memory controller needs to provide to meet the data requests of the computing units without bottlenecks. Interface data throughput refers to the predicted total amount of data that needs to be transferred between the system and extended functional modules through high-speed interfaces (such as PCIe) within the preset future time window, or the average transfer rate that needs to be maintained.

[0101] For example, suppose the system identifies the atomic operators to be executed as including 5 convolutions (each with a historical memory access frequency of 1.2GB) and 10 ReLUs (each with a historical memory access frequency of 0.1GB). Using a trained linear regression algorithm (whose model may be simplified to: total bandwidth = Σ(number of atomic operators × memory access frequency of the atomic operator) × a preset coefficient), it predicts that in the next 1-millisecond time window, the required memory controller bandwidth configuration is 8.0GB / s, and the PCIe interface data throughput between the AI ​​accelerator card needs to reach 5.5GB / s.

[0102] S1064. Based on the memory controller bandwidth configuration and interface data throughput, calculate the power consumption increment value through a preset power consumption model.

[0103] Specifically, based on the two key load indicators of memory controller bandwidth configuration and interface data throughput predicted in the previous step, these parameters are used as core input parameters and input into a preset power consumption model. This model encapsulates the functional relationship between the power consumption of the memory controller and I / O interface and its workload (bandwidth and throughput). After the model runs, it will calculate a power consumption increment value. This power consumption increment value specifically refers to the additional dynamic power consumption of system components such as memory controller and I / O interface in order to support the data transfer requirements of the current computing task, in addition to the total baseline power consumption value (the theoretical power consumption of the computing core).

[0104] The preset power consumption model refers to a pre-established mathematical model or lookup table used to estimate the dynamic power consumption of hardware modules. It is typically built based on chip power consumption characteristic analysis or measured data. It can be a simple linear model (e.g., power increment = α × memory bandwidth + β × interface throughput) or a more complex nonlinear model considering voltage frequency. The model parameters (α, β) are pre-calibrated. The power increment value is a power value (e.g., in watts) used to represent the additional power consumption generated due to memory access and I / O data transfer activities on top of the total baseline power consumption. This expands the total power consumption prediction of the system from the simple computing core to the entire compute-storage-interconnect system.

[0105] For example, suppose the memory controller bandwidth needs to be configured to 10GB / s and the PCIe interface data throughput to be 6GB / s. Input these values ​​into a preset power consumption model. This model defines: memory controller power consumption increment = 0.15W / (GB / s) * bandwidth, PCIe interface power consumption increment = 0.1W / (GB / s) * throughput. The calculated power consumption increment is (0.15 * 10) + (0.1 * 6) = 1.5W + 0.6W = 2.1W. This 2.1W is the additional power consumed by the data transport subsystem beyond the calculated core power consumption.

[0106] S1065. Calculate the sum of the total reference power consumption value and the power consumption increment value to obtain the predicted power consumption value in the preset future time window.

[0107] Specifically, the total baseline power consumption value is directly added to the power consumption increment value, integrating the two separately predicted values ​​representing different power consumption sources into a unified and more representative total value. This results in a predicted power consumption value within a preset future time window. This final predicted power consumption value provides a single, clear quantitative indicator of the total power expected to be consumed by the entire reconfigurable hardware suite (including computing units, memory controllers, and high-speed I / O interfaces) while executing the current task queue within the upcoming preset future time window.

[0108] The predicted power consumption value is a power value (usually measured in watts, W), which is a final estimate of the total power consumption of the system within a preset future time window.

[0109] S1066. The memory controller bandwidth configuration, interface data throughput, and predicted power consumption are used together as system load prediction information.

[0110] Specifically, the three core prediction metrics obtained in the previous steps—memory controller bandwidth configuration (quantifying memory pressure), interface data throughput (quantifying I / O pressure), and predicted power consumption (quantifying total energy consumption)—are packaged, categorized, and output as a complete and structured system load prediction information. This process marks the end of the prediction phase, and the resulting system load prediction information becomes a comprehensive data package containing the system's load status across multiple key dimensions within a future time window, providing comprehensive and accurate input for performing forward-looking resource adjustments.

[0111] S107. Based on system load prediction information, dynamically configure the reconfigurable hardware kit through the hardware management unit.

[0112] Specifically, based on key parameters such as memory controller bandwidth configuration, interface data throughput, and predicted power consumption contained in the prediction information, specific control instructions are issued to the hardware management unit. The hardware management unit, as the dedicated logic responsible for executing the underlying hardware control in the system, parses these instructions and directly operates the corresponding hardware registers and control circuits to perform real-time dynamic configuration of the entire reconfigurable hardware suite (including the dynamically reconfigurable computing unit, memory controller, high-speed I / O interface, etc.). This configuration process is forward-looking and proactive, aiming to adjust the hardware state to the optimal operating point that matches the predicted load before the actual system load arrives.

[0113] The Hardware Management Unit (HMU) is the physical entity that performs configuration actions. It is a dedicated, high-privilege hardware control subsystem within the system, typically independent of the main computing pipeline, and responsible for power supply, clock, and thermal management. Dynamic configuration refers to a series of real-time operations that change the hardware's operating state. Its core components include, but are not limited to: voltage and frequency scaling: adjusting the voltage and frequency of the dynamically reconfigurable computing unit and its components based on predicted power consumption values; bandwidth allocation: adjusting the memory controller's arbitration strategy and clock frequency based on the memory controller's bandwidth configuration; and link management: adjusting the link width, speed, and power state of high-speed I / O interfaces based on interface data throughput.

[0114] For example, the hardware management unit receives a system load prediction information {memory bandwidth: 8.0GB / s, interface throughput: 5.5GB / s, total power consumption: 7.9W}. Based on this information, it performs dynamic configuration: First, it determines that the predicted power consumption value of 7.9W is lower than the current power consumption limit of the system, so it increases the operating frequency of the NPU by one level to pursue higher performance. At the same time, in order to ensure that the memory controller bandwidth is configured to 8.0GB / s, it sets the clock frequency of the memory controller to the corresponding mode. In order to meet the interface data throughput of 5.5GB / s, it wakes up the power state of the PCIe link from the low-power L1 state to the full-speed L0 state.

[0115] Through the above embodiments, a closed loop from perception and prediction to active control is realized. Instead of passively reducing frequency and limiting current after a performance bottleneck or overheating occurs, it is based on accurate prediction to configure hardware resources to the optimal state in advance. This ensures that the reconfigurable hardware kit can continuously and stably output its maximum possible computing performance under strict power consumption and heat dissipation constraints, thereby achieving the optimal balance between energy efficiency and performance and meeting the dual demanding requirements of edge intelligent devices for high performance and low power consumption.

[0116] Based on the above embodiments, as an optional embodiment, for Figure 2 The step S107 shown can be implemented through steps S1071-S1074, which will be explained in detail below.

[0117] S1071. Based on the memory controller bandwidth configuration, adjust the bandwidth, operating mode, and clock frequency of the main computing module's memory controller.

[0118] Specifically, for the memory subsystem, based on the memory controller bandwidth configuration parameters in the predicted information, specific control commands are generated, and several key operating parameters of the memory controller located in the main computing module are adjusted. These adjustments directly affect the hardware registers, first adjusting their bandwidth-related settings, which is usually achieved by changing the depth of the read / write queue, the prefetch strategy, and the priority of the arbitration algorithm to match the target bandwidth requirements. At the same time, its operating mode is adjusted, such as switching between low-latency mode and high-bandwidth mode, or enabling / disabling certain power-saving features, and dynamically adjusting its clock frequency. This is the most direct means of controlling bandwidth, linearly scaling its maximum data transfer capacity by increasing or decreasing the operating clock of the memory controller and its associated physical layer.

[0119] In this context, the memory controller of the main computing module specifically refers to the hardware unit integrated within the main computing module's SoC (System-on-a-Chip) that manages communication with off-chip dynamic memory (such as DRAM). Bandwidth refers to the actual data transfer rate that the memory controller can provide after configuration; adjusting bandwidth involves changing the efficiency and concurrent processing capabilities of its internal data paths. Operating modes refer to the different operating profiles supported by the memory controller, such as: performance-priority mode (disabling some power-saving functions to reduce access latency), power-saving mode (actively using clock gating and power gating), and automatic frequency adjustment mode (dynamically adjusting frequency and voltage based on load). Clock frequency refers to the clock signal frequency that drives the core logic of the memory controller and its interface with DRAM; increasing the clock frequency directly improves the controller's instruction processing speed and data throughput.

[0120] S1072. Based on the interface data throughput, adjust the link rate and power management status of the high-speed input / output interface between the main computing module and the extended function module through the resource control unit.

[0121] Specifically, based on the interface data throughput parameters in the predicted information, an instruction is issued to the resource control unit. As the direct manager of high-speed I / O resources, the resource control unit receives and executes the instruction, adjusting two key operating states of the high-speed input / output interface (such as the PCIe interface) connecting the main computing module and the extended functional module. This involves adjusting the link rate of the interface, i.e., dynamically switching the physical layer's operating speed level through the link training process (e.g., from 16.0GT / s in PCIe 4.0 to 8.0GT / s in PCIe 3.0, or vice versa), to match its data transmission capability with the predicted throughput demand. Simultaneously, the power management state of the interface is adjusted. For example, when the predicted throughput is low, it is switched from the active L0 state to the low-power L1 state to save energy; when a high throughput demand is predicted, it is woken up from the low-power state to the L0 state in advance to ensure the timeliness and integrity of data transmission.

[0122] High-speed input / output interfaces refer to standard interfaces used for high-speed data communication between the main computing module and extended functional modules, such as PCIe and CXL. Link rate refers to the number of signals transmitted per second on the physical link of this interface (e.g., GT / s, GigaTransferspersecond), which directly determines the theoretical peak bandwidth of the interface. Power management states refer to the different power consumption modes supported by the interface, such as L0 (full-function), L0s (fast wake-up low power), and L1 (deep low power) states defined by the PCIe standard. Different states involve trade-offs between power consumption and wake-up latency.

[0123] Through the above embodiments, fine-grained management of the energy efficiency of high-speed I / O interfaces is achieved. By dynamically adapting the link rate and power management status of the interface to the actual data transmission requirements, static power consumption waste caused by the interface always running in the highest performance mode is avoided, and the interface performance is prevented from becoming a system bottleneck.

[0124] S1073. If the predicted power consumption value is greater than the preset power consumption threshold, then look up the first frequency voltage combination corresponding to the power consumption value not exceeding the preset power consumption threshold in the preset frequency voltage configuration table, and reduce the operating voltage and operating frequency of the dynamic reconfigurable computing unit to the value corresponding to the first frequency voltage combination.

[0125] Specifically, when the hardware management unit determines that the predicted power consumption value exceeds the preset power consumption threshold specified by the system safety or energy efficiency strategy, it searches a preset frequency-voltage configuration table. This table pre-stores typical power consumption values ​​of the dynamically reconfigurable computing unit under various combinations of operating voltage and frequency. The goal of the search is to find the combination with the highest performance among all combinations where the power consumption value does not exceed the preset power consumption threshold. This combination is defined as the first frequency-voltage combination, and the operating voltage and frequency of the dynamically reconfigurable computing unit are immediately reduced to the values ​​corresponding to the first frequency-voltage combination. This is a coordinated adjustment process; the reduction in voltage provides stability for the reduction in frequency and also directly contributes to the reduction in power consumption.

[0126] The preset power consumption threshold refers to a power limit that is not allowed to be exceeded, determined by system design or runtime strategies, and may be based on thermal design power (TDP), power supply capacity, or energy efficiency targets. The preset frequency-voltage configuration table is a predefined lookup table that records the typical power consumption of dynamically reconfigurable computing units at different voltage frequency points (VFPoints), serving as the basis for voltage-frequency scaling (DVFS) decisions. The first frequency-voltage combination is the result of the lookup operation; it is a pair of specific values ​​representing the highest performance operating point that the system can maintain while satisfying power consumption constraints.

[0127] For example, assuming the preset power consumption threshold is 10W and the predicted power consumption is 12W, which is greater than the threshold, the system searches the preset frequency and voltage configuration table and finds that the power consumption of the combination (F=800MHz, V=0.75V) is 9.5W (not exceeding 10W), and its performance is higher than other combinations that meet the conditions. This is the first frequency and voltage combination. Then, the operating frequency of the dynamically reconfigurable computing unit is reduced to 800MHz and the operating voltage is reduced to 0.75V.

[0128] S1074. If the predicted power consumption value is less than or equal to the preset power consumption threshold, calculate the difference between the preset power consumption threshold and the predicted power consumption value to obtain the power consumption margin. Find the second frequency voltage combination corresponding to the power consumption increase value not exceeding the power consumption margin in the frequency voltage configuration table, and increase the operating voltage and operating frequency of the dynamic reconfigurable computing unit to the value corresponding to the second frequency voltage combination.

[0129] Specifically, when the hardware management unit determines that the predicted power consumption value is within the system's safe range (i.e., less than or equal to the preset power consumption threshold), it calculates the difference between the preset power consumption threshold and the predicted power consumption value. This difference is defined as the power consumption margin, which clearly quantifies the performance improvement space that the current system can still utilize under power consumption constraints. It then uses the frequency and voltage configuration table again to perform a lookup operation, but this time the lookup target is different from the previous one. It aims to find all possible frequency and voltage combinations whose corresponding power consumption increase value (i.e., the power consumption increment of the combination relative to the current operating point) does not exceed the power consumption margin just calculated. It then selects the highest-performing combination from these candidate combinations, which is defined as the second frequency and voltage combination. The operating voltage and operating frequency of the dynamically reconfigurable computing unit are then increased and set to the values ​​corresponding to the second frequency and voltage combination. This proactively and maximizes the improvement of system performance while ensuring that the total power consumption does not exceed the limit.

[0130] Here, the power consumption margin, calculated above, is a power value (unit: watts), representing the additional power the system can consume while meeting power consumption constraints. The power consumption increase is relative to the current operating point; the goal of the search is to find a new operating point within the power consumption margin that offers the greatest performance improvement. The second frequency-voltage combination is the result of this search operation, representing the new, higher performance operating point the system can achieve after fully utilizing the power consumption margin.

[0131] The reconfigurable hardware kit control device in the embodiments of this invention is described below from the perspective of hardware processing. Please refer to [link / reference needed]. Figure 3 , Figure 3 This is a schematic diagram of the structure of a reconfigurable hardware kit control device provided in an embodiment of this application.

[0132] It should be noted that, Figure 3 The structure of the reconfigurable hardware kit control device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0133] like Figure 3 As shown, the reconfigurable hardware suite control device includes a central processing unit 301, which can perform various appropriate actions and processes based on a program stored in read-only memory 302 or a program loaded from storage section 308 into random access memory 303, such as performing the methods described in the above embodiments. The random access memory 303 also stores various programs and data required for system operation. The central processing unit 301, read-only memory 302, and random access memory 303 are interconnected via bus 304. Input / output interface 305 is also connected to bus 304.

[0134] The following components are connected to the input / output interface 305: an input section 306 including audio input devices, push-button switches, etc.; an output section 307 including a liquid crystal display (LCD) and audio output devices, indicator lights, etc.; a storage section 308 including a hard disk, etc.; and a communication section 309 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 309 performs communication processing via a network such as the Internet. A drive 310 is also connected to the input / output interface 305 as needed. A removable medium 311, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 310 as needed so that computer programs read from it can be installed into the storage section 308 as needed.

[0135] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing a computer program for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 309, and / or installed from removable medium 311. When the computer program is executed by central processing unit 301, it performs the various functions defined in the present invention. It should be noted that specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0136] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, program segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those shown in the drawings.

[0137] Specifically, the reconfigurable hardware kit control device in this embodiment includes a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements the reconfigurable hardware kit control method provided in the above embodiment.

[0138] In another aspect, the present invention also provides a computer-readable storage medium, which may be included in the reconfigurable hardware kit control device described in the above embodiments; or it may exist independently and not assembled into the reconfigurable hardware kit control device. The storage medium carries one or more computer programs that, when executed by a processor of the reconfigurable hardware kit control device, cause the reconfigurable hardware kit control device to implement the reconfigurable hardware kit control method provided in the above embodiments.

[0139] The above description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of other embodiments of this disclosure upon considering the specification and the disclosure of practical truth. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure. The specification and embodiments are considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A control method for a reconfigurable hardware kit, applied to a reconfigurable hardware kit, characterized in that, The reconfigurable hardware kit includes a main computing module and at least one extended functional module. The main computing module includes a dynamically reconfigurable computing unit, a hardware management unit, and a resource control unit. The extended functional module includes a gold finger interface unit and a storage unit. The method includes: In response to the access event of the extended function module, the main computing module reads and parses the module file information in the storage unit through the gold finger interface unit to obtain hardware resource requirements and operating system adaptation information. The module file information is used to store the configuration data of the extended function module. Based on the hardware resource requirements, hardware resources are allocated to the extended function module through the resource control unit. In response to a module hot-plug event, the extended function module is initialized and its driver is loaded based on the operating system adaptation information, so that the extended function module can be put into a usable state. In response to the task chain issued by the artificial intelligence application, the task chain is decomposed into a sequence of atomic operators by the dynamically reconfigurable computing unit, and the sequence of atomic operators includes multiple different types of atomic operators; Based on the computational characteristics of the various atomic operators, a reconfigurable interconnection network is configured in the dynamically reconfigurable computing unit; Based on the computational characteristics of various atomic operators and the real-time task queue depth, system load prediction information is generated. Based on the system load prediction information, the reconfigurable hardware suite is dynamically configured through the hardware management unit.

2. The method according to claim 1, characterized in that, The gold finger interface unit includes a first configuration pin. In response to the access event of the extended function module, the main computing module reads and parses the module file information in the storage unit through the gold finger interface unit to obtain hardware resource requirements and operating system compatibility information, including: In response to the access event, the main computing module accesses the module file information of the storage unit through the first configuration pin. The module file information includes at least the module identifier, power consumption requirement information, the number of required high-speed input / output channels, interrupt mapping scheme, and driver configuration scripts for different operating systems. The power consumption requirement information and the required number of high-speed input / output channels are used as the hardware resource requirements, and each of the driver configuration scripts is used as the operating system adaptation information.

3. The method according to claim 2, characterized in that, The gold finger interface unit further includes a second configuration pin. After the main computing module reads and parses the module file information in the storage unit through the gold finger interface unit to obtain hardware resource requirements and operating system adaptation information in response to the access event of the extended function module, the method further includes: The main computing module communicates bidirectionally with the extended function module through the second configuration pin to obtain the electrical parameter set corresponding to the various operating modes supported by the extended function module. The electrical parameter set includes the reference power supply requirement and the reference signal rate. Obtain the real-time power demand and real-time signal rate monitored by the main computing module; Based on the real-time power supply requirement and the real-time signal rate, and matched with each set of electrical parameters, a target level operating mode is determined. The target level operating mode is used to characterize the highest level operating mode in which the reference power supply requirement does not exceed the real-time power supply requirement and the reference signal rate does not exceed the real-time signal rate. Based on the reference power supply requirements and the reference signal rate of the target level operating mode, update the power consumption requirements and the required number of high-speed input / output channels for the hardware resources.

4. The method according to claim 1, characterized in that, The dynamically reconfigurable computing unit includes a neural network processing unit (NPU) and a hardware task chain parsing component. In response to a task chain issued by an artificial intelligence application, the dynamically reconfigurable computing unit decomposes the task chain into a sequence of atomic operators, including: The task chain is parsed by the hardware task chain parsing component to obtain the dependency analysis results of the task chain. The dependency analysis results are used to characterize the data dependency relationships in the task chain. The data dependency relationships include at least parallel branch relationships and serial dependency relationships. Based on the dependency analysis results, the task chain is decomposed into multiple atomic operators including the execution order, resulting in the atomic operator sequence.

5. The method according to claim 4, characterized in that, The NPU includes multiple scalar processing units (SPUs), tensor processing units (TPUs), and vector processing units (VPUs). Based on the computational characteristics of the various atomic operators, a reconfigurable interconnect network is configured in the dynamically reconfigurable computing unit, including: Based on the computational characteristics, a set of target processing elements for the atomic operator sequence is determined. The set of target processing elements includes multiple target processing elements. One type of atomic operator corresponds to one or more target processing elements. The target processing elements are used to characterize any one of the SPU, TPU, and VPU. Based on the set of target processing elements, a data path for each of the target processing elements is established through the reconfigurable interconnection network; Based on the data path, atomic operators with the data dependencies are connected to configure the reconfigurable interconnect network.

6. The method according to claim 1, characterized in that, The generation of system load prediction information based on the computational characteristics of various atomic operators and the real-time task queue depth includes: Based on the computational characteristics of the various atomic operators, the reference power consumption values ​​of the various atomic operators under standard voltage and frequency, and the historical memory access frequencies of the various atomic operators during historical execution are obtained. Based on the real-time task queue depth, the type and number of atomic operators to be executed are identified, and the total baseline power consumption value of the current queue is calculated based on each baseline power consumption value and the preset weight set. Based on the historical memory access frequency and the type and number of atomic operators to be executed, the memory controller bandwidth configuration and interface data throughput in a preset future time window are predicted by a preset linear regression algorithm. Based on the memory controller bandwidth configuration and the interface data throughput, the power consumption increment is calculated using a preset power consumption model. The sum of the total reference power consumption value and the power consumption increment value is calculated to obtain the predicted power consumption value in the preset future time window; The memory controller bandwidth configuration, the interface data throughput, and the predicted power consumption value are used together as the system load prediction information.

7. The method according to claim 6, characterized in that, The step of dynamically configuring the reconfigurable hardware suite through the hardware management unit based on the system load prediction information includes: Based on the memory controller bandwidth configuration, adjust the bandwidth, operating mode, and clock frequency of the memory controller of the main computing module; Based on the interface data throughput, the link rate and power management status of the high-speed input / output interface between the main computing module and the extended function module are adjusted by the resource control unit. If the predicted power consumption value is greater than the preset power consumption threshold, then the first frequency voltage combination corresponding to the power consumption value not exceeding the preset power consumption threshold is searched in the preset frequency voltage configuration table, and the operating voltage and operating frequency of the dynamic reconfigurable computing unit are reduced to the value corresponding to the first frequency voltage combination. If the predicted power consumption value is less than or equal to the preset power consumption threshold, the difference between the preset power consumption threshold and the predicted power consumption value is calculated to obtain the power consumption margin. The second frequency voltage combination corresponding to the power consumption increase value not exceeding the power consumption margin is found in the frequency voltage configuration table, and the operating voltage and operating frequency of the dynamic reconfigurable computing unit are increased to the values ​​corresponding to the second frequency voltage combination.

8. A reconfigurable hardware kit control device, characterized in that, The reconfigurable hardware suite control device includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code including computer instructions, and the one or more processors invoke the computer instructions to cause the reconfigurable hardware suite control device to perform the method as described in any one of claims 1-7.

9. A computer-readable storage medium comprising instructions, characterized in that, When the instructions are executed on a reconfigurable hardware suite control device, the reconfigurable hardware suite control device performs the method as described in any one of claims 1-7.

10. A computer program product, characterized in that, When the computer program product is run on a reconfigurable hardware kit control device, the reconfigurable hardware kit control device performs the method as described in any one of claims 1-7.

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