Control method based on self-adaptive storage backplane, self-adaptive storage backplane and device

Abstract

The invention relates to a control method based on a self-adaptive storage backboard, the self-adaptive storage backboard and a device, and the method comprises the steps: collecting a side-band signal, an out-of-band signal and the state of a PCIe link training and state machine when a slot insertion or topology change event is detected, and carrying out the analysis and processing of the signals, and obtaining a recognition result of a slot; configuring a high-speed differential cross matrix of the storage backboard based on a slot identification result so as to switch slot attribution among a plurality of main control domains of a channel, splicing and binding or splitting the channel width as required, and performing sequence adjustment and polarity remapping on the channel; a reference clock source of the slot is switched to a matching mode in a burr-free mode through a phase alignment and gating technology; obtaining a link margin of the PCIe link and an equalizer parameter, and writing the link margin and the equalizer parameter into a nonvolatile memory to form a slot portrait; and completing the power supply and power-on of the slot under the control of the pre-charging and eFuse device. According to the invention, on the premise of supporting multi-protocol mixed insertion, the signal quality and reliability are ensured at the same time.

Description

Technical Field

[0001] This invention relates to the field of computer storage hardware technology, and in particular to a control method, adaptive storage backplane, and device based on an adaptive storage backplane. Background Technology

[0002] With the explosive growth of cloud computing, big data, and artificial intelligence services, servers and storage systems have placed rigid demands on backplanes for "multi-protocol mixing, high bandwidth, high reliability, and zero-interruption maintenance." Traditional storage backplanes are typically designed with hard-wired connections for a single protocol (SAS or NVMe), with fixed mappings between slots and controller ports, immutable channel widths, and clock modes, signal integrity parameters, and power supply timings all set at the factory. When services require expansion, upgrades, or replacement with hard drives of different protocols or speed levels, the entire system must be powered off, jumpers / DIP switches manually adjusted, or even the entire backplane replaced, leading to service interruptions, high maintenance costs, and low resource utilization.

[0003] To alleviate these pain points, existing technologies attempt to introduce an "automatic protocol identification" function on the motherboard side or within the HBA / RAID card: determining the type of inserted device by detecting the PCIe link training state machine or out-of-band signals, and then reallocating port resources via the BIOS or HBA firmware. However, this type of solution has the following drawbacks: multi-protocol compatibility mainly relies on the main control side, and the backplane lacks autonomy; the high-speed channel topology is fixed, resulting in insufficient resource utilization and scalability; clock and signal integrity control are disconnected, making it difficult to maintain high generational speed capabilities in multi-protocol environments; and power supply hot-swapping control is decoupled from protocol switching, posing a risk of glitches and surges affecting high-speed links. Summary of the Invention

[0004] This invention provides a control method, an adaptive storage backplane, and a device based on an adaptive storage backplane, aiming to solve at least one of the technical problems existing in the prior art.

[0005] The technical solution of this invention is a control method based on an adaptive storage backplane, which includes: Insertion and removal detection and protocol identification are performed on the storage backplane. When a slot insertion or topology change event is detected, sideband signals, out-of-band signals, and the status of PCIe link training and state machine are collected. The sideband signal, the out-of-band signal, the PCIe link training and state machine state are identified and analyzed to obtain the identification result of the slot; Based on the identification results of the slots, the high-speed differential cross matrix of the storage backplane is configured to switch the slot affiliation of channels between multiple master control domains, to perform splicing or splitting of channel widths as needed, and to adjust the channel order and remap polarity. Based on the PCIe link training and state machine state, the reference clock source of the slot is switched to the matching mode without glitches through phase alignment and gating technology. Obtain the link margin and equalizer parameters of the PCIe link, and write the link margin and equalizer parameters to a field replaceable unit or non-volatile memory to form a slot profile. Based on the slot profile, the slot is powered on under the control of pre-charging and eFuse devices.

[0006] According to some embodiments of the present invention, the sideband signals include interface detection signals, serial general-purpose I / O signals, sleep signals, reset signals, and clock request signals, and the out-of-band signals include disk link initialization signals and wake-up signals. The process of identifying and analyzing the sideband signal, the out-of-band signal, the PCIe link training, and the state machine to obtain the slot identification result includes: The sideband signal acquisition unit performs debouncing processing on the interface detection signal, the serial general-purpose I / O signal, the sleep signal, the reset signal, and the clock request signal, and determines the stability of each signal's state. The envelope shape and time interval of the initialization signal and wake-up signal on the hard disk link are detected by simulating the front-end circuit through the out-of-band signal envelope detection unit. The state transition process of the PCIe link training state machine is monitored and analyzed within a preset time window using a timing sampling unit, and the state analysis results of the PCIe link training and state machine are obtained. The interface detection signal after debouncing, serial general-purpose I / O signal, sleep signal, reset signal, clock request signal, initialization signal and wake-up signal on the hard disk link, as well as the state analysis results of the PCIe link training and state machine are comprehensively analyzed to obtain the target protocol type, channel width and rate level of the slot, and output the plug-in / plug-out event and re-judgment window control signal.

[0007] According to some embodiments of the present invention, the high-speed differential cross matrix of the storage backplane is configured based on the slot identification result to achieve the following: switching the slot affiliation of channels among multiple master control domains, performing concatenation or splitting of the channel width as needed, and adjusting the channel order and remapping polarity. Based on the slot identification results, the high-speed differential cross matrix of the storage backplane is configured so that the high-speed differential cross matrix supports the switching of slot affiliation between the PCIe domain and the SAS domain, and realizes that the same slot can be mapped to the CPU root port, PCIe switching chip or SAS HBA / RAID controller, so as to realize dynamic multiplexing of channel resources and multi-protocol mixed insertion. Based on the channel width in the slot identification result, several x4 channels can be combined into an x8 channel according to actual needs, or the x8 channel can be split into multiple x4 channels. An internal programmable switch network is formed by mapping each pair of high-speed differential channels to the memory backplane slots. The MCU / CPLD controls the on / off state of the internal programmable switch network through registers to remap the channel order and polarity to adapt to the wiring constraints of the motherboard and memory backplane.

[0008] According to some embodiments of the present invention, the step of switching the reference clock source of the slot to a glitched matching mode without glitches, based on the identification result of the slot and the state of the PCIe link training and state machine, through phase alignment and gating technology, includes: Obtain the training and state machine status of the PCIe link; When the PCIe link training and state machine are in polling or recovery state, open the always-toggle window; By using phase alignment and gated output circuitry, the reference clock source used by the slot can be smoothly switched from the independent spread spectrum clock separation reference clock mode to the separation reference clock mode without spread spectrum clock, or from the separation reference clock mode without spread spectrum clock back to the independent spread spectrum clock separation reference clock mode.

[0009] According to some embodiments of the present invention, obtaining the link margin and equalizer parameters of the PCIe link, and writing the link margin and equalizer parameters to a non-volatile memory to form a slot profile includes: Using the clock restorer or signal repeater on the storage backplane as the core, online signal integrity testing is performed; The link margin of the PCIe link is obtained, and the parameters of the continuous-time linear equalizer, decision feedback equalizer, and transmitter pre-emphasis equalizer are automatically adjusted according to the test results of the signal integrity test. The final stable parameters are written into the field replaceable unit or non-volatile memory to form a slot profile.

[0010] According to some embodiments of the present invention, the step of automatically adjusting the continuous-time linear equalizer, decision feedback equalizer, and transmitter pre-emphasis equalizer parameters based on the test results of the signal integrity test, and writing the final stable parameters into a field-replaceable unit or non-volatile memory to form a slot profile, includes: If the maintenance window or business load allows, start the equalizer adaptive process to inject a pseudo-random binary sequence into the target channel or use the running data to perform bit error rate and eye diagram margin statistics. Based on the current bit error rate and eye diagram metrics obtained from the test, determine whether the link margin of the PCIe link meets the preset threshold. When the link margin of the PCIe link does not meet the preset threshold, the equalizer parameter adjustment step is entered. The continuous time linear equalizer, the decision feedback equalizer and the transmitter pre-emphasis equalization parameters are iteratively optimized, and the online testing and evaluation steps are repeated. When the link margin of the PCIe link meets the preset threshold, the converged equalizer parameters are written to the field replaceable unit or non-volatile memory bound to the slot to form a signal integrity profile for that slot.

[0011] According to some embodiments of the present invention, the step of powering on the slot based on the slot profile under the control of pre-charging and eFuse devices includes: Upon detecting the insertion signal of the storage backplane, the pre-charge circuit is activated to provide a soft start for the load of the slot; After pre-charging is completed and it is confirmed that there is no short circuit in the slot, the eFuse device is closed to provide main power supply, and the power supply to the slot is powered on based on the slot profile. If an overcurrent or short circuit is detected during power-on, disconnect the eFuse device and record the fault information.

[0012] This invention also relates to an adaptive storage backplane for executing the control method based on the adaptive storage backplane described in the above embodiments, comprising: The protocol identification module is used to perform insertion / removal detection and protocol identification on the storage backplane. When a slot insertion or topology change event is detected, it collects sideband signals, out-of-band signals, and the status of the PCIe link training and state machine. It then identifies and analyzes the sideband signals, out-of-band signals, and the status of the PCIe link training and state machine to obtain the identification result of the slot. The cross-matrix module is used to configure the high-speed differential cross-matrix of the storage backplane based on the identification result of the slot, so as to realize the switching of the slot affiliation of the channel between multiple master control domains, the splicing or splitting of the channel width as needed, and the adjustment of channel order and polarity remapping. The clock management module is used to switch the reference clock source of the slot to a glitched matching mode without glitches, based on the state of the PCIe link training and state machine, through phase alignment and gating technology. An adaptive module is used to obtain the link margin and equalizer parameters of the PCIe link, and write the link margin and equalizer parameters to a field replaceable unit or non-volatile memory to form a slot profile. The power supply and hot-swap control module is used to power on the slot based on the slot profile and under the control of the pre-charge and eFuse devices.

[0013] According to some embodiments of the present invention, the adaptive storage backplane further includes a control and monitoring unit. The motherboard BMC of the storage backplane communicates bidirectionally with the control and monitoring unit through an I²C bus, a PMBus bus, and / or a GPIO interface. The control and monitoring unit is connected to the protocol identification module, the cross-matrix module, the clock management module, the adaptive module, and the power supply and hot-swap control module through a control bus. The control and monitoring unit is used to issue configuration commands to each module and collect the operating status, alarm information, and self-test results of each module. The control and monitoring unit is an MCU or a CPLD.

[0014] The present invention also relates to a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the above-described method.

[0015] The control method, adaptive storage backplane, and device based on adaptive storage backplane provided in this invention have at least one of the following advantages or beneficial effects: When a new module is inserted into a slot on the storage backplane or a topology change occurs, a detection mechanism is triggered. This mechanism collects sideband signals, out-of-band signals, and the status of the PCIe link training and state machine in real time. By processing and analyzing these signals and statuses, the slot identification result is obtained. The entire identification process does not rely on the motherboard firmware; it can complete the identification and adaptive configuration of multiple protocols on the storage backplane side. Based on the slot identification result, channels are dynamically switched between multiple master control domains to achieve flexible resource allocation. Channel widths can be bundled (merging multiple channels) or split as needed to adapt to the requirements of different modules and improve channel resource utilization. Signal transmission performance is optimized by adjusting the channel order and remapping polarity.

[0016] Based on the PCIe link training and state machine state, phase alignment and gating techniques are used to switch the slot's reference clock source to matched mode. This ensures signal stability and continuity during clock source switching, avoiding signal jitter or interruption, significantly reducing the impact of switching on link training, and lowering the probability of spurious training and link instability. The PCIe link's link margin and equalizer parameters are acquired and written to field-replaceable units or non-volatile memory. Slot configuration information and performance parameters are recorded to form a slot profile. This slot profile enables rapid restoration to an optimal configuration during equipment replacement or protocol switching, facilitating subsequent management and optimization. Powering up the slot is completed under the control of pre-charging and eFuse devices (electronic fuses). Pre-charging before formal power supply avoids current surges, provides overcurrent protection, and ensures the safety of the power supply process.

[0017] By automating detection, identification, and configuration, dynamic management and optimization of storage backplane slots are achieved. This not only improves the flexibility and reliability of the control method, but also facilitates subsequent maintenance and management through parameter storage and slot profiling. This technology has significant application value in fields such as high-performance computing and data centers.

[0018] Furthermore, additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] Figure 1 This is a general flowchart of the control method based on adaptive storage backplane provided in the embodiments of the present invention; Figure 2 This is a detailed flowchart of step S200 in the control method based on adaptive storage backplane provided in the embodiment of the present invention; Figure 3 This is a detailed flowchart of step S300 in the control method based on adaptive storage backplane provided in the embodiment of the present invention; Figure 4 This is a detailed flowchart of step S400 in the control method based on adaptive storage backplane provided in the embodiment of the present invention; Figure 5 This is a timing diagram of the dynamic switching of the reference clock source for PCIe training and state machine awareness provided in an embodiment of the present invention; Figure 6 This is a detailed flowchart of step S500 in the control method based on adaptive storage backplane provided in the embodiment of the present invention; Figure 7 This is a detailed flowchart of step S520 in the control method based on adaptive storage backplane provided in the embodiment of the present invention; Figure 8This is a detailed flowchart of step S600 in the control method based on adaptive storage backplane provided in the embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of the adaptive storage backplane provided in an embodiment of the present invention. Detailed Implementation

[0020] The following will provide a clear and complete description of the concept, specific structure, and technical effects of the present invention in conjunction with the embodiments and accompanying drawings, so as to fully understand the purpose, solution, and effects of the present invention.

[0021] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. The singular forms "a," "described," and "the" used herein are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and not for limiting the invention. The term "and / or" as used herein includes any combination of one or more of the associated listed items.

[0022] It should be understood that although the terms first, second, third, etc., may be used to describe various elements in this disclosure, these elements should not be limited to these terms. These terms are used only to distinguish elements of the same type from one another. For example, a first element may also be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element may also be referred to as a first element. Any and all instances or exemplary language (“e.g.,” “such as,” etc.) provided herein are intended only to better illustrate embodiments of the invention and, unless otherwise required, do not impose a limitation on the scope of the invention.

[0023] This invention provides a control method, adaptive storage backplane, and device based on an adaptive storage backplane. It can accurately identify the protocol type of storage devices and, driven by the identification results, complete high-speed channel topology reconstruction, clock mode switching, signal integrity parameter adaptation, and power supply hot-plug timing coordination. Thus, while supporting multi-protocol mixing, it ensures signal quality and system reliability at high generational speeds.

[0024] Please refer to the following. Figures 1 to 9 The following description further illustrates the control method, adaptive storage backplane, and device based on the adaptive storage backplane provided in the embodiments of the present invention.

[0025] Reference Figure 1 As shown, Figure 1This is a general flowchart of the control method based on an adaptive storage backplane provided in this embodiment of the invention. The control method based on an adaptive storage backplane includes, but is not limited to, steps S100 to S600. Specifically, S100: Performs insertion and removal detection and protocol identification on the storage backplane. When a slot insertion or topology change event is detected, it collects sideband signals, out-of-band signals, and the status of the PCIe link training and state machine. S200: Identifies and analyzes the state of sideband signals, out-of-band signals, PCIe link training, and state machines to obtain the slot identification results; S300: Based on the slot identification results, the high-speed differential cross matrix of the storage backplane is configured to switch the slot affiliation of channels between multiple master control domains, to perform splicing or splitting of channel width as needed, and to adjust the channel order and remap polarity. S400: Based on PCIe link training and state machine state, the reference clock source of the slot is switched to the matching mode without glitches through phase alignment and gating technology; S500: Obtain the link margin and equalizer parameters of the PCIe link, and write the link margin and equalizer parameters to the field replaceable unit or non-volatile memory to form a slot profile. S600: Based on the slot profile, it completes the power supply to the slot under the control of pre-charge and eFuse devices.

[0026] In some embodiments of the present invention, the control method based on an adaptive storage backplane includes: triggering a detection mechanism when a new module is inserted into a slot on the storage backplane or when a topology change occurs; and real-time acquisition of sideband signals, out-of-band signals, and the status of the PCIe link training and state machine. It is understood that sideband signals are used for low-speed control and status indication, out-of-band signals are used for device management, configuration, and status monitoring, and the status of the PCIe link training and state machine reflects the current operating status of the link. Through analysis of the above signals and statuses, the slot identification result is obtained. The entire identification process does not rely on a specific HBA or motherboard firmware; the identification and adaptive configuration of protocols such as NVMe / SAS / SATA can be completed on the storage backplane side, reducing system platform binding and improving backplane reusability.

[0027] Based on slot identification results, channels are dynamically switched between multiple master control domains to achieve flexible resource allocation. Channel widths are bundled (merging multiple channels) or split as needed to adapt to the requirements of different modules and improve channel resource utilization. Signal transmission performance is optimized through channel order adjustment and polarity remapping.

[0028] Based on PCIe link training and state machine states, the reference clock source of the slot is switched to matching mode through phase alignment and gating technology. This ensures the stability and continuity of the signal during clock source switching, avoids signal jitter or interruption, significantly reduces the impact of switching on link training, and reduces the probability of spurious training and link instability.

[0029] The system acquires the link margin and equalizer parameters of the PCIe link, writes these parameters to a field-replaceable unit or non-volatile memory, and records the slot configuration information and performance parameters to create a slot profile. This slot profile enables rapid restoration to an optimal configuration during equipment replacement or protocol switching, facilitating subsequent management and optimization. Powering on the slot is completed under the control of pre-charging and eFuse devices (electronic fuses). Pre-charging before formal power supply avoids current surges, provides overcurrent protection, and ensures the safety of the power supply process.

[0030] By automating detection, identification, and configuration, dynamic management and optimization of storage backplane slots are achieved. This not only improves system flexibility and reliability but also facilitates subsequent maintenance and management through parameter storage and slot profiling. This technology has significant application value in high-performance computing, data centers, and other fields.

[0031] Reference Figure 2 As shown, Figure 2 This is a detailed flowchart of step S200 in the control method based on adaptive storage backplane provided in this embodiment of the invention. Step S200 includes, but is not limited to, steps S210 to S240. Specifically, S210: The sideband signal acquisition unit performs debouncing processing on the interface detection signal, serial general-purpose I / O signal, sleep signal, reset signal and clock request signal respectively, and judges the stability of the state of each signal; S220: The envelope shape and time interval of the initialization signal and wake-up signal on the hard disk link are detected by the out-of-band signal envelope detection unit to simulate the front-end circuit. S230: Use the timing sampling unit to monitor and analyze the state transition process of the PCIe link training state machine within a preset time window, and obtain the state analysis results of the PCIe link training and state machine; S240: Performs comprehensive analysis on the debouncing interface detection signals, serial general-purpose I / O signals, sleep signals, reset signals, clock request signals, hard disk link initialization signals and wake-up signals, as well as the state analysis results of PCIe link training and state machine, to obtain the target protocol type, channel width and rate level of the slot, and outputs plug-in / plug-out events and re-judgment window control signals.

[0032] In some embodiments of the present invention, the identification and analysis of sideband signals, out-of-band signals, PCIe link training, and state machine status are performed to obtain the slot identification results. These results include: by fusing multi-source information such as sideband signal acquisition, out-of-band signal envelope detection, link training, and state machine timing sampling, the protocol type (NVMe / SAS / SATA), channel width (number of lanes), and rate level of each slot are determined, and plug-in / plug-out events and re-judgment window control signals are generated.

[0033] Specifically, the sideband signal acquisition unit samples and debounces sideband signals such as interface detection signals (IFDET information), serial general-purpose I / O signals (SGPIO signals), sleep signals (DEVSLP signals), reset signals (PERST signals, active low), and clock request signals (CLKREQ signals, active low), and determines their stable state; the out-of-band signal (OOB signal) envelope detection unit detects the envelope shape and time interval of out-of-band signal sequences such as initialization signals (COMINIT signals) and wake-up signals (COMWAKE signals) on the SAS / SATA link through analog front-end circuitry; the link training and state machine timing sampling unit monitors the state transition process of the PCIe link training state machine within a preset time window; the fusion decision unit performs comprehensive analysis of the above multi-source information to obtain the target protocol type (NVMe / SAS / SATA), channel width (number of lanes), and rate level of each slot, and outputs insertion / removal events and re-decision window control signals for subsequent high-speed channel reconstruction, clock management, and power supply control modules to call.

[0034] The entire device identification and analysis process does not rely on specific HBAs or motherboard firmware. It can complete the identification and adaptive configuration of protocols such as NVMe / SAS / SATA on the storage backplane side, reducing the binding of the entire platform and improving the reusability of the backplane.

[0035] Reference Figure 3 As shown, Figure 3 This is a detailed flowchart of step S300 in the control method based on adaptive storage backplane provided in this embodiment of the invention. Step S300 includes, but is not limited to, steps S310 to S330. Specifically, S310: Configure the high-speed differential cross matrix of the storage backplane based on the slot identification result so that the high-speed differential cross matrix can support the switching of channel slot affiliation between the PCIe domain and the SAS domain, and realize that the same slot can be mapped to the CPU root port, PCIe switching chip or SAS HBA / RAID controller to achieve dynamic multiplexing of channel resources and multi-protocol mixed insertion. S320: Based on the channel width in the slot identification result, several x4 channels are combined into an x8 channel according to actual needs, or an x8 channel is split into multiple x4 channels. S330: It uses the mapping matrix of each pair of high-speed differential channels and memory backplane slots to form an internal programmable switch network. The MCU / CPLD controls the on and off of the internal programmable switch network through registers to remap the channel order and polarity to adapt to the wiring constraints of the motherboard and memory backplane.

[0036] In some embodiments of the present invention, a high-speed differential cross-matrix dynamic configuration method based on slot identification is used to realize dynamic multiplexing and multi-protocol hybrid insertion of storage backplane channel resources between PCIe and SAS protocols, specifically: Slot identification and ownership switching mechanism: The slot identification module obtains the physical access status and protocol type (PCIe / SAS) of each slot in real time, and dynamically configures the channel affiliation logic of the high-speed differential cross matrix accordingly, so that the same slot can be mapped to any of the following targets: CPU root port, PCIe switch chip, SAS HBA / RAID controller, thereby realizing the dynamic switching and multiplexing of channel resources between the PCIe domain and the SAS domain.

[0037] Dynamic channel width reconfiguration mechanism: Based on the channel width information in the slot identification results and combined with the actual bandwidth requirements of the system, the channels are logically reconfigured through a cross matrix: multiple independent x4 channels are combined into x8 channels to meet the needs of high-bandwidth devices; or x8 channels are split into multiple x4 channels to support more low-bandwidth devices to access; thereby achieving flexible configuration and efficient utilization of channel resources.

[0038] Programmable internal switch network and signal remapping mechanism: Construct a programmable mapping matrix between each pair of high-speed differential channels and the storage backplane slots to form an internal cross switch network; The MCU or CPLD controls the on / off state of the switch through the register interface to achieve dynamic remapping of the channel order and polarity, so as to adapt to the complex wiring constraints and signal integrity requirements between the motherboard and the backplane, and improve system compatibility and wiring flexibility.

[0039] The method described above in this invention enables protocol-level dynamic reuse, elastic bandwidth configuration, and signal logic remapping of storage backplane channel resources without altering the physical hardware connections. This significantly improves the flexibility, scalability, and resource utilization of server / storage systems in multi-protocol hybrid deployment scenarios.

[0040] Reference Figure 4 As shown, Figure 4 This is a detailed flowchart of step S400 in the control method based on adaptive storage backplane provided in this embodiment of the invention. Step S400 includes, but is not limited to, steps S410 to S430. Specifically, S410: Obtain the state of the PCIe link training and state machine; S420: When the PCIe link training and state machine are in polling or recovery states, open the always-toggle window; S430: Through phase alignment and gated output circuitry, the reference clock source used by the slot can be smoothly switched from the independent spread spectrum clock separation reference clock mode to the separation reference clock mode without spread spectrum clock, or from the separation reference clock mode without spread spectrum clock back to the independent spread spectrum clock separation reference clock mode.

[0041] In some embodiments of the present invention, based on the state of the PCIe link training and state machine, switching the reference clock source of the slot to the matching mode without glitches through phase alignment and gating technology includes: first, monitoring the current state of the PCIe link training and state machine in real time; when the link training and state machine are detected to enter the polling state or the recovery state, it is determined that the link is in a window period that can be safely reconfigured, triggering the clock switching logic and opening the always-on switch window.

[0042] Within the switching window, the reference clock source used in the slot is switched losslessly through the phase alignment and gated output circuit: from Independent SSC Reference Clock (SRIS) mode to Non-SSC Reference Clock mode; or vice versa, from non-SSC mode back to SRIS mode; the clock continuity is maintained during the switching process to avoid phase jumps or period slippage, ensuring that the PCIe physical layer link does not trigger retraining or link drop.

[0043] After the clock switch is completed, the host system is notified through the internal status register or interrupt signal, and the link can continue the subsequent training process, realizing transparent and imperceptible clock source reconstruction.

[0044] A PCIe link-state-aware dynamic switching method for reference clock sources is used to achieve seamless switching between spread spectrum and non-spread spectrum clocks during link training. This method achieves dynamic switching of the reference clock source between spread spectrum and non-spread spectrum modes without interrupting the PCIe link, meeting the differentiated clock characteristics requirements of different devices in multi-protocol mixed-plug backplanes (e.g., SAS devices require non-spread spectrum, while PCIe devices support spread spectrum), while also being compatible with timing constraints during link training, thus improving system interoperability and signal integrity.

[0045] In one embodiment, refer to Figure 5 As shown, Figure 5 This is a timing diagram of the dynamic switching of the reference clock source for PCIe training and state machine awareness provided in this embodiment of the invention. In this invention, based on the protocol type identification result and link status, a selection is made between clock modes such as Separated Reference Clock with Independent SSC (SRIS), Separated Reference Clock without SSC (SRNS), and whether to enable Spread Spectrum Clock (SSC). Through phase alignment and gating technology, the reference clock source is switched without glitches within the time window allowed by the link training and state machine (LTSSM), ensuring the continuous and stable output clock.

[0046] When the LTSSM link is in a state that allows for brief instability, such as Polling or Recovery, the clock management module opens a clock switching window. Through phase alignment and gated output circuitry, it smoothly switches the reference clock used by the slot from SRIS mode to SRNS mode, or vice versa. Throughout the switching window, the output reference clock signal does not generate abnormal narrow pulses or significant glitches, thereby avoiding spurious training or instability in the link and ensuring link reliability under multi-protocol, multi-clock modes.

[0047] Reference Figure 6 As shown, Figure 6 This is a detailed flowchart of step S500 in the control method based on adaptive storage backplane provided in this embodiment of the invention. Step S500 includes, but is not limited to, steps S510 to S520. Specifically, S510: Uses the clock restorer or signal repeater on the storage backplane as the core to perform online signal integrity testing; S520: Obtains the link margin of the PCIe link, automatically adjusts the parameters of the continuous-time linear equalizer, decision feedback equalizer, and transmitter pre-emphasis equalizer based on the test results of the signal integrity test, and writes the final stable parameters into the field replaceable unit or non-volatile memory to form a slot profile.

[0048] In some embodiments of the present invention, obtaining the link margin and equalizer parameters of the PCIe link, and writing the link margin and equalizer parameters to a field-replaceable unit or non-volatile memory to form a slot profile includes: First, using the existing clock restorer (CDR) or high-speed signal repeater (Re-timer / Re-driver) on the storage backplane as a local probe node, and utilizing its built-in eye diagram monitoring / bit error counting / signal amplitude sampling functions, non-intrusive online signal integrity testing is performed on the PCIe high-speed differential signal passing through the node, and raw SI indicators such as eye height, eye width, jitter, and bit error rate are obtained in real time.

[0049] After the link training is completed, the host or backplane MCU reads the link margin register reported simultaneously by the root port, the terminal device and the CDR / repeater through the PCIe PHY Vendor-Specific ExtendedCapability or I²C sideband interface to obtain the voltage margin and timing margin of the entire link under the current equalizer settings.

[0050] Then, with the goal of maximizing link margin, an adaptive equalization convergence algorithm is run within the backplane MCU / CPLD: Continuous-Time Linear Equalizer (CTLE) — Peak gain / zero point adjustable; Decision Feedback Equalizer (DFE) — Tap1~Tapn coefficients are adjustable; Transmitter pre-emphasis (Tx FIR) — Pre-cursor, Main-cursor, and Post-cursor weights are adjustable; Gradient search / binary search / genetic algorithm is used to quickly traverse the equalizer space until the eye diagram opening degree is greater than or equal to the protocol threshold and the margin is optimized, and the final stable equalizer parameter set is recorded.

[0051] Finally, the converged optimal equalizer parameters, link margin, CDR / repeater eye diagram screenshot, protocol rate, slot ID, and timestamp are packaged into a slot profile and written into the field replaceable unit (or backplane shared non-volatile memory) of the corresponding slot. After a system restart or hot-plugging, this image is loaded first as the initial equalizer setting, shortening the link training time and achieving plug-and-play functionality and lifelong benefit from one-time learning.

[0052] By utilizing existing CDRs / repeaters on the storage backplane for local detection, without the need for external oscilloscopes or bit error rate testers, signal integrity assessment, equalizer parameter convergence, and slot-level profile solidification can be automatically completed during normal system operation. This solves the SI degradation problem caused by inconsistent wiring lengths and uncertain loads on multi-protocol backplanes, significantly improving the interoperability, maintainability, and reliability of server / storage systems.

[0053] Reference Figure 7 As shown, Figure 7 This is a detailed flowchart of step S520 in the control method based on adaptive storage backplane provided in this embodiment of the invention. Step S520 includes, but is not limited to, steps S521 to S524. Specifically, S521: When the maintenance window or business load allows, start the equalizer adaptive process to inject a pseudo-random binary sequence into the target channel or use the running data to perform bit error rate and eye diagram margin statistics. S522: Based on the bit error rate and eye diagram indicators obtained from the current test, determine whether the link margin of the PCIe link meets the preset threshold. S523: When the link margin of the PCIe link does not meet the preset threshold, the equalizer parameter adjustment step is entered. The parameters of the continuous time linear equalizer, the decision feedback equalizer, and the transmitter pre-emphasis equalizer are iteratively optimized, and the online test and evaluation steps are repeated. S524: When the link margin of the PCIe link meets the preset threshold, the converged equalizer parameters are written to the field replaceable unit or non-volatile memory bound to the slot to form a signal integrity profile for that slot.

[0054] In some embodiments of the present invention, obtaining the link margin of the PCIe link, automatically adjusting the parameters of the continuous-time linear equalizer, decision feedback equalizer, and transmitter pre-emphasis equalizer based on the test results of signal integrity testing, and writing the final stable parameters into a field-replaceable unit or non-volatile memory to form a slot profile specifically includes: During system maintenance windows or periods when the workload is below a set threshold, the backplane management controller (MCU / CPLD) or BMC issues an "adaptive start" command; depending on whether the online service can be interrupted, it adaptively selects one of the following two test stimuli to inject into the target channel: The pseudo-random binary sequence (PRBS23 / PRBS31) is generated by the PHY's built-in Pattern Generator; Alternatively, the normal data stream can be used to perform statistical analysis through the real-time error detector inside the CDR / Retimer.

[0055] During the duration of the stimulus, the following are read synchronously: Bit Error Rate (BER) counter value, eye diagram height, eye diagram width, peak-to-peak jitter, and vertical noise margin.

[0056] Based on the current bit error rate and eye diagram metrics obtained from the test, determine whether the link margin of the PCIe link meets the preset threshold. If the link margin of the PCIe link does not meet the preset threshold, proceed to the equalizer parameter adjustment step, iteratively optimize the parameters of the continuous-time linear equalizer, decision feedback equalizer, and transmitter pre-emphasis equalizer, and repeat the online test and evaluation steps.

[0057] When the link margin of the PCIe link meets the preset threshold, the converged optimal equalizer parameter set, corresponding eye diagram screenshot, bit error rate value, link speed, temperature, voltage, slot ID and timestamp are packaged into a signal integrity profile and written into the specified field of the field replaceable unit or backplane shared non-volatile memory bound to the slot, so that it can be quickly loaded when the device is replaced or the protocol is switched, so that the link can be restored to a better operating point.

[0058] By performing non-intrusive SI testing through maintenance windows or online business data, and combining eye diagrams and bit error rate (BER) margin assessments, closed-loop adaptive optimization is achieved. The final convergence parameters are then solidified into slot-level profiles, ensuring zero interruption in the production environment and resolving the link margin attenuation problem caused by wiring differences and temperature aging in multi-protocol mixed-insertion backplanes. This significantly improves the reliability, maintainability, and lifecycle management capabilities of server storage systems.

[0059] Reference Figure 8 As shown, Figure 8 This is a detailed flowchart of step S600 in the control method based on adaptive storage backplane provided in this embodiment of the invention. Step S600 includes, but is not limited to, steps S610 to S630. Specifically, S610: After detecting the insertion signal of the storage backplane, the precharge circuit is activated to provide a soft start for the load of the slot; S620: After pre-charging is complete and it is confirmed that there is no short circuit in the slot, the eFuse device is closed to provide main power supply, and the power supply to the slot is powered on based on the slot profile. S630: If an overcurrent or short circuit is detected during power-on, disconnect the eFuse device and record the fault information.

[0060] In some embodiments of the present invention, based on the slot profile, powering on the slot under the control of pre-charging and eFuse devices includes: employing a two-stage current-limiting structure for the main power supply paths of pre-charging and eFuse devices: after the device is inserted, it first undergoes a soft start via the pre-charging path, with the power-on slope controlled; after pre-charging is completed and no short circuit is confirmed, the main power supply of the eFuse device is closed; if an overcurrent or short circuit is detected, it is quickly disconnected and the fault is recorded. Surge suppression and glitch suppression are achieved during insertion / removal and protocol switching processes through synchronization with the protocol identification state machine, slot reset signal, and high-speed channel activation timing.

[0061] Specifically, the storage backplane power input provides soft-start for the slot load via a pre-charge circuit. The pre-charge circuit controls the power-on slope through a series current-limiting resistor and a controlled MOSFET, limiting inrush current to a safe range during the pre-charge phase. After pre-charging is complete and the slot is confirmed to be free of short circuits or other abnormalities, the main power supply path of the eFuse device is connected to provide normal operating current for the slot load. It also quickly disconnects upon detecting overcurrent or short circuit, thus achieving fault isolation. The protocol identification / state machine controls the start and stop of pre-charging and the eFuse device based on insertion / removal events and protocol switching states, and is linked with the slot reset signal and high-speed channel activation timing to ensure that power glitches and surges during insertion / removal and protocol switching do not interfere with link training or other slots.

[0062] By introducing pre-charge soft-start at the moment of insertion, the impact of traditional hot-swapping on the backplane power supply is eliminated; the slot profile is used to personalize the power-up sequence of multiple rails, taking into account the power supply characteristics of different PCIe / SAS devices; combined with highly integrated eFuse, it achieves fast protection at the <2 µs level and records fault data, which significantly improves the reliability, maintainability and lifecycle traceability of the storage backplane in multi-protocol mixed insertion and high availability scenarios.

[0063] In some embodiments of the present invention, the control method based on the adaptive storage backplane further includes: when a device replacement, a significant change in ambient temperature, or a decline in link quality is detected during the operation of the storage backplane, re-execute some of the above steps (such as protocol re-judgment, equalizer fine-tuning, etc.) to maintain long-term stability and performance in a multi-protocol mixed-insertion environment.

[0064] Continuously monitor the following three types of events during storage backplane operation: Device replacement events: Presence Detect signal toggles, field replaceable unit ID or non-volatile memory ID changes, link training state machine returns from LOS / L1 to Detect. Ambient temperature change event: The onboard temperature sensor sampling value changes by ≥ΔTth within Δt≤30 s (default 15°C); Link quality degradation events: Cumulative BER > 1E-12, eye height / eye width decrease ≥ 10%, or link margin index M decreases ≥ 15% compared to the profile baseline; Once any event is triggered, the "profile refresh request" flag is immediately set, and the slot protocol automatic identification step is re-executed: by detecting the PCIe TS1 / TS2 ordered set or SAS Identify Address Frame, the protocol type and link width of the currently inserted device are confirmed; If the protocol or width does not match the existing profile, the high-speed differential cross-connect matrix is ​​invoked to dynamically switch the channel, so that the channel is reassigned to the corresponding CPU root port, PCIe switch chip or SAS HBA / RAID controller, and the "Protocol & Width" field in the profile is updated.

[0065] Incremental image refresh and non-volatile storage: The generated protocol type, channel width, equalizer offset, temperature compensation coefficient, and timestamp are packaged into a Delta Profile, written into the Revision Area of ​​the original replaceable unit, and the Profile Ver. + 1 is incremented. The latest version of the profile is loaded first upon the next power-on, realizing parameter self-correction after hot-swapping, temperature drift, and aging, and maintaining optimal signal integrity and power supply timing matching over long periods.

[0066] By using an event-driven selective refresh mechanism, we can avoid service interruptions caused by full parameter retraining, and ensure that the backplane channel assignment, equalizer settings and power supply timing always match the latest hardware status after equipment replacement, ambient temperature drift or link aging. This significantly extends the service life of the multi-protocol mixed-plug system in the operating scenario and reduces on-site maintenance costs.

[0067] This invention also provides an adaptive storage backplane, as described in the embodiments of the present invention. Figure 9As shown, the adaptive storage backplane includes a protocol identification module, a cross-connect matrix module, a clock management module, an adaptive module, and a power supply and hot-swap control module. The protocol identification module is used for insertion / removal detection and protocol identification of the storage backplane. When a slot insertion or topology change event is detected, it collects sideband signals, out-of-band signals, and the status of the PCIe link training and state machine. It then identifies and analyzes the sideband signals, out-of-band signals, PCIe link training, and state machine status to obtain the slot identification result. The cross-matrix module is used to configure the high-speed differential cross-matrix of the storage backplane based on the slot identification results, so as to switch the slot affiliation of channels between multiple master control domains, perform splicing or splitting of channel width as needed, and adjust the channel order and remap polarity; the clock management module is used to switch the reference clock source of the slot to the matching mode without glitches based on the PCIe link training and state machine state, through phase alignment and gating technology; the adaptive module is used to obtain the link margin and equalizer parameters of the PCIe link, and write the link margin and equalizer parameters to the field replaceable cell or non-volatile memory to form a slot profile; the power supply and hot-swap control module is used to power on the slot based on the slot profile and under the control of pre-charge and eFuse devices.

[0068] Through the coordinated operation of five modules, the storage backplane can automatically identify protocols, dynamically assign channels, switch clocks without glitches, optimize signal integrity, and provide safe hot-swappable power without power outages or manual intervention. This enables plug-and-play, long-term stable operation, and maintainability of PCIe / SAS hybrid devices in the same slot.

[0069] In some embodiments of the present invention, the adaptive storage backplane further includes a control and monitoring unit. The motherboard BMC of the storage backplane communicates bidirectionally with the control and monitoring unit via an I²C bus, a PMBus bus, and / or a GPIO interface. The control and monitoring unit is connected to the protocol identification module, the cross-matrix module, the clock management module, the adaptive module, and the power supply and hot-swap control module via a control bus. The control and monitoring unit is used to issue configuration commands to each module and collect the operating status, alarm information, and self-test results of each module. The control and monitoring unit is an MCU or a CPLD.

[0070] Understandably, the main control side connects to the adaptive storage backplane via high-speed links and sideband signals. Under the unified management of the control and monitoring unit, the various functional modules inside the storage backplane work together to dynamically complete channel routing reconstruction, clock mode selection, equalizer parameter adjustment, and power supply hot-swap control based on the protocol type and link status of the actual device inserted in each slot. This enables plug-and-play and performance adaptation for multiple protocol devices on the same backplane.

[0071] By using the MCU / CPLD as a local control aggregation point, the backplane only needs a set of standardized I²C / PMBus / GPIO to interface with the motherboard BMC. This reduces the software complexity on the BMC side and ensures that the register configuration, status polling, and fault alarm of the five major modules are completed within 50 ms, meeting the requirements of real-time response and hot-swappable reliability in a multi-protocol mixed-plug environment.

[0072] It should be understood that the method steps in the embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The method can use standard programming techniques. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if necessary, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0073] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program comprises a plurality of instructions executable by one or more processors.

[0074] Furthermore, the method can be implemented in any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices, etc. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. When programmed according to the methods and techniques described in the invention, the invention may also include the computer itself.

[0075] A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects generated on the display.

[0076] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, as long as they achieve the technical effects of the present invention by the same means, should be included within the scope of protection of the present invention. Within the scope of protection of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A control method based on an adaptive storage backplane, characterized in that, include: Insertion and removal detection and protocol identification are performed on the storage backplane. When a slot insertion or topology change event is detected, sideband signals, out-of-band signals, and the status of PCIe link training and state machine are collected. The sideband signal, the out-of-band signal, the PCIe link training and state machine state are identified and analyzed to obtain the identification result of the slot; Based on the identification results of the slots, the high-speed differential cross matrix of the storage backplane is configured to switch the slot affiliation of channels between multiple master control domains, to perform splicing or splitting of channel widths as needed, and to adjust the channel order and remap polarity. Based on the PCIe link training and state machine state, the reference clock source of the slot is switched to the matching mode without glitches through phase alignment and gating technology. Obtain the link margin and equalizer parameters of the PCIe link, and write the link margin and equalizer parameters to a field replaceable unit or non-volatile memory to form a slot profile. Based on the slot profile, the slot is powered on under the control of pre-charging and eFuse devices.

2. The control method based on adaptive storage backplane according to claim 1, characterized in that, The sideband signals include interface detection signals, serial general-purpose I / O signals, sleep signals, reset signals, and clock request signals; the out-of-band signals include disk link initialization signals and wake-up signals. The process of identifying and analyzing the sideband signal, the out-of-band signal, the PCIe link training, and the state machine to obtain the slot identification result includes: The sideband signal acquisition unit performs debouncing processing on the interface detection signal, the serial general-purpose I / O signal, the sleep signal, the reset signal, and the clock request signal, and determines the stability of each signal's state. The envelope shape and time interval of the initialization signal and wake-up signal on the hard disk link are detected by simulating the front-end circuit through the out-of-band signal envelope detection unit. The state transition process of the PCIe link training state machine is monitored and analyzed within a preset time window using a timing sampling unit, and the state analysis results of the PCIe link training and state machine are obtained. The interface detection signal after debouncing, serial general-purpose I / O signal, sleep signal, reset signal, clock request signal, initialization signal and wake-up signal on the hard disk link, as well as the state analysis results of the PCIe link training and state machine are comprehensively analyzed to obtain the target protocol type, channel width and rate level of the slot, and output the plug-in / plug-out event and re-judgment window control signal.

3. The control method based on adaptive storage backplane according to claim 2, characterized in that, The configuration of the high-speed differential cross matrix of the storage backplane based on the slot identification result enables the switching of channel slot affiliation among multiple master control domains, the splicing or splitting of the channel width as needed, and the adjustment of channel order and polarity remapping, including: Based on the slot identification results, the high-speed differential cross matrix of the storage backplane is configured so that the high-speed differential cross matrix supports the switching of channel slot affiliation between the PCIe domain and the SAS domain, and realizes that the same slot can be mapped to the CPU root port, PCIe switching chip or SAS HBA / RAID controller, so as to realize dynamic multiplexing of channel resources and multi-protocol mixed insertion. Based on the channel width in the slot identification result, several x4 channels can be combined into an x8 channel according to actual needs, or the x8 channel can be split into multiple x4 channels. An internal programmable switch network is formed by mapping each pair of high-speed differential channels to the memory backplane slots. The MCU / CPLD controls the on / off state of the internal programmable switch network through registers to remap the channel order and polarity to adapt to the wiring constraints of the motherboard and memory backplane.

4. The control method based on adaptive storage backplane according to claim 2, characterized in that, The process of switching the reference clock source of the slot to a glitched matching mode without glitches, based on the slot identification result and the PCIe link training and state machine state, using phase alignment and gating techniques, includes: Obtain the training and state machine status of the PCIe link; When the PCIe link training and state machine are in polling or recovery state, open the always-toggle window; By using phase alignment and gated output circuitry, the reference clock source used by the slot can be smoothly switched from the independent spread spectrum clock separation reference clock mode to the separation reference clock mode without spread spectrum clock, or from the separation reference clock mode without spread spectrum clock back to the independent spread spectrum clock separation reference clock mode.

5. The control method based on adaptive storage backplane according to claim 1, characterized in that, The step of obtaining the link margin and equalizer parameters of the PCIe link, and writing the link margin and equalizer parameters to non-volatile memory to form a slot profile includes: Using the clock restorer or signal repeater on the storage backplane as the core, online signal integrity testing is performed; The link margin of the PCIe link is obtained, and the parameters of the continuous-time linear equalizer, decision feedback equalizer, and transmitter pre-emphasis equalizer are automatically adjusted according to the test results of the signal integrity test. The final stable parameters are written into the field replaceable unit or non-volatile memory to form a slot profile.

6. The control method based on adaptive storage backplane according to claim 5, characterized in that, The automatic adjustment of the continuous-time linear equalizer, decision feedback equalizer, and transmitter pre-emphasis equalizer parameters based on the signal integrity test results, and the writing of the final stable parameters into a field-replaceable unit or non-volatile memory to form a slot profile, includes: If the maintenance window or business load allows, start the equalizer adaptive process to inject a pseudo-random binary sequence into the target channel or use the running data to perform bit error rate and eye diagram margin statistics. Based on the current bit error rate and eye diagram metrics obtained from the test, determine whether the link margin of the PCIe link meets the preset threshold. When the link margin of the PCIe link does not meet the preset threshold, the equalizer parameter adjustment step is entered. The continuous time linear equalizer, the decision feedback equalizer and the transmitter pre-emphasis equalization parameters are iteratively optimized, and the online testing and evaluation steps are repeated. When the link margin of the PCIe link meets the preset threshold, the converged equalizer parameters are written to the field replaceable unit or non-volatile memory bound to the slot to form a signal integrity profile for that slot.

7. The control method based on adaptive storage backplane according to claim 1, characterized in that, The process of powering on the slot based on the slot profile, under the control of pre-charging and eFuse devices, includes: Upon detecting the insertion signal of the storage backplane, the pre-charge circuit is activated to provide a soft start for the load of the slot; After pre-charging is completed and it is confirmed that there is no short circuit in the slot, the eFuse device is closed to provide main power supply, and the power supply to the slot is powered on based on the slot profile. If an overcurrent or short circuit is detected during power-on, disconnect the eFuse device and record the fault information.

8. An adaptive storage backplane for executing the control method based on an adaptive storage backplane as described in any one of claims 1 to 7, characterized in that, include: The protocol identification module is used to perform insertion and removal detection and protocol identification of the storage backplane. When a slot insertion or topology change event is detected, it collects sideband signals, out-of-band signals, and the status of PCIe link training and state machine. The sideband signal, the out-of-band signal, the PCIe link training and state machine state are identified and analyzed to obtain the identification result of the slot; The cross-matrix module is used to configure the high-speed differential cross-matrix of the storage backplane based on the identification result of the slot, so as to realize the switching of the slot affiliation of the channel between multiple master control domains, the splicing or splitting of the channel width as needed, and the adjustment of channel order and polarity remapping. The clock management module is used to switch the reference clock source of the slot to a glitched matching mode without glitches, based on the state of the PCIe link training and state machine, through phase alignment and gating technology. An adaptive module is used to obtain the link margin and equalizer parameters of the PCIe link, and write the link margin and equalizer parameters to a field replaceable unit or non-volatile memory to form a slot profile. The power supply and hot-swap control module is used to power on the slot based on the slot profile and under the control of the pre-charge and eFuse devices.

9. The adaptive storage backplane according to claim 8, characterized in that, It also includes a control and monitoring unit. The motherboard BMC of the storage backplane communicates bidirectionally with the control and monitoring unit through the I²C bus, PMBus bus and / or GPIO interface. The control and monitoring unit is connected to the protocol identification module, the cross matrix module, the clock management module, the adaptive module and the power supply and hot-swap control module through the control bus. The control and monitoring unit is used to issue configuration commands to each module and collect the operating status, alarm information and self-test results of each module. The control and monitoring unit is an MCU or CPLD.

10. A computer device comprising a memory and a processor, characterized in that, When the processor executes a computer program stored in the memory, it performs the method as described in any one of claims 1 to 7.

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