GDL circuitry, driving methods, display panels, and display devices

Abstract

This application relates to a GDL circuit, driving method, display panel, and display device. The circuit includes: a gate driving module, which is used to receive a scan driving signal and enable the current pixel row to display the current frame under the drive of the scan driving signal; a dual noise cancellation transistor module, which is connected to the gate driving module and is used to receive a noise cancellation signal to perform noise cancellation processing on the gate driving module when the current frame is in the display stage, wherein the noise cancellation transistor in the dual noise cancellation transistor module is in a first bias state during the display stage; and a bias control module, which is connected to the dual noise cancellation transistor module and is used to receive a bias control signal when the current frame is in a blank stage to control the noise cancellation transistor in the dual noise cancellation transistor module to be in a second bias state. This circuit solves the technical problem of the inability to suppress the right shift of the IV characteristic of the dual noise cancellation transistor in the GDL circuit in the prior art.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a GDL circuit, driving method, display panel, and display device. Background Technology

[0002] With the continuous development of display technology, LCD (Liquid Crystal Display) products are widely used in mobile phones, automobiles, central control systems, smart homes, smart offices, watches, wristbands, and many other fields. However, during screen display, the dual noise cancellation transistors in existing LCD designs operate at a forward bias of 28V for most of the time (approximately 88%), causing the IV (Current-Voltage) characteristic of the dual noise cancellation transistors to shift to the right. Especially in high-temperature and high-humidity environments, prolonged operation accelerates the rightward shift of the IV characteristic of the dual noise cancellation transistors, leading to a decrease in their turn-on capability and noise control ability. This, in turn, increases the risk of noise generation in the GDL (Gate Driverless) circuit due to signal source interference, potentially causing unstable or abnormal output signals in the GDL circuit, ultimately severely impacting the overall display performance of the LCD product.

[0003] Therefore, how to suppress the rightward shift of the IV characteristic of the dual noise reduction transistors in the GDL circuit to improve the display performance of LCD products is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a GDL circuit, driving method, display panel, and display device to solve the technical problem in the prior art that the rightward shift of the IV characteristic of the dual noise-canceling transistors in the GDL circuit cannot be suppressed.

[0005] In a first aspect, this application provides a GDL circuit, the GDL circuit comprising: a gate driving module, the gate driving module being used to receive a scan driving signal and enable the current pixel row to display the current frame image under the drive of the scan driving signal; a dual noise cancellation tube module, the dual noise cancellation tube module being connected to the gate driving module, the dual noise cancellation tube module being used to receive a noise cancellation signal to perform noise cancellation processing on the gate driving module when the current frame image is in the display stage, wherein the noise cancellation tube in the dual noise cancellation tube module is in a first bias state during the display stage; and a bias control module, the bias control module being connected to the dual noise cancellation tube module, the bias control module being used to receive a bias control signal to control the noise cancellation tube in the dual noise cancellation tube module to be in a second bias state when the current frame image is in a blank stage, wherein the bias direction of the second bias state is opposite to that of the first bias state.

[0006] Optionally, the gate driving module includes a noise reduction control unit, the controlled terminal of the dual noise reduction transistor module is connected to the noise reduction control unit, and the connection node is a first node; the bias control module includes a first signal terminal, the first signal terminal is connected to a first terminal of the dual noise reduction transistor module; wherein, the noise reduction control unit is used to output a low-level signal to the first node when the current frame is in the blank stage, so as to turn off the dual noise reduction transistor module; the first signal terminal is used to connect a high-level signal when the current frame is in the blank stage, so as to control the dual noise reduction transistor module to be in a negative bias state.

[0007] Optionally, the bias control module includes: a first switching unit, an energy storage unit, a second signal terminal, and a third signal terminal. The first terminal of the first switching unit is connected to the first terminal of the dual noise cancellation tube module, the second terminal of the first switching unit is connected to the second signal terminal, and the first controlled terminal of the first switching unit is connected to the second signal terminal. The first capacitor terminal of the energy storage unit is connected to the first terminal of the dual noise cancellation tube module, and the second capacitor terminal of the energy storage unit is connected to the third signal terminal. The blanking phase consists of a first blanking sub-phase and a second blanking sub-phase. The third signal terminal is used to input a low-level signal when the current frame is in the first blanking sub-phase, and the second signal terminal is used to input a low-level signal when the current frame is in the first blanking sub-phase. When the frame is in the first blank sub-stage, a high-level signal is applied. The first switching unit is turned on when a high-level signal is applied to the first controlled terminal, so that the second signal terminal charges the first terminal of the energy storage unit. When the current frame is in the second blank sub-stage, a low-level signal is applied. When the first controlled terminal receives a low-level signal, the first switching unit is turned off. The third signal terminal is used to apply a high-level signal when the current frame is in the second blank sub-stage. When the energy storage unit receives a high-level signal at the second capacitor terminal, the voltage at the first capacitor terminal of the energy storage unit is adjusted by charge conservation to control the dual noise cancellation module to be in a negative bias state.

[0008] Optionally, the bias control module includes: a fourth signal terminal, wherein the second controlled terminal of the first switching unit is connected to the fourth signal terminal; wherein the fourth signal terminal is used to connect a high-level signal when the current frame is in the display stage, the second signal terminal is used to connect a low-level signal when the current frame is in the display stage, the switching unit is used to turn on when the second controlled terminal connects to a high-level signal, so that the second signal terminal outputs a low-level signal to the first terminal of the dual noise cancellation tube module; the fourth signal terminal is used to connect a low-level signal when the current frame is in the blank stage.

[0009] Optionally, the gate driving module includes a noise reduction control unit, wherein the controlled terminal of the dual noise reduction tube module is connected to the noise reduction control unit, and the connection node is a first node. The noise reduction control unit is used to output a low-level signal to the first node when the current frame is in the blank stage, so as to turn off the dual noise reduction tube module.

[0010] Optionally, the gate driving module includes: a pre-charge unit, an output unit, and a noise reduction control unit. The pre-charge unit is connected to the controlled terminal of the output unit, and the connection node is the second node. One noise reduction transistor in the dual noise reduction transistor module is an eighth thin-film transistor, and the other noise reduction transistor in the dual noise reduction transistor module is a ninth thin-film transistor. The first terminal of the eighth thin-film transistor and the first terminal of the ninth thin-film transistor are connected to form the first terminal of the dual noise reduction transistor module. The controlled terminal of the eighth thin-film transistor is connected to the controlled terminal of the ninth thin-film transistor and is connected to the noise reduction control unit, and the connection node is the first node. The bias control... The module includes a second switch unit and a third switch unit. The controlled terminals of the second and third switch units are both connected to the fourth signal terminal. The first terminal of the second switch unit is connected to the second terminal of the eighth thin-film transistor, and the second terminal of the second switch unit is connected to the second node. The first terminal of the third switch unit is connected to the second terminal of the ninth thin-film transistor, and the second terminal of the third switch unit is connected to the output terminal of the output unit. The noise reduction control unit is used to output a high-level signal to the first node when the current frame is in the blank stage, thereby turning on the dual noise reduction transistor module.

[0011] Optionally, the first switching unit is a dual-gate thin-film transistor, wherein the positive gate of the dual-gate thin-film transistor is the first controlled terminal of the first switching unit, and the back gate of the dual-gate thin-film transistor is the second controlled terminal of the first switching unit.

[0012] Secondly, this application provides a driving method for a GDL circuit, which is applied to any of the GDL circuits described above. The method includes: receiving a gate driving signal through the gate driving module and enabling the current pixel row to display the current frame under the drive of the gate driving signal; when the current frame is in the display stage, performing noise reduction processing on the gate driving module by receiving a noise reduction signal through the dual noise reduction tube module, wherein the noise reduction tube in the dual noise reduction tube module is in a first bias state during the display stage; when the current frame is in the blank stage, controlling the noise reduction tube in the dual noise reduction tube module to be in a second bias state by receiving a bias control signal through the bias control module, wherein the bias direction of the second bias state is opposite to that of the first bias state.

[0013] Thirdly, this application provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including any of the GDL circuits described above.

[0014] Fourthly, this application also provides a display device, the display device including the aforementioned display panel, memory, processor, and a driver for a GDL circuit stored in the memory and executable on the processor, wherein the processor, when executing the driver for the GDL circuit, implements the steps of the driving method for the GDL circuit.

[0015] In this embodiment, the noise cancellation tube in the dual noise cancellation tube module is in a first bias state during the display phase, causing the IV characteristic of the noise cancellation tube in the dual noise cancellation tube module to shift to the left after experiencing the display phase. This application sets a bias control module in the GDL circuit. When the current frame is in a blank phase, the bias control module connects a bias control signal to control the dual noise cancellation tube module to be in a second bias state, so that the IV characteristic of the noise cancellation tube in the dual noise cancellation tube module shifts to the right after experiencing the blank phase, thereby offsetting part of the rightward shift of the IV characteristic of the noise cancellation tube in the dual noise cancellation tube module and suppressing the rightward shift of the IV characteristic of the dual noise cancellation tube in the GDL circuit. This solves the problem that the prior art cannot suppress the rightward shift of the IV characteristic of the dual noise cancellation tube in the GDL circuit and improves the LCD display performance. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 A schematic diagram of a GDL circuit provided for the prior art;

[0020] Figure 2 A schematic diagram of a first type of GDL circuit provided in an embodiment of this application;

[0021] Figure 3 A schematic diagram of a second type of GDL circuit provided in an embodiment of this application;

[0022] Figure 4 A schematic diagram of a third type of GDL circuit provided in an embodiment of this application;

[0023] Figure 5 A schematic diagram of a fourth type of GDL circuit provided in an embodiment of this application;

[0024] Figure 6 A signal timing diagram of a GDL circuit provided in an embodiment of this application;

[0025] The symbols in the attached image are explained as follows:

[0026] 10. Gate drive module; 101. Noise reduction control unit; 102. Precharge unit; 103. Output unit; 104. First reset unit; 105. Second reset unit; 20. Dual noise reduction tube module; 30. Bias control module; 301. First switching unit; 302. Energy storage unit; 303. Second switching unit; 304. Third switching unit. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0029] The following definitions are provided for the terms used:

[0030] Forward bias and negative bias: For an N-type thin film transistor, a thin film transistor is in a negative bias state when the gate voltage is higher than the drain voltage or higher than the source voltage. A thin film transistor is in a negative bias state when the source voltage or drain voltage is higher than the gate voltage.

[0031] With the rapid development of LCD display technology, LCD products have been widely used in many fields such as mobile phones, automobiles, central control, smart homes, smart offices, watches, and wristbands. With the emergence of many application demands such as technological sophistication, intelligence, and integration, the market is increasingly demanding higher product quality and reliability, and the requirements for specifications are becoming more stringent. However, the design of existing LCD products still has shortcomings.

[0032] like Figure 1 As shown, the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, the seventh thin-film transistor T7, the eighth thin-film transistor T8, the ninth thin-film transistor T9, the tenth thin-film transistor T10, and the eleventh thin-film transistor T11 in the GDL circuit are all N-type thin-film transistors. One frame of the image consists of a display phase and a blank phase. The display phase includes a charging phase, a reset phase, and a sustain phase. The charging phase includes a pre-charging phase and an output phase. The specific processes of the pre-charging phase and the output phase are as follows:

[0033] During the pre-charge period, the VDS signal terminal is connected to a high-level signal VGH, and the Gn-2 signal terminal of this stage is also connected to a high-level signal VGH, which turns on the first thin-film transistor T1 and pre-charges point Q (charging the second capacitor C2) when it is turned on, so that the voltage of point Q is at a high-level signal VGH. Since the voltage of point Q is at a high-level signal VGH, the tenth thin-film transistor T10 turns on. However, since the CLK signal terminal is connected to a low-level signal VGL at this time, the tenth thin-film transistor T10 has no output, and the voltage of point Gn is at a low-level signal VGL. The third thin-film transistor T3 and the fifth thin-film transistor T5 are both connected to a low-level signal VGL. Since the voltage of point Q is at a high-level signal VGH, the third thin-film transistor T3 and the fifth thin-film transistor T5 are both turned on. The third thin-film transistor T3 and the fifth thin-film transistor T5 work together to pull down the voltage of point QB to a low-level signal VGL. Since the voltage of point QB is at a low-level signal VGL, the dual noise cancellation transistors (the eighth thin-film transistor T8 and the ninth thin-film transistor T9) are turned off.

[0034] During the output phase, a low-level signal VGH is connected to the Gn-2 signal terminal of this stage, the first thin-film transistor T1 is turned off, and a high-level signal VGH is connected to the CLK signal terminal of this stage. The voltage at point Q is at a high-level signal VGH during the pre-charge phase, which has already turned on the tenth thin-film transistor T10. Since the CLK signal terminal of this stage is connected to a high-level signal VGH at this time, the voltage at point Q will be coupled to a higher level signal by the second capacitor C2, which will fully turn on the tenth thin-film transistor T10. At this time, the tenth thin-film transistor T10 outputs a high-level signal VGH to point Gn, and the voltage at point Gn is at a high-level signal VGH. Since the voltage at point Q will be coupled to a higher level by the second capacitor C2, the third thin-film transistor T3 and the fifth thin-film transistor T5 remain on, the voltage at point QB is still at a low-level signal VGL, and the dual noise cancellation transistors (the eighth thin-film transistor T8 and the ninth thin-film transistor T9) remain off.

[0035] The specific process of the reset phase is as follows:

[0036] When the Gn-2 signal terminal of this stage is connected to a low-level signal VGH, the first thin-film transistor T1 is turned off, the VSD signal terminal is connected to a low-level signal VGL, and the Gn+2 signal terminal of this stage is connected to a high-level signal, which turns on the eleventh thin-film transistor T11. When it turns on, it resets the voltage at point Q to the low-level signal VGL. At this time, the CLK signal terminal of this stage is connected to a low-level signal VGL, the tenth thin-film transistor T10 is turned off and has no output, and the voltage at point Gn is at the low-level signal VGL. At this time, the voltage across the second capacitor C2 is also at the low-level signal VGL. Since the voltage at point Q is at the low-level signal VGL, the third thin-film transistor T3 and the fifth thin-film transistor T5 are turned off, the GCH signal terminal is connected to a high-level signal VGH, and the second thin-film transistor T2 and the fourth thin-film transistor T4 are turned on. When they are turned on, they charge point QB, making the voltage at point QB at the high-level signal VGH. At this time, the dual noise cancellation transistors (the eighth thin-film transistor T8 and the ninth thin-film transistor T9) are turned on.

[0037] The specific process of the maintenance phase is as follows:

[0038] Both the Gn-2 and Gn+2 signal terminals of this stage are connected to a low-level signal VGH. The first thin-film transistor T1 and the eleventh thin-film transistor T11 are turned off, and the voltage at point Q is maintained at a low-level signal VGL. Therefore, the third thin-film transistor T3 and the fifth thin-film transistor T5 are still turned off. The GCH signal terminal is connected to a high-level signal VGH, and the voltage at point QB is still at a high-level signal VGH. The dual noise cancellation transistors (the eighth thin-film transistor T8 and the ninth thin-film transistor T9) are still turned on. Since both the eighth thin-film transistor T8 and the ninth thin-film transistor T9 are connected to a low-level signal VGL, the eighth thin-film transistor T8 pulls down the voltage at point Q to a low-level signal VGL, and the ninth thin-film transistor T9 pulls down the voltage at point Gn to a low-level signal VGL.

[0039] The specific process of the blank phase is as follows:

[0040] When the STV0 signal terminal is connected to a high-level signal VGH, and all other signal terminals are connected to low-level signals, the sixth thin-film transistor T6 and the seventh thin-film transistor T7 are turned on. Both the sixth and seventh thin-film transistors T6 and T7 are connected to a low-level signal VGL. Therefore, when the sixth thin-film transistor T6 is turned on, the voltage at point Q is pulled down again, making the voltage at point Q a low-level signal VGL. When the seventh thin-film transistor T7 is turned on, the voltage at point Gn is pulled down again, making the voltage at point Gn a low-level signal VGL. Since the voltage at point Q is a low-level signal VGL, the third thin-film transistor T3 and the fifth thin-film transistor T5 remain off. At this time, the GCH signal terminal is connected to a low-level signal VGL, therefore the voltage at point QB is a low-level signal VGL, and the dual noise-canceling transistors (the eighth thin-film transistor T8 and the ninth thin-film transistor T9) are turned off.

[0041] In summary, the dual noise cancellation transistors (eighth TFT T8 and ninth TFT T9) are on during the display phase of each frame, except when they are off during the charging phase of the pixels in their respective row. Assuming the resolution of the display panel is 1000 levels, the working time of the dual noise cancellation transistors during the display phase is 999 / 1000 = 99.9%. As the resolution increases, the working time of the dual noise cancellation transistors will also increase. During the blank phase, the dual noise cancellation transistors are off, and the blank phase of each frame lasts for about 2ms. Assuming the screen refresh rate is 60Hz, then the working time of the dual noise cancellation transistors in one frame is approximately 14.67ms / 16.67ms ≈ 88%.

[0042] When the eighth thin-film transistor T8 and the ninth thin-film transistor T9 are working, the gate voltage is at a high level signal VGH (17V) and the drain voltage is at a low level signal VGL (-11V). Therefore, the dual noise cancellation transistor is in a forward bias state for a long time, and the bias voltage is V=17-(-11)=28V.

[0043] In summary, during the reliability verification of LCD products, i.e., operation under extreme conditions of high temperature and high humidity (also known as the dual 85 test), the dual noise cancellation transistors are under a 28V forward bias state 88% of the time. High temperature and high humidity will accelerate the rightward shift of the IV characteristic of the dual noise cancellation transistors, resulting in a decrease in the turn-on capability of the dual noise cancellation transistors and a decrease in the noise control capability. During the high-temperature operation, the GDL circuit is easily affected by source signal interference, which can easily generate noise. If this noise cannot be effectively controlled, it will cause abnormal GDL output.

[0044] To address the technical problem of the inability to suppress the rightward shift of the IV characteristic of the dual noise-canceling transistors in GDL circuits in the prior art, this application provides a GDL circuit, driving method, display panel, and display device that can suppress the rightward shift of the IV characteristic of the dual noise-canceling transistors in the GDL circuit, thereby improving the LCD display performance.

[0045] Figure 2 A GDL circuit is provided in an embodiment of this application, the GDL circuit comprising:

[0046] Gate driving module 10, the gate driving module 10 is used to receive the scan driving signal, and enable the current pixel row to display the current frame under the drive of the scan driving signal;

[0047] For example, such as Figure 3 , Figure 4 and Figure 5As shown, the gate drive module 10 includes: a noise reduction control unit 101, a precharge unit 102, an output unit 103, a first reset unit 104, and a second reset unit 105. The noise reduction control unit 101 includes: a second thin-film transistor T2, a third thin-film transistor T3, a fourth thin-film transistor T4, a fifth thin-film transistor T5, and a GCH signal terminal. The gate of T2 is connected to the drain of T5, the source of T2 is connected to the GCH signal terminal, and the drain of T2 is connected to the first node QB. The gate of T3 is connected to the second node Q, and the drain of T3 is connected to point QB. The gate of T4 is connected to the GCH signal terminal, the source of T4 is connected to the GCH signal terminal, the drain of T4 is connected to the drain of T5, and the gate of T5 is connected to the second node Q. The precharge unit 102 includes: a first thin-film transistor T1, the Gn-2 signal terminal of this stage, and a VDS signal terminal. The output unit 103 includes: a tenth thin-film transistor T10, a second capacitor C2, and the CLK signal terminal of this stage. The gate of T1 is connected to the Gn-2 signal terminal of this stage, the source of T1 is connected to the VDS signal terminal, the drain of T1 is connected to the gate of T10, and the source of T10 is connected to the CLK signal terminal of this stage, with the connection node being the second node Q. The drain of T10 is at point Gn. The first reset unit 104 includes: the Gn+2 signal terminal of this stage, the VSD signal terminal, and the eleventh thin-film transistor T11. The gate of T11 is connected to the Gn+2 signal terminal of this stage, and the source of T11 is connected to the VDS signal terminal. The SD signal terminal is connected, the drain of T11 is connected to the second node Q, and the second reset unit 105 includes: a sixth thin film transistor T6, a seventh thin film transistor T7, a VGL signal terminal and an STV0 signal terminal. The gates of T6 and T7 are both connected to the STV0 signal terminal, the sources of T6 and T7 are both connected to the VGL signal terminal, the drain of T6 is connected to the second node Q, the drain of T7 is connected to point Gn, and the sources of T3 and T5 are both connected to the VGL signal terminal.

[0048] For example, the scan drive signal set in this application can be understood as the voltage signal on the second node Q of the output stage of the above-mentioned display stage.

[0049] Dual noise cancellation module 20, which is connected to the gate drive module 10, is used to input a noise reduction signal to the gate drive module 10 for noise reduction processing when the current frame is in the display stage. The noise reduction tube in the dual noise cancellation module 20 is in a first bias state during the display stage.

[0050] For example, such as Figure 3 , Figure 4 and Figure 5As shown, one noise cancellation transistor in the dual noise cancellation module 20 is the eighth thin-film transistor T8, and the other noise cancellation transistor is the ninth thin-film transistor T9. The gate of T8 is connected to the gate of T9, and the connection node is the first node QB. The source of T8 is connected to the source of T9. The drain of T8 is connected to the second node Q, and the drain of T9 is connected to the Gn point.

[0051] Bias control module 30, which is connected to the dual noise cancellation tube module 20, is used to input a bias control signal when the current frame is in a blank stage, so as to control the noise cancellation tube in the dual noise cancellation tube module 20 to be in the second bias state.

[0052] The second bias state has the opposite bias direction to the first bias state.

[0053] It should be noted that the first bias state is a positive bias state, and the second bias state is a negative bias state.

[0054] Through the above embodiments, the noise cancellation tube in the dual noise cancellation tube module is in a first bias state during the display stage, causing the IV characteristic of the noise cancellation tube in the dual noise cancellation tube module to shift to the left after experiencing the display stage. This application sets a bias control module in the GDL circuit. When the current frame is in a blank stage, the bias control module connects a bias control signal to control the dual noise cancellation tube module to be in a second bias state, so that the IV characteristic of the noise cancellation tube in the dual noise cancellation tube module shifts to the right after experiencing the blank stage, thereby offsetting part of the rightward shift of the IV characteristic of the noise cancellation tube in the dual noise cancellation tube module and suppressing the rightward shift of the IV characteristic of the dual noise cancellation tube in the GDL circuit. This solves the problem that the prior art cannot suppress the rightward shift of the IV characteristic of the dual noise cancellation tube in the GDL circuit and improves the LCD display performance.

[0055] In one alternative embodiment, such as Figure 3 As shown, the gate drive module 10 includes: a noise reduction control unit 101, the controlled terminal of the dual noise reduction transistor module 20 is connected to the noise reduction control unit 101, and the connection node is the first node QB; the bias control module 30 includes:

[0056] First signal terminal A1, which is connected to the first terminal of the dual noise cancellation module 20;

[0057] The noise reduction control unit 101 is used to output a low-level signal to the first node QB when the current frame is in the blank stage, so that the dual noise reduction tube module 20 is turned off.

[0058] The first signal terminal A1 is used to connect a high-level signal when the current frame is in the blank stage, so as to control the dual noise reduction tube module to be in a negative bias state.

[0059] For example, such as Figure 3 As shown, the gate of the eighth thin-film transistor T8 is connected to the gate of the ninth thin-film transistor T9, forming the controlled terminal of the dual noise reduction module 20, which is connected to the noise reduction control unit 101, and the connection node is the first node QB. In the blanking phase, the voltage of the second node Q is at a low level signal VGL (-11V). Therefore, T3 and T5 in the noise reduction control unit 101 are both turned off. Therefore, it is only necessary to control the GCH signal terminal to connect a low level signal VGL (-11V) in the blanking phase to turn off T4 and T2, thereby making the voltage of the first node QB at a low level signal VGL (-11V). This enables the noise reduction control unit 101 to output a low level signal VGL to the first node QB, so that T8 and T9 are in the off state. At this time, the voltage of the gate of T8 and the gate of T9 are both at a low level signal VGL (-11V).

[0060] For example, such as Figure 3 As shown, the sources of T8 and T9 are connected to form the first terminal of the dual noise cancellation module 20, which is connected to the first signal terminal A1. When the current frame is in a blank phase, the first signal terminal A1 is connected to a high-level signal VGL (17V), so that the voltage of the source of T8 and the source of T9 are both at the high-level signal VGL (17V). In the blank phase, the voltage of the gate of T8 and the gate of T9 are both at the low-level signal VGL (-11V). The voltage of the source of both T8 and T9 is greater than the voltage of the gate. Therefore, both T8 and T9 are in a negative bias state, and the bias voltage is V = -11 - 17 = -28V.

[0061] For example, the bias control signal is a high-level signal that is connected to the first signal terminal when the current frame is in the blank phase.

[0062] It should be noted that, as Figure 1 As shown, in the existing GDL circuit, the sources of the eighth thin-film transistor T8 and the ninth thin-film transistor T9 are connected to the VGL signal terminal. The VGL signal terminal is always connected to a low-level signal VGL during both the display and blanking phases. This ensures that during the maintenance phase of the display phase, when T8 is turned on, it pulls down the voltage of the second node Q to the low-level signal VGL. Similarly, during the maintenance phase of the display phase, when T9 is turned on, it pulls down the voltage of point Gn to the low-level signal VGL. In other words, during the maintenance phase of the display phase, T8 and T9 perform noise reduction processing on the second nodes Q and Gn, respectively. Figure 3As shown, in an optional GDL circuit of this application, the source of the eighth thin-film transistor T8 and the source of the ninth thin-film transistor T9 are both connected to the first signal terminal A1. In order to ensure the noise reduction function of the eighth thin-film transistor T8 and the ninth thin-film transistor T9 during the display stage, the first signal terminal A1 is used to connect a low-level signal VGL when the current frame is in the display stage, so that the source of T8 and the source of T9 are connected to the low-level signal VGL, that is, the noise reduction signal is connected, and the voltage of the second node Q and the voltage of the Gn point are pulled down to the low-level signal VGL in order to eliminate potential electrical noise interference, thereby ensuring the display quality of the LCD product.

[0063] In one alternative embodiment, such as Figure 4 and Figure 5 As shown, the bias control module 30 includes:

[0064] The system comprises a first switching unit 301, an energy storage unit 302, a second signal terminal A2, and a third signal terminal A3. The first terminal of the first switching unit 301 is connected to the first terminal of the dual noise cancellation module 20, the second terminal of the first switching unit 301 is connected to the second signal terminal A2, and the first controlled terminal of the first switching unit 301 is connected to the second signal terminal A2. The first capacitive terminal of the energy storage unit 302 is connected to the first terminal of the dual noise cancellation module 20, and the second capacitive terminal of the energy storage unit 302 is connected to the third signal terminal A3.

[0065] Among them, such as Figure 6 As shown, a frame consists of a Display phase and a Blank phase. The Blank phase is composed of a first Blank sub-phase B1 and a second Blank sub-phase B2. The third signal terminal A3 is used to apply a low-level signal when the current frame is in the first Blank sub-phase B1, and the second signal terminal A2 is used to apply a high-level signal when the current frame is in the first Blank sub-phase B1. The first switch unit 301 is used to turn on when a high-level signal is applied to the first controlled terminal, so that the second signal terminal A2 controls the energy storage unit 3. The first terminal of 02 is charged. The second signal terminal A2 is used to connect a low-level signal when the current frame is in the second blank sub-stage B2. The first switch unit 301 is used to turn off when the first controlled terminal is connected to a low-level signal. The third signal terminal A3 is used to connect a high-level signal when the current frame is in the second blank sub-stage B2. The energy storage unit 302 is used to perform charge conservation adjustment on the terminal voltage of the first capacitor terminal of the energy storage unit 302 when the second capacitor terminal is connected to a high-level signal, so as to control the dual noise cancellation tube module 20 to be in a negative bias state.

[0066] In one alternative embodiment, such as Figure 4and Figure 5 As shown, the bias control module 30 includes a fourth signal terminal A4, and the second controlled terminal of the first switching unit 301 is connected to the fourth signal terminal A4.

[0067] Wherein, the fourth signal terminal A4 is used to connect a high-level signal when the current frame is in the display stage, the second signal terminal A2 is used to connect a low-level signal when the current frame is in the display stage, and the first switch unit 301 is used to turn on when the second controlled terminal is connected to a high-level signal, so that the second signal terminal A2 outputs a low-level signal to the first terminal of the dual noise reduction tube module.

[0068] The fourth signal terminal A4 is used to input a low-level signal when the current frame is in the blank phase.

[0069] It should be noted that the aforementioned bias control signal includes a low-level signal connected to the third signal terminal when the current frame is in the first blank sub-stage, a high-level signal connected to the second signal terminal when the current frame is in the first blank sub-stage, a low-level signal connected to the second signal terminal when the current frame is in the second blank sub-stage, a high-level signal connected to the third signal terminal when the current frame is in the second blank sub-stage, and a low-level signal connected to the fourth signal terminal when the current frame is in the blank stage.

[0070] For example, such as Figure 4 and Figure 5 As shown, in the GDL circuit of this application, the source of the eighth thin-film transistor T8 and the source of the ninth thin-film transistor T9 are connected to form the first terminal of the dual noise cancellation module 20, which is connected to the first terminal of the first switching unit 301. In order to ensure the noise cancellation function of the eighth thin-film transistor T8 and the ninth thin-film transistor T9 during the display stage, the fourth signal terminal A4 is used to connect a high-level signal when the current frame is in the display stage, so that the second controlled terminal of the first switching unit 301 is connected to a high-level signal. The second signal terminal A2 is used to connect a low-level signal when the current frame is in the display stage. The first switching unit 301 is used to turn on when the second controlled terminal is connected to a high-level signal, so that the second signal terminal A2 outputs a low-level signal to T8 and T9, that is, T8 and T9 are connected to the above-mentioned noise cancellation signal, and the voltage of the second node Q and the voltage of the Gn point are pulled down to the low-level signal VGL in order to eliminate potential electrical noise interference, thereby ensuring the display quality of the LCD product.

[0071] For example, such as Figure 4 and Figure 5As shown, the first switching unit 301 is a dual-gate thin-film transistor T0. The positive gate of the dual-gate thin-film transistor T0 is the first controlled terminal of the first switching unit 301, the back gate of the dual-gate thin-film transistor T0 is the second controlled terminal of the first switching unit 301, the drain of the dual-gate thin-film transistor T0 is the first terminal of the first switching unit 301, and the source of the dual-gate thin-film transistor T0 is the second terminal of the first switching unit 301.

[0072] For example, such as Figure 4 and Figure 5 As shown, the energy storage unit 302 is the first capacitor C1.

[0073] In the case where the bias control module 30 includes a first switching unit 301, an energy storage unit 302, a second signal terminal A2, and a third signal terminal A3:

[0074] In a first alternative embodiment, such as Figure 4 As shown, the noise reduction control unit 101 is used to output a low-level signal to the first node QB when the current frame is in the blank stage, so that the dual noise reduction tube module 20 is turned off.

[0075] For example, such as Figure 4 As shown, the gate of the eighth thin-film transistor T8 is connected to the gate of the ninth thin-film transistor T9, forming the controlled terminal of the dual noise reduction module 20, which is connected to the noise reduction control unit 101, and the connection node is the first node QB. In the blanking phase, the voltage of the second node Q is at a low level signal VGL (-11V). Therefore, T3 and T5 in the noise reduction control unit 101 are both turned off. Therefore, it is only necessary to control the GCH signal terminal to connect a low level signal VGL (-11V) in the blanking phase to turn off T4 and T2, thereby making the voltage of the first node QB at a low level signal VGL (-11V). This enables the noise reduction control unit 101 to output a low level signal VGL to the first node QB, so that T8 and T9 are in the off state. At this time, the voltage of the gate of T8 and the gate of T9 are both at a low level signal VGL (-11V).

[0076] For example, the source of the eighth thin-film transistor T8 in the dual noise cancellation module 20 is connected to the source of the ninth thin-film transistor T9, forming the first terminal of the dual noise cancellation module 20, which is connected to the first capacitor terminal A of the energy storage unit 302, as shown below. Figure 4 and Figure 6As shown, during the Blank phase of the current frame, the second signal terminal A2 and the third signal terminal A3 are connected to high-level signals at staggered times. The second signal terminal A2 is connected to a high-level signal during the first Blank sub-phase B1, causing the first controlled terminal of the first switching unit 301 to connect to a high-level signal, opening the first switching unit 301. The second signal terminal A2 charges the energy storage unit 302, causing the source voltages of T8 and T9 to both be at a high-level signal VGH (17V). Then, during the Blank phase... The gate voltages of T8 and T9 are both at a low level signal VGL (-11V). At this time, the source voltages of both T8 and T9 are greater than their gate voltages, and T8 and T9 are in a negative bias state with a bias voltage of V = -11 - 17 = -28V. Energy storage unit 302 is fully charged. In the second blanking stage, the second signal terminal A2 of B2 is connected to a low level signal VGL (-11V), the first switching unit 301 is turned off, and charge is stored in energy storage unit 302. At this time, the energy storage unit... The voltage at the first capacitor terminal A of energy storage unit 302 is at a high level signal VGH (17V), and the voltage at the second capacitor terminal of energy storage unit 302 is at a low level signal VGL (-11V). The third signal terminal A3 is connected to the high level signal VGH (17V) at the second blanking stage B2, meaning the second capacitor terminal B is connected to the high level signal VGH (17V). The voltage at the second capacitor terminal B changes from the low level signal VGL to the high level signal VGH (17V), with a change in voltage of -11V to -17V. =28V. According to the law of conservation of charge, the change in charge at point A of the first capacitor is equal to the change in charge at point B. Therefore, the voltage at the first capacitor A is 17 + 28 = 45V. At this time, the source voltage of T8 and the source voltage of T9 are 45V. The gate voltage of T8 and the gate voltage of T9 are at a low level (-11V). The source voltage of both T8 and T9 is greater than the gate voltage. Both T8 and T9 are in a negative bias state, and the bias voltage is V = -11 - 45 = -56V.

[0077] In the case where the bias control module 30 includes a first switching unit 301, an energy storage unit 302, a second signal terminal A2, and a third signal terminal A3:

[0078] In a second alternative embodiment, such as Figure 5As shown, the gate drive module 10 includes a pre-charge unit 102, an output unit 103, and a noise reduction control unit 101. The pre-charge unit 102 is connected to the controlled terminal of the output unit 103, and the connection node is the second node Q. One noise reduction transistor in the dual noise reduction transistor module is an eighth thin-film transistor T8, and the other noise reduction transistor in the dual noise reduction transistor module is a ninth thin-film transistor T9. The first terminal of the eighth thin-film transistor T8 and the first terminal of the ninth thin-film transistor T9 are connected to form the first terminal of the dual noise reduction transistor module. The controlled terminal of the eighth thin-film transistor T8 is connected to the controlled terminal of the ninth thin-film transistor T9, and is also connected to the noise reduction control unit 101, with the connection node being the first node QB. The bias control module includes:

[0079] The second switching unit 303 and the third switching unit 304 are connected to the fourth signal terminal A4. The first terminal of the second switching unit 303 is connected to the second terminal of the eighth thin-film transistor T8 and the second terminal of the third switching unit 304 is connected to the second node Q. The first terminal of the third switching unit 304 is connected to the second terminal of the ninth thin-film transistor T9 and the second terminal of the third switching unit 304 is connected to the output terminal of the output unit.

[0080] The noise reduction control unit 101 is used to output a high-level signal to the first node QB when the current frame is in the blank stage, so that the dual noise reduction tube module 20 is turned on.

[0081] For example, such as Figure 5 As shown, the gate of the eighth thin-film transistor T8 is connected to the gate of the ninth thin-film transistor T9, forming the controlled terminal of the dual noise cancellation module 20, which is connected to the noise reduction control unit 101, and the connection node is the first node QB. In the blank stage, the voltage of the second node Q is at a low level signal VGL (-11V). Therefore, T3 and T5 in the noise reduction control unit 101 are both turned off. Therefore, it is only necessary to control the GCH signal terminal to connect a high level signal VGH (17V) in the blank stage to turn on T4 and T2, thereby making the voltage of the first node QB at a high level signal VGH (17V). This enables the noise reduction control unit 101 to output a high level signal VGH to the first node QB, making T8 and T9 turn on. At this time, the voltage of the gate of T8 and the gate of T9 are both at a high level signal VGH (17V).

[0082] For example, such as Figure 5 and Figure 6As shown, the source of the eighth thin-film transistor T8 in the dual noise cancellation module 20 is connected to the source of the ninth thin-film transistor T9, forming the first terminal of the dual noise cancellation module 20, which is connected to the first capacitor terminal A of the energy storage unit 302. When the current frame is in the blank stage, the second signal terminal A2 and the third signal terminal A3 are connected to high-level signals at different times. The second signal terminal A2 is connected to a high-level signal in the first blank sub-stage B1, so that the first controlled terminal of the first switching unit 301 is connected to a high-level signal, the first switching unit 301 is turned on, and the second signal terminal A2 is connected to the energy storage unit. Energy storage unit 302 is charged, causing the source voltages of T8 and T9 to be at a high level signal VGH (17V). During the blank phase, the gate voltages of T8 and T9 are also at a high level signal (17V). At this time, the source voltages of T8 and T9 are equal to their gate voltages. T8 and T9 are not under bias, and the bias voltage is V=17-17=0V. Energy storage unit 302 is fully charged. During the second blank phase, a low level signal VGL (-11V) is connected to the second signal terminal A2 of B2. The first switching unit 301 is closed, and charge is stored in the energy storage unit 302. At this time, the voltage of the first capacitor terminal A of the energy storage unit 302 is at a high level signal VGH (17V), and the voltage of the second capacitor terminal of the energy storage unit 302 is at a low level signal VGL (-11V). The third signal terminal A3 is connected to the high level signal VGH (17V) during the second blanking phase, that is, the second capacitor terminal B is connected to the high level signal VGH (17V), and the voltage of the second capacitor terminal B jumps from the low level signal VGL (-11V) to the high level signal VGH (17V). The voltage change at capacitor B is -11 - 17V = 28V. According to the law of conservation of charge, the change in charge at capacitor A is equal to the change in charge at capacitor B. Therefore, the voltage at capacitor A is 17 + 28 = 45V. That is, the source voltage of T8 and the source voltage of T9 are 45V. The gate voltage of T8 and the gate voltage of T9 are at a high level (17V). Since the source voltage of both T8 and T9 is greater than the gate voltage, both T8 and T9 are in a negative bias state, and the bias voltage is V = -17 - 45 = -28V.

[0083] For example, such as Figure 5As shown, if the dual noise cancellation module 20 is controlled to be in a negative bias state while simultaneously being turned on, a second switch unit 303 and a third switch unit 304 are added to the bias control module 30. The controlled terminals of both the second and third switch units 303 and 304 are connected to the fourth signal terminal A4. Since the fourth signal terminal A4 receives a low-level signal during the blanking phase, both the second and third switch units 303 and 304 are turned off during the blanking phase, disconnecting the eighth thin-film crystal in the dual noise cancellation module. The connection between transistor T8 and the second node Q is broken, and the connection between the ninth thin-film transistor T9 and point Gn in the dual noise cancellation module is disconnected. Since the fourth signal terminal A4 is connected to a high-level signal during the display stage, both the second switch unit 303 and the third switch unit 304 are turned on during the display stage, so that the eighth thin-film transistor T8 in the dual noise cancellation module is connected to the second node Q, and the ninth thin-film transistor T9 in the dual noise cancellation module is connected to point Gn, thus ensuring the noise reduction function of the eighth thin-film transistor T8 and the ninth thin-film transistor T9 in the dual noise cancellation module 20 during the display stage.

[0084] For example, such as Figure 5 As shown, the second switching unit 303 is the twelfth thin-film transistor Tb, and the third switching unit 304 is the thirteenth thin-film transistor Ta. The controlled terminal of the second switching unit 303 is the gate of the twelfth thin-film transistor Tb, the first terminal of the second switching unit 303 is the source of the twelfth thin-film transistor Tb, and the second terminal of the second switching unit 303 is the drain of the twelfth thin-film transistor Tb. The controlled terminal of the third switching unit 304 is the gate of the thirteenth thin-film transistor Ta, the first terminal of the third switching unit 304 is the source of the thirteenth thin-film transistor Ta, and the second terminal of the third switching unit 304 is the drain of the thirteenth thin-film transistor Ta. Both the twelfth thin-film transistor Tb and the thirteenth thin-film transistor Ta are N-type thin-film transistors.

[0085] For example, such as Figure 6As shown, the gate of the eighth thin-film transistor T8 is the controlled terminal of the eighth thin-film transistor T8, the source of the eighth thin-film transistor T8 is the first terminal of the eighth thin-film transistor T8, and the drain of the eighth thin-film transistor T8 is the second terminal of the eighth thin-film transistor T8. The gate of the ninth thin-film transistor T9 is the controlled terminal of the ninth thin-film transistor T9, the source of the ninth thin-film transistor T9 is the first terminal of the ninth thin-film transistor T9, and the drain of the ninth thin-film transistor T9 is the second terminal of the ninth thin-film transistor T9. The precharge unit 102 includes: the Gn-2 signal terminal, the VDS signal terminal, and the first thin-film transistor of this stage. T1, output unit 103 includes: the CLK signal terminal of this stage and the tenth thin film transistor T10. The controlled terminal of output unit 103 is the gate of the tenth thin film transistor T10. The output terminal of output unit 103 is the drain (i.e., Gn point) of the tenth thin film transistor T10. The source of the tenth thin film transistor T10 is connected to the CLK signal terminal of this stage. The gate of the first thin film transistor is connected to the Gn-2 signal terminal of this stage. The source of the first thin film transistor is connected to the VDS signal terminal. The drain of the first thin film transistor is connected to the gate of the tenth thin film transistor T10, and the connection node is the second node Q.

[0086] This application provides a driving method for the GDL circuit described above, which is applied to any of the aforementioned GDL circuits. The method includes:

[0087] Step S401: The gate driving signal is accessed through the gate driving module, and the current frame image is enabled to be displayed in the current pixel row under the drive of the gate driving signal.

[0088] Step S402: When the current frame is in the display stage, the gate drive module is denoised by the denoising signal connected to the dual noise cancellation tube module. The noise cancellation tube in the dual noise cancellation tube module is in the first bias state during the display stage.

[0089] Step S403: When the current frame is blank, the noise reduction tube in the dual noise reduction tube module is controlled to be in a second bias state by the bias control signal connected to the bias control module. The second bias state is opposite to the bias direction of the first bias state.

[0090] Through the above embodiments, the noise cancellation tube in the dual noise cancellation tube module is in a first bias state during the display stage, causing the IV characteristic of the noise cancellation tube in the dual noise cancellation tube module to shift to the left after experiencing the display stage. This application sets a bias control module in the GDL circuit. When the current frame is in a blank stage, the bias control module connects a bias control signal to control the dual noise cancellation tube module to be in a second bias state, so that the IV characteristic of the noise cancellation tube in the dual noise cancellation tube module shifts to the right after experiencing the blank stage, thereby offsetting part of the rightward shift of the IV characteristic of the noise cancellation tube in the dual noise cancellation tube module and suppressing the rightward shift of the IV characteristic of the dual noise cancellation tube in the GDL circuit. This solves the problem that the prior art cannot suppress the rightward shift of the IV characteristic of the dual noise cancellation tube in the GDL circuit and improves the LCD display performance.

[0091] This application provides a display panel, which includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes any of the above-described GDL circuits.

[0092] This application embodiment also provides a display device, which includes the aforementioned display panel, memory, processor, and a driver for a GDL circuit stored in the memory and executable on the processor. When the processor executes the driver for the GDL circuit, it implements the steps of the driving method for the GDL circuit.

[0093] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0094] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0095] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0096] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A GDL circuit, characterized in that, The GDL circuit includes: A gate driving module is used to receive a scan driving signal and enable the current pixel row to display the current frame under the drive of the scan driving signal. A dual noise cancellation transistor module is connected to the gate driving module. The dual noise cancellation transistor module is used to input a noise reduction signal to perform noise reduction processing on the gate driving module when the current frame is in the display stage. The noise reduction transistor in the dual noise cancellation transistor module is in a first bias state during the display stage. A bias control module is connected to the dual noise cancellation tube module. The bias control module is used to input a bias control signal when the current frame is in a blank stage, so as to control the noise cancellation tube in the dual noise cancellation tube module to be in a second bias state, wherein the bias direction of the second bias state is opposite to that of the first bias state. The bias control module includes: The system comprises a first switching unit, an energy storage unit, a second signal terminal, and a third signal terminal. The first terminal of the first switching unit is connected to the first terminal of the dual noise cancellation tube module, the second terminal of the first switching unit is connected to the second signal terminal, and the first controlled terminal of the first switching unit is connected to the second signal terminal. The first capacitor terminal of the energy storage unit is connected to the first terminal of the dual noise cancellation tube module, and the second capacitor terminal of the energy storage unit is connected to the third signal terminal. The blanking phase consists of a first blanking sub-phase and a second blanking sub-phase. The third signal terminal is used to connect a low-level signal when the current frame is in the first blanking sub-phase. The second signal terminal is used to connect a high-level signal when the current frame is in the first blanking sub-phase. The first switching unit is used to turn on when the first controlled terminal connects to a high-level signal, so that the second signal terminal charges the first terminal of the energy storage unit. The second signal terminal is used to connect a low-level signal when the current frame is in the second blanking sub-phase. The first switching unit is used to turn off when the first controlled terminal connects to a low-level signal. The third signal terminal is used to connect a high-level signal when the current frame is in the second blanking sub-phase. The energy storage unit is used to perform charge conservation regulation on the voltage of the first capacitor terminal of the energy storage unit when the second capacitor terminal connects to a high-level signal, so as to control the dual noise cancellation tube module to be in a negative bias state. The energy storage unit is a first capacitor, with the first capacitor terminal being one end of the first capacitor and the second capacitor terminal being the other end of the first capacitor.

2. The GDL circuit according to claim 1, wherein the gate driving module comprises: A noise reduction control unit, wherein the controlled terminal of the dual noise reduction tube module is connected to the noise reduction control unit, and the connection node is the first node, characterized in that the bias control module includes: The first signal terminal is connected to the first terminal of the dual noise cancellation module; The noise reduction control unit is used to output a low-level signal to the first node when the current frame is in the blank stage, so as to turn off the dual noise reduction tube module. The first signal terminal is used to input a high-level signal when the current frame is in the blank stage, so as to control the dual noise cancellation tube module to be in a negative bias state.

3. The GDL circuit according to claim 1, characterized in that, The bias control module includes: a fourth signal terminal, wherein the second controlled terminal of the first switching unit is connected to the fourth signal terminal; The fourth signal terminal is used to receive a high-level signal when the current frame is in the display stage, the second signal terminal is used to receive a low-level signal when the current frame is in the display stage, and the first switch unit is used to turn on when the second controlled terminal receives a high-level signal, so that the second signal terminal outputs a low-level signal to the first terminal of the dual noise reduction tube module. The fourth signal terminal is used to connect a low-level signal when the current frame is in the blank phase.

4. The GDL circuit according to claim 3, wherein the gate driving module comprises: A noise reduction control unit, wherein the controlled terminal of the dual noise reduction tube module is connected to the noise reduction control unit and the connection node is the first node, characterized in that the noise reduction control unit is used to output a low-level signal to the first node when the current frame is in the blank stage, so as to turn off the dual noise reduction tube module.

5. The GDL circuit according to claim 3, wherein the gate driving module comprises: The system comprises a pre-charge unit, an output unit, and a noise reduction control unit. The pre-charge unit is connected to the controlled terminal of the output unit, and the connection node is the second node. One noise reduction transistor in the dual noise reduction transistor module is an eighth thin-film transistor, and the other noise reduction transistor in the dual noise reduction transistor module is a ninth thin-film transistor. The first terminals of the eighth and ninth thin-film transistors are connected to form the first terminal of the dual noise reduction transistor module. The controlled terminal of the eighth and ninth thin-film transistors is connected to the controlled terminal of the ninth thin-film transistor and is also connected to the noise reduction control unit, with the connection node being the first node. The bias control module includes: The second switch unit and the third switch unit are connected to the fourth signal terminal. The first terminal of the second switch unit is connected to the second terminal of the eighth thin-film transistor. The second terminal of the second switch unit is connected to the second node. The first terminal of the third switch unit is connected to the second terminal of the ninth thin-film transistor. The second terminal of the third switch unit is connected to the output terminal of the output unit. The noise reduction control unit is used to output a high-level signal to the first node when the current frame is in the blank stage, so as to turn on the dual noise reduction tube module.

6. The GDL circuit according to claim 3, characterized in that, The first switching unit is a dual-gate thin-film transistor, the positive gate of the dual-gate thin-film transistor is the first controlled terminal of the first switching unit, and the back gate of the dual-gate thin-film transistor is the second controlled terminal of the first switching unit.

7. A driving method for a GDL circuit, characterized in that, The driving method for the GDL circuit is applied to the GDL circuit according to any one of claims 1 to 5, the method comprising: The gate driving module receives the gate driving signal and enables the current pixel row to display the current frame under the drive of the gate driving signal. When the current frame is in the display stage, the gate drive module is denoised by the denoising signal connected to the dual denoising tube module. The denoising tube in the dual denoising tube module is in the first bias state during the display stage. When the current frame is blank, the bias control module receives a bias control signal to control the noise reduction tube in the dual noise reduction tube module to be in a second bias state, wherein the bias direction of the second bias state is opposite to that of the first bias state.

8. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes the GDL circuit according to any one of claims 1 to 6.

9. A display device, characterized in that, The display device includes the display panel as described in claim 8, a memory, a processor, and a driver for a GDL circuit stored in the memory and executable on the processor. When the processor executes the driver for the GDL circuit, it implements the steps of the driving method for the GDL circuit as described in claim 7.

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