Display device

Abstract

A display device is disclosed. The display device includes: a substrate; a first planarization layer disposed on the substrate; conductive patterns disposed on the first planarization layer and spaced apart from each other; a barrier layer disposed on the first planarization layer, at least a portion of a top surface of the conductive pattern being not covered by the barrier layer; and a second planarization layer disposed on the conductive pattern and the barrier layer. According to the invention, the flatness of the pixel electrode is improved, and the degassing from the planarization layer is reduced, so that the low-power display device is realized.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, for example, but not limited to, a display device in which the flatness of pixel electrodes is improved. Background Technology

[0002] With the development of the information society, the demand for display devices that display images has increased, and various types of display devices such as liquid crystal displays and light-emitting displays are being used.

[0003] A light-emitting display device includes a light-emitting device that emits light in a display area, and the light-emitting device includes an anode, a light-emitting layer, and a cathode. The light-emitting device must be formed on a flat surface to emit light uniformly and consistently.

[0004] Various components, including wiring and driving elements for supplying signals and voltages, are formed beneath the light-emitting device. These components cause surface unevenness and result in height differences.

[0005] A planarization layer made of organic material can be provided to stably position the light-emitting device on the planarization surface and planarize the lower part of the light-emitting device.

[0006] The description provided in the Background section should not be assumed to be prior art simply because it is mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter art, and the description in this section does not limit this disclosure. Summary of the Invention

[0007] The inventors have recognized the problems and shortcomings in the related art. Therefore, exemplary embodiments of this disclosure can provide a display device with improved flatness in which the flatness of the pixel electrodes is improved.

[0008] Exemplary embodiments of this disclosure can provide a display device with improved visibility under reflected light.

[0009] Exemplary embodiments of this disclosure may provide a display device that improves gas release from a planarization layer.

[0010] The exemplary embodiments disclosed herein are not limited to the objectives described above, and other objectives not specifically mentioned will be clearly understood by those skilled in the art from the following description.

[0011] Exemplary embodiments of this disclosure may provide a display device comprising: a substrate; a first planarization layer disposed on the substrate; conductive patterns disposed on the first planarization layer, adjacent conductive patterns being spaced apart from each other; a barrier layer disposed on the first planarization layer, wherein at least a portion of the top surface of the conductive patterns is not covered by the barrier layer; and a second planarization layer disposed on the conductive patterns and the barrier layer, wherein the barrier layer includes through-holes located between the conductive patterns.

[0012] Exemplary embodiments of this disclosure may provide a display device comprising: a substrate; a first planarization layer disposed on the substrate; a conductive pattern disposed on the first planarization layer and arranged along a first direction; a barrier layer disposed on the first planarization layer; a second planarization layer disposed on the conductive pattern and the barrier layer; a pixel electrode disposed on the second planarization layer; and a dam disposed on the pixel electrode and including an opening that exposes a portion of the top surface of the pixel electrode, wherein the barrier layer includes an open region, wherein at least a portion of the top surface of the conductive pattern is not covered by the barrier layer, and the open region is positioned to overlap at least a portion of the pixel electrode.

[0013] Exemplary embodiments of this disclosure may provide a display device comprising: a substrate; a first planarization layer disposed on the substrate; a conductive pattern disposed on the first planarization layer and extending along a first direction, adjacent conductive patterns being spaced apart along a second direction perpendicular to the first direction; a barrier layer disposed on the conductive pattern and the first planarization layer; a second planarization layer disposed on the conductive pattern and the barrier layer; and a light-emitting region configured to overlap with the conductive pattern, wherein the barrier layer includes an open region, wherein at least a portion of the top surface of the conductive pattern is not covered, and the open region is positioned to overlap at least a portion of the light-emitting region.

[0014] Exemplary embodiments of this disclosure may provide a display device in which a blocking layer includes a through-hole located between conductive patterns, and a first planarization layer and a second planarization layer may contact each other at the through-hole.

[0015] Exemplary embodiments of this disclosure may provide a display panel comprising: a substrate; a first planarization layer disposed on the substrate; conductive patterns disposed on the first planarization layer, adjacent conductive patterns being spaced apart from each other; a barrier layer disposed on the first planarization layer, wherein at least a portion of the top surface of the conductive patterns is not covered by the barrier layer; and a second planarization layer disposed on the conductive patterns and the barrier layer, wherein the barrier layer includes through-holes located between the conductive patterns.

[0016] Exemplary embodiments of this disclosure may provide a display panel comprising: a substrate; a first planarization layer disposed on the substrate; a conductive pattern disposed on the first planarization layer and arranged along a first direction; a barrier layer disposed on the first planarization layer; a second planarization layer disposed on the conductive pattern and the barrier layer; a pixel electrode disposed on the second planarization layer; and a dam disposed on the pixel electrode and including an opening that exposes a portion of the top surface of the pixel electrode, wherein the barrier layer includes an open region, wherein at least a portion of the top surface of the conductive pattern is not covered by the barrier layer, and the open region is positioned to overlap at least a portion of the pixel electrode.

[0017] Exemplary embodiments of this disclosure may provide a display panel comprising: a substrate; a first planarization layer disposed on the substrate; a conductive pattern disposed on the first planarization layer and extending along a first direction, adjacent conductive patterns being spaced apart along a second direction perpendicular to the first direction; a barrier layer disposed on the conductive pattern and the first planarization layer; a second planarization layer disposed on the conductive pattern and the barrier layer; and a light-emitting region configured to overlap with the conductive pattern, wherein the barrier layer includes an open region, wherein at least a portion of the top surface of the conductive pattern is not covered, and the open region is positioned to overlap at least a portion of the light-emitting region.

[0018] According to an exemplary embodiment of the present disclosure, a display device can provide improved flatness of pixel electrodes by providing a barrier layer between conductive patterns located below the pixel electrodes.

[0019] According to an exemplary embodiment of this disclosure, visibility under reflected light can be improved by enhancing the flatness of the pixel electrodes.

[0020] According to an exemplary embodiment of this disclosure, a display device that improves gas release from the planarization layers can be provided by providing a barrier layer with through holes between the planarization layers.

[0021] According to exemplary embodiments of this disclosure, a low-power display device can be provided by improving the flatness of the pixel electrodes and the degassing characteristics of the planarization layer.

[0022] The effects of the exemplary embodiments described herein are not limited to those listed above, and those skilled in the art will clearly understand from the scope of the claims any additional effects not specifically mentioned. Attached Figure Description

[0023] This disclosure will be more fully understood from the following detailed description and accompanying drawings. The detailed description and accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this specification.

[0024] Figure 1This is a system configuration diagram of a display device according to an exemplary embodiment of the present disclosure.

[0025] Figure 2 A display panel according to an exemplary embodiment of the present disclosure is shown.

[0026] Figure 3 This is a cross-sectional view of a display panel according to an exemplary embodiment of the present disclosure.

[0027] Figure 4 This is a schematic plan view illustrating a plurality of sub-pixels arranged in a display area of ​​a display panel according to an exemplary embodiment of the present disclosure.

[0028] Figure 5 , Figure 6 and Figure 7 It is along Figure 4 Example cross-section diagram taken from line AB in the diagram.

[0029] Figure 8 and Figure 9 It is along Figure 4 Example cross-sectional view taken from line C–D in the diagram.

[0030] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Implementation

[0031] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. The described progression of processing steps and / or operations is illustrative; however, the order of steps and / or operations is not limited to that described herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following explanation may have been chosen merely for convenience of writing the specification and may therefore differ from the names used in actual products.

[0032] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that can be implemented, and wherein the same reference numerals and symbols may be used to denote the same or similar components, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that such detailed descriptions might make the subject matter of some embodiments of this disclosure considerably unclear.

[0033] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc. of the elements shown in the accompanying drawings for describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.

[0034] The dimensions of the various components shown in the accompanying drawings, including size and thickness, are shown for ease of description, and this disclosure is not limited to the size and thickness of the components shown. However, it should be noted that the relative dimensions of the components shown in the various accompanying drawings, including relative size, position, and thickness, are part of this disclosure.

[0035] Terms such as “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed by,” “composed of,” and “component of” as used herein are generally intended to allow for the addition of other components, unless these terms are used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0036] When using terms such as “on top of,” “above,” “above,” “below,” “below,” “next to,” “under,” “near,” “close to,” “adjacent to,” “on the side of,” or “near” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless the term is used with the terms “exactly” or “directly.”

[0037] Spatially relative terms such as “below,” “under,” “below,” “lower,” “above,” “upper,” etc., may be used in this document to describe the relationship between one element or feature and another element or feature as illustrated in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of elements in use or operation. For example, if an element in the figure is inverted, an element described as “below” or “below” other elements or features would be oriented as “above” other elements or features. Thus, the exemplary term “below” can include both lower and upper orientations. Similarly, the exemplary terms “above” or “above” can include both upper and lower orientations.

[0038] The term “exemplary” is used to indicate that something is an example or illustration. “Aspect” refers to an exemplary aspect. “Implementation,” “example,” “aspect,” etc., should not be construed as superior to or best of other implementations. Unless otherwise stated, implementation, example, exemplary implementation, aspect, etc., may refer to one or more implementations, one or more examples, one or more exemplary implementations, one or more aspects, etc.

[0039] When an element or layer is placed "on" another element or layer, the other layer or element can be directly inserted on or between the other element.

[0040] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of this disclosure. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but merely to distinguish the corresponding element from other elements.

[0041] When referring to the first element and the second element as "connected or joined," "in contact or overlapping," etc., it should be interpreted as meaning that not only can the first element be "directly connected or joined" or "directly in contact or overlapping" with the second element, but also that a third element can be "inserted" between the first and second elements, or that the first and second elements can be "connected or joined," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc., with each other.

[0042] When time-related terms such as “after,” “following,” “next,” or “before” are used to describe a process or operation of an element or configuration, or a flow or step in an operating method, processing method, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless the terms “directly” or “immediately” are used together.

[0043] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical or corresponding information of an element or feature (e.g., level, range, etc.) includes the tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.), even if no relevant description is specified. Moreover, the term "may" fully encompasses all the meanings of the term "able to".

[0044] The term "at least one" should be understood to include all possible combinations that can be suggested from one or more related projects. For example, "at least one of the first, second, or third projects" can mean each of the first, second, or third projects, and can also mean all possible combinations that can be suggested from two or more of the first, second, and third projects.

[0045] As used herein, the term "device" can refer to a display device that includes a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting elements, etc. Additionally, examples of devices may include laptops, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as assemblies of electronic devices (or equipment) or assemblies (or devices) that include light-emitting elements, etc., as complete products or end products, such as mobile electronic devices like smartphones or tablets, but embodiments of this disclosure are not limited thereto.

[0046] Features of the various embodiments of this disclosure may be partially or wholly adhered to or combined with each other, and may be interlocked and operated in various technical ways, and the embodiments may be performed independently or in association with each other.

[0047] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will be further understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0048] In this disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode are used interchangeably. A source electrode can be a drain electrode, and a drain electrode can be a source electrode. Furthermore, a source electrode in any aspect of this disclosure can be a drain electrode in another aspect of this disclosure, and a drain electrode in any aspect of this disclosure can be a source electrode in another aspect of this disclosure.

[0049] In the specification, when adding reference numerals to elements in each figure, care should be taken to ensure that, whenever possible, the same reference numerals used to denote the element in other figures are used for that element. Furthermore, for ease of description, the scale of the constituent elements shown in the figures may differ from the actual scale. That is, the scale of the constituent elements shown in the figures should not be interpreted as the same as the scale shown in the figures.

[0050] Various exemplary embodiments of this specification will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 This is a system configuration diagram of a display device 100 according to an exemplary embodiment of the present disclosure.

[0052] Reference Figure 1The display device 100 according to an exemplary embodiment of the present disclosure may include components for image display, such as a display panel 110, and a display driving circuit. The display driving circuit may be a circuit for driving the display panel 110, and may include a data driving circuit 120, a gating driving circuit 130, and a controller 140.

[0053] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111.

[0054] The substrate 111 may include a display area DA that can display images and a non-display area NDA located outside the display area DA.

[0055] The substrate 111 can be made of glass, metal, plastic, etc., but is not limited thereto. When the display device is a flexible display device, the substrate 101 can be made of a flexible material such as plastic. For example, the substrate may include a flexible polymer film. For example, the flexible polymer film can be made of any of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyaryl ester (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS). For example, the substrate 111 may include a transparent polyimide material, and this disclosure is not limited thereto.

[0056] The display area DA can also be called the display region, and multiple sub-pixels SP used for image display can be set in the display area DA. The non-display area NDA can also be called the non-display region, and may include pad areas.

[0057] In the display panel 110 according to an exemplary embodiment of the present disclosure, the non-display area NDA can be very small. In this specification, the non-display area NDA may also be referred to as a "bezel". For example, the non-display area NDA may include a first non-display area located outside the display area DA along a first direction, a second non-display area located outside the display area DA along a second direction, a third non-display area located outside the display area DA along a direction opposite to the first direction, and a fourth non-display area located outside the display area DA along a direction opposite to the second direction.

[0058] The first non-display area may include a pad area connected to or bonded with driving circuitry. The second to fourth non-display areas can be very small in size.

[0059] In another example, the boundary region between the display area DA and the non-display area NDA can be bent, such that the non-display area NDA lies below the display area DA. In this case, the non-display area NDA may be almost invisible or completely invisible when a user views the display device 100 from the front. For example, the first non-display area may include a bent region. By bending the bent region, the first non-display area may be invisible from the front.

[0060] Various types of signal lines for driving multiple sub-pixels SP can be provided on the substrate 111 of the display panel 110.

[0061] The display device 100 according to an exemplary embodiment of the present disclosure may be a liquid crystal display device or a self-emissive display device in which the display panel 110 emits its own light. When the display device 100 is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting device.

[0062] For example, the display device 100 according to an exemplary embodiment of this disclosure may be an organic light-emitting display device, wherein the light-emitting device is implemented as an organic light-emitting diode (OLED). In another example, the display device 100 may be an inorganic light-emitting display device, wherein the light-emitting device is implemented as a light-emitting diode based on inorganic materials. In yet another example, the display device 100 may be a quantum dot display device, wherein the light-emitting device is implemented as a quantum dot, which is a self-emissive semiconductor crystal.

[0063] A unit pixel is composed of red (R) subpixels, green (G) subpixels, and blue (B) subpixels, or it is composed of red (R) subpixels, green (G) subpixels, blue (B) subpixels, and white (W) subpixels. However, this disclosure is not limited to this. The multiple subpixels SP constituting a unit pixel can be modified in various ways in terms of color and configuration as needed.

[0064] For example, each of the plurality of sub-pixels SP can emit light with a different wavelength from each other. For example, the plurality of sub-pixels SP may include red sub-pixels, green sub-pixels, and blue sub-pixels, wherein the red, green, and blue sub-pixels may be arranged in a repeating manner. Alternatively, the plurality of sub-pixels SP may include red, green, blue, and white sub-pixels, wherein the red, green, blue, and white sub-pixels may be arranged in a repeating manner, or the red, green, blue, and white sub-pixels may be arranged in a quadrilateral pattern. For example, the red, blue, and green sub-pixels may be arranged sequentially along the row direction, or the red, blue, green, and white sub-pixels may be arranged sequentially along the row direction. However, in embodiments of this disclosure, the color type, arrangement type, and arrangement order of the sub-pixels are not limited and can be configured in various forms according to light-emitting characteristics, device lifetime, and device specifications.

[0065] Furthermore, depending on their light-emitting characteristics, sub-pixels can have different light-emitting areas. For example, a sub-pixel that emits light of a different color than the blue sub-pixel can have a different light-emitting area than the blue sub-pixel. For example, red, blue, and green sub-pixels, or red, blue, white, and green sub-pixels, can each have different light-emitting areas.

[0066] The structure of each subpixel SP can vary depending on the type of display device 100. For example, when the display device 100 is a self-emissive display device in which the subpixels SP emit their own light, each subpixel SP may include a light-emitting device, one or more transistors, and one or more capacitors.

[0067] For example, various types of signal lines may include multiple data lines DL for transmitting data signals (also known as data voltages or image signals) and multiple gating lines GL for transmitting gating signals (also known as scan signals).

[0068] For example, multiple data lines DL and multiple gate lines GL can intersect each other. Each of the multiple data lines DL can extend and be configured along a first direction, and each of the multiple gate lines GL can extend and be configured along a second direction. The first direction can be a column direction, and the second direction can be a row direction. Alternatively, the first direction can be a row direction, and the second direction can be a column direction. In the following description, for convenience, the first direction will be referred to as the column direction, and the second direction as the row direction. Therefore, each of the multiple data lines DL is configured along the column direction, and each of the multiple gate lines GL is configured along the row direction. However, the exemplary embodiments of this disclosure are not limited thereto.

[0069] The data driving circuit 120 can be a circuit used to drive multiple data lines DL, and can output data signals to multiple data lines DL.

[0070] The data drive circuit 120 can receive digital image data DATA from the controller 140, convert the received image data DATA into analog data signals, and output the data signals to multiple data lines DL.

[0071] For example, the data drive circuit 120 can be connected to the display panel 110 via a tape-on-absence (TAB) method, to the bonding pads of the display panel 110 via a chip-on-glass (COG) method or a chip-on-panel (COP) method, or to the display panel 110 via a chip-on-film (COF) method. However, the connection method is not limited to these.

[0072] The data driving circuit 120 may be connected to one side of the display panel 110 (e.g., the top or bottom side). Alternatively, depending on the driving method and panel design, the data driving circuit 120 may be connected to both sides of the display panel 110 (e.g., the top and bottom sides), or to two or more of the four sides of the display panel 110.

[0073] The data driving circuit 120 can be connected to the outer area of ​​the display area DA of the display panel 110. In another example, the data driving circuit 120 can be disposed within the display area DA of the display panel 110.

[0074] The gating drive circuit 130 can be a circuit used to drive multiple gating lines GL, and can output gating signals to multiple gating lines GL.

[0075] The gating drive circuit 130 can receive a first gating voltage corresponding to the on level and a second gating voltage corresponding to the off level, and together receive a gating drive control signal GCS. The gating drive circuit 130 can generate a gating signal based on the received signal and supply the generated gating signal to multiple gating lines GL.

[0076] In the display device 100 according to an exemplary embodiment of the present disclosure, the gating drive circuit 130 may be embedded in the display panel 110 as an in-panel gating (GIP) type. When the gating drive circuit 130 is an in-panel gating type, it may be formed on the substrate 111 of the display panel 110 during the manufacturing process of the display panel 110.

[0077] For example, the gating drive circuit 130 can be set in the non-display area NDA of the display panel 110.

[0078] In another example, the gating drive circuit 130 may be disposed in the display area DA of the display panel 110. In this case, for example, the gating drive circuit 130 may be disposed in a first sub-region within the display area DA (e.g., the left or right sub-region within the display area DA). In another example, the gating drive circuit 130 may be disposed in a first sub-region (e.g., the left or right sub-region within the display area DA) and a second sub-region (e.g., the right or left sub-region within the display area DA) within the display area DA.

[0079] In this disclosure, the gating drive circuit 130 embedded in the display panel 110 as an in-panel gating type can also be referred to as an "in-panel gating circuit".

[0080] The controller 140 can be configured to connect to various processors, such as microprocessors, mobile processors, application processors, etc., depending on the device installed therein.

[0081] The controller 140 can be a device for controlling the data drive circuit 120 and the gating drive circuit 130, and can control the driving timing of multiple data lines DL and multiple gating lines GL.

[0082] The controller 140 can supply a data drive control signal DCS to the data drive circuit 120 for control, and can supply a gating drive control signal GCS to the gating drive circuit 130 for control.

[0083] The controller 140 can receive input image data from the host system 150 and supply image data DATA to the data drive circuit 120 based on the input image data.

[0084] The controller 140 can be implemented as a separate component from the data drive circuit 120, or it can be integrated with the data drive circuit 120 into a single integrated circuit.

[0085] Controller 140 may be a timing controller used in display technology or a control device that includes a timing controller and performs additional control functions. Alternatively, controller 140 may be a control device or circuitry within a control device that differs from a timing controller. Controller 140 may be implemented using various types of circuitry or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors, but is not limited thereto.

[0086] The controller 140 can be mounted on a printed circuit board (PCB), flexible printed circuit (FPC), etc., and can be electrically connected to the data drive circuit 120 and the gating drive circuit 130 via the PCB, FPC, etc.

[0087] The controller 140 can send signals to and receive signals from the data drive circuit 120 according to one or more predetermined interfaces. For example, the interface may include a low-voltage differential signaling (LVDS) interface, an embedded point-to-point clock interface (EPI), a serial peripheral interface (SPI), etc., but is not limited to these.

[0088] A display device 100 according to an exemplary embodiment of the present disclosure may include a touch sensor and a touch sensing circuit, thereby providing not only image display functionality but also touch sensing functionality, which detects that a touch has occurred by a touch object such as a finger or a pen or detects the touch location.

[0089] The touch sensing circuit may include a touch driving circuit and a touch controller. The touch driving circuit drives and senses the touch sensor to generate and output touch sensing data. The touch controller detects whether a touch has occurred or detects the touch location based on the touch sensing data.

[0090] A touch sensor may include multiple touch electrodes. A touch sensor may also include multiple touch lines that electrically connect the multiple touch electrodes to touch driving circuitry.

[0091] The touch sensor can be disposed outside the display panel 110 in the form of a touch panel, or it can be located inside the display panel 110. When the touch sensor is located outside the display panel 110 in the form of a touch panel, it is referred to as an external type. When the touch sensor is of the external type, the touch panel and the display panel 110 can be manufactured separately and joined together during assembly. The external type touch panel may include a touch panel substrate and a plurality of touch electrodes formed on the touch panel substrate.

[0092] When the touch sensor is located inside the display panel 110, the touch sensor can be formed on the substrate together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0093] The touch driving circuit can provide a touch driving signal to at least one of a plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0094] Touch sensing circuits can perform touch sensing using self-capacitance sensing or mutual capacitance sensing methods.

[0095] When a touch sensing circuit performs touch sensing using a self-capacitance sensing method, it can perform touch sensing based on the capacitance between each touch electrode and the touched object (e.g., a finger or pen). In the self-capacitance sensing method, each of a plurality of touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all or some of the plurality of touch electrodes and sense all or some of the plurality of touch electrodes.

[0096] When a touch sensing circuit uses a mutual capacitance sensing method to perform touch sensing, it can perform touch sensing based on the capacitance between the touch electrodes. In the mutual capacitance sensing method, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0097] The touch driving circuit and touch controller included in the touch sensing circuit can be implemented as separate devices or a single integrated device. Similarly, the touch driving circuit and data driving circuit can be implemented as separate devices or a single device.

[0098] The display device 100 may also include a power supply circuit for providing various power supplies to the display driving circuit and / or touch sensing circuit.

[0099] The display device 100 according to the exemplary embodiments of this disclosure may be a mobile terminal such as a smartphone or tablet computer, or a monitor or television (TV) of various sizes, but is not limited thereto. It may be a display of various types and sizes capable of displaying information or images.

[0100] The display device 100 according to an exemplary embodiment of this disclosure may also include electronic devices such as a camera (image sensor) and a detection sensor. For example, the detection sensor may be a sensor that detects objects or the human body by receiving light such as infrared light, ultrasonic light, or ultraviolet light.

[0101] Figure 2 A display panel 110 according to an exemplary embodiment of the present disclosure is shown. In the following description, references will be omitted or briefly described. Figure 1 The content described is the same or similar.

[0102] Reference Figure 2 The display panel 110 may include a substrate 111 having a plurality of sub-pixels SP and an encapsulation layer 200 located on the substrate 111. The encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation section.

[0103] Reference Figure 2When the display device 100 according to an exemplary embodiment of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP disposed on the substrate 111 may include a light-emitting device ED and a sub-pixel circuit SPC for driving the light-emitting device ED.

[0104] Reference Figure 2 The sub-pixel circuit SPC may include a plurality of transistors for driving the light-emitting device ED and at least one capacitor. In this disclosure, the sub-pixel circuit SPC can drive the light-emitting device ED by supplying a drive current to the light-emitting device ED at predetermined timings. The light-emitting device ED can emit light by being driven by the drive current.

[0105] The multiple transistors may include a driving transistor DT for driving the light-emitting device ED and a scanning transistor ST that is turned on or off according to the scanning signal SC.

[0106] The active layer of a transistor can be formed from semiconductor materials, such as oxide semiconductors, amorphous semiconductors, or polycrystalline semiconductors, but is not limited to these.

[0107] Oxide semiconductor materials offer excellent leakage current prevention and relatively low manufacturing costs. Oxide semiconductors can be made from metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals and their oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti). Specifically, oxide semiconductors can include, but are not limited to, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO).

[0108] Polycrystalline semiconductor materials exhibit high mobility due to the fast movement speed of charge carriers such as electrons and holes, resulting in low energy consumption and excellent reliability. Polycrystalline semiconductors can be made of polycrystalline silicon (poly-Si), but are not limited to this.

[0109] Amorphous semiconductor materials can be made of amorphous silicon (a-Si), but are not limited to this.

[0110] The driving transistor DT can supply driving current to the light-emitting device ED.

[0111] The scanning transistor ST can be configured to control the electrical state of the corresponding node within the sub-pixel circuit SPC, or to control the state or operation of the driving transistor DT.

[0112] At least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during a frame.

[0113] To drive the sub-pixel SP, a data signal VDATA, which serves as an image signal, and a scan signal SC, which serves as a gating signal, can be applied to the sub-pixel SP. Furthermore, to drive the sub-pixel SP, a common driving voltage comprising a first common driving voltage VDD and a second common driving voltage VSS can be applied to the sub-pixel SP.

[0114] The light-emitting device (ED) may include a pixel electrode (PE), an intermediate layer (EL), and a common electrode (CE). The intermediate layer (EL) may be disposed between the pixel electrode (PE) and the common electrode (CE).

[0115] For example, a pixel electrode PE can be an electrode disposed in each sub-pixel SP, and a common electrode CE can be an electrode commonly disposed for multiple sub-pixels SP. In one example, the pixel electrode PE can be an anode, and the common electrode CE can be a cathode. In another example, the pixel electrode PE can be a cathode, and the common electrode CE can be an anode. In the following description, for ease of illustration, an example is given where the pixel electrode PE is an anode and the common electrode CE is a cathode.

[0116] When the light-emitting device ED is an organic light-emitting device, the intermediate layer EL may include a light-emitting layer EML, a first common intermediate layer COM1 located between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 located between the light-emitting layer EML and the common electrode CE. The first common intermediate layer COM1 and the second common intermediate layer COM2 can be collectively referred to as the common intermediate layer EL_COM.

[0117] An emissive layer EML can be set for each sub-pixel SP, and a common intermediate layer EL_COM can be set above multiple sub-pixels SP.

[0118] An E-layer (EML) can be set for each luminescent region, and a common intermediate layer (EL_COM) can be set on multiple luminescent and non-luminescent regions.

[0119] For example, the first common intermediate layer COM1 may include a hole injection layer HIL and a hole transport layer HTL. The second common intermediate layer COM2 may include an electron transport layer ETL and an electron injection layer EIL.

[0120] The hole injection layer injects holes from the pixel electrode (PE) into the hole transport layer, and the hole transport layer transmits the holes to the light-emitting layer (EML). The electron injection layer injects electrons from the common electrode (CE) into the electron transport layer, and the electron transport layer transmits the electrons to the light-emitting layer (EML).

[0121] For example, the common electrode CE can be electrically connected to the second common driving voltage line VSSL. The second common driving voltage VSS can be applied to the common electrode CE through the second common driving voltage line VSSL. The pixel electrode PE can be electrically connected directly or indirectly (through another transistor) to the first node N1 of the driving transistor DT in each sub-pixel SP. In this disclosure, the "second common driving voltage VSS" can also be referred to as the "base voltage", and the "second common driving voltage line VSSL" can also be referred to as the "low-potential power supply voltage line" or the "base voltage line".

[0122] Each light-emitting device (ED) can be formed in the overlapping region of the pixel electrode (PE), the light-emitting layer (EML) within the intermediate layer (EL), and the common electrode (CE). The light-emitting region can be formed by each ED. For example, the light-emitting region of each ED may include the overlapping region of the pixel electrode (PE), the light-emitting layer (EML) within the intermediate layer (EL), and the common electrode (CE).

[0123] The light-emitting device (ED) can be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), or a quantum dot light-emitting device. For example, when the ED is an organic light-emitting diode, the intermediate layer (EL) of the ED can include organic materials.

[0124] The driving transistor DT can be a transistor used to supply drive current to the light-emitting device ED. The driving transistor DT can be connected between the first common drive voltage line VDDL and the light-emitting device ED.

[0125] The driving transistor DT may include a first node N1, a second node N2, and a third node N3. The first node N1 may be electrically connected to the light-emitting device ED. The second node N2 may be a node to which a data signal VDATA is applied. The third node N3 may be a node to which a first common driving voltage VDD is applied from a first common driving voltage line VDDL.

[0126] In the driving transistor DT, the second node N2 can be used as the gate node, the first node N1 can be used as the source node or the drain node, and the third node N3 can be used as the drain node or the source node. In the following description, for ease of illustration, examples are given of the second node N2 being used as the gate node (or gate electrode), the first node N1 being used as the source node (or source electrode), and the third node N3 being used as the drain node (or drain electrode), but the exemplary embodiments of this disclosure are not limited thereto.

[0127] Figure 2 The scanning transistor ST included in the sub-pixel circuit SPC shown can be a switching transistor, which is used to send the data signal VDATA, which is the image signal, to the second node N2, which is the gate node of the driving transistor DT.

[0128] The scanning transistor ST can be turned on or off by the scan signal SC, thereby controlling the electrical connection between the second node N2 of the driving transistor DT and the data line DL. The scan signal SC is a gating signal applied via the scan line SCL, which is a gating line of type GL. The drain or source electrode of the scanning transistor ST can be electrically connected to the data line DL. The source or drain electrode of the scanning transistor ST can be electrically connected to the second node N2 of the driving transistor DT. The gate electrode of the scanning transistor ST can be electrically connected to the scan line SCL.

[0129] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst can include a first capacitor electrode electrically connected to the first node N1 of the driving transistor DT or corresponding to the first node N1, and a second capacitor electrode electrically connected to the second node N2 of the driving transistor DT or corresponding to the second node N2.

[0130] The storage capacitor Cst can be an external capacitor designed outside the driving transistor DT, rather than an internal parasitic capacitor (e.g., Cgs or Cgd) that may exist between the first node N1 and the second node N2 of the driving transistor DT.

[0131] Each of the driving transistor DT and the scanning transistor ST can be an n-type transistor or a p-type transistor.

[0132] The display panel 110 may have a top-emitting structure or a bottom-emitting structure.

[0133] When the display panel 110 has a top-emitting structure, at least a portion of the sub-pixel circuit SPC can overlap with at least a portion of the light-emitting device ED in the vertical direction. Therefore, the area of ​​the light-emitting region can be increased, and the aperture ratio can be improved.

[0134] When the display panel 110 has a bottom light-emitting structure, the sub-pixel circuit SPC can be designed not to overlap with the light-emitting device ED in the vertical direction.

[0135] like Figure 2 As shown, the subpixel circuit SPC can have a 2T1C structure, which includes two transistors (DT and ST) and one capacitor (Cst). In some cases, the subpixel circuit SPC may also include one or more additional transistors or one or more additional capacitors.

[0136] For example, a subpixel circuit SPC can have an 8T1C structure comprising eight transistors and one capacitor. In another example, a subpixel circuit SPC can have a 6T2C structure comprising six transistors and two capacitors. In yet another example, a subpixel circuit SPC can have a 7T1C structure comprising seven transistors and one capacitor. However, the exemplary embodiments of this disclosure are not limited thereto.

[0137] The type and number of gating lines supplying gating signals to the sub-pixel SP can vary depending on the structure of the sub-pixel circuit SPC. Furthermore, the type and number of common driving voltages supplied to the sub-pixel SP can also vary depending on the structure of the sub-pixel circuit SPC.

[0138] Reference Figure 2 The circuit elements included in each sub-pixel SP (e.g., light-emitting devices ED implemented as organic light-emitting diodes (OLEDs) containing organic materials) are susceptible to the effects of external moisture and oxygen. Therefore, an encapsulation layer 200 can be provided in the display panel 110 to prevent such external moisture or oxygen from penetrating into circuit elements such as the light-emitting devices EDs.

[0139] The encapsulation layer 200 can be configured in various ways to prevent the light-emitting device (ED) from being exposed to moisture or oxygen. For example, the encapsulation layer 200 may comprise two or more layers of alternating organic and inorganic layers. However, exemplary embodiments of this disclosure are not limited thereto.

[0140] For example, the encapsulation layer 200 has a structure of alternating inorganic and organic encapsulation layers, which allows the encapsulation layer 200 to protect the light-emitting element while inhibiting the penetration of moisture or oxygen into the light-emitting element. For example, the encapsulation layer 200 can have a multi-insulating film structure with alternating stacked organic and inorganic films. The inorganic film can block the penetration of moisture or oxygen. The organic film can planarize the surface of the inorganic film. When organic and inorganic films are stacked in multiple layers, the movement path of moisture or oxygen can be longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting layer. The encapsulation layer 200 can be formed by sequentially stacking a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer 200 may further include one or more organic encapsulation layers and / or at least one inorganic encapsulation layer.

[0141] Reference Figure 2 The display device 100 according to an exemplary embodiment of the present disclosure may include a touch sensor layer 210 for sensing user touch, which includes a plurality of sensor electrodes, a touch driving circuit 220 for sensing the plurality of sensor electrodes, and a touch controller 230 for determining whether a touch has occurred or determining touch coordinates based on the sensing results (touch sensing data) from the touch driving circuit 220.

[0142] The touch sensor layer 210 can be embedded in the display panel 110. For example, the touch sensor layer 210 can be disposed on the encapsulation layer 200 in the display panel 110.

[0143] The display panel 110 may also include a plurality of touch pads TP electrically connected to the touch driving circuit 220, and a plurality of touch lines TL for electrically connecting a plurality of sensor electrodes in the touch sensor layer 210 to the plurality of touch pads TP connected to the touch driving circuit 220.

[0144] Figure 3 This is a cross-sectional view of a display panel 110 according to an exemplary embodiment of the present disclosure. In the following description, references will be omitted or briefly described. Figure 1 and Figure 2 Details that are the same or similar in content.

[0145] Reference Figure 3 The display panel 110 according to an exemplary embodiment of the present disclosure may include a transistor forming section, a light-emitting device forming section, and a packaging section in terms of its vertical structure.

[0146] The substrate 111 can be a single-layer or multi-layer substrate, and can be made of glass or plastic. When the substrate 111 is a multi-layer structure, it may include a first substrate 301, a substrate intermediate layer 302, and a second substrate 303. The substrate intermediate layer 302 may be located between the first substrate 301 and the second substrate 303. For example, each of the first substrate 301 and the second substrate 303 may be a polyimide (PI) layer. The substrate intermediate layer 302 may be an inorganic insulating layer. When charge accumulates in the first substrate 301, which is a polyimide layer, the substrate intermediate layer 302 can prevent the charge from affecting the transistors formed on the second substrate 303, which is also a polyimide layer.

[0147] The substrate intermediate layer 302 can also prevent moisture from penetrating upwards through the first substrate 301. For example, the substrate intermediate layer 302 can be formed of a single-layer or multi-layer structure of silicon nitride (SiNx) or silicon oxide (SiOx), or a double-layer structure of silicon oxide (SiOx) and silicon nitride (SiNx). For example, the substrate intermediate layer 302 can be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, while the multi-layer inorganic film can be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto. However, depending on the structure or characteristics of the display device, the substrate intermediate layer 302 may not be included. However, the exemplary embodiments of this disclosure are not limited thereto.

[0148] The transistor forming section may include a substrate 111, various insulating layers 311, 312, 313, 321, 322 and 323 located on the substrate 111, various transistors TFT1 and TFT2, storage capacitor Cst and various electrodes or signal lines.

[0149] The transistors TFT1 and TFT2 included in the transistor forming section may include a first transistor TFT1 and a second transistor TFT2.

[0150] The first transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c. The first active layer ACT1 may be a first semiconductor layer, but exemplary embodiments of this disclosure are not limited thereto. For example, the first active layer ACT1 may be formed of oxide semiconductor, amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon (LTPS), but is not limited thereto. The first transistor TFT1 may be implemented as a p-channel transistor or an n-channel transistor.

[0151] The first electrode E1a can be a gate electrode, the second electrode E1b can be a source electrode or a drain electrode, and the third electrode E1c can be a drain electrode or a source electrode. In the following description, for ease of explanation, the first electrode E1a is referred to as the first gate electrode, the second electrode E1b as the first source electrode, and the third electrode E1c as the first drain electrode. However, the exemplary embodiments of this disclosure are not limited thereto.

[0152] The second transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c. The second active layer ACT2 may be a second semiconductor layer, but is not limited thereto. For example, the second active layer ACT2 may be formed of oxide semiconductor, amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon (LTPS), but exemplary embodiments of this disclosure are not limited thereto. The second transistor TFT2 may be implemented as a p-channel transistor or an n-channel transistor.

[0153] For example, one of the first transistor TFT1 and the second transistor TFT2 may include an oxide semiconductor as an active layer. In another example, one of the first transistor TFT1 and the second transistor TFT2 may include a low-temperature polysilicon (LTPS) as an active layer. In another example, both the first transistor TFT1 and the second transistor TFT2 may include an oxide semiconductor as an active layer. In another example, both the first transistor TFT1 and the second transistor TFT2 may include a LPS as an active layer. In yet another example, the driving transistor DT in the first transistor TFT1 and the second transistor TFT2 may include an oxide semiconductor as an active layer, and the scanning transistor ST may include a LPS as an active layer. In yet another example, the driving transistor DT may include a LPS as an active layer, and the scanning transistor ST may include an oxide semiconductor as an active layer. In yet another example, the transistors included in the in-panel gate (GIP) type gate driving circuit 130 may include an oxide semiconductor or a LPS as an active layer. In yet another example, all transistors formed on the substrate 111 and the transistors included in the GIP type gate driving circuit 130 may include an oxide semiconductor as an active layer.

[0154] The fourth electrode E2a can be a gate electrode, the fifth electrode E2b can be a source electrode or a drain electrode, and the sixth electrode E2c can be a drain electrode or a source electrode. In the following description, for ease of explanation, the fourth electrode E2a is referred to as the second gate electrode, the fifth electrode E2b as the second source electrode, and the sixth electrode E2c as the second drain electrode. However, the exemplary embodiments of this disclosure are not limited thereto.

[0155] The second active layer ACT2 of the second transistor TFT2 can be positioned higher than the first active layer ACT1 of the first transistor TFT1 from the substrate 111.

[0156] The first buffer layer 311 can be disposed below the first active layer ACT1 of the first transistor TFT1, and the second buffer layer 321 can be disposed below the second active layer ACT2 of the second transistor TFT2. For example, the first active layer ACT1 of the first transistor TFT1 can be located on the first buffer layer 311, and the second active layer ACT2 of the second transistor TFT2 can be located on the second buffer layer 321. The position of the second buffer layer 321 can be positioned higher than the first buffer layer 311.

[0157] The storage capacitor Cst can be disposed in various metal layers within the display panel 110. For example, the storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0158] The light-emitting device forming section may include a plurality of light-emitting devices ED disposed on at least one planarization layer 331 or 333. Each of the plurality of light-emitting devices ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0159] The encapsulation portion may include an encapsulation layer 200 located on multiple light-emitting devices (EDs). The encapsulation layer 200 may be a single layer or multiple layers. In addition to the encapsulation layer 200, the encapsulation portion may also include a dam (DAM).

[0160] In the following text, reference will be made to Figure 3 The vertical structure of the display panel 110 according to an exemplary embodiment of the present disclosure will be described in more detail.

[0161] Reference Figure 3 The first buffer layer 311 can be disposed on the substrate 111. The first buffer layer 311 can be a single layer or multiple layers. When the first buffer layer 311 is a multi-layer structure, it can include multiple buffer layers 311a and active buffer layers 311b.

[0162] The multiple buffer layer 311a can be an inorganic insulating layer. The multiple buffer layer 311a can prevent or delay the diffusion of moisture or oxygen that has already penetrated the substrate 111. For example, the multiple buffer layer 311a can be formed from a single layer or multiple layers of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy), but is not limited thereto. For example, the multiple buffer layer 311a can be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) film, silicon nitride (SiNx) film, and silicon oxynitride (SiOxNx) film. For example, the multi-buffer layer 311a can be formed by a single or multiple inorganic film. For example, the single inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy) film, while the multi-layer inorganic film can be formed by alternately stacking at least one of one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more silicon oxynitride (SiOxNy) films and one or more amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0163] The active buffer layer 311b can be an inorganic insulating layer. The active buffer layer 311b can protect the first active layer ACT1 and can be used to prevent or delay various types of defects from entering from the substrate 111. For example, the active buffer layer 311b can be formed of a single layer or multiple layers of amorphous silicon (a-Si), silicon nitride (SiNx), or silicon oxide (SiOx), but is not limited thereto.

[0164] The first active layer ACT1 of the first transistor TFT1 can be disposed on the first buffer layer 311. The first active layer ACT1 may include a channel region with a channel formed therein, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region.

[0165] The first gate insulating layer 312 may be disposed on the first active layer ACT1 of the first transistor TFT1. The first gate insulating layer 312 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. For example, the first gate insulating layer 312 may be formed by a single layer or multiple layers of inorganic film. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, while the multiple layers of inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto. The first gate electrode E1a of the first transistor TFT1 may be disposed on the first gate insulating layer 312.

[0166] The first interlayer insulating layer 313 may be disposed on the first gate electrode E1a of the first transistor TFT1. The first interlayer insulating layer 313 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. For example, the first interlayer insulating layer 313 may be formed by a single layer or multiple layers of inorganic film. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, while the multiple layers of inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0167] The second buffer layer 321 may be disposed on the first interlayer insulating layer 313. The second buffer layer 321 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. For example, the second buffer layer 321 may be formed by a single layer or multiple layers of inorganic film. For example, the single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, while the multiple layers of inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0168] The second active layer ACT2 of the second transistor TFT2 can be disposed on the second buffer layer 321. The second active layer ACT2 may include a channel region with a channel formed, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region.

[0169] The second gate insulating layer 322 can be disposed on the second active layer ACT2 of the second transistor TFT2. The second gate insulating layer 322 can be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. For example, the second gate insulating layer 322 can be formed by a single layer or multiple layers of inorganic films. For example, the single-layer inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, while the multiple-layer inorganic film can be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto. The second gate electrode E2a of the second transistor TFT2 can be disposed on the second gate insulating layer 322.

[0170] The second interlayer insulating layer 323 can be disposed on the second gate electrode E2a of the second transistor TFT2. The second interlayer insulating layer 323 can be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. For example, the second interlayer insulating layer 323 can be formed by a single layer or multiple layers of inorganic film. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, while the multiple layers of inorganic film can be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0171] The first source electrode E1b and the first drain electrode E1c of the first transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 can be disposed on the second interlayer insulating layer 323.

[0172] The first source electrode E1b and the first drain electrode E1c of the first transistor TFT1 can be connected to the source connection region and the drain connection region of the first active layer ACT1 through contact holes in the second interlayer insulating layer 323, the second gate insulating layer 322, the second buffer layer 321, the first interlayer insulating layer 313 and the first gate insulating layer 312.

[0173] The second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 can be connected to the source connection region and the drain connection region of the second active layer ACT2 through contact holes in the second interlayer insulating layer 323 and the second gate insulating layer 322.

[0174] The first source electrode E1b and the first drain electrode E1c of the first transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2, may include a first metal and may be disposed in a first metal layer. Here, the first metal and the first metal layer may be referred to as the first source-drain metal and the first source-drain metal layer, respectively.

[0175] For example, refer to Figure 3 The storage capacitor Cst can be formed by a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In some cases, the storage capacitor Cst can be formed by three or more capacitor electrodes, or it can be configured as two or more capacitors connected in parallel.

[0176] Each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 can be disposed in various metal layers within the display panel 110.

[0177] For example, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate electrode E1a of the first transistor TFT1 formed on the first gate insulating layer 312, and may be disposed in the first gate metal layer.

[0178] For example, the second capacitor electrode CAPE2 can be disposed on the first interlayer insulating layer 313.

[0179] The second source electrode E2b of the second transistor TFT2 can be electrically connected to the second capacitor electrode CAPE2 through contact holes in the second interlayer insulating layer 323, the second gate insulating layer 322, and the second buffer layer 321.

[0180] For example, the first transistor TFT1 can correspond to Figure 2 The scanning transistor ST, and the second transistor TFT2 can correspond to Figure 2 The driving transistor DT.

[0181] The transistor forming section may also include various metal patterns MP1 and MP2. For example, the first metal pattern MP1 may be disposed between the multiple buffer layers 311a and the active buffer layer 311b included in the first buffer layer 311. The second metal pattern MP2 may include the same first gate metal as the first gate electrode E1a of the first transistor TFT1, and may be disposed in the first gate metal layer. However, the exemplary embodiments of this disclosure are not limited thereto.

[0182] Each of the first metal pattern MP1 and the second metal pattern MP2 can be set in the display area DA or the non-display area NDA.

[0183] Reference Figure 3The transistor forming portion may further include a first shielding metal BSM1, which is disposed on the substrate 111, overlaps with the first active layer ACT1 of the first transistor TFT1, and is located below the first active layer ACT1 of the first transistor TFT1. For example, the first shielding metal BSM1 may be disposed between the substrate 111 and the first buffer layer 311, or between the multiple buffer layer 311a and the active buffer layer 311b.

[0184] The transistor forming section may further include a second shielding metal BSM2, which is disposed on the substrate 111, overlaps with the second active layer ACT2 of the second transistor TFT2, and is located below the second active layer ACT2 of the second transistor TFT2.

[0185] For example, the second shielding metal BSM2 can be disposed in a metal layer located between the first interlayer insulating layer 313 and the second buffer layer 321. The second shielding metal BSM2 can be disposed in the same metal layer as the second capacitor electrode CAPE2.

[0186] In another example, the second shielding metal BSM2 may be disposed in the same first gate metal layer as the first gate electrode E1a of the first transistor TFT1. (See reference...) Figure 3 The transistor forming section may further include a common drive voltage pattern CVP to which a common drive voltage is applied. For example, the common drive voltage applied to the common drive voltage pattern CVP may be referred to as a power supply signal, and may be a first common drive voltage VDD or a second common drive voltage VSS. The first common drive voltage VDD may also be referred to as a high-potential power supply voltage (high-potential power supply signal), and the second common drive voltage VSS may also be referred to as a low-potential power supply voltage (low-potential power supply signal) or a base voltage.

[0187] The common drive voltage pattern CVP can be set in the display area DA or the non-display area NDA.

[0188] At least one planarization layer may be disposed on the first transistor TFT1 and the second transistor TFT2. Figure 3 The example shown illustrates a configuration where two planarization layers 331 and 333 are disposed on the first transistor TFT1 and the second transistor TFT2. In some cases, three or more planarization layers may be disposed thereon; however, the exemplary embodiments of this disclosure are not limited thereto. The planarization layer may be an organic insulating layer capable of performing planarization functions.

[0189] Reference Figure 3The first planarization layer 331 can be disposed on the first source electrode E1b and the first drain electrode E1c of the first transistor TFT1 and on the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2. The first planarization layer 331 can be configured to cover the first transistor TFT1 and the second transistor TFT2. The first planarization layer 331 can be an organic insulating layer that planarizes and protects the upper part of the first transistor TFT1 and the second transistor TFT2. For example, the first planarization layer 331 can be formed of an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0190] Reference Figure 3 Various conductive patterns can be formed on the first planarization layer 331. The conductive patterns may include a first conductive pattern, a second conductive pattern, and a third conductive pattern. The conductive patterns can be formed using metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials.

[0191] Reference Figure 3 The relay electrode RE can be disposed on the first planarization layer 331. The relay electrode RE can correspond to the third conductive pattern. The relay electrode RE can be electrically connected to the second source electrode E2b of the second transistor TFT2 through the contact holes of the first planarization layer 331. Here, the second source electrode E2b of the second transistor TFT2 can be electrically connected to the second capacitor electrode CAPE2 of the storage capacitor Cst.

[0192] The relay electrode RE can be disposed in the second metal layer on the first planarization layer 331, and can include a second metal. The second metal and the second metal layer can be referred to as the second source-drain metal and the second source-drain metal layer, respectively.

[0193] A barrier layer 332 may be disposed on the first planarization layer 331. The barrier layer 332 may be configured to expose the top surface of the relay electrode RE. The barrier layer 332 may compensate for step differences formed by various components such as signal lines, voltage lines, and driving elements. The barrier layer 332 may comprise an inorganic insulating material. For example, the barrier layer 332 may be formed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or aluminum oxide (AlOx), but is not limited thereto.

[0194] The second planarization layer 333 can be disposed on the barrier layer 332 and the relay electrode RE. For example, the second planarization layer 333 can be formed of an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0195] Reference Figure 3The light-emitting device forming portion can be disposed on the second planarization layer 333. The light-emitting device ED can be formed on the second planarization layer 333 and can include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The light-emitting region of the light-emitting device ED can be formed in the region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap and are in contact with each other.

[0196] The pixel electrode PE can be disposed on the second planarization layer 333. The pixel electrode PE can be electrically connected to the relay electrode RE through the contact holes of the second planarization layer 333.

[0197] A dam 334 can be disposed on the pixel electrode PE. An opening in the dam 334 can expose a portion of the pixel electrode PE to form a light-emitting area. For example, the opening in the dam 334 can overlap with a portion of the pixel electrode PE. The dam 334 can be formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as benzocyclobutene resin, acryloyl resin, or imide resin, but is not limited thereto. Spacers can also be disposed on the dam 334.

[0198] Furthermore, the barrier may include a first barrier and a second barrier. The first barrier may be made of an opaque material (e.g., a black material) to suppress optical interference between adjacent sub-pixels. The second barrier may be made of a transparent material. The first and second barriers may include, but are not limited to, light-shielding materials made of at least one of colored pigments, organic black materials, and carbon.

[0199] Furthermore, the first and second dike sections can be formed as separate structures, or they can be formed as a single dike section. In other words, the first and second dike sections can be integrated into a single dike section.

[0200] The first and second dikes can be set at the boundaries between multiple sub-pixels SP and suppress color mixing of beams from multiple sub-pixels SP.

[0201] The intermediate layer EL of the light-emitting device ED can be disposed on a portion of the pixel electrode PE and on the embankment 334. The common electrode CE can be disposed on the intermediate layer EL.

[0202] Reference Figure 3 The encapsulation portion can be disposed on the light-emitting device forming portion and can be located on the common electrode CE. The encapsulation portion may include an encapsulation layer 200 formed on the common electrode CE.

[0203] The encapsulation layer 200 can prevent moisture or oxygen from penetrating into the light-emitting device ED. For example, the encapsulation layer 200 can prevent moisture or oxygen from penetrating into the organic material contained in the intermediate layer EL of the light-emitting device ED. The encapsulation layer 200 can be a single-layer or multi-layer structure; however, the exemplary embodiments of this disclosure are not limited thereto.

[0204] For example, refer to Figure 3 The encapsulation layer 200 may include a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343. The first encapsulation layer 341 and the third encapsulation layer 343 may include inorganic layers, and the second encapsulation layer 342 may include an organic layer.

[0205] The first encapsulation layer 341 can be disposed on the common electrode CE and positioned closest to the light-emitting device ED. The first encapsulation layer 341 can be formed of an inorganic insulating material that allows for low-temperature deposition. For example, the first encapsulation layer 341 can be formed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or aluminum oxide (AlOx). Because the first encapsulation layer 341 is deposited under low-temperature conditions, damage to the intermediate layer EL containing organic materials during the deposition process can be prevented.

[0206] The second encapsulation layer 342 can be formed to have a smaller area than the first encapsulation layer 341. In this case, the second encapsulation layer 342 can be formed to expose both ends of the first encapsulation layer 341. The second encapsulation layer 342 can serve as a buffer layer to alleviate interlayer stress caused by bending of the display device and can enhance planarization performance. For example, the second encapsulation layer 342 can be formed from an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbide (SiOC). For example, the second encapsulation layer 342 can be formed by an inkjet process, but is not limited thereto.

[0207] The third encapsulation layer 343 can be formed on the upper side of the substrate 111 on which the second encapsulation layer 342 is formed, and can cover the upper and side surfaces of each of the second encapsulation layer 342 and the first encapsulation layer 341. In this case, the third encapsulation layer 343 can minimize or prevent moisture or oxygen from penetrating into the first encapsulation layer 341 and the second encapsulation layer 342. For example, the third encapsulation layer 343 can be formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or aluminum oxide (AlOx), but is not limited thereto.

[0208] The display panel 110 according to an exemplary embodiment of the present disclosure may include an embedded touch sensor. In this case, the display panel 110 may include a touch sensor layer 210 formed on the encapsulation layer 200.

[0209] Reference Figure 3 The touch sensor layer 210 may include a plurality of touch electrodes TE, and may also include a sensor metal TSM and a bridging metal BRG to form the plurality of touch electrodes TE. In an exemplary embodiment of this disclosure, the sensor metal TSM may also be referred to as a sensor metal layer TSM, and the bridging metal BRG may also be referred to as a bridging metal layer BRG.

[0210] The touch sensor layer 210 may also include insulating layers, such as a sensor buffer layer 351 disposed on the encapsulation layer 200, an inter-sensor insulating layer 352 disposed on the sensor buffer layer 351, and a sensor passivation layer 353 disposed on the inter-sensor insulating layer 352. Here, the sensor buffer layer 351 may be omitted.

[0211] The bridging metal BRG can be disposed between the sensor buffer layer 351 and the sensor interlayer insulation layer 352, and the sensor metal TSM can be disposed between the sensor interlayer insulation layer 352 and the sensor passivation layer 353.

[0212] A sensor buffer layer 351 may be disposed on the encapsulation layer 200. The sensor buffer layer 351 can prevent damage to the encapsulation layer 200 and can be used to prevent interference signals from transistors TFT1 and TFT2 from affecting the touch electrode TE. The sensor buffer layer 351 can facilitate the formation of the touch electrode TE on the encapsulation layer 200 and can improve the adhesion between the touch electrode TE and the encapsulation layer 200. The sensor buffer layer 351 may be an inorganic insulating layer. For example, the sensor buffer layer 351 may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy), and may be a single-layer or multi-layer structure, but is not limited thereto. For example, the sensor buffer layer 351 may be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) film, silicon nitride (SiNx) film, and silicon oxynitride (SiOxNx) film. For example, the sensor buffer layer 351 can be formed by a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy) film, while the multiple layers of inorganic films can be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiOxNy) film and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0213] A sensor buffer layer 351 may be disposed on the encapsulation layer 200. The sensor buffer layer 351 may facilitate the formation of the touch electrode TE on the encapsulation layer 200 and may enhance the adhesion of the touch electrode TE to the encapsulation layer 200. The sensor buffer layer 351 may also be an organic insulating layer. For example, the sensor buffer layer 351 may be formed of an organic insulating material such as an acrylic-based, epoxy-based, or siloxane-based resin, but is not limited thereto.

[0214] Each of the multiple touch electrodes TE can be formed from a sensor metal TSM. Each of the multiple touch electrodes TE can be a mesh electrode with multiple openings.

[0215] Multiple touch electrodes TE may include a first touch electrode TE1 and a second touch electrode TE2. The sensor metal TSM included in the first touch electrode TE1 may be electrically connected via a bridging metal BRG. That is, the sensor metal TSMs spaced apart from each other may be electrically connected via the bridging metal BRG to form a single first touch electrode TE1.

[0216] A bridging metal BRG can be disposed on the sensor buffer layer 351, and an interlayer insulating layer 352 can be disposed on the bridging metal BRG. The interlayer insulating layer 352 can be an inorganic insulating layer. For example, the interlayer insulating layer 352 can be formed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), titanium oxide (TiOx), or aluminum oxide (AlOx), but is not limited thereto. For example, the interlayer insulating layer 352 can be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) film, silicon nitride (SiNx) film, and silicon oxynitride (SiOxNx) film. For example, the interlayer insulating layer 352 of the sensor can be formed by a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy) film, while the multiple layers of inorganic film can be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiOxNy) film and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0217] The sensor metal TSM can be disposed on the sensor interlayer insulating layer 352. A portion of the sensor metal TSM can be connected to the corresponding bridging metal BRG through the contact holes of the sensor interlayer insulating layer 352.

[0218] Reference Figure 3 The sensor metal TSM and bridging metal BRG can be configured not to overlap with the light-emitting device ED. The sensor metal TSM and bridging metal BRG can overlap with the embankment 334.

[0219] Multiple sensor metal TSMs can be formed into a single touch electrode TE, and can be arranged in a mesh pattern and electrically connected. One part of the sensor metal TSM and another part of the sensor metal TSM can be electrically connected through a bridging metal BRG to form a single touch electrode TE.

[0220] The sensor passivation layer 353 can be configured to cover the sensor metal TSM and the bridging metal BRG. The sensor passivation layer 353 can be an organic insulating layer. For example, this organic insulating layer can be formed from the same material as the aforementioned planarization layers 331 and 333. The organic insulating layer can be formed from a different material than the second encapsulation layer 342. For example, the sensor passivation layer 353 can be formed from a photocurable organic material selected from acrylic, polyimide, or siloxane resins, but is not limited thereto.

[0221] Reference Figure 3 The touch line TL electrically connects the touch electrode TE and the touch pad TP. The touch line TL can be formed from at least one of the sensor metal TSM and the bridging metal BRG.

[0222] When the display panel 110 includes a built-in touch sensor, the touch line TL can extend along the inclined outer surface SLP_ENCAP of the package layer 200 and can extend across the dam (DAM) to the touch pad TP located in the non-display area NDA.

[0223] Figure 4 This is a schematic plan view illustrating a plurality of sub-pixels SP disposed in a display area DA of a display panel 110 according to an exemplary embodiment of the present disclosure. In the following description, descriptions or references are omitted or briefly simplified. Figures 1 to 3 The provided descriptions are the same or similar.

[0224] exist Figure 4 In Figure 3 Among the various components described, the light-emitting region EA, conductive patterns VL1, VL2, 410 and RE, barrier layer 332, and pixel electrode PE are shown. The light-emitting region EA may correspond to the opening portion of the aforementioned embankment 334.

[0225] Reference Figure 4 Multiple sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3, each comprising a light-emitting region EA for emitting light of a corresponding color. The first sub-pixel SP1 may include a first light-emitting region EA1 emitting light of a first color, the second sub-pixel SP2 may include a second light-emitting region EA2 emitting light of a second color, and the third sub-pixel SP3 may include a third light-emitting region EA3 emitting light of a third color.

[0226] The first luminous area EA1 can be a red luminous area, the second luminous area EA2 can be a green luminous area, and the third luminous area EA3 can be a blue luminous area, but is not limited to these. One first luminous area EA1, two second luminous areas EA2, and one third luminous area EA3 can form a single pixel arranged in a diamond shape.

[0227] Reference Figure 4 Conductive patterns VL1, VL2, 410, and RE can be configured. The conductive patterns may include first conductive patterns VL1 and VL2, a second conductive pattern 410, and a third conductive pattern RE. The first conductive patterns VL1 and VL2 can be data lines DL used to transmit data voltages. The second conductive pattern 410 can be a drive voltage line DVL used to transmit high-level drive voltages. The third conductive pattern RE can be a relay electrode. These conductive patterns can be formed from the aforementioned second source-drain metal.

[0228] Reference Figure 4 The first conductive patterns VL1 and VL2 and the second conductive pattern 410 can extend along the first direction and are disposed on the first planarization layer 331. The light-emitting regions EA1, EA2 and EA3 of the plurality of sub-pixels SP can be disposed to overlap with at least one of the first conductive patterns VL1 and VL2 and / or at least one of the second conductive patterns 410, but are not limited thereto.

[0229] Reference Figure 4 The first light-emitting region EA1 and the third light-emitting region EA3 can be configured to overlap with a portion of at least one of the first conductive patterns VL1 and VL2. In other words, the openings corresponding to the first light-emitting region EA1 and the third light-emitting region EA3 can be positioned to partially overlap with the conductive patterns VL1 and VL2. For example, the opening corresponding to the first light-emitting region EA1 can be positioned to partially overlap with the conductive pattern VL1, and the opening corresponding to the first light-emitting region EA1 can be positioned to partially overlap with the conductive pattern VL2, and the opening corresponding to the third light-emitting region EA3 can be positioned to partially overlap with the conductive pattern VL1, and the opening corresponding to the third light-emitting region EA3 can be positioned to partially overlap with the conductive pattern VL2, but this is not limited to these configurations. From the perspective of the first conductive patterns VL1 and VL2, multiple first conductive patterns can be configured to pass below at least one of the first light-emitting region and the third light-emitting region.

[0230] Reference Figure 4The second light-emitting region EA2 can be configured to overlap with a portion of at least one of the second conductive patterns 410. In other words, the opening corresponding to the second light-emitting region EA2 can be positioned to overlap with a portion of the second conductive pattern 410. From the perspective of the second conductive pattern 410, the second conductive pattern 410 can be configured to pass below at least one of the second light-emitting regions EA2. The second light-emitting region EA2 may not overlap with the first conductive patterns VL1 and VL2.

[0231] The second light-emitting region EA2 can be disposed in a direction inclined relative to the first direction. Specifically, the second light-emitting region EA2 can be disposed at a predetermined angle relative to the first direction in which the plurality of first conductive patterns VL1 and VL2 and the second conductive pattern 410 extend.

[0232] Reference Figure 4 Multiple first conductive patterns VL1 and VL2 can be arranged in pairs.

[0233] For example, refer to Figure 4 The first conductive patterns VL1 and VL2 can be arranged in pairs adjacent to each other. A pair of first conductive patterns VL1 and VL2 can be disposed in the region between two different second conductive patterns 410. For example, a pair of first conductive patterns VL1 and VL2 can be disposed in the region between two different second conductive patterns 410, and portions of the pair of first conductive patterns VL1 and VL2 can overlap with the openings corresponding to the first light-emitting region EA1 and the third light-emitting region EA3, but are not limited thereto.

[0234] The first conductive pattern VL1 can supply data voltage for image display to the first sub-pixel SP1. The first conductive pattern VL2 can supply data voltage for image display to the third sub-pixel SP3. The first conductive pattern VL1 can supply data voltage for image display to the second sub-pixel SP2.

[0235] Alternatively, the first conductive pattern VL1 can supply data voltage for image display to the second sub-pixel SP2, and the first conductive pattern VL2 can supply data voltage for image display to the first sub-pixel SP1 and the third sub-pixel SP3.

[0236] The second conductive pattern 410 can send a high-level driving voltage for driving the sub-pixel SP.

[0237] Reference Figure 4 The first light-emitting region EA1 and the third light-emitting region EA3 can be disposed on the first conductive patterns VL1 and VL2. The second light-emitting region EA2 can be disposed on the second conductive pattern 410. Depending on the design of the conductive pattern, the second light-emitting region EA2 can partially overlap with the second conductive pattern 410.

[0238] Reference Figure 4 The third conductive pattern RE can be configured to partially overlap with the pixel electrode PE of the light-emitting device. The third conductive pattern RE can be a relay electrode electrically connecting the pixel electrode PE of the light-emitting device and the source / drain electrode of the transistor. The contact hole CH connecting the pixel electrode PE of the light-emitting device to the relay electrode RE can be located in an area that does not overlap with the light-emitting region EA.

[0239] At the same time, such as Figure 3 and Figure 4 As shown, multiple light-emitting regions EA can be arranged in a narrow area, and various components, including multiple wirings for supplying signals and voltages and multiple driving elements, can be formed below the light-emitting regions EA to overlap with them. When these various components are formed, the surface may become uneven due to level differences, and this unevenness may be transferred to the pixel electrodes of the light-emitting device when the pixel electrodes are formed. When step differences exist in the pixel electrodes, the emitted light may become non-uniform, and the reflectivity may deteriorate.

[0240] To stably position the light-emitting devices on a flat surface and improve the flatness of the pixel electrodes, multiple planarization layers made of organic materials can be formed. During the process of forming such organic planarization layers, gases may be generated from the organic film, and if these gases are not adequately released, it may lead to a decrease in the reliability of the display panel.

[0241] Therefore, a solution is needed to address the step difference caused by the conductive pattern located below the pixel electrode and the degassing problem from multiple planarization layers.

[0242] Reference Figure 4 The barrier layer 332 can be configured to cover the entire lower region of the pixel electrode PE. The barrier layer 332 can be arranged such that a portion of the top surface of the conductive patterns VL1, VL2, 410 and RE is exposed. For example, the barrier layer 332 can be arranged such that a portion of the top surface of each of the conductive patterns VL1, VL2, 410 and RE is exposed, thereby reducing or preventing step differences caused by the conductive patterns.

[0243] Reference Figure 4 A via TH can be provided between the conductive patterns VL1, VL2, 410, and RE. The via TH can be configured not to overlap with the conductive patterns. The via TH can be included in a barrier layer 332 disposed on the planarization layer. By providing the via TH in the barrier layer 332, gas generated from the planarization layer below the barrier layer 332 can be continuously discharged.

[0244] Figure 5 , Figure 6 and Figure 7It is along Figure 4 An exemplary cross-sectional view taken from line AB in the diagram. In the following description, details already referenced are omitted or briefly described. Figures 1 to 4 The content described is the same or similar.

[0245] Reference Figure 5 The display device may include a first planarization layer 331, conductive patterns VL1, VL2, 410 and RE, a barrier layer 332, a second planarization layer 333, a light-emitting device ED, a dam 334 and an encapsulation layer 200.

[0246] Conductive patterns VL1, VL2, 410, and RE can be disposed on the first planarization layer 331 and spaced apart from each other. The conductive patterns may include first conductive patterns VL1 and VL2, second conductive pattern 410, and third conductive pattern RE. First conductive patterns VL1 and VL2 can be data lines DL for transmitting data voltages. Second conductive pattern 410 can be a voltage line DVL for transmitting high-level drive voltages. Third conductive pattern RE can be a relay electrode.

[0247] A barrier layer 332 may be disposed on the first planarization layer 331. The barrier layer 332 may be disposed in the regions of the first planarization layer 331 where the conductive patterns VL1, VL2, 410, and RE are not formed. The barrier layer 332 may not be disposed on at least a portion of the top surface of the conductive patterns; for example, the barrier layer 332 may not be disposed on at least a portion of the top surface of each of the conductive patterns VL1, VL2, 410, and RE. By being disposed between the conductive patterns VL1, VL2, 410, and RE, the barrier layer 332 can mitigate the step difference caused by the conductive patterns.

[0248] The barrier layer 332 may include vias TH located between the conductive patterns. The vias TH may be used to discharge gases that may be generated from the first planarization layer 331 made of organic film (i.e., for degassing).

[0249] The second planarization layer 333 can be disposed on the conductive patterns VL1, VL2, 410 and RE, and the barrier layer 332. The second planarization layer 333 can further improve the surface flatness by covering the conductive patterns and the barrier layer.

[0250] Reference Figure 5The barrier layer 332 may not be provided on a portion of the top surface of the conductive patterns VL1, VL2, 410, and RE. For example, the barrier layer 332 may not be provided on a portion of the top surface of each of the conductive patterns VL1, VL2, 410, and RE. For example, the barrier layer 332 may be provided on the remaining area other than a portion of the top surface of the conductive patterns. Alternatively, the barrier layer 332 may not be provided on the entire top surface of the conductive patterns VL1, VL2, 410, and RE. For example, the barrier layer 332 may not be provided on the entire top surface of each of the conductive patterns VL1, VL2, 410, and RE. The area on the top surface of the conductive patterns VL1, VL2, 410, and RE not covered by the barrier layer 332 may be referred to as an open area. That is, the open area may correspond to a portion or all of the top surface of the conductive patterns VL1, VL2, 410, and RE.

[0251] Reference Figure 5 The barrier layer 332 can be configured to contact the side surfaces of the conductive patterns VL1, VL2, 410, and RE. For example, the barrier layer 332 can be configured to contact the side surfaces of each of the conductive patterns VL1, VL2, 410, and RE. The barrier layer 332 can be disposed at the same or lower height than the top surfaces of the conductive patterns VL1, VL2, 410, and RE. The barrier layer 332 can be configured to contact the side surfaces of the conductive patterns VL1, VL2, 410, and RE, and the second planarization layer 333 can be configured to contact the top surfaces of the conductive patterns VL1, VL2, 410, and RE. Since the barrier layer 332 is disposed at a height equal to or lower than that of the conductive patterns VL1, VL2, 410, and RE, step differences caused by the conductive patterns VL1, VL2, 410, and RE can be reduced or prevented.

[0252] Reference Figure 5 A via TH can be formed in the barrier layer 332. At the via TH, the first planarization layer 331 and the second planarization layer 333 can contact each other. The via TH can be located between the conductive patterns VL1, VL2, 410, and RE. The via TH can be disposed in a region that overlaps with or does not overlap with the opening of the dam 334. For example, the via TH can be disposed in both a region that overlaps with the opening of the dam 334 and a region that does not overlap with the opening of the dam 334. In another example, the via TH can be disposed in a region that overlaps with the opening of the dam 334, and may not be disposed in a region that does not overlap with the opening of the dam 334. In yet another example, the via TH can be disposed in a region that does not overlap with the opening of the dam 334, and may not be disposed in a region that overlaps with the opening of the dam 334.

[0253] The light-emitting device ED can be formed on the second planarization layer 333. The light-emitting device ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The light-emitting region EA1 of the light-emitting device ED can be formed in the region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE are stacked and in contact with each other.

[0254] The pixel electrode PE can be disposed on the second planarization layer 333.

[0255] A dam 334 may be disposed on the pixel electrode PE. An opening portion of the dam 334 may expose a portion of the pixel electrode PE to define a light-emitting area. For example, the opening may overlap with a portion of the pixel electrode PE. The opening of the dam 334 may correspond to the light-emitting area EA1.

[0256] The intermediate layer EL of the light-emitting device ED can be disposed on a portion of the dam 334 and the pixel electrode PE. The common electrode CE can be disposed on the intermediate layer EL.

[0257] The encapsulation layer 200 can be disposed on the common electrode CE. The encapsulation layer 200 can prevent moisture or oxygen from penetrating into the light-emitting device ED.

[0258] For example, the encapsulation layer 200 has a structure of alternating inorganic and organic encapsulation layers, which allows the encapsulation layer 200 to protect the light-emitting element while inhibiting the penetration of moisture or oxygen into the light-emitting element. For example, the encapsulation layer 200 can have a multi-insulating film structure with alternating stacked organic and inorganic films. The inorganic film can block the penetration of moisture or oxygen. The organic film can planarize the surface of the inorganic film. When organic and inorganic films are stacked in multiple layers, the movement path of moisture or oxygen can be longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting layer. The encapsulation layer 200 can be formed by sequentially stacking a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer 200 may further include one or more organic encapsulation layers and / or at least one inorganic encapsulation layer.

[0259] The first and second inorganic encapsulation layers can be made of inorganic insulating materials that can be deposited at low temperatures, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3), but are not limited thereto.

[0260] The first organic encapsulation layer can be made of organic insulating materials, such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon carbide (SiOC), but is not limited to these.

[0261] Alternatively, the encapsulation layer 200 includes a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer stacked sequentially. However, this disclosure is not limited thereto.

[0262] The first, second, and third inorganic encapsulation layers can be used to block the penetration of moisture or oxygen. The first, second, and third inorganic encapsulation layers can be made of inorganic materials, such as silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx). However, this disclosure is not limited thereto.

[0263] A first organic encapsulation layer is disposed between a first inorganic encapsulation layer and a second inorganic encapsulation layer, and a second organic encapsulation layer is disposed between the second and third inorganic encapsulation layers. The first and second organic encapsulation layers may each have a greater thickness than each of the first, second, and third inorganic encapsulation layers to adsorb or block particles that may be generated during the manufacturing process of the display device. The first and second organic encapsulation layers may fill cracks that may form in the first and second inorganic encapsulation layers. The first and second organic encapsulation layers can planarize the upper portions of the first and second inorganic encapsulation layers by respectively covering particles on the first and second inorganic encapsulation layers. For example, the first organic encapsulation layer can planarize the upper portion of the first inorganic encapsulation layer by covering particles on the first inorganic encapsulation layer. For example, the second organic encapsulation layer can planarize the upper portion of the second inorganic encapsulation layer by covering particles on the second inorganic encapsulation layer. The first and second organic encapsulation layers may be made of organic materials, and for example, epoxy polymers, acrylic polymers, etc., may be used. However, this disclosure is not limited thereto.

[0264] Furthermore, the encapsulation layer 200 is not limited to three or five layers. For example, it may include n layers of inorganic and organic encapsulation layers stacked alternately (where n is an integer greater than 3).

[0265] Figure 6 It is along Figure 4 Another exemplary cross-sectional view taken from line AB in the diagram. Figure 6 The cross section shown is Figure 5 The only difference in the cross-section is the structure of the conductive patterns VL1, VL2, 410 and RE, and the barrier layer 332; the other configurations are basically the same, so they will not be described in detail.

[0266] Reference Figure 6 The barrier layer 332 may be disposed in the regions of the first planarization layer 331 where the conductive patterns VL1, VL2, 410 and RE are not formed. The barrier layer 332 may not be disposed on at least a portion of the top surface of the conductive patterns; for example, the barrier layer 332 may not be disposed on at least a portion of the top surface of each of the conductive patterns VL1, VL2, 410 and RE.

[0267] like Figure 6 As shown, a barrier layer 332 can be provided such that it contacts the lower portions of the conductive patterns VL1, VL2, 410, and RE, but is spaced apart from the upper portions of the conductive patterns VL1, VL2, 410, and RE. A gap portion GP can be defined between the upper side surface of the barrier layer 332 and the upper side surface of the conductive patterns. The barrier layer 332 can be provided at a height lower than the top surface of the conductive patterns. The second planarization layer 333 can be provided to contact the top surface and side surfaces (including the gap portion GP) of the conductive patterns. Because the barrier layer 332 is provided at a height lower than the conductive patterns VL1, VL2, 410, and RE, the step difference caused by the conductive patterns can be improved.

[0268] Reference Figure 6 A via TH can be disposed in the barrier layer 332. The first planarization layer 331 and the second planarization layer 333 can contact each other at the via TH. The via TH can be located between the conductive patterns VL1, VL2, 410, and RE. The via TH can be disposed in a region that overlaps with and / or does not overlap with the opening of the dam 334. For example, the via TH can be disposed in both a region that overlaps with the opening of the dam 334 and a region that does not overlap with the opening of the dam 334. In another example, the via TH can be disposed in a region that overlaps with the opening of the dam 334, and may not be disposed in a region that does not overlap with the opening of the dam 334. In yet another example, the via TH can be disposed in a region that does not overlap with the opening of the dam 334, and may not be disposed in a region that overlaps with the opening of the dam 334.

[0269] Figure 7 It is along Figure 4 Another exemplary cross-sectional view taken from line AB in the diagram. Figure 7 The cross section shown is Figure 5 and Figure 6 The only differences in the mid-section are the structure of the conductive patterns VL1, VL2, 410, and RE, and the barrier layer 332. The other components are basically the same, so they will not be described in detail.

[0270] Reference Figure 7 The barrier layer 332 may be disposed in the region of the first planarization layer 331 where the conductive patterns VL1, VL2, 410 and RE are not formed. The barrier layer 332 may not be disposed on at least a portion of the top surface of the conductive patterns VL1, VL2, 410 and RE. For example, the barrier layer 332 may not be disposed on at least a portion of the top surface of each of the conductive patterns VL1, VL2, 410 and RE.

[0271] like Figure 7As shown, the barrier layer 332 can be spaced apart from the conductive patterns VL1, VL2, 410, and RE. A gap GP can be defined between the side surface of the barrier layer 332 and the side surfaces of the conductive patterns VL1, VL2, 410, and RE. The barrier layer 332 can be positioned at a height lower than the top surface of the conductive patterns VL1, VL2, 410, and RE. The second planarization layer 333 can be positioned in contact with the top and side surfaces (including the gap GP) of the conductive patterns VL1, VL2, 410, and RE; for example, the second planarization layer 333 can be positioned in contact with the top and side surfaces (including the gap GP) of each of the conductive patterns VL1, VL2, 410, and RE. Because the barrier layer 332 is positioned below the height of the conductive patterns VL1, VL2, 410, and RE, the step difference caused by the conductive patterns can be improved.

[0272] Reference Figure 7 A via TH can be disposed in the barrier layer 332. The first planarization layer 331 and the second planarization layer 333 can contact each other at the via TH. The via TH can be disposed between the conductive patterns VL1, VL2, 410, and RE. The via TH can be located in a region that overlaps with and / or does not overlap with the opening of the dam 334. For example, the via TH can be disposed in both a region that overlaps with the opening of the dam 334 and a region that does not overlap with the opening of the dam 334. In another example, the via TH can be disposed in a region that overlaps with the opening of the dam 334, and may not be disposed in a region that does not overlap with the opening of the dam 334. In yet another example, the via TH can be disposed in a region that does not overlap with the opening of the dam 334, and may not be disposed in a region that overlaps with the opening of the dam 334.

[0273] Figure 8 and Figure 9 It is along Figure 4 An exemplary cross-sectional view taken from line CD. In the following description, omitted or brief descriptions have been referenced. Figures 1 to 7 The content described.

[0274] Reference Figure 8 and Figure 9 The display device may include a first planarization layer 331, conductive patterns VL1, VL2, 410 and RE, a barrier layer 332, a second planarization layer 333, a light-emitting device ED, a dam 334 and an encapsulation layer 200.

[0275] like Figure 8 and Figure 9As shown, conductive patterns VL1, VL2, 410, and RE can be disposed on the first planarization layer 331 and spaced apart from each other. The conductive patterns may include first conductive patterns VL1 and VL2, second conductive pattern 410, and third conductive pattern RE. The first conductive patterns VL1 and VL2 and the second conductive pattern 410 may extend along a first direction and be spaced apart along a second direction. The first conductive patterns VL1 and VL2 may be data lines DL for transmitting data voltages, the second conductive pattern 410 may be voltage lines DVL for transmitting high-level drive voltages, and the third conductive pattern RE may be a relay electrode.

[0276] Reference Figure 8 and Figure 9 The barrier layer 332 can be disposed on the first planarization layer 331. The barrier layer 332 can be disposed in the regions of the first planarization layer 331 where the conductive patterns VL1, VL2, 410 and RE are not formed. That is, the barrier layer 332 can be located between the conductive patterns VL1, VL2, 410 and RE on the first planarization layer.

[0277] like Figure 8 and Figure 9 As shown, the barrier layer 332 may not be disposed on at least a portion of the top surface of the conductive patterns VL1, VL2, 410, and RE. For example, the barrier layer 332 may not be disposed on at least a portion of the top surface of each of the conductive patterns VL1, VL2, 410, and RE. By being positioned between the conductive patterns VL1, VL2, 410, and RE, the barrier layer 332 can improve the step difference caused by the conductive patterns VL1, VL2, 410, and RE.

[0278] Reference Figure 8 and Figure 9 The barrier layer 332 may include a via TH disposed between the conductive patterns VL1, VL2, 410 and RE. The via TH can be used to discharge gas generated from the first planarization layer 331, which is an organic membrane (i.e., degassing).

[0279] The second planarization layer 333 can be disposed on the conductive patterns VL1, VL2, 410 and RE and the barrier layer 332. The second planarization layer 333 can further improve the flatness by covering both the conductive patterns VL1, VL2, 410 and RE and the barrier layer 332.

[0280] The light-emitting device ED can be formed on the second planarization layer 333. The light-emitting device ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The light-emitting region EA1 of the light-emitting device ED can be formed in the region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE are stacked and in contact.

[0281] The pixel electrode PE can be disposed on the second planarization layer 333.

[0282] A dam 334 can be disposed on the pixel electrode PE. An opening portion of the dam 334 can expose a part of the pixel electrode PE to form a light-emitting region. For example, the opening of the dam 334 can overlap with a part of the pixel electrode. The opening of the dam can correspond to the light-emitting region EA1.

[0283] Reference Figure 8 The barrier layer 332 may not be provided on some portions of the top surfaces of the conductive patterns VL1, VL2, 410, and RE. For example, the barrier layer 332 may not be provided on a portion of the top surface of each of the conductive patterns VL1, VL2, 410, and RE. For example, the barrier layer 332 may not be provided on some areas of the top surfaces of the conductive patterns VL1, VL2, 410, and RE, but may be provided on the remaining areas of the top surfaces of the conductive patterns VL1, VL2, 410, and RE. The area on the top surface of the conductive patterns VL1, VL2, 410, and RE where the barrier layer 332 is not provided may be referred to as an open area IOA. That is, the open area IOA may correspond to a portion of the top surface of the conductive patterns VL1, VL2, 410, and RE. Furthermore, the open area IOA may correspond to the entire top surface of the conductive patterns VL1, VL2, 410, and RE.

[0284] Reference Figure 8 The open region IOA can be configured to overlap with at least a portion of the light-emitting region EA. The open region IOA can be arranged to overlap with at least a portion of the pixel electrode PE.

[0285] Reference Figure 8 The open region IOA can correspond to the area where the pixel electrode PE is provided. By providing an open region IOA on the conductive patterns VL1, VL2, 410 and RE in the area where the blocking layer 332 is not provided, the step difference in the area where the pixel electrode PE is provided can be improved, thereby improving the flatness of the pixel electrode PE.

[0286] In the open area IOA, the second planarization layer 333 can be disposed on the conductive patterns VL1, VL2, 410 and RE.

[0287] The intermediate layer EL of the light-emitting device ED can be disposed on a portion of the pixel electrode PE and on the embankment 334. The common electrode CE can be disposed on the intermediate layer EL.

[0288] The encapsulation layer 200 can be disposed on the common electrode CE. The encapsulation layer 200 can prevent moisture or oxygen from penetrating into the light-emitting device ED.

[0289] For example, the encapsulation layer 200 has a structure of alternating inorganic and organic encapsulation layers, which allows the encapsulation layer 200 to protect the light-emitting element while inhibiting the penetration of moisture or oxygen into the light-emitting element. For example, the encapsulation layer 200 can have a multi-insulating film structure with alternating stacked organic and inorganic films. The inorganic film can block the penetration of moisture or oxygen. The organic film can planarize the surface of the inorganic film. When organic and inorganic films are stacked in multiple layers, the movement path of moisture or oxygen can be longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light-emitting layer. The encapsulation layer 200 can be formed by sequentially stacking a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer 200 may further include one or more organic encapsulation layers and / or at least one inorganic encapsulation layer.

[0290] Figure 9 It is along Figure 4 Another exemplary cross-sectional view taken from line CD in the diagram. (Compared to...) Figure 8 Compared to the cross-sectional view shown, only the conductive patterns VL1, VL2, 410, and RE, as well as the barrier layer 332, are different; the other components are basically the same, so they will not be described in detail.

[0291] Reference Figure 9 The barrier layer 332 may not be provided on some portions of the top surface of the conductive patterns VL1, VL2, 410 and RE. For example, the barrier layer 332 may not be provided on a portion of the top surface of each of the conductive patterns VL1, VL2, 410 and RE. For example, the barrier layer 332 may be provided on the remaining portions of the conductive patterns VL1, VL2, 410 and RE, excluding those portions.

[0292] like Figure 9 As shown, the open region IOA can be configured to at least partially overlap with the light-emitting region EA. The open region 10a can also overlap with at least a portion of the pixel electrode PE.

[0293] exist Figure 9 In this context, the open region IOA can correspond to the opening of the defined light-emitting region EA of the embankment. By providing an open region IOA in which the blocking layer 332 is not located on the conductive pattern in the region corresponding to the light-emitting region EA, the step difference in the region where the light-emitting region is formed can be improved, thereby enhancing the flatness of the pixel electrode PE.

[0294] In the open area IOA, the second planarization layer 333 can be disposed on the conductive patterns VL1, VL2, 410 and RE.

[0295] A brief overview of exemplary embodiments of this disclosure is as follows.

[0296] A display device according to an exemplary embodiment of the present disclosure may include: a substrate; a first planarization layer disposed on the substrate; a conductive pattern disposed on the first planarization layer, adjacent conductive patterns being spaced apart from each other; a barrier layer disposed on the first planarization layer, wherein at least a portion of the top surface of the conductive pattern is not covered by the barrier layer; and a second planarization layer disposed on the conductive pattern and the barrier layer.

[0297] In a display device according to an exemplary embodiment of the present disclosure, the barrier layer may include vias formed between conductive patterns. A first planarization layer and a second planarization layer may contact each other at the vias.

[0298] The display device according to an exemplary embodiment of the present disclosure may further include a dam disposed on a second planarization layer, the dam having an opening, wherein the opening may be configured to at least partially overlap with a conductive pattern.

[0299] In a display device according to an exemplary embodiment of the present disclosure, the through hole may not be provided in the area overlapping with the opening.

[0300] In a display device according to an exemplary embodiment of the present disclosure, the opening may include a first opening and a second opening. The conductive pattern may include data lines and voltage lines. The first opening may overlap at least partially with the data lines, and the second opening may overlap at least partially with the voltage lines.

[0301] In a display device according to an exemplary embodiment of the present disclosure, a blocking layer may be configured to contact at least a portion of the side surface of a conductive pattern, and a second planarization layer may be configured to contact at least a portion of the top surface of the conductive pattern.

[0302] In a display device according to an exemplary embodiment of the present disclosure, a barrier layer may contact a lower side surface of at least a portion of the conductive pattern and be spaced apart from its upper side surface. A second planarization layer may contact a top surface and an upper side surface of at least a portion of the conductive pattern.

[0303] In a display device according to an exemplary embodiment of the present disclosure, a barrier layer may be spaced apart from at least a portion of a conductive pattern, and a second planarization layer may be configured to contact the top and side surfaces of at least a portion of the conductive pattern.

[0304] In a display device according to an exemplary embodiment of the present disclosure, the first planarization layer and the second planarization layer may include organic insulating materials, and the barrier layer may include inorganic insulating materials.

[0305] In a display device according to an exemplary embodiment of the present disclosure, the conductive pattern may further include a relay electrode. The relay electrode may be configured to overlap with a contact hole in the first planarization layer.

[0306] In a display device according to an exemplary embodiment of the present disclosure, the display device may further include a transistor disposed on a substrate. The transistor may include a source electrode, a drain electrode, an active layer, and a gate electrode overlapping the active layer. A relay electrode may be electrically connected to the source electrode through a contact hole in a first planarization layer.

[0307] In a display device according to an exemplary embodiment of the present disclosure, the display device may further include a light-emitting device disposed on a second planarization layer. The light-emitting device may include: a pixel electrode disposed on the second planarization layer; an intermediate layer disposed on the pixel electrode; and a common electrode disposed on the intermediate layer. The pixel electrode may be electrically connected to a relay electrode through contact holes in the second planarization layer.

[0308] In a display device according to an exemplary embodiment of the present disclosure, a barrier layer may be disposed on a first planarization layer such that the barrier layer is not disposed on the entire top surface of the conductive pattern.

[0309] In a display device according to an exemplary embodiment of the present disclosure, the conductive pattern includes a first conductive pattern, a second conductive pattern, and a third conductive pattern, wherein the first conductive pattern is a data line for transmitting a data voltage, the second conductive pattern is a drive voltage line for transmitting a high-level drive voltage, and the third conductive pattern is a relay electrode.

[0310] In a display device according to an exemplary embodiment of the present disclosure, a plurality of sub-pixels are disposed on a substrate, the plurality of sub-pixels including a first sub-pixel, a second sub-pixel and a third sub-pixel, wherein the first sub-pixel includes a first light-emitting region that emits light of a first color, the second sub-pixel includes a second light-emitting region that emits light of a second color, and the third sub-pixel includes a third light-emitting region that emits light of a third color, wherein the first light-emitting region and the third light-emitting region overlap with portions of the first conductive pattern, and wherein the second light-emitting region overlaps with portions of the second conductive pattern.

[0311] In a display device according to an exemplary embodiment of the present disclosure, the first conductive pattern includes a pair of first conductive patterns spaced apart from each other and respectively serving as the data lines.

[0312] A display device according to an exemplary embodiment of the present disclosure may include: a substrate; a first planarization layer disposed on the substrate; a conductive pattern disposed on the first planarization layer and extending along a first direction; a barrier layer disposed on the first planarization layer; a second planarization layer disposed on the conductive pattern and the barrier layer; a pixel electrode disposed on the second planarization layer; and a dam disposed on the pixel electrode and including an opening that exposes a portion of the top surface of the pixel electrode. The barrier layer may include an open region that does not cover at least a portion of the top surface of the conductive pattern, and the open region may be configured to overlap at least a portion of the pixel electrode.

[0313] In a display device according to an exemplary embodiment of the present disclosure, the open area may correspond to the area of ​​the pixel electrode.

[0314] In a display device according to an exemplary embodiment of the present disclosure, the open area may correspond to the area of ​​the opening.

[0315] In a display device according to an exemplary embodiment of the present disclosure, a second planarization layer may be disposed on a conductive pattern in an open area.

[0316] In a display device according to an exemplary embodiment of the present disclosure, conductive patterns may be spaced apart in a second direction perpendicular to the first direction. A barrier layer may include through-holes disposed between the conductive patterns. A first planarization layer and a second planarization layer may contact each other at the through-holes.

[0317] A display device according to an exemplary embodiment of the present disclosure may include: a substrate; a first planarization layer disposed on the substrate; a conductive pattern disposed on the first planarization layer and extending along a first direction, with adjacent conductive patterns spaced apart in a second direction perpendicular to the first direction; a barrier layer disposed on the first planarization layer; a second planarization layer disposed on the conductive pattern and the barrier layer; and a light-emitting region overlapping the conductive pattern. The barrier layer may include an open region, wherein the barrier layer is not disposed on at least a portion of the top surface of the conductive pattern, and the open region may be configured to overlap at least a portion of the light-emitting region.

[0318] In a display device according to an exemplary embodiment of the present disclosure, the barrier layer may include through-holes disposed between conductive patterns, and the first planarization layer and the second planarization layer may contact each other through the through-holes.

[0319] In a display device according to an exemplary embodiment of the present disclosure, the open area may correspond to the entire top surface of the conductive pattern.

[0320] A display panel according to an exemplary embodiment of the present disclosure may include: a substrate; a first planarization layer disposed on the substrate; conductive patterns disposed on the first planarization layer, adjacent conductive patterns being spaced apart from each other; a barrier layer disposed on the first planarization layer, wherein at least a portion of the top surface of the conductive patterns is not covered by the barrier layer; and a second planarization layer disposed on the conductive patterns and the barrier layer, wherein the barrier layer includes through-holes located between the conductive patterns.

[0321] A display panel according to an exemplary embodiment of the present disclosure may include: a substrate; a first planarization layer disposed on the substrate; a conductive pattern disposed on the first planarization layer and arranged along a first direction; a barrier layer disposed on the first planarization layer; a second planarization layer disposed on the conductive pattern and the barrier layer; a pixel electrode disposed on the second planarization layer; and a dam disposed on the pixel electrode and including an opening that exposes a portion of the top surface of the pixel electrode, wherein the barrier layer includes an open region in which at least a portion of the top surface of the conductive pattern is not covered by the barrier layer, and the open region may be configured to overlap with at least a portion of the pixel electrode.

[0322] A display panel according to an exemplary embodiment of the present disclosure may include: a substrate; a first planarization layer disposed on the substrate; a conductive pattern disposed on the first planarization layer and extending along a first direction, with adjacent conductive patterns spaced apart in a second direction perpendicular to the first direction; a barrier layer disposed on the first planarization layer; a second planarization layer disposed on the conductive pattern and the barrier layer; and a light-emitting region overlapping the conductive pattern. The barrier layer may include an open region, wherein at least a portion of the top surface of the conductive pattern is not covered by the barrier layer, and the open region is positioned to overlap at least a portion of the light-emitting region.

[0323] According to an exemplary embodiment of this disclosure, the flatness of a pixel electrode can be improved by providing a barrier layer between conductive patterns disposed below the pixel electrode.

[0324] According to an exemplary embodiment of this disclosure, the visibility of reflected light in a display device can be enhanced by improving the flatness of the pixel electrodes.

[0325] According to an exemplary embodiment of this disclosure, degassing from the planarization layers can be improved by providing a barrier layer with through holes between the planarization layers.

[0326] The above description has been presented to enable any person skilled in the art to implement and use the technical concepts of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described exemplary embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other exemplary embodiments and applications without departing from the spirit and scope of this disclosure. The above description and figures are provided as examples of the technical concepts of this disclosure for illustrative purposes only. That is, the disclosed exemplary embodiments are intended to illustrate the scope of the technical concepts of this disclosure.

[0327] Cross-reference to related applications

[0328] This application claims priority and benefit to Korean Patent Application No. 10-2024-0151728, filed on October 31, 2024, the entire contents of which are incorporated herein by reference for all purposes.

Claims

1. A display device, the display device comprising: substrate; A first planarization layer is disposed on the substrate; Conductive patterns are disposed on the first planarization layer, with adjacent conductive patterns spaced apart from each other. A barrier layer is disposed on the first planarization layer, and at least a portion of the top surface of the conductive pattern is not covered by the barrier layer; as well as A second planarization layer is disposed on the conductive pattern and the barrier layer. The barrier layer includes through-holes located between the conductive patterns.

2. The display device according to claim 1, in, The first planarization layer and the second planarization layer are in contact with each other at the via.

3. The display device according to claim 1, further comprising a dam portion disposed on the second planarization layer and including an opening. in, The opening overlaps at least partially with the conductive pattern.

4. The display device according to claim 3, in, The through hole is not located in the area overlapping with the opening.

5. The display device according to claim 3, in, The opening includes a first opening and a second opening. The conductive pattern includes a data line for transmitting data voltage and a drive voltage line for transmitting a high-level drive voltage. Wherein, the first opening is configured to at least partially overlap with the data line, and The second opening is configured to overlap at least a portion of the driving voltage line.

6. The display device according to claim 1, in, The barrier layer is configured to contact at least a portion of the side surface of the conductive pattern, and The second planarization layer is in contact with the top surface of at least a portion of the conductive pattern.

7. The display device according to claim 1, in, The barrier layer is configured to contact the lower side of at least a portion of the side surface of the conductive pattern, and is configured to be spaced apart from the upper side of at least said portion of the side surface of the conductive pattern. The second planarization layer is in contact with the upper side and top surface of at least the portion of the conductive pattern.

8. The display device according to claim 1, in, The barrier layer is configured to be spaced apart from at least a portion of the conductive pattern, and The second planarization layer is configured to contact at least the side and top surfaces of the conductive pattern.

9. The display device according to claim 1, in, The first planarization layer and the second planarization layer comprise organic insulating materials, and The barrier layer comprises an inorganic insulating material.

10. The display device according to claim 5, in, The conductive pattern also includes relay electrodes, and The relay electrode is configured to overlap with the contact hole in the first planarization layer.

11. The display device according to claim 10, further comprising transistors disposed on the substrate. in, The transistor includes a source electrode, a drain electrode, an active layer, and a gate electrode configured to overlap with the active layer. The relay electrode is electrically connected to the source electrode through the contact hole of the first planarization layer.

12. The display device according to claim 11, further comprising a light-emitting device disposed on the second planarization layer, in, The light-emitting device includes: A pixel electrode, wherein the pixel electrode is disposed on the second planarization layer; An intermediate layer, the intermediate layer being disposed on the pixel electrode; and A common electrode, wherein the common electrode is disposed on the intermediate layer, The pixel electrode is electrically connected to the relay electrode through the contact hole of the second planarization layer.

13. The display device according to claim 1, wherein, The barrier layer is disposed on the first planarization layer such that the barrier layer does not cover the entire top surface of the conductive pattern.

14. The display device according to claim 1, wherein, The conductive pattern includes a first conductive pattern, a second conductive pattern, and a third conductive pattern, and The first conductive pattern is a data line for transmitting data voltage, the second conductive pattern is a drive voltage line for transmitting high-level drive voltage, and the third conductive pattern is a relay electrode.

15. A display device comprising: substrate; A first planarization layer is disposed on the substrate; A conductive pattern is disposed on the first planarization layer and along a first direction; A barrier layer is disposed on the first planarization layer; A second planarization layer is disposed on the conductive pattern and the barrier layer; A pixel electrode, wherein the pixel electrode is disposed on the second planarization layer; as well as A dam portion, the dam portion being disposed on the pixel electrode and including an opening in which a portion of the top surface of the pixel electrode is exposed, The barrier layer includes an open region in which at least a portion of the top surface of the conductive pattern is not covered by the barrier layer. The open region overlaps with at least a portion of the pixel electrode.

16. The display device according to claim 15, in, The open area corresponds to the pixel electrode.

17. The display device according to claim 15, in, The open area corresponds to the opening.

18. The display device according to claim 15, in, The second planarization layer is disposed on the conductive pattern in the open area.

19. The display device according to claim 15, in, Adjacent conductive patterns are spaced apart along a second direction perpendicular to the first direction. The barrier layer includes through-holes located between the conductive patterns, and The first planarization layer and the second planarization layer are in contact with each other at the through-hole.

20. A display device comprising: substrate; A first planarization layer is disposed on the substrate; A conductive pattern is located on the first planarization layer and extends along a first direction, with adjacent conductive patterns spaced apart along a second direction perpendicular to the first direction. A barrier layer is disposed on the first planarization layer; A second planarization layer is disposed on the conductive pattern and the barrier layer; as well as The light-emitting area is configured to overlap with the conductive pattern. The barrier layer includes an open region in which at least a portion of the top surface of the conductive pattern is not covered by the barrier layer. The open region overlaps at least partially with the light-emitting region.

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