Method and apparatus for read disturb detection of memory device for data integrity control

Abstract

Methods and apparatus for read disturb detection of memory devices with aid of hash-based address mapping for data integrity control are provided. The method may include: establishing a read count table to record a plurality of first read counts about a plurality of first addresses; performing hash-based address mapping on a group of second addresses for which the read operation is detected to convert the group of second addresses into a group of first addresses in the plurality of first addresses for updating a group of first read counts; monitoring at least one highest first read count to determine whether the highest first read count reaches a first read count threshold; carrying out reverse mapping on the first address which detects the highest first read count so as to convert the first address into a target second address; and performing a media scanning procedure for the target second address.

Description

Technical Field

[0001] This invention relates to memory control, and more particularly to a method for data integrity control by detecting read-disturbance of a memory device using hash-based address mapping, and related apparatus such as the memory device, an electronic device containing the memory device, and a memory controller within the memory device. Background Technology

[0002] Memory devices can include flash memory for storing data, and access management for flash memory is relatively complex. For example, memory devices can be memory cards, embedded storage devices, or solid-state drives (SSDs), such as SSDs compliant with the Peripheral Component Interconnect Express (PCIe) specification. This memory device can be used to store various files in the host's file system, such as system files and user files. More specifically, memory devices like PCIe SSDs, due to their speed, low latency, scalability, reliability, and support for advanced protocols such as NVMe, are well-suited for database applications on computers, significantly improving the performance and responsiveness of database systems, thereby enhancing efficiency and user experience. According to related technologies, database systems can divide PCIe SSDs into multiple data spaces of different sizes for different use cases and simultaneously read different data spaces in parallel. Applications that frequently access the database's file directory or index areas may easily lead to over-reading of a single logical block address (LBA), causing severe single-page read interference. Such read interference can affect the data correctness at corresponding locations in the upper or lower layers of the three-dimensional (3D) stacked structure of flash memory. The erase state at the corresponding location may shift, causing uncorrectable errors. Even when the page at the read location is not faulty but there are many faulty bits in the physical location neighbor page, since the read location itself is not an faulty location, efficient detection of read interference errors is necessary.

[0003] To address the aforementioned issues, several suggestions can be proposed to attempt solutions, but these may also introduce additional problems such as side effects. For example, a first suggestion might involve refreshing a superblock when the number of read operations on that superblock reaches a threshold. Since data may be refreshed too frequently, the SSD may undergo frequent garbage collection (GC), leading to performance degradation. In another example, a second suggestion might involve refreshing a block when the number of read operations on that block reaches a threshold. However, the associated integrated circuit (IC) might require external memory to store the relevant records, as the internal storage space of the IC is often insufficient, and the records in external memory must be updated after each read operation. Furthermore, single-page read interference cannot be completely overcome, and the threshold might need to be set lower, resulting in a certain percentage of useless data being refreshed. Additionally, the aforementioned data block refresh mechanism may lead to performance degradation in current and future high-stack 3D flash memory applications. No suitable suggestions appear to exist in the relevant technologies. Therefore, a novel approach and related architecture are needed to address these problems without introducing side effects or in a way that is unlikely to introduce side effects. Summary of the Invention

[0004] The purpose of this invention is to provide a method for detecting read interference in a memory device by means of hash-based address mapping for data integrity control, and related devices such as the memory device, an electronic device containing the memory device, and a memory controller within the memory device, to solve the above-mentioned problems.

[0005] At least one embodiment of the present invention provides a method for detecting read interference in a memory device for data integrity control by means of hash-based address mapping. This method can be applied to a memory controller of the memory device. The memory device may include a memory controller and non-volatile (NV) memory, and the NV memory may include at least one NV memory element (e.g., one or more NV memory elements). The method may include: establishing a read count table to record multiple first read counts for multiple first addresses, wherein the multiple first addresses belong to a first memory address space smaller than a second memory address space; performing the hash-based address mapping on a set of second addresses that detect a read operation, to convert the set of second addresses into a set of first addresses among the multiple first addresses, for updating the set of first read counts for the set of first addresses in the read count table, wherein the set of second addresses belongs to the second memory address space; monitoring at least one highest first read count among the multiple first read counts in the read count table to determine whether the highest first read count reaches a first read count threshold; in response to the highest first read count reaching the first read count threshold, performing the hash-based address mapping reverse mapping on a first address that detects the highest first read count, to convert the first address into all second addresses corresponding to the first address as a set of target second addresses; and performing a media scan procedure on each of the set of target second addresses to maintain the data integrity of the data in the NV memory. integrity).

[0006] In addition to the methods described above, the present invention also provides a memory controller for detecting read interference in a memory device for data integrity control by means of a hash-based address mapping, wherein the memory device includes a memory controller and an NV memory. The NV memory may include at least one NV memory element (e.g., one or more NV memory elements). Furthermore, the memory controller includes a processing circuit configured to control the memory controller according to multiple host commands from a host device, to allow the host device to access the NV memory through the memory controller. More specifically, the memory controller is configured to establish a read count table to record multiple first read counts for multiple first addresses, wherein the multiple first addresses belong to a first memory address space smaller than a second memory address space; the memory controller is configured to perform the hash-based address mapping on a set of second addresses that detect a read operation, to convert the set of second addresses into a set of first addresses among the multiple first addresses, for updating the set of first read counts for the set of first addresses among the multiple first read counts in the read count table, wherein the set of second addresses belongs to the second memory address space; the memory controller is configured to monitor... The memory controller is configured to determine whether the highest first read count among the plurality of first read counts on the read count table reaches a first read count threshold; in response to the highest first read count reaching the first read count threshold, the memory controller is configured to perform the hash-based address mapping reverse mapping on a first address where the highest first read count is detected, to convert the first address into all second addresses corresponding to the first address as a set of target second addresses; and the memory controller is configured to perform a media scan procedure for each of the set of target second addresses to maintain the data integrity of the data in the NV memory.

[0007] In addition to the methods described above, the present invention also provides a memory device including the memory controller described above, wherein the memory device includes: the NV memory for storing information; and the memory controller coupled to the NV memory for controlling the operation of the memory device.

[0008] Furthermore, the present invention also provides an electronic device including the aforementioned memory device, wherein the electronic device further includes a host device coupled to the memory device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor for providing power to the at least one processor and the memory device. Additionally, the memory device can provide storage space for the host device.

[0009] According to some embodiments, the device may include at least a portion (e.g., a portion or all) of the electronic device. For example, the device may include the memory controller in the memory device. As another example, the device may include the memory device. Yet another example, the device may include the electronic device.

[0010] The method and related apparatus of the present invention can ensure the normal operation of the memory device under various conditions. For example, the memory controller within the memory device can perform related operations according to at least one control scheme (e.g., one or more control schemes) of the method, in particular, reading the respective physically adjacent pages of the pages located at the set of target second addresses to generate their respective read results, for determining whether these physically adjacent pages are healthy, and identifying any unhealthy physically adjacent pages as read-disturbance-affected pages, such as pages affected by read interference, so as to preemptively process the read-disturbance-affected pages before they are corrupted. The memory controller can write any partial data stored in the read-disturbance-affected page into a new page at a new second address to maintain the data integrity of the data in the NV memory, and mark the read-disturbance-affected page as an invalid physical page to allow the read-disturbance-affected page to be corrupted during any further read of the target second address without degrading the data integrity of the data in the NV memory. Furthermore, the method and related apparatus of the present invention can solve the problems in the related art without introducing side effects or by means unlikely to introduce side effects. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 The lower half of the diagram illustrates an address hashing and table shrinking control scheme for a method of detecting read interference in a memory device for data integrity control using hash-based address mapping, according to an embodiment of the present invention. Figure 2 The upper half of the diagram illustrates the control scheme for a non-address-hashing-based huge table for better understanding.

[0013] Figure 3 An embodiment of the present invention is illustrated Figure 2 The diagram illustrates a series of address hashing operations involved in the address hashing and table shrinking control scheme.

[0014] Figure 4 An embodiment of the present invention illustrates a hash-based address mapping and reverse mapping control scheme of the method.

[0015] Figure 5 According to an embodiment of the present invention, one of the scanlocation generators involved in the method is illustrated.

[0016] Figure 6 According to an embodiment of the present invention, the read count screening and scan location generation control scheme of the method is illustrated.

[0017] Figure 7 A schematic diagram of a three-dimensional (3D) NAND flash memory involved in the method is illustrated according to an embodiment of the present invention.

[0018] Figure 8 According to an embodiment of the present invention, a reading interference position relationship is illustrated.

[0019] Figure 9 An embodiment of the present invention illustrates a workflow of the method.

[0020] Figure 10 According to an embodiment of the present invention, the read-count clear and reduction control scheme of the method is illustrated.

[0021] [Symbol Explanation]

[0022] 10: Electronic devices

[0023] 50: Main unit

[0024] 52: Processor

[0025] 54: Power Supply Circuit

[0026] 58,118: Transmission interface circuit

[0027] 100: Memory device

[0028] 110: Flash memory controller

[0029] 112: Microprocessor

[0030] 112C: Program Code

[0031] 112M: Read-Only Memory (ROM)

[0032] 114: Control Logic Circuit

[0033] 116: Random Access Memory (RAM)

[0034] 120: Flash memory module

[0035] 122-1~122-N: Flash memory elements

[0036] 130: Read Interference Detection and Data Integrity Control (RDD&DIC) Circuit

[0037] 131: Read Counter Adder (RCA) Circuit

[0038] 132: Hash-based address mapping (HAM) circuit

[0039] 133: Reverse Mapping (RM) Circuit

[0040] 201: Second Memory Address Space

[0041] 202: First memory address space

[0042] 210, 220: Read the counting table

[0043] 216: Static Random Access Memory (SRAM)

[0044] 290: Dynamic Random Access Memory (DRAM)

[0045] RC(0),RC(1),RC(2)~RC(2j-1): Read count; SEC(1),SEC(2)~SEC(2k): Address segment

[0046] GRP(0), GRP(1)~GRP(2j-1): a group of inputs (or "input group") GRP(J0): a group of outputs (or "output group")

[0047] 500: Scan Position Generator

[0048] 501: Main read count storage unit

[0049] 510: Address Read / Write (R / W) Control Circuit

[0050] 520: Read counter comparator and maximum value scanning circuit

[0051] 531: Reading the counting adder circuit

[0052] 532: Hash Function Circuit

[0053] 533: Inverse Mapping Circuit

[0054] 534: Read counter clear / decrease circuit

[0055] 601: Top-tier group processing

[0056] 610: Address Hash Operation

[0057] 620: Read count accumulation operation

[0058] 630: Cumulative Comparison Operation

[0059] 640: Reverse mapping operation

[0060] 645: Media Scanning Procedure

[0061] 650: Read count clear / decrease operation

[0062] 655: Top group processing completed inspection operation

[0063] 660: Top-tier group search operation

[0064] M(1,1,1)~M(Nx,Ny,Nz): memory cells

[0065] MBLS(1,1)~MBLS(Nx,Ny): Upper-level selection circuit; MSLS(1,1)~MSLS(Nx,Ny): Lower-level selection circuit; BL(1)~BL(Nx): Bit lines

[0066] BLS(1)~BLS(Ny): Upper layer selection line

[0067] WL(1,1)~WL(Ny,Nz): Word lines

[0068] SLS(1)~SLS(Ny): Lower layer selection lines

[0069] SL(1)~SL(Ny): Source line

[0070] PS2D(1)~PS2D(Ny): Circuit Module

[0071] 801, 811, 821: First Page

[0072] 802: Floor

[0073] 810, 820, 830, 840: A set of pages

[0074] S11~S15: Steps

[0075] CNT_index: Error count index

[0076] ERROR_CNT(CNT_index), ERROR_CNT(1)~ERROR_CNT(3): Error count

[0077] ERROR_CNTTHRESHOLD: Error count threshold Detailed Implementation

[0078] Figure 1 This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors), collectively referred to as processor 52, and may further include a power supply circuit 54 coupled to processor 52. Processor 52 is used to control the operation of the host device 50, while the power supply circuit 54 is used to provide power to processor 52 and memory device 100, and to output one or more drive voltages to memory device 100. The function of memory device 100 is to provide storage space for host device 50 and to obtain one or more drive voltages from host device 50 as power for memory device 100. Examples of host device 50 include, but are not limited to, personal computers such as multifunction mobile phones, wearable devices, tablet computers, desktop computers, and laptop computers. Examples of memory device 100 include, but are not limited to, SSDs such as PCIe SSDs, and various embedded memory devices such as embedded memory devices compliant with PCIe specifications. According to this embodiment, the memory device 100 may include a memory controller, such as a flash memory controller 110, and may further include an NV memory, such as a flash memory, which may be implemented as a flash memory module 120. The flash memory controller 110 is used to control the operation of the memory device 100 and access the flash memory module 120, while the flash memory module 120 is used to store information. The NV memory, such as the flash memory module 120, may include at least one NV memory element (e.g., one or more NV memory elements), such as a plurality of flash memory elements 122-1, 122-2, ... and 122-N, where "N" represents a positive integer greater than 1. For better understanding, these flash memory elements 122-1, 122-2, ... and 122-N can be implemented by means of flash memory chips or flash memory dies.

[0079] like Figure 1As shown, the flash memory controller 110 may include a processing circuit, such as a microprocessor 112, a storage unit, such as a read-only memory (ROM) 112M, a control logic circuit 114, a random-access memory (RAM) 116, and a transmission interface circuit 118, wherein the above components can be coupled to each other via a bus. RAM 116 is implemented using static random-access memory (SRAM), but the invention is not limited thereto. RAM 116 can be used to provide internal storage space for the flash memory controller 110. For example, RAM 116 can be used as a buffer memory to buffer data. Furthermore, in this embodiment, ROM 112M is used to store program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to the flash memory 120. In some embodiments, program code 112C may be stored in RAM 116 or any other type of memory. Furthermore, the control logic circuit 114 can be used to control the flash memory 120, and may include a read-disturbance detection (RDD) and data integrity control (DIC) circuit 130 (denoted as "RDD&DIC circuit" for simplicity) for performing data integrity control. The read-disturbance detection and data integrity control circuit 130 may include a read count adder (RCA) circuit 131, a hash-based address mapping (HAM) circuit 132, a reverse mapping (RM) circuit 133 (denoted as "RCA circuit", "HAM circuit", and "RM circuit" respectively for simplicity) and other circuits. The transmission interface circuit 118 may conform to one or more communication specifications (e.g., Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect (PCI) specification, High-Speed ​​Peripheral Component Interconnect (PCIe) specification, Embedded Multi Media Card (eMMC) specification, and Universal Flash Storage (UFS) specification), and may communicate with the host device 50 (or the corresponding transmission interface circuit 58 therein) according to one or more of these communication specifications.Similarly, the transmission interface circuit 58 may also conform to one or more communication specifications and communicate with the memory device 100 (or the transmission interface circuit 118 therein) according to one or more communication specifications.

[0080] In this embodiment, the host device 50 can transmit host commands and corresponding logical addresses to the flash memory controller 110 to access the memory device 100. The flash memory controller 110 receives the host commands and logical addresses, converts the host commands into memory operation commands (hereinafter referred to as operation commands), and further uses the operation commands to control the flash memory module 120 to perform read, write / program, and other operations on memory cells (e.g., data pages) with physical addresses within the flash memory module 120, wherein these physical addresses can be associated with logical addresses. When the flash memory controller 110 performs an erase operation on any flash memory element 122-n (where “n” represents any integer in the range [1, N]) of a plurality of flash memory elements 122-1, 122-2, ..., and 122-N, at least one block of a plurality of blocks in the flash memory element 122-n can be erased, wherein each of these blocks can contain multiple pages (e.g., data pages), and access operations such as read or write operations can be performed on one or more pages.

[0081] Figure 2 The lower half of the diagram illustrates an address hashing and table shrinking control scheme, according to an embodiment of the present invention, for data integrity control by means of a method for detecting read interference in a memory device using hash-based address mapping. Figure 2 The upper half of the diagram illustrates a non-address hash-based mega-table control scheme for better understanding. It is assumed that one or more functions of memory device 100 can be temporarily disabled to allow flash memory controller 110 and flash memory module 120 to... Figure 2The non-address hash-based mega-table control scheme shown in the upper part operates, but the invention is not limited thereto. For example, when the flash memory controller 110 detects that a read count (e.g., the number of read operations) of a superblock (e.g., a combination of blocks across different channels and / or across different flash memory wafers / dies) reaches a threshold, the flash memory controller 110 can be configured to perform a data block refresh on that superblock. Assuming there are 256 superblocks, and the read count of each superblock is recorded using four bytes, a kilobyte (1KB) table is required. However, the records in such a 1KB table may be too inaccurate and may lead to excessively frequent data refreshes, thus the memory device 100 may frequently initiate garbage collection (GC), resulting in poor performance of the memory device 100. To obtain more accurate records, the flash memory controller 110 can be configured to perform a data block refresh on a block when a read count (e.g., the number of read operations) of a block is detected to reach a threshold. Taking an enterprise-grade SSD as an example, assuming each logical unit number (LUN) has 2048 blocks and 128 LUNs, and the read count for each block is recorded using four bytes, a massive table of one million bytes (1MB) is required. The storage space for such a 1MB table typically requires dynamic random access memory (DRAM), and the massive table must be updated with each read operation. Even with this massive table, single-page read interference cannot be completely overcome. Since the flash memory module 120 may be more susceptible to damage from single-page read interference than full-block sequential reads, a lower threshold should be set, which will result in a certain percentage of useless data being flushed.

[0082] Based on this non-address hash-based jumbo table control scheme, the flash memory controller 110 can create the jumbo table, such as a read count table 210 for one of multiple physical addresses (e.g., the physical address of the NV memory, such as the flash memory module 120, which can be accessed by the flash memory controller 110), and requires a large amount of storage space to store this jumbo table, such as the read count table 210. As mentioned above, the RAM 116 in the flash memory controller 110 is typically implemented using SRAM, such as an SRAM 216, and it is generally not possible to prepare such a large amount of storage space inside the flash memory controller 110. When using this non-address hash-based jumbo table control scheme, the memory device 100 may be forced to further include an external memory of the flash memory controller 110, such as a DRAM 290 located outside the flash memory controller 110, to provide the aforementioned large amount of storage space, thereby increasing the associated costs, such as material costs, labor costs, etc.

[0083] like Figure 2 As shown in the lower half, the flash memory controller 110 can operate according to this address hashing and table shrinking control scheme to shrink the massive table into a smaller table, such as a read count table 220 stored in RAM 116, such as SRAM 216, to achieve better overall performance. More specifically, the flash memory controller 110 can maintain the read count table 220 with reference to a first memory address space 202 instead of a second memory address space 201 for read interference detection, wherein a plurality of second addresses belonging to the second memory address space 201 can represent a plurality of physical addresses of the NV memory, such as the flash memory module 120, that are accessible by the flash memory controller 110. Furthermore, the flash memory controller 110 can perform a read operation on the flash memory module 120 at any of the plurality of second addresses. In response to any of the aforementioned second addresses (denoted as "read addresses" for brevity) where the read operation was performed, the flash memory controller 110 may perform address translation to convert the address in the second memory address space 201 to an address in the first memory address space 202 for updating the read count table 220 and performing read interference detection based on the read count table 220. For example, the relevant operation may include:

[0084] (1) The flash memory controller 110 can establish a read count table 220 to record multiple first read counts {RC} for multiple first addresses, which belong to a first memory address space 202, and the first memory address space 202 is smaller than the second memory address space 201;

[0085] (2) The flash memory controller 110 can perform the hash-based address mapping on a set of second addresses that detect a read operation, so as to convert the set of second addresses into a set of first addresses among the plurality of first addresses, so as to update the set of first read counts {RC} with respect to the set of first addresses in the plurality of first read counts {RC} on the read count table 220, wherein the set of second addresses belongs to the second memory address space 201. For example, the plurality of second addresses may contain the set of second addresses, and the set of second addresses may be regarded as a subset of the plurality of second addresses.

[0086] (3) The flash memory controller 110 can monitor at least one of the highest first read counts {RC} on the read count table 220 to determine whether the highest first read count RC has reached a first read count threshold RCTHRESHOLD.

[0087] (4) In response to the highest first read count RC reaching a first read count threshold RCTHRESHOLD, the flash memory controller 110 may perform the reverse mapping of the hash-based address mapping on a first address where the highest first read count RC is detected, to convert the first address into all second addresses corresponding to the first address, such as all second addresses mapped to the first address in the hash-based address mapping, as a set of target second addresses; and

[0088] (5) The flash memory controller 110 can perform a media scan program for each of the target second addresses to maintain the data integrity of the data in the NV memory.

[0089] The plurality of first addresses belonging to the first memory address space 202 can be implemented as a portion of the plurality of second addresses belonging to the second memory address space 201, but the present invention is not limited thereto.

[0090] When operating according to the address hashing and table shrinking control scheme, the flash memory controller 110 can record the plurality of first read counts {RC} for the plurality of first addresses on the read count table 220, instead of recording the plurality of second read counts {RC'} for the plurality of second addresses on a large table such as read count table 210. Furthermore, the flash memory controller 110 can monitor at least the highest first read count RC among the plurality of first read counts {RC} on read count table 220 to determine whether the highest first read count RC reaches a first read count threshold RCTHRESHOLD, without needing to monitor any highest second read count RC' among the plurality of second read counts {RC'} on a large table such as read count table 210 to determine whether the highest second read count RC' reaches any second read count threshold RCTHRESHOLD'. For example, the flash memory controller 110 can use a hashing function to convert the set of second addresses to the set of first addresses among the plurality of first addresses, and can use a reverse hashing function to convert the first address to all the aforementioned second addresses corresponding to the first address. The hash function can be implemented as a many-to-one function, such as a modulo function, for performing the hash-based address mapping, while the reverse hash function can be implemented as a multivalued function for performing the reverse mapping; however, the invention is not limited thereto. In some examples, the hash function and the reverse hash function can be different. According to some embodiments, the hash-based address mapping can represent a first mapping for mapping any one of the multiple input groups (or any input group) of the first mapping to the same output among the multiple outputs of the first mapping, while the reverse mapping can represent a second mapping for mapping any one of the multiple inputs of the second mapping to the same output group (or the same output group) among the multiple output groups (or multiple output groups) of the second mapping. For example, the first mapping can be implemented using the many-to-one function such as the modulo function, and the second mapping can be implemented using the multivalued function.

[0091] Figure 3 An embodiment of the present invention is illustrated Figure 2 The address hashing and table shrinking control scheme shown involves a series of address hashing operations, where multiple address segments (or "multi-segment addresses"), associated hashed addresses, and associated read count table entries can be plotted. Figure 3 To facilitate better understanding, let's assume that "m", "j", and "k" are positive integers, and m = (j + k). Then, the plurality of second addresses (e.g., the plurality of physical addresses) belonging to the second memory address space 201 can contain 2m second addresses and can be divided into 2k address segments (or "2k segment addresses") {SEC(1), SEC(2), ..., SEC(2k)}. The plurality of first addresses (e.g., the hash addresses) belonging to the first memory address space 202 can contain 2j first addresses, for example, 2j addresses {0, 1, ..., (2j-1)}. Using this modulo function as an example of the hash function, the flash memory controller 110 can perform this hash-based address mapping to convert the plurality of second addresses belonging to the second memory address space 201 into the plurality of first addresses belonging to the first memory address space 202, such as... Figure 3 As indicated by the arrow. More specifically, the aforementioned multiple address segments, such as the 2k address segments (or the 2k address segments) {SEC(1), SEC(2), ..., SEC(2k)} among the multiple second addresses belonging to the second memory address space 201, can respectively contain addresses {{0,1, ...,(2j-1)},{(2j+0),(2j+1),...,(2j+1-1)},...,{((2j*(2k-1))+0),((2j*(2k-1))+1),...,(2j+k-1)}} (where “(2j*(2k-1))” can be written as “2j(2k-1)” for brevity), belonging to The aforementioned associated hash addresses in the first memory address space 202 may include the 2j addresses {0,1,…,(2j-1)}, and the aforementioned associated read count table entries may include 2j read count table entries corresponding to the 2j addresses {0,1,…,(2j-1)}, such as the first read count {RC(0),RC(1),RC(2),…,RC(2j-1)} (or “read count {RC(0),RC(1),RC(2),…,RC(2j-1)}”) associated with the 2j addresses {0,1,…,(2j-1)} recorded by the flash memory controller 110. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0092] According to some embodiments, m = 29, j = 16, and k = 13, but the invention is not limited thereto. According to some embodiments, m, j, and k can be varied, and in particular, can be equal to any other set of fixed values ​​different from the above set of fixed values ​​(m = 29, j = 16, k = 13). For the sake of simplicity, similar details in these embodiments will not be repeated here.

[0093] Figure 4According to an embodiment of the present invention, a hash-based address mapping and reverse mapping control scheme of the method is illustrated. The flash memory controller 110 can perform the hash-based address mapping (e.g., the first mapping) to map the multiple group inputs (or the multiple input groups) {GRP(0),GRP(1),...,GRP(2j-1)} (e.g., the 2j group address belonging to the second memory address space 201 {{0,(2j+0),...,((2j*(2k-1))+0)},{1,(2j+1),...,((2j*(2k-1))+1)},...,{(2j-1),(2j+1-1),...,(2j+k-1)}}, where “(2j*(2k-1))” can be written as “2j(2k-1)” for brevity. GRP() maps any group of inputs (or any input group) in the first mapping to the same output among the plurality of outputs of the first mapping, for example, one of the 2j addresses {0,1,…,(2j-1)} belonging to the first memory address space 202, and performs the reverse mapping, for example, the second mapping, to map the plurality of inputs of the second mapping (e.g., addresses {J|J=J0,J1,…,J(NRC_top_group-1)} belonging to the first memory address space 202, where addresses {J0,J1,…,J(NRC_top_group-1)} are a subset of the 2j addresses {0,1,…,(2j-1)}, denoted as ... Any input (e.g., address J) of the second mapping is mapped to the multigroup output (or the multiple output groups) of the second mapping {GRP(J)|J=J0,J1,…,J(NRC_top_group-1); The same group of outputs (or the same output group) GRP(J) belongs to the second memory address space 201. According to some viewpoints, the multiple input groups (or the multiple input groups) {GRP(0), GRP(1), ..., GRP(2j-1)} and the input group (or the input group) GRP() can also be referred to as the multiple address groups (or the multiple address groups) {GRP(0), GRP(1), ..., GRP(2j-1)} and the address group (or the address group) GRP(), respectively, while the multiple output groups (or the multiple output groups)... The output of this group (or the output group) GRP(J) can also be referred to as the multi-group address (or the multiple address groups) {GRP(J)|J=J0,J1,…,J(NRC_top_group-1); And the group address (or the group of addresses) GRP(J).

[0094] like Figure 4As shown, the read count RC(J0) can be equal to the maximum value of the read counts {RC(0),RC(1),…,RC(2j-1)}, Max({RC(0),RC(1),…,RC(2j-1)} (denoted as “RC(J0)=Max({RC(0),…,RC(2j-1)})”, where “Max()” can represent the maximum value function), and therefore can be called the highest read count RC(J0), while the read counts {RC(J)|J=J0,J1,…,J(NRC_top_group-1); The top NRC_top_group read counts can be represented by RC(J0)≥RC(J1)≥…≥RC(NRC_top_group-1). For example, when NRC_top_group = 20, the top NRC_top_group read counts can be the first 20 read counts, but the invention is not limited thereto. In some examples, the number of read counts in the top NRC_top_group read counts, NRC_top_group, can be varied, in particular, it can be equal to any other value (e.g., one of the values ​​in the interval [1,2j]). Furthermore, the multi-group output of this second mapping {GRP(J)|J=J0,J1,…,J(NRC_top_group-1); Any group of outputs GRP(J) can contain 2k addresses {J,(2j+J),…,((2j*(2k-1))+J)}. For example, when J=J0, this group of outputs GRP(J0) can contain 2k addresses {J0,(2j+J0),…,((2j*(2k-1))+J0)}; when J=J1, this group of outputs GRP(J1) can contain 2k addresses {J1,(2j+J1),…,((2j*(2k-1))+J1)}; and so on. For the sake of simplicity, similar content will not be repeated in this embodiment.

[0095] Some implementation details of the reverse mapping of hash-based address mapping can be described below. According to some embodiments, address J0 may be one of the 2j addresses {0,1,…,(2j-1)} in the first memory address space 202. If J0 = 0, then the 2k addresses {J0,(2j+J0),…,((2j*(2k-1))+J0)} in the output group GRP(J0=0) can be rewritten as the address {0,(2j+0),…,((2j*(2k-1))+0)}, which is equal to the address {0,(2j+0),…,((2j*(2k-1))+0)} in the input group GRP(0), indicating the reverse mapping of the case where J0 = 0; if J0 = 1, then the 2k addresses {J0,(2j+J0),…,((2j*(2k-1))+J0)} in the output group GRP(J0=1) can be rewritten as the address {1,(2j+1),…,((2j*(2k-1))+1)}, which is equal to the address {1,(2j+1),…,((2j*(2k-1))+1)} in the input group GRP(1) 1,(2j+1),…,((2j*(2k-1))+1)}, which indicates the reverse mapping of the case J0=1;…; and if J0=(2j-1), then the 2k addresses {J0,(2j+J0),…,((2j*(2k-1))+J0)} in the output group GRP(J0=(2j-1)) can be rewritten as the addresses {(2j-1),(2j+(2j-1)),…,((2j*(2k-1))+(2j-1))} or the addresses {(2j-1),(2j+1-1),…,(2j+k-1)}, which are equal to the addresses {(2j-1),(2j+1-1),…,(2j+k-1)} in the input group GRP(2j-1), which indicates the reverse mapping of the case J0=(2j-1). For the sake of simplicity, similar content in these embodiments will not be repeated here.

[0096] exist Figure 4 In the illustrated embodiment, the address hashing operation can be presented in a group-by-group manner to indicate the relationship between the hash-based address mapping and the reverse mapping, but the invention is not limited thereto. Since the plurality of second addresses (e.g., the plurality of physical addresses) can increase from the starting address of the second memory address space 201, the plurality of second addresses belonging to the second memory address space 201 should be arranged according to... Figure 3 Arrange them in the order shown, and the address hash operations applied to / generated on these multiple second addresses should be arranged as follows: Figure 3As shown by the arrows, the 2k address segments {SEC(1),SEC(2),…,SEC(2k)} belonging to the second memory address space 201 can be hashed by the flash memory controller 110 to generate corresponding hash addresses, such as the 2j addresses {0,1,…,(2j-1)} belonging to the first memory address space 202.

[0097] Figure 5 A scan position generator 500 involved in the method is illustrated according to an embodiment of the present invention. The scan position generator 500 can... Figure 1 The flash memory controller 110 shown is implemented within the flash memory controller and may include a main read count storage unit 501, an address read / write (R / W) control circuit 510 (denoted as "address R / W control circuit" for simplicity), a read count comparator and maximum value scan circuit 520, a read count adder circuit 531, a hash function circuit 532, a reverse mapping circuit 533, and a read count clear / decrement circuit 534. More specifically, the main read count storage unit 501 can be implemented through a storage area within RAM 116, while other components in the scan position generator 500 (such as...) Figure 5 (As shown) can then be integrated into Figure 1 Within the read interference detection and data integrity control circuit 130, the read counter adder circuit 531, the hash function circuit 532, and the reverse mapping circuit 533 can respectively serve as... Figure 1 Examples of the read counter adder circuit 131, the hash-based address mapping circuit 132, and the reverse mapping circuit 133 shown are illustrated.

[0098] The main read count storage unit 501 can be configured to store the read count table 220, and the address read / write control circuit 510 can be configured to perform address read / write control on the main read count storage unit 501. Furthermore, the read count comparator and the maximum value scan circuit 520 can be configured to obtain at least a portion of the read counts {RC} (e.g., a portion of the read counts {RC} or all of the read counts {RC}) from the read count table 220 in the main read count storage unit 501, to perform read count comparison and read count maximum value scan, to scan for the maximum value to find at least the maximum value, such as the highest read count RC(J0) (e.g., the maximum value Max({RC(0),RC(1),…,RC(2j-1)} of the read counts {RC(0),RC(1),…,RC(2j-1)}), thereby outputting an address index of the maximum value, such as address J0, but the invention is not limited thereto. During the read count comparison and read count maximum value scan, the read count comparator and maximum value scan circuit 520 can also find the top NRC_top_group read counts {RC(J)|J=J0,J1,…,J(NRC_top_group-1); (For example: the top twenty read counts {RC(J)|J=J0,J1,…,J19}, for the case of NRC_top_group=20), to output these top NRC_top_group read counts {RC(J)|J=J0,J1,…,J(NRC_top_group-1); The address index of any read count RC(J) (e.g., address J) is used to perform the reverse mapping using the reverse mapping circuit 533 to convert the address index, e.g., address J, into the 2k addresses {J,(2j+J),…,((2j*(2k-1))+J)}.

[0099] like Figure 5As shown, the read counter adder circuit 531 and the hash function circuit 532 can be coupled to the main read counter storage unit 501 to access (e.g., read or write) the main read counter storage unit 501, thereby updating the read counter table 220 stored in the main read counter storage unit 501. For example, the read counter adder circuit 531 can be configured to perform read counter addition or accumulation operations to accumulate the read counters {RC(0), RC(1), ..., RC(2j-1)}. Additionally, the hash function circuit 532 can be configured to provide the hash function for performing the hash-based address mapping, mapping addresses in the second memory address space 201 to addresses in the first memory address space 202, thereby hashing a read address in the second memory address space 201 (e.g., a read physical address, such as the physical address where a read operation is performed) to generate a hash address in the first memory address space 202. In response to the read operation at the read address and / or the receipt of the read address, the hash function circuit 532 can convert the read address in the second memory address space 201 into the hash address, for example, the address corresponding to one of the addresses {0,…,(2j-1)} in the first memory address space 202, and the address read / write control circuit 510 can update the read count table 220 in the main read count storage unit 501. In particular, the read count RC on the read count table 220 corresponding to the hash address (e.g., the address corresponding to the address in the address {0,…,(2j-1)}) is updated by means of or with the aid of the read count adder circuit 531, so that the read count RC increases by a predetermined increment (e.g., one). Over time, one or more read counts {RC}, such as at least a portion of the aforementioned read counts {RC(0), RC(1), ..., RC(2j-1)}, can be incremented, and the read count comparator and maximum value scan circuit 520 can perform read count comparison and read count maximum value scan operations to output the address index (e.g., any address J in the address {J|J=J0,J1,...,J(NRC_top_group-1)}). The reverse mapping circuit 533 can be configured to perform the reverse mapping of the hash-based address mapping to map or convert the address index, such as address J, into a group of scan address candidates, such as the 2k addresses {J,(2j+J),...,((2j*(2k-1))+J)}. For example, when J = J0, the reverse mapping circuit 533 can perform the reverse mapping to map or convert the address index, such as address J0, into a group of scan address candidates such as address {J0,(2j+J0),…,((2j*(2k-1))+J0)}.When needed, the read count clearing / decrease circuit 534 can be configured to perform read count clearing or decrementing operations to selectively clear the highest read count RC(J0) or decrement the highest read count RC(J0) to derate / derate the read count RC(J0) (or reduce the rating of the read count RC(J0)), thereby reducing the rated read-disturbance metric, such as the read interference metric, indicated by the read count RC(J0). Furthermore, an external system of the scan position generator 500 (e.g., a system implemented as system code running on the microprocessor 112) can selectively trigger read count addition / accumulation operations or read count clearing / decrease operations (labeled "Trigger Read Count and Decrement" for brevity). For simplicity, similar descriptions are not repeated here in this embodiment.

[0100] Figure 6 According to an embodiment of the present invention, a read count filtering and scan position generation control scheme for this method is illustrated. For example, a scan position generator 500 within a flash memory controller 110 may operate according to this read count filtering and scan position generation control scheme, and the related operations may include:

[0101] (1) In an address hashing operation 610, the scan position generator 500 can receive a read address (e.g., the physical address where the read operation is performed) as an input signal to the hash function circuit 532, so as to map the read address in the second memory address space 201 to the hash address in the first memory address space 202 (e.g., the corresponding address in the aforementioned address {0,…,(2j-1)}) through the hash function of the hash function circuit 532;

[0102] (2) In a read count accumulation operation 620, the scan position generator 500 (or the read count adder circuit 531 therein) can read the read count RC corresponding to the hash address (e.g., the address in address {0,…,(2j-1)}) from the read count table 220 stored in the main read count storage unit 501, and increment the read count RC by the predetermined increment (e.g., one) so that the read count RC in the read count table 220 is updated by an increment operator (e.g., RC++);

[0103] (3) In an accumulative comparison operation 630, the scan position generator 500 (or the read count comparator and maximum value scan circuit 520 therein) can obtain the accumulated read counts {RC} from the main read count storage unit 501, such as at least a portion of the read counts {RC(0), RC(1), ..., RC(2j-1)}, for real-time calculation and comparison, and set the top NRC_top_group read counts {RC(J)|J=J0,J1,...,J(NRC_top_group-1); (For example: the top twenty read counts {RC(J)|J=J0,J1,…,J19}, for the case of NRC_top_group=20) and their address indices such as the relevant addresses {J0,J1,…,J(NRC_top_group-1)} in the first memory address space 202 (for example: address {J0,J1,…,J19}, for the case of NRC_top_group=20) are recorded to a storage cell, such as a temporary register circuit, within the scan position generator 500. For multiple read operations, a partial workflow including address hashing operation 610, read count accumulation operation 620 and accumulation comparison operation 630 can be performed multiple times, as shown by the arrows drawn in dashed lines. After comparing the accumulated read count results such as at least a portion of the read counts {RC} mentioned above, the read count comparator and the maximum value scan circuit 520 can output the top NRC_top_group read counts {RC(J)|J=J0,J1,…,J(NRC_top_group-1); The address index of any of the above read counts RC(J) (e.g., address J) is associated with the address J0 of the highest read count RC(J0) in the case of J = J0, and is sent to the reverse mapping circuit 533;

[0104] (4) Under the control of an external system (or a system running on microprocessor 112) of the scan position generator 500, during a reverse mapping operation 640, the scan position generator 500 (or its internal reverse mapping circuit 533) can perform the reverse mapping to map or convert an address index, such as address J, into the group of scan address candidates such as the 2k addresses {J,(2j+J),…,((2j*(2k-1))+J)} (e.g., address {J0,(2j+J0),…,((2j*(2k-1))+J0)}, for In the case of J = J0, these 2k addresses {J,(2j+J),…,((2j*(2k-1))+J)} can represent physical addresses where read interference may occur, while for J = J0, these 2k addresses {J0,(2j+J0),…,((2j*(2k-1))+J0)} can represent physical addresses where read interference is most likely.

[0105] (5) After the media scan program 645 is triggered by the external system (or the system running on the microprocessor 112) of the scan position generator 500, during a read count clearing / decrementing operation 650, the scan position generator 500 (or the address read / write control circuit 510, with the aid of the read count clearing / decrementing circuit 534) may update the read count RC(J) (e.g., the highest read count RC(J0), for the case of J = J0) according to the error status of the media scan program 645 (e.g., number of error bits / count, or referred to as “error count” for brevity) to selectively reset the read count RC(J) to zero or decrement the read count RC(J), wherein the flash memory controller 110 (or the system running on the microprocessor 112) may perform a top group processing completion check operation 655 to determine the top NRC_top_group of read counts {RC(J)|J = J0, J1, ..., J(NRC_top_group-1); Whether the corresponding top group processing 601 (which may include a reverse mapping operation 640, a media scanning procedure 645, and a read count clearing / decrease operation 650) is complete (marked as "top group processing complete" for brevity), to repeat top group processing 601 for the next read count RC(J+1) following the current read count RC(J); and

[0106] (6) For the top NRC_top_group of read counts {RC(J)|J=J0,J1,…,J(NRC_top_group-1); After the top group processing 601 of each read count RC(J) is completed, during a top group search operation 660, the flash memory controller 110 (or the system running on the microprocessor 112) can read the latest read count {RC(0), RC(1), ..., RC(2j-1)} in the read count table 220 to search for the latest top NRC_top_group read counts {RC(J)|J=J0,J1,...,J(NRC_top_group-1); To continue the relevant operations in order to maintain the data integrity of the data in the NV memory, such as the flash memory module 120;

[0107] The flash memory controller 110 may perform a media scanning procedure 645 to test the physical locations of pages located at the respective target second addresses obtained in the reverse mapping operation 640, but the invention is not limited thereto. In some embodiments, Figure 1 The architecture of the flash memory controller 110 shown Figure 5 The architecture of the scan position generator 500 shown Figure 6 One or more parts of the workflow and / or related operations shown may differ. According to some viewpoints, the read counter adder circuit 531 can be considered an accumulative adder, while the read counter comparator and maximum value scan circuit 520 can be considered accumulative comparators. For the sake of simplicity, similar descriptions are not repeated here.

[0108] Some implementation details of the read count filtering and scan position generation control scheme can be further described below. According to some embodiments, the flash memory controller 110 (or the system running on the microprocessor 112) can determine in advance the health status of pages adjacent to the physical location for data protection to prevent data in the flash memory module 120 from being damaged by read interference, thereby maintaining data integrity. When media scanning procedure 645 is performed to test the physical location neighboring pages of the respective pages located at the set of target second addresses obtained in reverse mapping operation 640, such as the physical location neighboring page {PAGENEIGHBOR(JTARGET)} of the page {PAGETARGET(JTARGET)} located at the set of target second addresses {JTARGET} (e.g., the 2k addresses {J,(2j+J),…,((2j*(2k-1))+J)} determined in reverse mapping operation 640), the flash memory controller 110 can read at least one physical location neighboring page PAGENEIGHBOR(JTARGET) of any page PAGETARGET(JTARGET) located at any target second address JTARGET in the set of target second addresses {JTARGET} (e.g., one or more physical location neighboring pages {PAGENEIGHBOR(JTARGET)}), which can be collectively referred to as the physical location neighboring pages {PAGE The process generates at least one read result (e.g., one or more read results) of the physical location neighboring page {PAGENEIGHBOR(JTARGET)} to determine whether the physical location neighboring page {PAGENEIGHBOR(JTARGET)} is healthy. For example, it determines whether one or more of its error counts {ERROR_CNT} (or the number of errors {ERROR_CNT}) are below a predetermined error count threshold ERROR_CNTTHRESHOLD, and determines any unhealthy physical location neighboring page {PAGENEIGHBOR(JTARGET)} as a read interference affected page PAGERD(JTARGET), so as to preemptively process the read interference affected page PAGERD(JTARGET) before it is corrupted. For example, any unhealthy physical location neighbor page PAGENEIGHBOR(JTARGET) can be an unhealthy physical location neighbor page PAGENEIGHBOR(JTARGET) whose error count ERROR_CNT reaches (or is greater than or equal to) a predetermined error count threshold ERROR_CNTTHRESHOLD.

[0109] Flash memory controller 110 can write any local data stored in the read interference affected page PAGERD(JTARGET) to a new page at a new address in the second memory address space 201 to protect the local data and maintain the data integrity of the data in flash memory module 120. It also marks the read interference affected page PAGERD(JTARGET) as an invalid physical page, allowing it to be corrupted during further reads at any of the target second address JTARGET without compromising the data integrity of the data in flash memory module 120. For example, the new address may represent one of the plurality of physical addresses, and flash memory controller 110 can establish at least one logical-to-physical (L2P) address mapping table in flash memory module 120 to manage the relationship between multiple physical addresses and multiple logical addresses, and update the at least one L2P address mapping table to record the relationship between the new address (e.g., the physical address) and a host address (e.g., a logical address of any of the local data).

[0110] For better understanding, the symbol "JTARGET" for any of the aforementioned target second address JTARGET, and the symbol "JTARGET" in the respective symbols of page PAGETARGET (JTARGET), the physically adjacent page(JTARGET)}, any of the aforementioned unhealthy physically adjacent pages PAGENEIGHBOR (JTARGET), and the page PAGERD (JTARGET) affected by read interference, may be appended with "(1)" to indicate the physically adjacent page {PAGENEIGHBOR (JTARGET)} of page PAGETARGET (JTARGET (1)) located at any of the aforementioned target second address JTARGET (1). Any unhealthy physical location neighbor page PAGENEIGHBOR(JTARGET(1)) (or read interference-affected page PAGERD(JTARGET(1))) mentioned above in NEIGHBOR(JTARGET(1))} may have a higher error count ERROR_CNT(1) (e.g., the highest error count) among the respective error counts {ERROR_CNT} of the relevant physical location neighbor page {PAGENEIGHBOR(JTARGET)} corresponding to the second address {JTARGET} of the group of targets (e.g., the 2k addresses {J,(2j+J),…,((2j*(2k-1))+J)} determined in the reverse mapping operation 640). For example, the error count ERROR_CNT(1) may be higher than the error count {ERROR_CNT} of the physical neighboring page {PAGENEIGHBOR(JTARGET(2))} of another page PAGETARGET(JTARGET(2)) located at any other target second address {JTARGET} in the group of target second addresses {JTARGET} (e.g., the physical neighboring page {PAGENEIGHBOR(JTARGET(2))} of the 2k addresses {J,(2j+J),…,((2j*(2k-1))+J)}).

[0111] Additionally, the flash memory controller 110 can read at least one other physically adjacent page PAGENEIGHBOR(JTARGET(2)) (e.g., one or more other physically adjacent pages {PAGENEIGHBOR(JTARGET(2))}) of the other page PAGETARGET(JTARGET(2)) located in the group of target second addresses {JTARGET}, which can be collectively referred to as the other physically adjacent pages {PAGENEIGHBOR(JTARGET(2))}, to generate At least one other read result (e.g., one or more other read results) of the other physically adjacent page {PAGENEIGHBOR(JTARGET(2))} is used to determine whether the other physically adjacent page {PAGENEIGHBOR(JTARGET(2))} is healthy, and based on whether the other physically adjacent page {PAGENEIGHBOR(JTARGET(2))} is healthy, the highest read count RC(J) (e.g., the highest read count RC(J0) for the case where J = J0) is selectively reset to zero on the read count table 220. More specifically, if it is determined that the other physically adjacent page {PAGENEIGHBOR(JTARGET(2))} is healthy, for example, if its error count {ERROR_CNT} is less than a predetermined error count threshold ERROR_CNTTHRESHOLD, then the flash memory controller 110 may reset the highest read count RC(J) to zero on the read count table 220.If it is determined that the adjacent pages {PAGENEIGHBOR(JTARGET(2))} in other physical locations are unhealthy, for example, if their error count {ERROR_CNT} reaches (or is greater than or equal to) a predetermined error count threshold ERROR_CNTTHRESHOLD, the flash memory controller 110 may reduce the highest read count RC(J) to a non-zero value on the read count table 220. Instead of resetting the highest read count RC(J) to zero, the latest read count RC(J) (which has been reduced from the highest read count RC(J) to this non-zero value) can reach the first read count threshold RCTHRESHOLD again as soon as possible, so that the probability of media scanning procedure 645 occurring for at least one of the remaining target second addresses JTARGET (1) in the set of target second addresses {JTARGET} is higher than the probability of media scanning procedure 645 occurring for another set of target second addresses {JTARGET'} corresponding to another first address (e.g., any of the remaining first addresses in the plurality of first addresses, excluding the first address that detected the highest first read count RC), wherein the at least one remaining target second address JTARGET includes any other target second address JTARGET (2). For the sake of brevity, similar content in these embodiments will not be repeated here.

[0112] Figure 7 A schematic diagram of a 3D NAND flash memory involved in the method is illustrated according to an embodiment of the present invention, wherein any memory element of flash memory elements 122-1, 122-2, ... and 122-N, such as any of the aforementioned flash memory elements 122-n, can be obtained by means of... Figure 7 The invention is implemented using a 3D NAND flash memory, but is not limited thereto.

[0113] According to this embodiment, 3D NAND flash memory can contain multiple memory cells arranged in a 3D structure, such as (Nx*Ny*Nz) memory cells arranged in an Nz layer perpendicular to the Z-axis and aligned in the three directions corresponding to the X-axis, Y-axis, and Z-axis respectively: {{M(1,1,1),…,M(Nx,1,1)},{M(1,2,1),…,M(Nx,2,1)},…,{M(1,Ny,1),…,M(Nx,Ny,1)}}, {{M(1,1,2),…,M(Nx,1,2)},{M(1,2,2),…,M(Nx,2,2)},…,{M(1,Ny,2),…,M(Nx,Ny,2)}},… and {{M(1,1,Nz),…,M(Nx,1,Nz)},{M(1,2,Nz),… M(Nx,2,Nz)},…,{M(1,Ny,Nz),…,M(Nx,Ny,Nz)}} may also include multiple selection circuits for selection control, such as (Nx*Ny) upper-layer selection circuits {MBLS(1,1),…,MBLS(Nx,1)}, {MBLS(1,2),…,MBLS(Nx,2)},… and {MBLS(1,Ny),…,MBLS(Nx,Ny)} arranged in the upper layer above the Nz layer, and (Nx*Ny) lower-layer selection circuits {MSLS(1,1),…,MSLS(Nx,1)}, {MSLS(1,2),…,MSLS(Nx,2)},… and {MSLS(1,Ny),…,MSLS(Nx,Ny)} arranged in the lower layer below the Nz layer. In addition, the 3D NAND flash memory may also include multiple bit lines and multiple word lines for access control, such as Nx bit lines BL(1), ... and BL(Nx) arranged in the top layer above the upper layer, and (Ny*Nz) word lines {WL(1,1),WL(2,1),...,WL(Ny,1)}, {WL(1,2),WL(2,2),...,WL(Ny,2)}, ... and {WL(1,Nz),WL(2,Nz),...,WL(Ny,Nz)} arranged in the Nz layer. In addition, the 3D NAND flash memory may also include multiple select lines for selection control, such as Ny upper-layer select lines BLS(1), BLS(2), ... and BLS(Ny) arranged in the upper layer and Ny lower-layer select lines SLS(1), SLS(2), ... and SLS(Ny) arranged in the lower layer, and may also include multiple source lines for providing reference levels, such as Ny source lines SL(1), SL(2), ... and SL(Ny) arranged in the lower layer below the lower layer.

[0114] like Figure 7As shown, the 3D NAND flash memory can be divided along the Y-axis into Ny circuit modules PS2D(1), PS2D(2), ..., and PS2D(Ny). For ease of understanding, these circuit modules PS2D(1), PS2D(2), ..., and PS2D(Ny) can have certain electrical characteristics similar to a planar NAND flash memory containing memory cells arranged in a single layer, and therefore can be regarded as virtual two-dimensional (pseudo-2D) circuit modules, but the present invention is not limited thereto. In addition, any one of the circuit modules PS2D(1), PS2D(2), ..., and PS2D(Ny) can contain Nx secondary circuit modules S(1,ny), ..., and S(Nx,ny), where “ny” represents any integer in the interval [1,Ny]. For example, circuit module PS2D(1) may contain Nx secondary circuit modules S(1,1), ... and S(Nx,1), circuit module PS2D(2) may contain Nx secondary circuit modules S(1,2), ... and S(Nx,2), ..., circuit module PS2D(Ny) may contain Nx secondary circuit modules S(1,Ny), ... and S(Nx,Ny). In the circuit module PS2D(ny), any one of the secondary circuit modules S(1,ny), ..., S(Nx,ny) may contain Nz memory cells M(nx,ny,1), M(nx,ny,2), ..., M(nx,ny,Nz), and may contain a set of selection circuits corresponding to these memory cells M(nx,ny,1), M(nx,ny,2), ..., M(nx,ny,Nz), such as the upper-level selection circuit MBLS(nx,ny) and the lower-level selection circuit MSLS(nx,ny), where "nx" represents any integer in the interval [1,Nx]. The upper-level selection circuit MBLS(nx,ny) and the lower-level selection circuit MSLS(nx,ny), as well as the memory cells M(nx,ny,1), M(nx,ny,2), ..., M(nx,ny,Nz), can be implemented using transistors. For example, the upper-layer selection circuit MBLS(nx,ny) and the lower-layer selection circuit MSLS(nx,ny) can use ordinary transistors instead of floating gates, and any memory cell M(nx,ny,nz) among memory cells M(nx,ny,1), M(nx,ny,2), ... and M(nx,ny,Nz) can be implemented using a floating gate transistor, where “nz” represents any integer in the interval [1,Nz], but the present invention is not limited thereto.Furthermore, the upper-level selection circuits MBLS(1,ny), ... and MBLS(Nx,ny) in the circuit module PS2D(ny) can be selected according to the selection signal on the corresponding selection line BLS(ny), while the lower-level selection circuits MSLS(1,ny), ... and MSLS(Nx,ny) in the circuit module PS2D(ny) can be selected according to the selection signal on the corresponding selection line SLS(ny).

[0115] To better understand, Figure 7 The architecture shown, circuit module {PS2D(ny)|ny=1…Ny}, secondary circuit module {S(nx,ny)|nx=1…Nx,ny=1…Ny}, memory cell {M(nx,ny,nz)|nx=1…Nx,ny=1…Ny,nz=1…Nz}, and bit line {BL(Nx)|nx=1…Nx} can be respectively used as... Figure 3 Examples of the embodiments shown include any of the above-described blocks BLK, word line groups {WL0,WL1,...}, sub-blocks (or strings) {SB0,SB1,...}, memory cells {M}, and bit rows in blocks {BLK0,BLK1,...}, but the invention is not limited thereto.

[0116] Figure 8 A read interference positional relationship is illustrated according to an embodiment of the present invention. For example, the NV memory, such as flash memory module 120, may be configured as a quad-level cell (QLC) flash memory, but the invention is not limited thereto. In some examples, the level count (e.g., four for the QLC flash memory) of the memory cells (e.g., multiple QLCs) in flash memory module 120 may be varied. Figure 8As shown, the horizontal axis can be labeled with four sets of pages 810, 820, 830, and 840, indicating that each layer in the Nz layer can contain four pair pages, and that each of these four pair pages can contain four pages, including a first (1st) page, a second (2nd) page, a third (3rd) page, and a fourth (4th) page (labeled "1st", "2nd", "3rd", and "4th" for simplicity), corresponding to the fourth order of these QLCs in the flash memory module 120, respectively. Each of these QLCs can be configured to store four bits. The vertical axis can represent the word-line index (labeled "WL index" for simplicity), such as the index corresponding to the Nz layer (e.g., Nz physical stack-up layers). In addition, some pages (e.g., the pages corresponding to the interval [83,93] on the vertical axis) can be drawn with small rectangles with different types of shading to indicate the error bit counts at different levels, while other pages can be omitted for brevity.

[0117] Read interference (or read attack) can occur in layer 802 where the word line index is 88, particularly in one of the first pages 801 of each of these first paired pages (or the group of pages 810), such as the first page 811 of the first paired page in layer 802, and thus can be considered as single-page read interference. The attacked page, such as the first page 811 of the first paired page in layer 802, can be an example of page PAGETARGET(JTARGET) located at any of the aforementioned target second address JTARGET, and these physically adjacent pages of first page 811 can be examples of the physically adjacent pages {PAGENEIGHBOR(JTARGET)}. Page PAGETARGET(JTARGET), such as first page 811, does not have a large number of error bits. Conversely, one or more unhealthy physical location adjacent pages {PAGENEIGHBOR(JTARGET)}, such as the first page of the first paired page in the adjacent layer below the first page 811, the first page of the second paired page in the same adjacent layer, and the first page 821 of the second paired page in another adjacent layer, may each have a large number of error bits. The flash memory controller 110, operating according to this method, can write the local data stored in the one or more unhealthy physical location adjacent pages {PAGENEIGHBOR(JTARGET)}, such as the pages listed above, such as the first page 821, to multiple new pages at multiple new addresses in the second memory address space 201, thereby protecting the local data of these pages, such as the first page 821, and maintaining the data integrity of the data in the flash memory module 120. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0118] According to some embodiments, the order of the memory cells (e.g., the plurality of QLCs) in the flash memory module 120 (e.g., four for the QLC flash memory), the page count for each mating page, and the mating page count for each layer (e.g., four for the four sets of pages 810, 820, 830, and 840) are specified. Figure 8 The pages involved in the illustrated embodiments, the error bit counts associated with these pages, such as Figure 8The method used to present the relevant error bit count, the word line index of the layer 802 where the read interference occurred (e.g., 88), the page PAGETARGET (JTARGET) such as the first page 811, and / or the one or more unhealthy physical location neighboring pages {PAGENEIGHBOR (JTARGET)} such as the first page 821, etc., can be varied. Furthermore, the aforementioned first (1st), second (2nd), third (3rd), and fourth (4th) pages can also be referred to as lower page (LP), middle page (MP), upper page (UP), and top page (TP), respectively, and these four pages can also be referred to as four sub-blocks. For the sake of simplicity, similar content in these embodiments will not be repeated here.

[0119] Figure 9 A workflow of the method is illustrated according to an embodiment of the present invention. The aforementioned memory controller, such as flash memory controller 110, can be based on... Figure 9 The workflow shown is used to perform steps S11 to S15, but the invention is not limited thereto.

[0120] In step S11, the flash memory controller 110 may establish a read count table 220 to record the plurality of first read counts {RC} for the plurality of first addresses, wherein the plurality of first addresses may belong to a first memory address space 202 which is smaller than the second memory address space 201. For example, the plurality of first read counts {RC} may include the read counts {RC(0), RC(1), ..., RC(2j-1)} in the first memory address space 202, and the plurality of first addresses may include the 2j addresses {0, 1, ..., (2j-1)} in the first memory address space 202.

[0121] In step S12, the flash memory controller 110 may perform the hash-based address mapping on at least a subset of the plurality of second addresses, such as the group of second addresses where a read operation is detected, to convert the group of second addresses into the group of first addresses among the plurality of first addresses, so as to update the group of first read counts {RC} with respect to the group of first addresses in the plurality of first read counts {RC} on the read count table 220, wherein the group of second addresses belongs to the second memory address space 201.

[0122] In step S13, the flash memory controller 110 can monitor at least the highest first read count RC among the plurality of first read counts {RC} on the read count table 220, such as the highest read count RC(J0), to determine whether the highest first read count RC has reached the first read count threshold RCTHRESHOLD.

[0123] In step S14, in response to the highest first read count RC (e.g., highest read count RC(J0)) reaching a first read count threshold RCTHRESHOLD, the flash memory controller 110 may perform the reverse mapping of the hash-based address mapping on the first address that detects the highest first read count RC, to convert the first address into all second addresses corresponding to the first address, such as all second addresses mapped to the first address in the hash-based address mapping, as a set of target second addresses. For example, the first address may represent address J, such as address J0, and all the aforementioned second addresses corresponding to the first address may represent the 2k addresses {J,(2j+J),…,((2j*(2k-1))+J)} such as address {J0,(2j+J0),…,((2j*(2k-1))+J0)}.

[0124] In step S15, the flash memory controller 110 may perform a media scan procedure 645 for each of the target second addresses to maintain the data integrity of the data in the NV memory (e.g., flash memory module 120). For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0125] To better understand this method, it can be achieved through... Figure 9 The workflow shown is for illustrative purposes only, but the invention is not limited thereto. According to certain embodiments, Figure 9Certain steps can be added, deleted, or modified in the illustrated workflow. For example, the flash memory controller 110 can perform a media scanning procedure 645 to test the physical location neighboring pages {PAGENEIGHBOR(JTARGET)} of the page {PAGETARGET(JTARGET)} located at the group of target second addresses {JTARGET} (e.g., the 2k addresses {J,(2j+J),…,((2j*(2k-1))+J)} determined in the reverse mapping operation 640), and determine the health status of these physical location neighboring pages {PAGENEIGHBOR(JTARGET)} in advance to protect data from damage caused by read interference in the flash memory module 120, thereby maintaining data integrity. Additionally, the flash memory controller 110 can determine the error count ERROR_CNT(1) of any of the aforementioned unhealthy physical location neighboring pages {PAGENEIGHBOR(JTARGET(1))} in the page PAGETARGET(JTARGET(1)) of any of the aforementioned target second addresses JTARGET(1), and the respective error counts {ERROR_CNT(2), ERROR_CNT(3), ...} of the physical location neighboring pages {PAGENEIGHBOR(JTARGET(2)), PAGENEIGHBOR(JTARGET(3)), ...} of other pages {PAGETARGET(JTARGET(2)), PAGETARGET(JTARGET(3)), ...} in the other target second addresses {JTARGET} of the same group of target second addresses {JTARGET}, and the respective error counts {ERROR_CNT(2), ERROR_CNT(3), ...} of these physical location neighboring pages {PAGENEIGHBOR(JTARGET(2)), PAGENEIGHBOR(JTARGET(3)), ...}. For example, ERROR_CNT(1)≥ERROR_CNT(2), ERROR_CNT(2)≥ERROR_CNT(3), and so on.When the physical location of the page PAGETARGET(JTARGET(CNT_index)|CNT_index>1) located at other target second addresses JTARGET(CNT_index>1) (e.g., any of all other target second addresses {JTARGET} in this group of target second addresses {JTARGET} except for any of the aforementioned target second addresses JTARGET(1)) has an error count {ERROR_CNT(CNT_index)|CNT_index>1}, such as the page located above CNT_index=2, the error count of the page {PAGENEIGHBOR(JTARGET(CNT_index))|CNT_index>1} is greater than that of the page located above. If the error counts {ERROR_CNT(2)} of the physical location neighboring pages {PAGENEIGHBOR(JTARGET(2))} of any other page PAGETARGET(JTARGET(2)) of any other target second address JTARGET(2) are below the predetermined error count threshold ERROR_CNTTHRESHOLD, the flash memory controller 110 can confirm that these physical location neighboring pages {PAGENEIGHBOR(JTARGET(CNT_index))|CNT_index>1} such as physical location neighboring page {PAGENEIGHBOR(JTARGET(2))} are healthy, and reset the highest read count RC(J) to zero on the read count table 220.When the physical location of the page PAGETARGET(JTARGET(CNT_index)|CNT_index>1) located at other target second addresses JTARGET(CNT_index>1) (e.g., any of the other target second addresses {JTARGET} in the group of target second addresses {JTARGET} besides any of the above target second addresses JTARGET(1)) is adjacent to the page {PAGENEIGHBOR(JTARGET(CNT_index))|CNT_index>1}, any error count ERROR_CNT(CNT_index)|CNT_index>1 in the respective error count {ERROR_CNT(CNT_index)|CNT_index>1}, such as the physical location of the page PAGETARGET(JTARGET(2)) located at any of the other target second addresses JTARGET(2) mentioned above, is adjacent to the page {PAGENEIGHBOR(JTARGET(CNT_index))|CNT_index>1}, such as the physical location of the page PAGETARGET(JTARGET(2)) located at any of the other target second addresses JTARGET(2) mentioned above, for the case of CNT_index=2. If any error count ERROR_CNT(2) in the respective error counts {ERROR_CNT(2)} of the physical location neighboring pages {PAGENEIGHBOR(JTARGET(CNT_index))|CNT_index>1} reaches (or is greater than or equal to) a predetermined error count threshold ERROR_CNTTHRESHOLD, the flash memory controller 110 may determine that at least one physical location neighboring page PAGENEIGHBOR(JTARGET(CNT_index)) in the physical location neighboring pages {PAGENEIGHBOR(JTARGET(2))}, such as at least one physical location neighboring page PAGENEIGHBOR(JTARGET(2))}, is unhealthy, and reduces the highest read count RC(J) on the read count table 220 to that non-zero value, instead of resetting the highest read count RC(J) to zero. For the sake of simplicity, similar content in these embodiments will not be repeated here.

[0126] Figure 10According to an embodiment of the present invention, a read count clearing and reduction control scheme of the method is illustrated. The horizontal axis may represent the error count index CNT_index, and the vertical axis may represent the error count ERROR_CNT(CNT_index), such as the error count {ERROR_CNT(CNT_index)|CNT_index=1,2,3,…}, where the error count index CNT_index may be equal to a positive integer. For example, the error count {ERROR_CNT(CNT_index)|CNT_index=1,2,3,…} may be displayed as ERROR_CNT(1)>ERROR_CNT(2)>ERROR_CNT(3)>…, and for any of these cases, CNT_index=1, CNT_index=2, CNT_index=3, etc., an error count ERROR_CNT(CNT_index) may be displayed, but the present invention is not limited thereto. In some examples, the error count {ERROR_CNT(CNT_index)|CNT_index=1,2,3,…} can vary. In particular, it can be displayed as ERROR_CNT(1)≥ERROR_CNT(2)≥ERROR_CNT(3)≥…, and / or for any of these cases CNT_index=1, CNT_index=2, CNT_index=3, etc., one or more error counts {ERROR_CNT(CNT_index)} can be displayed.

[0127] When it is detected that an error count {ERROR_CNT} corresponding to any one of all other target second addresses {JTARGET} in the group of target second addresses {JTARGET} except any of the above target second addresses JTARGET(1) is lower than a predetermined error count threshold ERROR_CNTTHRESHOLD. For example, in the case where the respective error counts {ERROR_CNT(2)} of the physically adjacent pages {PAGENEIGHBOR(JTARGET(2))} to the other page PAGETARGET(JTARGET(2)) located at any of the above other target second addresses JTARGET(2) are lower than the predetermined error count threshold ERROR_CNTTHRESHOLD as shown in sub - figure (a), the flash memory controller 110 can confirm that these physically adjacent pages {PAGENEIGHBOR(JTARGET(2))} are healthy and reset the highest read count RC(J) to zero in the read count table 220. In this case, when it is determined that the physically adjacent pages {PAGENEIGHBOR(JTARGET(2))} are healthy based on ERROR_CNT(2) < ERROR_CNTTHRESHOLD, the flash memory controller 110 can determine that the physically adjacent pages {PAGENEIGHBOR(JTARGET(2)), PAGENEIGHBOR(JTARGET(3)),...} are healthy based on ERROR_CNTTHRESHOLD > ERROR_CNT(2) ≥ ERROR_CNT(3) ≥... and reset the highest read count RC(J) to zero in the read count table 220.When any error count ERROR_CNT in the error count {ERROR_CNT} corresponding to any of the other target second addresses {JTARGET} besides any of the aforementioned target second addresses JTARGET(1) in the group of target second addresses {JTARGET} reaches (or is greater than or equal to) a predetermined error count threshold ERROR_CNTTHRESHOLD, for example, if the physical location of another page PAGETARGET(JTARGET(2)) located at any of the other target second addresses JTARGET(2) above is adjacent to the page {PAGENEIGHBOR(JTARGET(2))}, the error count is detected. If any error count ERROR_CNT(2) in the respective error counts {ERROR_CNT(2)} of these physically adjacent pages {PAGENEIGHBOR(JTARGET(2))} reaches (or is greater than or equal to) a predetermined error count threshold ERROR_CNTTHRESHOLD as shown in either of the subgraphs (b) and (c), the flash memory controller 110 may determine that at least one physically adjacent page PAGENEIGHBOR(JTARGET(2)) in these physically adjacent pages {PAGENEIGHBOR(JTARGET(2))} is unhealthy, and reduce the highest read count RC(J) to that non-zero value on the read count table 220, instead of resetting the highest read count RC(J) to zero. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0128] According to some embodiments, a predetermined error count threshold ERROR_CNTTHRESHOLD for determining whether physically adjacent pages {PAGENEIGHBOR(JTARGET)}, such as those physical adjacent pages {PAGENEIGHBOR(JTARGET(1))}, those other physical adjacent pages {PAGENEIGHBOR(JTARGET(2))}, are healthy can correspond to Figure 1 An error correction code (ECC) circuit in the architecture shown (in) Figure 1The ECC circuitry (not shown in the text) is capable of ECC encoding and decoding to protect data and / or correct errors in any one of a plurality of sub-storage units within a physical page. This physical page can be located at one of the plurality of physical addresses, and the plurality of sub-storage units can have the same size, for example, a predetermined size smaller than the physical page, but the invention is not limited thereto. Furthermore, the ECC circuitry is capable of correcting up to ERROR_CNTMAX errors (e.g., error bits) within the physical page, and the predetermined error count threshold ERROR_CNTTHRESHOLD can be proportional to the maximum correctable error count ERROR_CNTMAX (or "maximum correctable error count ERROR_CNTMAX") of each physical page, specifically, it can be equal to the product of a predetermined coefficient / factor FACTOR and the maximum correctable error count ERROR_CNTMAX (FACTOR * ERROR_CNTMAX). For example, FACTOR = 1, but the invention is not limited thereto. In some instances, the predetermined coefficient / factor FACTOR may be equal to any other value (e.g., a value within the interval (0,1)) as long as it does not impede the implementation of the invention. For the sake of brevity, similar details in these embodiments will not be repeated here.

[0129] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A method for data integrity control of a memory device by means of hash-based address mapping for read-disturbance detection, the method being adapted to a memory controller of the memory device, the memory device including the memory controller and a non-volatile (NV) memory, the non-volatile memory including at least one non-volatile memory element, the method comprising: Establish a read count table to record multiple first read counts for multiple first addresses, wherein the multiple first addresses belong to a first memory address space that is less than a second memory address space; The hash-based address mapping is performed on a set of second addresses that detect a read operation to convert the set of second addresses into a set of first addresses among the plurality of first addresses, so as to update a set of first read counts with respect to the set of first addresses in the plurality of first read counts on the read count table, wherein the set of second addresses belongs to the second memory address space; Monitor at least one of the highest first read counts among the plurality of first read counts on the read count table to determine whether the highest first read count has reached a first read count threshold; In response to the highest first read count reaching the first read count threshold, the hash-based address mapping is reversed for a first address that detects the highest first read count, so as to convert the first address into all second addresses corresponding to the first address as a set of target second addresses; as well as A media scan procedure is performed on each of the target second addresses to maintain the data integrity of the data in the non-volatile memory.

2. The method as described in claim 1, characterized in that, The plurality of second addresses belonging to the second memory address space represent a plurality of physical addresses of the non-volatile memory that are accessible by the memory controller, wherein the plurality of second addresses include the set of second addresses.

3. The method as described in claim 1, characterized in that, The memory controller is configured to record the plurality of first read counts for the plurality of first addresses on the read count table, without needing to record the plurality of second read counts for the plurality of second addresses on any other read count table larger than the read count table.

4. The method as described in claim 3, characterized in that, The memory controller is configured to monitor at least the highest first read count among the plurality of first read counts on the read count table to determine whether the highest first read count has reached the first read count threshold, without needing to monitor any highest second read count among the plurality of second read counts on the other read count table to determine whether the highest second read count has reached any second read count threshold.

5. The method as described in claim 1, characterized in that, The conversion of this group of second addresses to the group of first addresses further includes: Use a hash function to convert the second address in the set to the first address in the set of multiple first addresses.

6. The method as described in claim 5, characterized in that, Converting the first address to all the second addresses corresponding to the first address further includes: Use a reverse hashing function to convert the first address into all the second addresses corresponding to the first address.

7. The method as described in claim 6, characterized in that, The reverse hash function is implemented as a multivalued function for performing the reverse mapping.

8. The method as described in claim 1, characterized in that, The hash-based address mapping represents a first mapping used to map any one group of inputs from the multiple groups of inputs of the first mapping to the same output among the multiple outputs of the first mapping.

9. The method as described in claim 8, characterized in that, This first mapping is implemented using a modulofunction.

10. The method as described in claim 1, characterized in that, This inverse mapping represents a second mapping that maps any one of the multiple inputs of the second mapping to the same group of outputs in the multiple groups of outputs of the second mapping.

11. The method as described in claim 1, characterized in that, The second addresses corresponding to the first address represent all the second addresses mapped to the first address in the hash-based address mapping.

12. The method as described in claim 1, characterized in that, The media scanning procedure for each of the target second addresses also includes: Read at least one physical location neighbor page of any page located at any of the target second addresses in the group of target second addresses to generate at least one read result of the at least one physical location neighbor page for determining whether the at least one physical location neighbor page is healthy; as well as Identify any unhealthy physical location neighboring page of the at least one physical location neighboring page as a read-disturbance-affected page, so as to handle the read-disturbance-affected page in advance before it is corrupted.

13. The method as described in claim 12, characterized in that, Also includes: Any local data stored in the page affected by the read interference is written to a new page located at a new second address to maintain the data integrity of the data in the non-volatile memory; as well as The page affected by the read interference is marked as an invalid physical page, allowing the page affected by the read interference to be corrupted during further reads to any target second address without compromising the data integrity of the data in the non-volatile memory.

14. The method as described in claim 13, characterized in that, The plurality of second addresses belonging to the second memory address space represent a plurality of physical addresses of the non-volatile memory, wherein the plurality of second addresses includes the group of second addresses; the new second address represents one of the plurality of physical addresses; and the method further includes: Update at least one logical-to-physical (L2P) address mapping table in the non-volatile memory to record the relationship between the physical address and a logical address of any local data.

15. The method as described in claim 12, characterized in that, Also includes: Read at least one other physically adjacent page of another page located at any other target second address in the group of target second addresses, to generate at least one other read result of the at least one other physically adjacent page, for determining whether the at least one other physically adjacent page is healthy; as well as Depending on whether the page at least one other physical location is healthy, the highest read count on the read count table is selectively reset to zero.

16. The method as described in claim 15, characterized in that, Based on whether the page at least one other physically adjacent location is healthy, the highest first read count on the read count table is selectively reset to zero, further including: If it is determined that at least one other physical location adjacent to a healthy page, then the highest first read count is reset to zero on the read count table; as well as If it is determined that the page adjacent to at least one other physical location is unhealthy, the highest first read count in the read count table is reduced to a non-zero value instead of being reset to zero. This allows the probability of performing the media scan on at least one other target second address in the set of target second addresses (excluding any of the target second addresses) to be higher than the probability of performing the media scan on another set of target second addresses corresponding to another first address, wherein the at least one other target second address includes the other target second address.

17. A memory controller for detecting read-disturbance in a memory device for data integrity control by means of hash-based address mapping, the memory device including the memory controller and a non-volatile (NV) memory, the non-volatile memory including at least one non-volatile memory element, the memory controller comprising: A processing circuit is used to control the memory controller according to a plurality of host commands from a host device, so as to allow the host device to access the non-volatile memory through the memory controller. in: The memory controller is configured to establish a read count table to record multiple first read counts for multiple first addresses, wherein the multiple first addresses belong to a first memory address space that is less than a second memory address space; The memory controller is configured to perform the hash-based address mapping on a set of second addresses that detect a read operation, to convert the set of second addresses into a set of first addresses among the plurality of first addresses, for updating a set of first read counts with respect to the set of first addresses in the read count table, wherein the set of second addresses belongs to the second memory address space; The memory controller is configured to monitor at least one of the highest first read counts among the plurality of first read counts on the read count table to determine whether the highest first read count has reached a first read count threshold; In response to the highest first read count reaching the first read count threshold, the memory controller is configured to perform the hash-based address mapping reverse mapping on a first address where the highest first read count is detected, so as to convert the first address into all second addresses corresponding to the first address as a set of target second addresses; as well as The memory controller is configured to perform a mediascan procedure for each of the target second addresses in order to maintain the data integrity of the data in the non-volatile memory.

18. A memory device comprising the memory controller of claim 17, wherein the memory device comprises: This non-volatile memory is used to store information; and The memory controller, coupled to the non-volatile memory, is used to control the operation of the memory device.

19. An electronic device comprising the memory device of claim 18, wherein the electronic device comprises: The host device is coupled to the memory device, wherein the host device includes: At least one processor is used to control the operation of the host device; and A power supply circuit, coupled to the at least one processor, is used to provide power to the at least one processor and the memory device; The memory device provides storage space to the host device.

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