Memory and method capable of relieving BTI and supporting system visible life management

Abstract

The invention relates to a memory and method capable of relieving BTI and supporting system visible life management, and belongs to the field of high-reliability computing systems and memory architectures, and the memory comprises an aging sensing SRAM array which supports dual-mode work; the aging sensing control unit is connected with the SRAM array and is used for detecting an aging state in real time and outputting a digital signal; the service life management module is connected with the aging sensing control unit and is used for receiving the digital signal and generating a configuration instruction; the reconfigurable repetitive delay unit is embedded in the SRAM array and can switch modes according to a configuration instruction; the row decoder is connected with the life management module and is used for receiving time sequence parameter adjustment; the reading circuit is connected with the SRAM array and the service life management module and is used for outputting a sensing signal; wherein the life management module dynamically configures the row decoder, the reconfigurable repetitive delay unit and the readout circuit through closed-loop feedback. According to the invention, the high-performance memory system has a memory circuit architecture with anti-aging capability.

Description

Technical Field

[0001] This invention belongs to the field of high-reliability computing systems and memory architectures, specifically relating to an anti-aging memory with a built-in aging-aware interface that supports dynamic implementation of lifespan management strategies by the system. Background Technology

[0002] With the widespread adoption of computationally intensive applications such as large language models, their inference processes heavily rely on KV cache for efficient computation. This cache is distributed across multiple storage levels, with on-chip SRAM serving as the front-end level, responsible for handling frequent, random memory accesses generated by the numerous headers and layers of the model. During long-term, continuous model servicing, the KV cache is constantly under high load cycles and the resulting high temperatures, which significantly accelerates device aging and wear. Simultaneously, as transistor sizes continue to penetrate into the deep nanoscale, the thinner gate oxide layer and enhanced electric field further exacerbate the aging effect, making reliability a primary design goal, rather than a concern only at the end of the device's lifecycle.

[0003] Among numerous aging mechanisms, bias temperature instability (BTI) is one of the main reliability failure mechanisms affecting the performance of CMOS circuits. It manifests as an increase in transistor threshold voltage and a decrease in drain current, leading to a degradation in circuit performance over time. Therefore, circuits affected by BTI exhibit significant degradation in stability and performance, a problem particularly pronounced in the high-speed SRAM level of KVcache.

[0004] Specifically, the aging and degradation of high-speed SRAM caused by BTI is mainly manifested in three aspects: 1. For SRAM memory cells, the threshold voltage degradation caused by BTI reduces its static noise margin and may trigger data flips; at the same time, the increased access time caused by BTI may lead to functional errors in read and write operations. 2. For sensitive amplifiers, the threshold voltage and drain current degradation caused by BTI can worsen the input offset voltage, potentially leading to reading errors; the increased sensing delay caused by BTI can also cause functional failures. 3. For the control logic module, the threshold voltage degradation caused by BTI will cause the delay of each part to increase in an unbalanced way, which may lead to timing errors.

[0005] These effects are further amplified in harsh environments and long-term deployment scenarios (such as edge servers with high temperatures and limited manual maintenance), thus significantly increasing the risk of system failure and maintenance costs.

[0006] In summary, when high-speed storage circuits and systems are dealing with the challenges of BTI aging, there is an urgent need for an innovative solution that can effectively mitigate aging at the circuit level and provide a precise lifespan management interface for upper-level systems. Summary of the Invention

[0007] This invention addresses the problems of inaccurate aging state observation, lack of aging state data transmission interfaces, and limited aging mitigation strategies in traditional anti-aging design memory circuits and systems. It proposes an active regulation mechanism for aging-enhancing circuits and systems, enabling high-performance memory systems to possess anti-aging capabilities. This invention significantly extends system lifespan while maintaining high memory performance, thereby achieving highly reliable and long-life memory system management capabilities. This technology is suitable for applications requiring long-term reliability under high-intensity computing environments, such as edge computing devices, autonomous driving systems, and industrial control terminals.

[0008] To achieve the above objectives, the present invention provides a memory that can alleviate BTI and support system visible lifetime management, comprising: The aging-aware SRAM array supports dual-mode operation in both conventional storage mode and aging detection mode. An aging sensing and control unit, connected to an SRAM array, is used to detect the aging status of transistors in real time and output quantized digital signals. The lifespan management module, connected to the aging sensor control unit, is used to receive digitized aging status signals and dynamically generate configuration instructions. The reconfigurable repeatable delay unit, embedded in the SRAM array, can switch between delay reference mode and normal memory mode according to configuration instructions; The line decoder, connected to the lifetime management module, is used to receive dynamic timing parameter adjustments; The readout circuit, connected to the SRAM array and lifetime management module, is used to output sensing signals; The lifespan management module dynamically configures the row decoder, reconfigurable repetitive delay unit, and readout circuit through closed-loop feedback to achieve system-level lifespan management.

[0009] Preferably, the SRAM array includes multiple 7T SRAM cells, each cell comprising: An inverter pair formed by the cross-coupling of the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, and the second NMOS transistor NM2 is used to latch data. The first access transistor and the second access transistor are controlled by word line WL and are connected to memory nodes Q and QB and bit lines BL and BLB, respectively. The fifth NMOS transistor, NM5, is controlled by the aging detection enable inverting signal ATENB and is connected in series in the feedback path of the inverter pair. It is used to cut off the DC feedback in aging detection mode.

[0010] Preferably, the SRAM array is reconstructed in aging detection mode as follows: Inverter pairs of multiple 7T SRAM cells in the same row are disconnected from feedback by the fifth NMOS transistor NM5, and cascaded to form an inverter chain under the action of the inter-column connection transistor controlled by the aging detection enable signal ATEN, so that the total delay increases monotonically with the degree of transistor aging.

[0011] Preferably, the aging sensor control unit includes: The time-to-digital converter receives the input signal ATIN and the output signal ATOUT of the inverter chain, as well as the analog waveform of the aging-sensing amplifier, for measuring delay differences. The synchronization processing circuit, including cascaded D flip-flops, is used to convert the delay difference into a multi-bit digital code stream output to the lifetime management module.

[0012] Preferably, the reconfigurable repetitive delay unit is bidirectionally connected to the aging sensor control unit: In aging detection mode, a reference delay signal is provided to the aging sensing control unit; In conventional storage mode, it participates in data storage as a normal storage cell in a row of an SRAM array.

[0013] Preferably, it further includes: An aging-sensing sensitive amplifier, sharing bit lines BL and BLB with the SRAM array, includes: The third PMOS transistor PM3 is controlled by the inverted sensor enable signal SAEB. The aging of the inverter pairs PM1 / PM2 and the fifth NMOS transistor NM5, resulting in threshold voltage shift and sensing delay degradation, is directly reflected in the output signal OUT.

[0014] Preferably, a precharge module is provided at the top of each column of the SRAM array, consisting of three PMOS transistors controlled by the precharge enable signal PRE_EN, which is used to initialize the potential of bit lines BL and BLB before each operation.

[0015] The technical solution of the present invention provides a method that can alleviate BTI and support system visible lifetime management, comprising the following steps: The circuit is powered on; The initial aging state data of each memory cell is obtained through the aging sensor control unit; Based on the system configuration, aging thresholds are set to generate end-of-life status data. The aging state of the storage circuit is periodically observed and a quantized digital signal is output. When the aging status of the storage exceeds the aging threshold, the following actions are executed according to the preset working mode preference: If a high-performance mode is preferred, the core operating voltage will be increased. If the preference is to maintain functionality and lifespan, then reconfigure the memory control module; The system continuously performs periodic observations and dynamic adjustments until it is reset or powered off.

[0016] Preferably, aging status observation is achieved through the following methods: If the SRAM cell aging condition is selected as the aging standard, then in the aging test mode, the 7T SRAM cells are reconstructed into an inverter chain, and the delay difference between the chain input ATIN and output ATOUT is measured. If the aging condition of the sensitive amplifier is selected as the aging standard, the sensitive amplifier will be reconstructed into an inverter chain in the aging detection mode, and the delay difference between the chain input ATIN and output ATOUT will be measured. Process deviations are calibrated using a reference delay signal provided by a reconfigurable repetitive delay unit; The analog delay difference is converted into a multi-bit digital code stream by a time-to-digital converter, which serves as a quantitative representation of the aging state.

[0017] Preferably, in high-performance mode, the core operating voltage is increased to 0.95V.

[0018] Compared with the prior art, the present invention has the following beneficial technical effects: This invention addresses the problems of performance degradation, inaccurate status monitoring, lack of system management interface, and limited aging mitigation strategies caused by BTI aging in high-speed SRAM during long-term operation. It proposes an anti-aging memory system architecture, which performs synergistic optimization at three levels: circuit design, aging detection mechanism, and system management, and realizes lifetime management capabilities from the underlying circuit to the system layer.

[0019] 1. Aging-enhanced underlying circuitry and sensing interface: This invention utilizes an aging-sensing amplifier with a configurable topology and a 7T SRAM cell to construct an aging sensing interface that can directly monitor the aging of core functional paths, enabling in-situ observation of the actual aging state of the memory. 2. Reconfigurable aging detection module: This invention utilizes an on-chip reconfigurable aging detection circuit based on a time-to-digital converter, combined with a replacement mechanism for faulty units due to aging, to achieve quantitative evaluation of aging effects and replacement of faulty units, providing self-repair capability and enhancing the robustness of the system. 3. System-level lifespan management strategy: This invention utilizes a system-level lifespan management strategy to achieve proactive management of the memory health status by continuously monitoring the aging state, providing early warnings of the end of the lifespan, and triggering runtime mode reconfiguration, thus ensuring continuous and correct operation even at the end of the lifespan. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall memory architecture in a memory and method that can alleviate BTI and support system visible lifetime management according to the present invention; Figure 2 This is a schematic diagram showing that the aging-sensing sensitive amplifier and 7T SRAM are configured in aging detection mode in a memory and method that can alleviate BTI and support visible lifetime management of the system according to the present invention. Figure 3 This is a schematic diagram of the aging detection module and its connection relationship with the memory array and system-level lifetime management strategy in a memory and method that can alleviate BTI and support system visible lifetime management according to the present invention. Figure 4 This is a schematic diagram of the overall process of the system-level lifetime management strategy in a memory and method that can alleviate BTI and support system visible lifetime management according to the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention discloses a memory and method that can alleviate BTI and support visible lifetime management of the system. The overall architecture of the memory achieves full-stack aging management from the underlying circuit to the system layer through multi-level collaborative design.

[0023] like Figure 1 As shown, the memory includes core components such as a row decoder, an aging-sensing SRAM array, a reconfigurable repetitive delay unit (replaceable component), an aging-sensing SA (sensitivity amplifier), an aging sensing control unit, a life management module, and a readout circuit.

[0024] The row decoder directly operates on the aging-aware SRAM array to implement conventional word line gating functions. At the same time, the row decoder itself can also be configured by the lifetime management module. Its configuration parameters can be dynamically adjusted by the lifetime management module to adapt to the system configuration working mode after memory aging, ensuring that the overall functional correctness can still be maintained through working parameter optimization after device performance degradation.

[0025] As a component of the aging-aware SRAM array, the reconfigurable repetitive delay unit can dynamically switch its function according to system requirements. When the unit serves the aging sensing control unit, it acts as a repetitive delay unit to provide an accurate delay reference. When the unit is released by the aging sensing control unit, it becomes a normal storage unit in the aging-aware SRAM array and participates in data storage. This reconfigurable feature enables the system to achieve flexible reuse of delay calibration and storage capacity without increasing additional hardware overhead.

[0026] The aging sensing and control unit plays a crucial translation role between the aging sensing SRAM array and the life management module. This unit can detect the aging status of the SRAM array in real time and quantify the aging degree into a digital output, which is then transmitted to the life management module for subsequent decision processing. This analog-to-digital conversion mechanism provides a standardized aging status interface for the system layer.

[0027] The aging-sensing SRAM array employs a 7T SRAM cell structure to support dual-mode operation in both conventional storage and aging detection modes. For example... Figure 2 As shown, the main body consists of a row of SRAM memory cells in an n-column SRAM array and the SA sensing units equipped in each column of the array. Each column of SRAM memory cells and SA sensing units share BL and BLB. At the top of each column, a PRE_EN signal controls three PMOS transistors to pre-charge BL and BLB. NMOS transistors controlled by an ATEN signal are added between each column to implement the aging detection mode. Figure 2 The circuit diagram shown is configured for aging detection mode. The red cross indicates that the transistor is in the off state. At this time, the inverter in the selected SRAM memory cell is cut off by NM5 controlled by the ATENB signal. Under the action of NMOS controlled by ATEN, it is connected with other cells in the same row to form an inverter chain.

[0028] Each SRAM memory cell is composed of memory nodes Q and QB formed by inverter pairs. A pair of PMOS transistors PM1 and PM2 and a pair of NMOS transistors NM1 and NM2 are cross-coupled to form a data latch structure. In normal operating mode, the word line WL controls the conduction state of the access transistors. When WL is enabled, the access transistors connect memory nodes Q and QB to the bit line BL and complementary bit line BLB, respectively, enabling data read and write operations. Compared to the traditional 6T cell, this 7T cell adds an NM5 transistor controlled by the ATENB signal. This transistor plays a crucial role in aging detection mode. By cutting off the direct feedback path of the inverter pairs and cooperating with the inter-column connection NMOS transistor controlled by the ATEN signal, multiple SRAM cells in the same row can be cascaded to form an inverter chain structure, thereby converting the aging characteristics of the memory cells into measurable delay degradation. Each column in the array is equipped with a pre-charge module at the top. This module consists of three PMOS transistors controlled by the PRE_EN signal, connected to the bit line BL and the complementary bit line BLB. Before each read / write operation, the bit line pairs are pre-charged to ensure that the initial potential of the bit lines is in a defined state.

[0029] The aging-sensing SRAM array is enhanced to mitigate the BTI aging effect, directly incorporating the aging degradation of its input offset voltage and sensing delay into the monitoring range. This sensitive amplifier shares bit lines BL and BLB with the SRAM cells in the same column and includes core components such as a PM3 transistor (controlled by SAEB), an inverter pair (PM1 / PM2), and an NM5 transistor (controlled by ATENB). The output terminal OUT is connected to the subsequent readout circuitry to output the sensing signal. In aging detection mode, the sensitive amplifier's operating state is reconfigured, and the aging characteristics of its internal transistors are reflected in the output signal through delay variations or threshold shifts. The aging-sensing sensitive amplifier proposed in this invention achieves a sensitive amplifier performance index of 29.5 on TSMC's 28nm process. This performance index is defined as: 100 / {sensing delay offset value when SA is aged to 20 years × sensing delay in the initial state before aging × threshold voltage offset value of the worst transistor when SA is aged to 20 years}. This performance index (custom FoM value, Figure of Merit) intuitively reflects the comprehensive performance retention capability of the sensitive amplifier during the aging process, and improves the module life by more than 20 times compared with the existing technology.

[0030] When the memory is configured for aging detection mode, the entire array's topology undergoes a systematic restructuring. For example... Figure 2As shown, in aging detection mode, the transistors marked with a red cross are in the off state. At this time, the inverter pair in the selected row of SRAM memory cells has its DC feedback path cut off through the NM5 transistor. Simultaneously, the inter-column NMOS transistor controlled by the ATEN signal is turned on, connecting multiple SRAM cells in the same row via an inverter chain, forming a signal transmission path that runs through the entire row. Specifically, the output of each SRAM cell serves as the input to the next stage cell, cascading to form a long inverter chain. The input signal is injected at the head of the chain, accumulates the delay of all inverters in the chain, and is output from the tail of the chain. The total delay of this inverter chain directly reflects the aging state of all transistors in the chain. Because the threshold voltage increase caused by the BTI effect linearly increases the switching delay of each inverter, the delay of the entire inverter chain monotonically increases over time. The sensitive amplifier in each column is also included in this inverter chain, and its aging characteristics are also reflected through delay changes. The pre-charge module is still responsible for pre-charging the bit line pairs in this mode, but the charging frequency and timing may be dynamically adjusted by the aging sensing control unit according to detection requirements.

[0031] From the perspective of aging detection and lifespan management, memory macrocells provide SRAM aging tags, SA aging tags, and repetitive delay units. The aging detection module receives analog waveform signals from the aging tags, converts them into digital quantized outputs, and provides them to the lifespan management module in the memory lifespan management strategy. The memory lifespan management strategy compares the output of the aging detection module with the system-set aging threshold. When the memory circuit is detected to have reached the aging threshold, the memory lifespan management strategy configures and adjusts modules such as the decoder of the memory circuit according to the system's set operating state preferences to maintain a high-performance mode or ensure correct function and extend lifespan.

[0032] The aging detection module receives analog waveform signals from the ATIN input and ATOUT output of the SRAM aging tag, or similar analog waveform signals from the SA aging tag. All analog signals undergo precise time interval measurement. A reconfigurable repetitive delay unit is bidirectionally connected to the aging detection module, providing a reference delay signal and receiving excitation signals from the aging tags. This bidirectional interaction mechanism enables the system to calibrate process deviations and extract pure aging-related delay increments. After converting the measured delay difference into a digital quantized value, it is synchronized and pipelined through a series of cascaded D flip-flops. Each D flip-flop has a delay T0 to ensure signal integrity. All D flip-flops share the system clock, and the output signals are cascaded sequentially to form a multi-bit digital code stream transmitted to the lifetime management module. The memory lifetime management strategy compares and analyzes the preset aging threshold in the system configuration with the digital output of the aging detection module. When the aging state of the memory circuit is detected to have reached the lifetime threshold, the memory lifetime management strategy immediately initiates corresponding reconfiguration or voltage adjustment operations. The specific execution strategy depends on the operating state preferences set in the system configuration.

[0033] The lifespan management module continuously receives digitally quantized aging data from the aging sensor control unit and periodically compares it with the aging threshold stored in the configuration register. When the aging status data of any bank exceeds the preset lifespan end-of-life status data, the lifespan management module triggers an early warning mechanism and initiates a runtime operating mode reconfiguration process. The system provides two basic operating mode preference options: high-performance mode and maintenance function and lifespan mode. In high-performance mode, the lifespan management module issues a command to the power management unit to increase the core operating voltage from the nominal value of 0.9V to 0.95V, compensating for performance loss caused by aging through voltage overdrive and ensuring that the memory maintains a high operating frequency of over 1.47GHz. In maintenance function and lifespan mode, the lifespan management module prioritizes reconfiguring the memory control module, extending the system lifespan by adjusting timing parameters, reducing access frequency, and enabling redundant cell replacement. In this mode, the voltage remains at the nominal value to control power consumption and further aging rate. The control signals of the lifespan management module simultaneously act on the row decoder, the reconfigurable repetitive delay unit, and the readout circuit, realizing comprehensive dynamic configuration control of the memory macrocells.

[0034] The specific circuit module that executes is Figure 4The leftmost blue section, labeled "Involved Circuit Modules," indicates that the arrow pointing to this circuit means it is configured and controlled by the memory lifetime management strategy. The arrow pointing from this circuit to the green box in the flowchart indicates that this circuit is responsible for outputting the aging state mentioned in the green box. All conditional statements (white diamonds) in the flowchart are implemented by the memory lifetime management strategy. The strategy only performs reconfiguration or voltage adjustment operations when it detects that the memory circuit has reached the aging threshold. Whether it performs a reconfiguration of the control module or adjusts the voltage to enter high-performance mode is determined by the system configuration. The voltage adjustment range in high-performance mode is from the standard operating voltage of 0.9V to 0.95V.

[0035] Figure 4 The specific process starts with "powering on the circuit" and proceeds in the following steps: After the circuit is powered on, the initial state of each BANK is obtained through the aging detection module, and "initial state data (each BANK)" is generated. Based on the system configuration, set an acceptable aging threshold and generate "end-of-life status data (per bank)"; The aging detection module periodically observes the aging status of the storage circuit; Memory lifetime management strategies determine whether the current aging state has reached the lifetime threshold: If “No”: Return to the periodic aging observation steps and continue monitoring; If "yes": Proceed to the next step; Depending on the system configuration, select either "High Performance Mode" or "Maintain Functionality and Lifespan": If "High Performance Mode" is selected: the module is adjusted to a higher operating voltage to control the memory macrocells; If "Maintain Functionality and Lifespan" is selected: "Reconfigure Memory Control Module" is triggered, which controls the memory macrocells to maintain functionality and extend lifespan, and then returns a value to periodically observe the aging status step.

[0036] This invention is physically implemented using TSMC's 28nm process. The core array is 64Kb, containing four banks, each with an array size of 128×128 bits, and a core operating voltage of 0.9V. Verified through ten years of simulation, the proposed anti-aging memory solution achieves a maximum operating frequency of 1.47GHz. This performance improvement is primarily attributed to the latency optimization characteristics inherent in the aging-aware SRAM and SA structure. Compared to existing system-level designs, this invention achieves over 3.9 times the system lifetime improvement. This significant effect stems from the proactive intervention and dynamic optimization of the aging process through memory lifetime management strategies. The aging-aware sensitive amplifier's performance index of 29.5 indicates that even under extreme conditions of aging to 20 years, the product of its sensing latency offset and threshold voltage offset remains extremely low, ensuring long-term operational reliability. The reconfigurable repeatable delay unit design allows for a flexible balance between aging detection accuracy and storage capacity, while the standardized digital interface provided by the aging sensing control unit reduces the complexity of system-level aging management.

[0037] This invention is particularly suitable for application scenarios that require long-term reliability under high-intensity computing environments, such as edge computing devices, autonomous driving systems, and industrial control terminals. Through the built-in aging perception and active adjustment mechanism, it significantly reduces the risk of system failure and manual maintenance costs under harsh environments, and achieves comprehensive reliability enhancement from the underlying circuit to the system architecture.

[0038] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A memory that can alleviate BTI and support system-visible lifetime management, characterized in that, include: The aging-aware SRAM array supports dual-mode operation in both conventional storage mode and aging detection mode. An aging sensing and control unit, connected to an SRAM array, is used to detect the aging status of transistors in real time and output quantized digital signals. The lifespan management module, connected to the aging sensor control unit, is used to receive digital signals and dynamically generate configuration commands. The reconfigurable repeatable delay unit, embedded in the SRAM array, can switch between delay reference mode and normal memory mode according to configuration instructions; The line decoder, connected to the lifetime management module, is used to receive dynamic timing parameter adjustments; The readout circuit, connected to the SRAM array and lifetime management module, is used to output sensing signals; The lifespan management module dynamically configures the row decoder, reconfigurable repetitive delay unit, and readout circuit through closed-loop feedback to achieve system-level lifespan management.

2. A memory that can alleviate BTI and support system-visible lifetime management according to claim 1, characterized in that, The SRAM array comprises multiple 7T SRAM cells, each cell including: An inverter pair formed by the cross-coupling of the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, and the second NMOS transistor NM2 is used to latch data. The first access transistor and the second access transistor are controlled by word line WL and are connected to memory nodes Q and QB and bit lines BL and BLB, respectively. The fifth NMOS transistor, NM5, is controlled by the aging detection enable inverting signal ATENB and is connected in series in the feedback path of the inverter pair. It is used to cut off the DC feedback in aging detection mode.

3. A memory that can alleviate BTI and support system-visible lifetime management according to claim 2, characterized in that, The SRAM array was reconstructed in aging detection mode as follows: Inverter pairs of multiple 7T SRAM cells in the same row are disconnected from feedback by the fifth NMOS transistor NM5, and cascaded to form an inverter chain under the action of the inter-column connection transistor controlled by the aging detection enable signal ATEN, so that the total delay increases monotonically with the degree of transistor aging.

4. A memory that can alleviate BTI and support system-visible lifetime management according to claim 3, characterized in that, The aging sensor control unit includes: The time-to-digital converter receives the input signal ATIN and the output signal ATOUT of the inverter chain, as well as the analog waveform of the aging-sensing amplifier, for measuring delay differences. The synchronization processing circuit, including cascaded D flip-flops, is used to convert the delay difference into a multi-bit digital code stream output to the lifetime management module.

5. A memory that can alleviate BTI and support system-visible lifetime management according to claim 1, characterized in that, The reconfigurable repetitive delay unit is bidirectionally connected to the aging sensor control unit. In aging detection mode, a reference delay signal is provided to the aging sensing control unit; In conventional storage mode, it participates in data storage as a normal storage cell in a row of an SRAM array.

6. A memory and method for mitigating BTI and supporting visible lifespan management according to claim 1, characterized in that, Further includes: An aging-sensing sensitive amplifier, sharing bit lines BL and BLB with the SRAM array, includes: The third PMOS transistor PM3 is controlled by the inverted sensor enable signal SAEB. The aging of the inverter pairs PM1 / PM2 and the fifth NMOS transistor NM5, resulting in threshold voltage shift and sensing delay degradation, is directly reflected in the output signal OUT.

7. A memory that can alleviate BTI and support system-visible lifetime management according to claim 1, characterized in that, Each column of the SRAM array has a precharge module at the top, consisting of three PMOS transistors controlled by the precharge enable signal PRE_EN, which is used to initialize the potential of bit lines BL and BLB before each operation.

8. A method for using a memory according to any one of claims 1-7 that can alleviate BTI and support system visible lifetime management, characterized in that, Includes the following steps: The circuit is powered on; The initial aging state data of each memory cell is obtained through the aging sensor control unit; Based on the system configuration, aging thresholds are set to generate end-of-life status data. The aging state of the storage circuit is periodically observed and a quantized digital signal is output. When the aging status of the storage exceeds the aging threshold, the following actions are executed according to the preset working mode preference: If a high-performance mode is preferred, the core operating voltage will be increased. If the preference is to maintain functionality and lifespan, then reconfigure the memory control module; The system continuously performs periodic observations and dynamic adjustments until it is reset or powered off.

9. A method for mitigating BTI and supporting visible lifespan management according to claim 8, characterized in that, Aging status observation is achieved through the following methods: If the SRAM cell aging condition is selected as the aging standard, then in the aging test mode, the 7T SRAM cells are reconstructed into an inverter chain, and the delay difference between the chain input ATIN and output ATOUT is measured. If the aging condition of the sensitive amplifier is selected as the aging standard, the sensitive amplifier will be reconstructed into an inverter chain in the aging detection mode, and the delay difference between the chain input ATIN and output ATOUT will be measured. Process deviations are calibrated using a reference delay signal provided by a reconfigurable repetitive delay unit; The analog delay difference is converted into a multi-bit digital code stream by a time-to-digital converter, which serves as a quantitative representation of the aging state.

10. A method for mitigating BTI and supporting visible lifespan management according to claim 8, characterized in that, In high-performance mode, the core operating voltage is increased to 0.95V.

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