Address mapping method and device based on DDR interleaving, equipment and storage medium

Abstract

The application discloses a DDR interlacing-based address mapping method and device, equipment and a storage medium, and relates to the field of computer storage. The method comprises the following steps: sequentially mapping the interlacing bits of a basic address block by a lookup table to obtain a target mapping address; calculating the relative offset of different basic address blocks in the same DDR according to the distribution quantity of the sub-address blocks of the basic address block in the DDR channel y before interlacing and the sequence number of the basic address block; determining the adaptive offset between different DDR channels based on the sub-address block quantity of all DDR channels before the DDR channel y in interlacing which is mapped to the sub-address block of the DDR channel x after interlacing; and generating the target address corresponding to the address after interlacing based on the top_addr_bit, the target mapping address, the relative offset, the adaptive offset and the target address bit corresponding to the interlacing granularity, so that the addresses of the DDR after interlacing are sequentially arranged, thereby improving the read-write performance of the DDR.

Description

Technical Field

[0001] This application relates to the field of computer storage technology, specifically to an address mapping method, apparatus, device, and storage medium based on DDR interleaving. Background Technology

[0002] In high-performance computing systems, multi-channel DDR (Double Data Rate SDRAM) memory architectures are typically used to improve memory bandwidth. The CMN (Coherent Mesh Network) bus, provided by ARM, is used to achieve cache coherency in multiprocessor systems. It supports various DDR interleaving modes, including 3DDR and 6DDR interleaving. It's important to note that when using 3DDR or 6DDR interleaving modes, the top address bit (the most significant bit segment in the physical address) of the interleaved address is removed to ensure that addresses interleaved to different DDRs cover a contiguous address space.

[0003] In related technologies, for the CMN bus, the interleaving formula for the 3DDR interleaving mode is: SN={ADDR[k+2:k]+ADDR[k+5:k+3]+ADDR[k+8:k+6]+((top_addr_bit1<<1)|top_addr_bit0)}%3, and the formula for the 6DDR interleaving mode is: SN={ADDR[k+2:k]+ADDR[k+5:k+3]+ADDR[k+8:k+6]+((top_addr_bit2<<2)|(top_addr_bit1<<1)|top_addr_bit0)}%6 In the formula, SN is the calculation result of the interleaving channel, representing the specific DDR channel number to which the address should be mapped; ADDR is the system address before interleaving (for example, if the system address is 40 bits, then ADDR represents the 40-bit address before interleaving); top_addr_bit0, top_addr_bit1, and top_addr_bit2 are bits selected for interleaving calculation based on the DDR chip size (i.e., DDR capacity) and address allocation, with the aim of ensuring that the addresses interleaved to each DDR can be evenly distributed. The selection rules for top_addr_bit0-2 can be found in the CMN user manual; the value of k is determined by the interleaving granularity.

[0004] While the interleaving method described above allows interleaved addresses to cover a contiguous address space, it doesn't guarantee that the addresses are sequentially arranged. In certain application scenarios, this non-sequential address arrangement can prevent the DDR controller from fully utilizing burst transfer characteristics, thus failing to achieve the optimal bandwidth of DDR; for example, see... Figure 1 As shown, in 6DDR interleaving mode, the first 512 addresses interleaved to DDR0 are arranged in a non-contiguous and non-sequential manner, which reduces memory access efficiency. Summary of the Invention

[0005] This application provides an address mapping method, apparatus, device, and storage medium based on DDR interleaving, which can solve the problem in the prior art that the interleaved addresses cannot be arranged in order.

[0006] In a first aspect, embodiments of this application provide an address mapping method based on DDR interleaving, the address mapping method based on DDR interleaving including:

[0007] The interleaved bits of the base address block within the interleaved address are sequentially mapped using a lookup table to obtain the target mapped address within the base address block. The original values ​​of the interleaved bits are non-linearly distributed, and the table is used to store the one-to-one correspondence between all possible values ​​of the interleaved bits and consecutive sequential addresses.

[0008] The relative offset of different basic address blocks within the same DDR is calculated based on the number of basic address blocks interleaved from the basic address blocks in DDR channel y before interleaving to the sub-address blocks in DDR channel x after interleaving, and the sequence number of the basic address blocks.

[0009] The adaptive offset between different DDR channels is determined based on the number of sub-address blocks that are mapped from all DDR channels before the pre-interleaving DDR channel y to the post-interleaving DDR channel x.

[0010] The target address corresponding to the interleaved address is generated based on the top_addr_bit used to calculate the interleaving, the target mapping address, the relative offset, the adaptive offset, and the target address bit corresponding to the interleaving granularity.

[0011] In conjunction with the first aspect, in one implementation, generating a target address corresponding to the interleaved address based on the bits used for calculating interleaving (top_addr_bit), the target mapping address, the relative offset, the adaptive offset, and the target address bits corresponding to the interleaving granularity includes:

[0012] The processed address is obtained based on the target mapping address, the relative offset, and the adaptive offset;

[0013] Set top_addr_bit to 0 and combine it with the processed address and the target address bit to obtain the target address corresponding to the interleaved address.

[0014] In conjunction with the first aspect, in one implementation, the expression for calculating the processed address is:

[0015] ADDR_OUT(x)=ADDR_LUT+block_offset(y,x)+SN_offset(y,x)

[0016] In the formula, ADDR_OUT(x) represents the processed address in DDR channel x after interleaving; ADDR_LUT represents the target mapping address; (y,x) means that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x; block_offset(y,x) represents the relative offset; and SN_offset(y,x) represents the adaptive offset.

[0017] In conjunction with the first aspect, in one implementation, the expression for calculating the relative offset block_offset(y,x) is:

[0018] block_offset(y,x)=K×const(y,x)

[0019] In the formula, (y,x) indicates that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x, const(y,x) indicates the number of basic address blocks in DDR channel y before interleaving interleaved into sub-address blocks in DDR channel x after interleaving, and K represents the sequence number of the basic address blocks.

[0020] In conjunction with the first aspect, in one implementation, the adaptive offset SN_offset(y,x) is calculated as follows:

[0021]

[0022]

[0023] In the formula, (y,x) represents the address before interleaving belonging to the address space of DDR channel y and the address after interleaving belonging to the address space of DDR channel x, const(y,x) represents the number of basic address blocks in DDR channel y before interleaving interleaved into sub-address blocks in DDR channel x after interleaving, S represents the granularity of DDR, and the value of k is determined by the interleaving granularity.

[0024] Secondly, embodiments of this application provide an address mapping device based on DDR interleaving, the address mapping device based on DDR interleaving includes:

[0025] The first processing module is used to perform sequential mapping operations on the interleaved bits of the basic address block within the interleaved address through a lookup table to obtain the target mapped address within the basic address block. The original values ​​of the interleaved bits are non-linearly distributed, and the table is used to store the one-to-one correspondence between all possible values ​​of the interleaved bits and consecutive sequential addresses.

[0026] The second processing module is used to calculate the relative offset of different basic address blocks in the same DDR based on the number of basic address blocks in DDR channel y before interleaving and the number of sub-address blocks in DDR channel x after interleaving, and the sequence number of the basic address blocks.

[0027] The third processing module is used to determine the adaptive offset between different DDR channels based on the number of sub-address blocks that map all DDR channels before the pre-interleaving DDR channel y to the post-interleaving DDR channel x.

[0028] The address mapping module is used to generate a target address corresponding to the interleaved address based on the top_addr_bit used to calculate the interleaving, the target mapping address, the relative offset, the adaptive offset, and the target address bit corresponding to the interleaving granularity.

[0029] In conjunction with the second aspect, in one implementation, the address mapping module is specifically used for:

[0030] The processed address is obtained based on the target mapping address, the relative offset, and the adaptive offset;

[0031] Set top_addr_bit to 0 and combine it with the processed address and the target address bit to obtain the target address corresponding to the interleaved address.

[0032] In conjunction with the second aspect, in one implementation, the expression for calculating the processed address is:

[0033] ADDR_OUT(x)=ADDR_LUT+block_offset(y,x)+SN_offset(y,x)

[0034] In the formula, ADDR_OUT(x) represents the processed address in DDR channel x after interleaving; ADDR_LUT represents the target mapping address; (y,x) means that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x; block_offset(y,x) represents the relative offset; and SN_offset(y,x) represents the adaptive offset.

[0035] In conjunction with the second aspect, in one implementation, the expression for calculating the relative offset block_offset(y,x) is:

[0036] block_offset(y,x)=K×const(y,x)

[0037] In the formula, (y,x) indicates that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x, const(y,x) indicates the number of basic address blocks in DDR channel y before interleaving interleaved into sub-address blocks in DDR channel x after interleaving, and K represents the sequence number of the basic address blocks.

[0038] In conjunction with the second aspect, in one implementation, the adaptive offset SN_offset(y,x) is calculated as follows:

[0039]

[0040]

[0041] In the formula, (y,x) represents the address before interleaving belonging to the address space of DDR channel y and the address after interleaving belonging to the address space of DDR channel x, const(y,x) represents the number of basic address blocks in DDR channel y before interleaving interleaved into sub-address blocks in DDR channel x after interleaving, S represents the granularity of DDR, and the value of k is determined by the interleaving granularity.

[0042] Thirdly, embodiments of this application provide a DDR interleaving-based address mapping device, the DDR interleaving-based address mapping device including a processor, a memory, and a DDR interleaving-based address mapping program stored in the memory and executable by the processor, wherein when the DDR interleaving-based address mapping program is executed by the processor, it implements the steps of the aforementioned DDR interleaving-based address mapping method.

[0043] Fourthly, embodiments of this application provide a computer-readable storage medium storing a DDR-interleaved address mapping program, wherein when the DDR-interleaved address mapping program is executed by a processor, it implements the steps of the aforementioned DDR-interleaved address mapping method.

[0044] The beneficial effects of the technical solutions provided in this application include:

[0045] The target mapping address within the basic address block is obtained by sequentially mapping the interleaving bits of the basic address block within the interleaved address using a lookup table, thus achieving sequential mapping of sub-address blocks within the basic address block. Then, based on the number of sub-address blocks interleaved from the basic address block in DDR channel y before interleaving to the sub-address block in DDR channel x after interleaving, and the sequence number of the basic address block, the relative offset between different basic address blocks within the same DDR is calculated, achieving sequential mapping between different basic address blocks within the same DDR. Next, based on the number of sub-address blocks mapped from all DDR channels preceding DDR channel y before interleaving to DDR channel x after interleaving, an adaptive offset between different DDR channels is determined, achieving sequential mapping between different DDRs. Finally, based on top_addr_bit, target mapping address, relative offset, adaptive offset, and the target address bit corresponding to the interleaving granularity, the target address corresponding to the interleaved address is output, ensuring that the addresses originally input sequentially remain sequentially arranged in each DDR after interleaving, thereby improving DDR read / write performance. Attached Figure Description

[0046] Figure 1 This is a schematic diagram illustrating the ordering of the first 512 addresses interleaved to DDR0 in the existing 6DDR mode.

[0047] Figure 2 This is a schematic diagram of the structure corresponding to a 40-bit system address in the prior art.

[0048] Figure 3 This is a flowchart illustrating an embodiment of the DDR interleaving-based address mapping method of this application;

[0049] Figure 4 This is a schematic diagram of the structure corresponding to a 40-bit system address in this embodiment.

[0050] Figure 5 This is a schematic diagram showing the possible values ​​of the distribution quantity in the 6DDR mode involved in this embodiment.

[0051] Figure 6 This is a schematic diagram showing the sorting of the first 512 addresses interleaved to DDR0 in 6DDR mode, as described in the embodiments of this application.

[0052] Figure 7 This is a schematic diagram of the hardware structure of the address mapping device based on DDR interleaving involved in the embodiments of this application. Detailed Implementation

[0053] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0054] First, some of the technical terms used in this application will be explained to help those skilled in the art understand this application.

[0055] DDR: Double Data Rate Synchronous Dynamic Random Access Memory, which is the address mapping target carrier of this application.

[0056] LUT: Lookup table, which is used to implement the address order mapping within the basic address block in this application.

[0057] Interleave Granularity: Determines the smallest unit of address block interleaving in DDR. Its specific value can be determined according to actual needs; for example, the interleave granularity can be set to 256 bits, 1KB, 4KB, etc.; see also Figure 2 As shown, the address bits corresponding to the interleaving granularity Interleave are ADDR[k-1:0], where k is a positive integer and its value is determined according to the interleaving granularity (as shown in Table 1), i.e., 2. k =Interleave.

[0058] Table 1. Correspondence between interlacing particle size and k

[0059]

[0060] It should be noted that Table 1 is only a presentation of an example, and the contents of Table 1 can be adapted to meet actual needs.

[0061] Sub-address block: The address block corresponding to the interleaving granularity size.

[0062] Interleave bit: see Figure 2 As shown, it refers to 9 consecutive address bits of ADDR[k+8:k], with each address bit serving as an index of a sub-address block. That is, each index corresponds to an address block of interleaving granularity.

[0063] Basic address block: an address block unit jointly divided by ADDR[k+8:k] and ADDR[k-1:0].

[0064] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0065] In a first aspect, embodiments of this application provide an address mapping method based on DDR interleaving.

[0066] In one embodiment, reference is made to Figure 3 , Figure 3 This is a flowchart illustrating an embodiment of the DDR interleaving-based address mapping method of this application. Figure 3 As shown, the address mapping method based on DDR interleaving includes:

[0067] Step S10: Perform sequential mapping operation on the interleaved bits of the basic address block within the interleaved address using a lookup table to obtain the target mapped address within the basic address block. The original values ​​of the interleaved bits are non-linearly distributed, and the table is used to store the one-to-one correspondence between all possible values ​​of the interleaved bits and consecutive sequential addresses.

[0068] It should be noted that this embodiment provides a mapping method for interleaved addresses, without changing the original interleaving method. It is applicable to an n-way DDR interleaving architecture and the DDR channels are sequentially 0 to n-1, such as n=3 or 6. Since the address mapping logic and principle of each interleaved DDR channel are the same, for the sake of simplicity, the following embodiments will only use one interleaved DDR channel x as an example to describe the address mapping.

[0069] It is worth noting that since the CMN interleaving formula is a non-linear calculation, it is not possible to simply reverse it to arrange the interleaved addresses in order. Therefore, this embodiment will perform sequential mapping on the sub-address blocks within the basic address block that are mapped to the same DDR space. Specifically, it is preferable to use a lookup table (LUT) to complete the sequential mapping within the basic address block.

[0070] Specifically, for the basic address blocks within the interleaved address, see [link to relevant documentation]. Figure 4As shown, firstly, the interleaved bits ADDR[k+8:k] in the basic address block are extracted. These 9 bits are the core identifier of the basic address block, and their original values ​​(i.e., all possible values ​​from 0 to 511) are non-linearly distributed, corresponding to the out-of-order address basis in the prior art. Then, these 9 interleaved bits are input into a pre-configured lookup table LUT to perform a sequential mapping operation, thereby obtaining the continuous target mapping address ADDR_LUT within the basic address block, i.e., ADDR_LUT=F(ADDR[k+8:k]), where F represents the sequential mapping operation of the interleaved bit lookup table. The LUT lookup table pre-stores a one-to-one correspondence between all possible values ​​of ADDR[k+8:k] and consecutive sequential addresses. For example, the LUT lookup table stores a one-to-one correspondence between the original out-of-order values ​​0x00 and 0x01 of ADDR[k+8:k] and sequential addresses 0 and 1, respectively. If the original out-of-order value of ADDR[k+8:k] is 0x00, then after looking up the LUT, sequential address 0 can be used as ADDR_LUT, thereby realizing the mapping of interleaved bits from out-of-order to sequential.

[0071] Step S20: Calculate the relative offset of different basic address blocks within the same DDR based on the number of basic address blocks interleaved from the DDR channel y before interleaving to the sub-address blocks in the DDR channel x after interleaving and the sequence number of the basic address blocks.

[0072] As an example, in this embodiment, after the sub-address block sequential mapping is completed, sequential mapping processing is also required between the base address blocks within each DDR space, that is, to achieve sequential processing between different base address blocks within the same DDR. See [link to documentation]. Figure 4 As shown, the number of sub-address blocks distributed across different DDR spaces by the basic address block is pre-calculated using top_addr_bit and interleaving bits ADDR[k+8:k], where (y,x) indicates that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x. In 3DDR interleaving mode, the value of const(y,x) is 170 or 171, while in 6DDR interleaving mode, it is... Figure 5The values ​​of `const(y,x)` in 84, 85, and 87 are determined based on the combination of the DDR channel `y` before interleaving and the DDR channel `x` after interleaving. It should be noted that `top_addr_bit` refers to the bits selected for interleaving calculation based on the size and address allocation of the DDR chips. When the number of DDR chips, n=3, it includes `top_addr_bit0` and `top_addr_bit1`; when n=6, it includes `top_addr_bit0`, `top_addr_bit1`, and `top_addr_bit2`. Specifically, based on the interleaving formula for 3DDR or 6DDR, the channel number `SN` after interleaving the original addresses 0-512 can be calculated. By counting the number of `SN` values ​​corresponding to different `x` and `y` values, the number of sub-address block distributions `const(y,x)` can be obtained.

[0073] Based on this, see Figure 5 As shown, when the DDR channel number y=0 before interleaving and the DDR channel number x=0 after interleaving, const(0,0)=85; then, based on const(0,0)=85 and the corresponding basic address block sequence number K, the relative offset of different basic address blocks within the same DDR is calculated to achieve sequential mapping between different basic address blocks within the same DDR.

[0074] Furthermore, in one embodiment, the calculation expression for the relative offset block_offset(y,x) is:

[0075] block_offset(y,x)=K×const(y,x)

[0076] In the formula, (y,x) indicates that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x, const(y,x) indicates the number of basic address blocks in DDR channel y before interleaving interleaved into sub-address blocks in DDR channel x after interleaving, and K represents the sequence number of the basic address blocks.

[0077] As an example, in this embodiment, the sequence number K of the current basic address block is obtained, K∈[0,2]. N -1], N is determined by the DDR chip size S, and S is a positive integer power of 2, i.e. ; and through Figure 5The value of const(y,x) is determined, and then the sequence number K is multiplied by const(y,x) to obtain the relative offset block_offset(y,x) between basic address blocks mapped to the same DDR, i.e., block_offset(y,x) = K × const(y,x). It can be seen that this embodiment ensures the sequential arrangement of different basic address blocks within the same DDR by mapping different basic address blocks of the same DDR channel y before interleaving to consecutive address segments of the same DDR channel x after interleaving.

[0078] Step S30: Determine the adaptive offset between different DDR channels based on the number of sub-address blocks that are mapped from all DDR channels before the pre-interleaving DDR channel y to the post-interleaving DDR channel x.

[0079] As an example, it should be understood that after the above calculations, the addresses in different DDR channels before interleaving are sequentially arranged starting from 0 within each DDR channel after interleaving. That is, if addresses from different DDR channels before interleaving belong to the same DDR channel after interleaving, address overlap will occur. To solve this problem, it is also necessary to calculate the adaptive offset between different DDR channels. This involves adding the number of sub-address blocks interleaved from the preceding DDR channels to the current DDR channel to the address interleaved into the current DDR channel. Since DDR chips may have various sizes, the offset between different DDR addresses needs to be adaptively calculated based on the size of the DDR chips.

[0080] Specifically, based on the distribution of sub-address blocks within each DDR channel, the total number of sub-address blocks mapped from each pre-interleaving DDR channel to each post-interleaving DDR channel is calculated. Then, the number of all sub-address blocks mapped to the same DDR channel before the current pre-interleaving DDR channel is added together to obtain the address offset mapped from the current pre-interleaving DDR channel to each DDR channel, which is the adaptive offset SN_offset(y,x) between different DDRs, in order to achieve sequential mapping between different DDRs.

[0081] Furthermore, in one embodiment, the adaptive offset SN_offset(y,x) is calculated as follows:

[0082]

[0083]

[0084] In the formula, (y,x) represents the address before interleaving belonging to the address space of DDR channel y and the address after interleaving belonging to the address space of DDR channel x, const(y,x) represents the number of basic address blocks in DDR channel y before interleaving interleaved into the distribution of DDR channel x after interleaving, S represents the granularity of DDR, and the value of k is determined by the interleaving granularity.

[0085] As an example, in this embodiment, SN_offset(y,x) is the sum of the number of sub-address blocks mapped from all DDR channels preceding the pre-interleaving DDR channel y to the post-interleaving DDR channel x, i.e. Specifically, assuming y=0 and x=0, since y=0, there are no DDR channels preceding it, so SN_offset(0,0)=0; assuming y=1 and x=0, meaning the DDR channel preceding y=1 is y=0, then we need to count the total number of sub-address blocks mapped from y=0 to x=0 (i.e., const (0,0)=85), so SN_offset (1,0)=2. N ×85; Assuming y=2 and x=0, and the channels ahead of them are y=0 and y=1, then the statistics show that const (0,0)=85 for y=0 and const (0,0)=84 for y=1. Therefore, SN_offset (2,0)=2. N ×85+2 N ×84=169, and so on.

[0086] As can be seen, this embodiment adaptively compensates for the address offset between different DDR channels for different DDR chip sizes, avoiding the overlap of address segments mapped to the same target DDR by different DDR channels, so as to ensure the uniqueness and continuity of addresses.

[0087] Step S40: Generate a target address corresponding to the interleaved address based on the bit top_addr_bit used to calculate the interleaving, the target mapping address, the relative offset, the adaptive offset, and the target address bit corresponding to the interleaving granularity.

[0088] As an example, in this embodiment, the target address corresponding to the interleaved address can be output based on top_addr_bit, target mapping address, relative offset, adaptive offset, and target address bits ADDR[k-1:0] corresponding to the interleaving granularity; it can be seen that this embodiment can ensure that addresses originally input sequentially are still arranged sequentially to the addresses of each DDR after interleaving (e.g., Figure 6 As shown in the figure, this effectively improves the read and write performance of DDR.

[0089] In summary, this embodiment achieves a continuous sequential arrangement of addresses on each DDR channel after interleaving of sequentially input original addresses through three-layer address mapping and offset calculation. This solves the problem of low DDR bandwidth utilization caused by out-of-order addresses in existing technologies, enabling DDR to achieve optimal bandwidth in continuous address access scenarios. Furthermore, the SN_offset(y,x) function in this embodiment is adaptively calculated based on the DDR chip size, eliminating the need to redesign the mapping logic for different DDR chip sizes, thus exhibiting strong adaptability. In addition, the core mapping operation in this embodiment is completed through a lookup table, transforming the inverse mapping of nonlinear calculations into a lookup operation that can be quickly implemented in hardware, resulting in high computational efficiency and low hardware deployment difficulty.

[0090] Further, in one embodiment, generating the target address corresponding to the interleaved address based on the bits used to calculate interleaving (top_addr_bit), the target mapping address, the relative offset, the adaptive offset, and the target address bits corresponding to the interleaving granularity includes:

[0091] The processed address is obtained based on the target mapping address, the relative offset, and the adaptive offset; wherein, the calculation expression for the processed address is:

[0092] ADDR_OUT(x)=ADDR_LUT+block_offset(y,x)+SN_offset(y,x)

[0093] In the formula, ADDR_OUT(x) represents the processed address in DDR channel x after interleaving; ADDR_LUT represents the target mapping address; (y,x) means that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x; block_offset(y,x) represents the relative offset; and SN_offset(y,x) represents the adaptive offset.

[0094] Set top_addr_bit to 0 and combine it with the processed address and the target address bit to obtain the target address corresponding to the interleaved address.

[0095] In this exemplary embodiment, the ADDR_LUT, block_offset(y,x), and SN_offset(y,x) calculated in the aforementioned steps are added together to obtain the initial processing address of the interleaved DDR channel x (i.e., the processed address ADDR_OUT(x)), that is, ADDR_OUT(x) = ADDR_LUT + block_offset(y,x) + SN_offset(y,x). Then, top_addr_bit0 and bits above it are set to 0, retaining only the address segment below top_addr_bit0. The processed address is then shifted left by k bits. Finally, the address segment after setting to 0 is concatenated with the left-shifted address and the target address bits ADDR[k-1:0] to output the final target address, which is the final address mapped to DDR channel x. It can be seen that this embodiment retains the address removal logic of top_addr_bit, ensuring a one-to-one correspondence between addresses. Based on the continuous address coverage of each DDR after interleaving without gaps, the addresses are evenly distributed within each interleaved DDR channel.

[0096] Secondly, embodiments of this application also provide an address mapping device based on DDR interleaving.

[0097] In one embodiment, the DDR-interleaved address mapping apparatus includes:

[0098] The first processing module is used to perform sequential mapping operations on the interleaved bits of the basic address block within the interleaved address through a lookup table to obtain the target mapped address within the basic address block. The original values ​​of the interleaved bits are non-linearly distributed, and the table is used to store the one-to-one correspondence between all possible values ​​of the interleaved bits and consecutive sequential addresses.

[0099] The second processing module is used to calculate the relative offset of different basic address blocks in the same DDR based on the number of basic address blocks in DDR channel y before interleaving and the number of sub-address blocks in DDR channel x after interleaving, and the sequence number of the basic address blocks.

[0100] The third processing module is used to determine the adaptive offset between different DDR channels based on the number of sub-address blocks that map all DDR channels before the pre-interleaving DDR channel y to the post-interleaving DDR channel x.

[0101] The address mapping module is used to generate a target address corresponding to the interleaved address based on the top_addr_bit used to calculate the interleaving, the target mapping address, the relative offset, the adaptive offset, and the target address bit corresponding to the interleaving granularity.

[0102] Furthermore, in one embodiment, the address mapping module is specifically used for:

[0103] The processed address is obtained based on the target mapping address, the relative offset, and the adaptive offset;

[0104] Set top_addr_bit to 0 and combine it with the processed address and the target address bit to obtain the target address corresponding to the interleaved address.

[0105] Furthermore, in one embodiment, the expression for calculating the processed address is:

[0106] ADDR_OUT(x)=ADDR_LUT+block_offset(y,x)+SN_offset(y,x)

[0107] In the formula, ADDR_OUT(x) represents the processed address in DDR channel x after interleaving; ADDR_LUT represents the target mapping address; (y,x) means that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x; block_offset(y,x) represents the relative offset; and SN_offset(y,x) represents the adaptive offset.

[0108] Furthermore, in one embodiment, the calculation expression for the relative offset block_offset(y,x) is:

[0109] block_offset(y,x)=K×const(y,x)

[0110] In the formula, (y,x) indicates that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x, const(y,x) indicates the number of basic address blocks in DDR channel y before interleaving interleaved into sub-address blocks in DDR channel x after interleaving, and K represents the sequence number of the basic address blocks.

[0111] Furthermore, in one embodiment, the adaptive offset SN_offset(y,x) is calculated as follows:

[0112]

[0113]

[0114] In the formula, (y,x) represents the address before interleaving belonging to the address space of DDR channel y and the address after interleaving belonging to the address space of DDR channel x, const(y,x) represents the number of basic address blocks in DDR channel y before interleaving interleaved into sub-address blocks in DDR channel x after interleaving, S represents the granularity of DDR, and the value of k is determined by the interleaving granularity.

[0115] The functions of each module in the above-mentioned DDR interleaving-based address mapping device correspond to the steps in the above-mentioned DDR interleaving-based address mapping method embodiment, and their functions and implementation processes will not be described in detail here.

[0116] Thirdly, embodiments of this application provide an address mapping device based on DDR interleaving. The address mapping device based on DDR interleaving can be a personal computer (PC), a laptop computer, a server, or other device with data processing capabilities.

[0117] Reference Figure 7 , Figure 7 This is a schematic diagram of the hardware structure of the DDR interleaving-based address mapping device involved in the embodiments of this application. In the embodiments of this application, the DDR interleaving-based address mapping device may include a processor, a memory, a communication interface, and a communication bus.

[0118] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.

[0119] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces used for interconnecting devices within DDR-interleaved address mapping devices, as well as interfaces used for interconnecting DDR-interleaved address mapping devices with other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.

[0120] Memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0121] The processor can be a general-purpose processor, which can call a DDR-interleaved address mapping program stored in memory and execute the DDR-interleaved address mapping method provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit (CPU). The method executed when the DDR-interleaved address mapping program is called can be referred to in the various embodiments of the DDR-interleaved address mapping method of this application, and will not be repeated here.

[0122] Those skilled in the art will understand that Figure 7 The hardware structure shown does not constitute a limitation of this application and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0123] Fourthly, embodiments of this application also provide a computer-readable storage medium.

[0124] This application has a DDR-interleaved address mapping program stored on a readable storage medium, wherein when the DDR-interleaved address mapping program is executed by a processor, it implements the steps of the DDR-interleaved address mapping method described above.

[0125] The method implemented when the DDR interleaving-based address mapping program is executed can be referred to in the various embodiments of the DDR interleaving-based address mapping method of this application, and will not be repeated here.

[0126] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0127] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0128] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0129] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0130] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0131] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0132] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An address mapping method based on DDR interleaving, characterized in that, The address mapping method based on DDR interleaving includes: The interleaved bits of the base address block within the interleaved address are sequentially mapped using a lookup table to obtain the target mapped address within the base address block. The original values ​​of the interleaved bits are non-linearly distributed, and the lookup table is used to store the one-to-one correspondence between all possible values ​​of the interleaved bits and consecutive sequential addresses. The relative offset of different basic address blocks within the same DDR is calculated based on the number of basic address blocks interleaved from the basic address blocks in DDR channel y before interleaving to the sub-address blocks in DDR channel x after interleaving, and the sequence number of the basic address blocks. The adaptive offset between different DDR channels is determined based on the number of sub-address blocks that are mapped from all DDR channels before the pre-interleaving DDR channel y to the post-interleaving DDR channel x. The target address corresponding to the interleaved address is generated based on the top_addr_bit used to calculate the interleaving, the target mapping address, the relative offset, the adaptive offset, and the target address bit corresponding to the interleaving granularity. Wherein, the basic address block represents an address block unit jointly divided by ADDR[k+8:k] and ADDR[k-1:0], the value of k is determined by the interleaving granularity, and the sub-address block represents an address block corresponding to the interleaving granularity size.

2. The address mapping method based on DDR interleaving as described in claim 1, characterized in that, The process of generating a target address corresponding to the interleaved address based on the top_addr_bit used for interleaving calculation, the target mapping address, the relative offset, the adaptive offset, and the target address bits corresponding to the interleaving granularity includes: The processed address is obtained based on the target mapping address, the relative offset, and the adaptive offset; Set top_addr_bit to 0 and combine it with the processed address and the target address bit to obtain the target address corresponding to the interleaved address.

3. The address mapping method based on DDR interleaving as described in claim 2, characterized in that, The expression for calculating the processed address is: ADDR_OUT(x)=ADDR_LUT+block_offset(y,x)+SN_offset(y,x) In the formula, ADDR_OUT(x) represents the processed address in DDR channel x after interleaving; ADDR_LUT represents the target mapping address; (y,x) means that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x; block_offset(y,x) represents the relative offset; and SN_offset(y,x) represents the adaptive offset.

4. The address mapping method based on DDR interleaving as described in claim 1, characterized in that, The expression for calculating the relative offset block_offset(y,x) is: block_offset(y,x)=K×const(y,x) In the formula, (y,x) indicates that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x, const(y,x) indicates the number of basic address blocks in DDR channel y before interleaving interleaved into sub-address blocks in DDR channel x after interleaving, and K represents the sequence number of the basic address blocks.

5. The address mapping method based on DDR interleaving as described in claim 1, characterized in that, The expression for calculating the adaptive offset SN_offset(y,x) is: In the formula, (y,x) represents the address before interleaving belonging to the address space of DDR channel y and the address after interleaving belonging to the address space of DDR channel x, const(y,x) represents the number of basic address blocks in DDR channel y before interleaving interleaved into sub-address blocks in DDR channel x after interleaving, S represents the granularity of DDR, and the value of k is determined by the interleaving granularity.

6. An address mapping device based on DDR interleaving, characterized in that, The address mapping device based on DDR interleaving includes: The first processing module is used to perform sequential mapping operations on the interleaved bits of the basic address block within the interleaved address using a lookup table to obtain the target mapped address within the basic address block. The original values ​​of the interleaved bits are non-linearly distributed, and the lookup table is used to store the one-to-one correspondence between all possible values ​​of the interleaved bits and consecutive sequential addresses. The second processing module is used to calculate the relative offset of different basic address blocks in the same DDR based on the number of basic address blocks in DDR channel y before interleaving and the number of sub-address blocks in DDR channel x after interleaving, and the sequence number of the basic address blocks. The third processing module is used to determine the adaptive offset between different DDR channels based on the number of sub-address blocks that map all DDR channels before the pre-interleaving DDR channel y to the post-interleaving DDR channel x. The address mapping module is used to generate a target address corresponding to the interleaved address based on the top_addr_bit used to calculate the interleaving, the target mapping address, the relative offset, the adaptive offset, and the target address bit corresponding to the interleaving granularity. Wherein, the basic address block represents an address block unit jointly divided by ADDR[k+8:k] and ADDR[k-1:0], the value of k is determined by the interleaving granularity, and the sub-address block represents an address block corresponding to the interleaving granularity size.

7. The address mapping device based on DDR interleaving as described in claim 6, characterized in that, The address mapping module is specifically used for: The processed address is obtained based on the target mapping address, the relative offset, and the adaptive offset; Set top_addr_bit to 0 and combine it with the processed address and the target address bit to obtain the target address corresponding to the interleaved address.

8. The address mapping device based on DDR interleaving as described in claim 7, characterized in that, The expression for calculating the processed address is: ADDR_OUT(x)=ADDR_LUT+block_offset(y,x)+SN_offset(y,x) In the formula, ADDR_OUT(x) represents the processed address in DDR channel x after interleaving; ADDR_LUT represents the target mapping address; (y,x) means that the address before interleaving belongs to the address space of DDR channel y and the address after interleaving belongs to the address space of DDR channel x; block_offset(y,x) represents the relative offset; and SN_offset(y,x) represents the adaptive offset.

9. An address mapping device based on DDR interleaving, characterized in that, The DDR-interleaved address mapping device includes a processor, a memory, and a DDR-interleaved address mapping program stored in the memory and executable by the processor, wherein when the DDR-interleaved address mapping program is executed by the processor, it implements the steps of the DDR-interleaved address mapping method as described in any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a DDR-interleaved address mapping program, wherein when the DDR-interleaved address mapping program is executed by a processor, it implements the steps of the DDR-interleaved address mapping method as described in any one of claims 1 to 5.

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