Uplink channel time synchronization apparatus, method, device, medium and program product

Abstract

The invention relates to the field of satellite wireless communication, and provides an uplink channel time synchronization device, method and equipment, a medium and a program product, and the device comprises a first storage module which is used for caching received first data; the first processing module is used for processing the second data in the first storage module to obtain a first time delay estimation value, and processing the third data in the first storage module based on the first time delay estimation value; the second data is a part of the first data, and the third data is the remaining data in the first data with the first time delay estimation value as the starting position. According to the uplink channel time synchronization method and device, data caching and time delay correction are combined, and under the condition that the terminal equipment is not changed at all, the application scene that the terminal equipment is directly connected with the network equipment in any scene can be met only by adopting the uplink channel time synchronization device by the network equipment.

Description

Technical Field

[0001] This application relates to the field of wireless communication, and more specifically, to an uplink channel time synchronization device, method, apparatus, medium, and program product. Background Technology

[0002] Latency handling for direct network connection between terminal devices primarily focuses on the 3GPP (3rd Generation Partnership Project) 5G NTN (Non-Terrestrial Network) protocol, typically employing location-based uplink synchronization methods. However, due to network-wide time synchronization errors and various perturbation forces, even after pre-compensation, location-based uplink synchronization methods still exhibit significant time deviations. Furthermore, the instability of satellite-to-ground clocks and the timing drift of the wireless link caused by relative motion between terminal and network devices can severely impact the uplink channel arrival time at the payload, thereby impairing demodulation performance and potentially causing delays exceeding one OFDM (Orthogonal Frequency Division Multiplexing) symbol, resulting in demodulation failure and affecting application scenarios where terminal devices directly connect to network devices. Summary of the Invention

[0003] To address the aforementioned problems, this application provides an uplink channel time synchronization device, method, apparatus, medium, and program product to meet the application scenarios where terminal devices directly connect to network devices in any situation.

[0004] In a first aspect, this application provides an uplink channel time synchronization device, which is applied to a network device, and the device includes:

[0005] The first storage module is used to cache the received first data;

[0006] A first processing module is used to process the second data in the first storage module to obtain a first latency estimate, and to process the third data in the first storage module based on the first latency estimate; the second data is a part of the first data, and the third data is the remaining data in the first data starting from the first latency estimate.

[0007] In one or more embodiments of this application, the first processing module includes:

[0008] The first computing unit is used to process the second data to obtain the first processed data;

[0009] The second computing unit is used to process the first processed data to obtain a first time delay estimate.

[0010] In one or more embodiments of this application, the second computing unit performs correlation operations on the first processed data based on DMRS to obtain a first time delay estimate.

[0011] In one or more embodiments of this application, the second computing unit is specifically used for:

[0012] Based on the local DMRS sequence and the DMRS signal in the first processed data, a correlation operation is performed to obtain the maximum value of the correlation operation result and its corresponding position;

[0013] A first time delay estimate is obtained based on the corresponding location.

[0014] In one or more embodiments of this application, the corresponding position is determined based on the maximum value and the first threshold.

[0015] In one or more embodiments of this application, the first processing module further includes:

[0016] First storage control unit;

[0017] The first processing module reads and writes data in the first storage module based on the first storage control unit.

[0018] In one or more embodiments of this application, the first processing module further includes:

[0019] The first interface is used to transmit the received first data to the first storage control unit.

[0020] In one or more embodiments of this application, the uplink channel time synchronization device further includes:

[0021] The data acquisition module is used to receive raw data and perform analog-to-digital conversion to obtain the first data.

[0022] In one or more embodiments of this application, the first processing module further includes:

[0023] Third calculation unit;

[0024] The first computing unit is also used to process the third data to obtain second processed data;

[0025] The third computing unit is used to perform CP cyclic prefix removal processing on the second processed data to obtain the third processed data.

[0026] In one or more embodiments of this application, the first computing unit processes the third data in units of the length of the second data.

[0027] In one or more embodiments of this application, the first computing unit is an FFT processing module.

[0028] In one or more embodiments of this application, the uplink channel time synchronization device further includes:

[0029] The second storage module is used to cache the data processed by the third party.

[0030] In one or more embodiments of this application, the first processing module further includes:

[0031] Second storage control unit;

[0032] The first processing module reads and writes data in the second storage module based on the second storage control unit.

[0033] In one or more embodiments of this application, the first processing module further includes:

[0034] The second interface is used to output data from the second storage module.

[0035] In one or more embodiments of this application, the uplink channel time synchronization device further includes:

[0036] The second processing module is used to perform subsequent processing on the data output from the second storage module.

[0037] In one or more embodiments of this application, the first storage module is a DDR memory; the first storage control unit is a DDR memory controller.

[0038] In one or more embodiments of this application, the second storage module is a DDR memory; the second storage control unit is a DDR memory controller.

[0039] In one or more embodiments of this application, both the first processing module and the second processing module are implemented using FPGA.

[0040] Secondly, this application also provides a network device, wherein the network device is provided with the above-mentioned uplink channel time synchronization device.

[0041] Thirdly, this application also provides an uplink channel time synchronization method, which is applied to a network device, and the method includes:

[0042] Buffer the first received data;

[0043] The second data is processed to obtain a first time delay estimate, where the second data is a part of the first data.

[0044] The third data is processed, and the third data is the remaining data in the first data that starts from the first time delay estimate.

[0045] In one or more embodiments of this application, the processing of the second data includes:

[0046] The second data is processed to obtain the first processed data;

[0047] The first processed data is processed to obtain a first time delay estimate.

[0048] In one or more embodiments of this application, a first delay estimate is obtained by performing correlation operations on the first processed data based on DMRS.

[0049] In one or more embodiments of this application, the correlation operation on the first processed data based on DMRS includes:

[0050] Based on the local DMRS sequence and the DMRS signal in the first processed data, a correlation operation is performed to obtain the maximum value of the correlation operation result and its corresponding position;

[0051] A first time delay estimate is obtained based on the corresponding location.

[0052] In one or more embodiments of this application, obtaining the corresponding position includes:

[0053] The corresponding position is determined based on the maximum value and the first threshold.

[0054] In one or more embodiments of this application, the processing of the third data includes:

[0055] The third data is processed to obtain the second processed data;

[0056] The second processed data is subjected to CP loop prefix removal to obtain the third processed data.

[0057] In one or more embodiments of this application, the third data is processed in units of the length of the second data.

[0058] In one or more embodiments of this application, both the second data and the third data are subjected to FFT processing.

[0059] In one or more embodiments of this application, the uplink channel time synchronization method further includes:

[0060] The third processed data is cached.

[0061] In one or more embodiments of this application, the uplink channel time synchronization method further includes:

[0062] Read the cached third-party processing data and perform subsequent processing.

[0063] Fourthly, this application also provides an electronic device, comprising:

[0064] At least one processor; and a memory communicatively connected to said at least one processor;

[0065] The memory stores instructions that can be executed by the at least one processor. By executing the instructions stored in the memory, the at least one processor performs the aforementioned uplink channel time synchronization method.

[0066] Fifthly, this application also provides a computer-readable storage medium for storing instructions that, when executed, enable the aforementioned uplink channel time synchronization method to be implemented.

[0067] Sixthly, this application also provides a computer program product, which, when invoked by a computer, causes the computer to execute the above-described uplink channel time synchronization method. Attached Figure Description

[0068] Figure 1 A schematic diagram of a wireless communication system that allows terminal devices to directly connect to low-Earth orbit satellites.

[0069] Figure 2 This is a schematic diagram of the structure of a wireless communication system that uses an uplink channel time synchronization device provided in an embodiment of this application.

[0070] Figure 3 A detailed structural diagram of the first processing module provided in the embodiments of this application.

[0071] Figure 4 Another detailed structural diagram of the first processing module provided in the embodiments of this application.

[0072] Figure 5 This is a detailed structural diagram of an uplink channel time synchronization device provided in an embodiment of this application.

[0073] Figure 6 This is a flowchart of an uplink channel time synchronization method provided in an embodiment of this application.

[0074] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0075] Figure 8 It is a schematic structural diagram of a wireless communication system for another application of the uplink channel time synchronization device provided in the embodiments of the present application.

[0076] Icon:

[0077] 110 - First storage module, 120 - First processing module, 121 - First calculation unit, 122 - Second calculation unit, 123 - Third calculation unit, 124 - First storage control unit, 125 - Second storage control unit, 126 - First interface, 127 - Second interface, 130 - Second storage module, 140 - Second processing module, 150 - Data acquisition module;

[0078] 210 - Third processing module, 220 - Fourth processing module;

[0079] 310 - Processor, 320 - Memory, 330 - Bus. Detailed implementation manners

[0080] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. Components of the embodiments of the present application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0081] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0082] See Figure 1 , which is a schematic structural diagram of a wireless communication system in which a terminal device directly connects to a network device. In the wireless communication system in which a terminal device directly connects to a network device as shown in Figure 1 :

[0083] The network device can be a network device carried on a high-speed moving vehicle, and can also be called an airborne network device, an airborne base station, an airborne network side, a spaceborne network device, a satellite base station, a satellite network side, etc. For the convenience of description, the network device will be used as an example in the subsequent introduction process. Examples of some high-speed moving vehicles are: unmanned aerial vehicles, satellites, etc. The satellites can be low-earth orbit satellites, medium-earth orbit satellites, high-earth orbit satellites, etc.

[0084] Terminal devices can also be called terminals, terminal sides, wireless terminals, or wireless terminal equipment. For ease of description, we will use terminal devices as examples in the following introduction. Some examples of terminal devices include: mobile phones, tablets, laptops, PDAs, MID devices (Mobile Internet Devices), wearable devices, VR (Virtual Reality) devices, AR (Augmented Reality) devices, wireless terminal devices in industrial control, wireless terminal devices in self-driving, wireless terminal devices in remote medical surgery, wireless terminal devices in smart grids, wireless terminal devices in transportation safety, wireless terminal devices in smart cities, and wireless terminal devices in smart homes.

[0085] It should be noted that, Figure 1 This application does not limit the number of network devices and terminal devices included in a wireless communication system, but only as an example. Figure 1 The present invention only exemplarily illustrates a wireless communication system comprising a network device and a terminal device.

[0086] Currently, latency handling for direct network connection between terminal devices mainly focuses on the 3GPP 5G NTN protocol, typically employing location-based uplink synchronization methods. However, due to network-wide time synchronization errors and various perturbation forces, even after pre-compensation, location-based uplink synchronization methods still exhibit significant time deviations. Furthermore, the instability of satellite-to-ground clocks and the timing drift of the wireless link caused by relative motion between terminal and network devices can severely impact the uplink channel arrival time at the payload, thereby impairing demodulation performance and even causing delays exceeding one OFDM symbol, leading to demodulation failure and affecting application scenarios where terminal devices directly connect to network devices.

[0087] Therefore, this application provides an uplink channel time synchronization device to meet the application scenarios where terminal devices are directly connected to network devices in any situation.

[0088] See Figure 2 This is a schematic diagram of the structure of a wireless communication system that applies an uplink channel time synchronization device provided in an embodiment of this application. Figure 2 In the device structure shown, the uplink channel time synchronization device includes:

[0089] The first storage module 110 is used to cache the received first data;

[0090] The first processing module 120 is used to process the second data in the first storage module 110 to obtain a first delay estimate, and to process the third data in the first storage module 110 based on the first delay estimate; the second data is a part of the first data, and the third data is the remaining data in the first data starting from the first delay estimate.

[0091] Because the large time delay leads to an uncertain signal start position, the first storage module 110 caches data to gradually search for the start position. Then, the first processing module 120 determines whether it is the signal start position and feeds back a first time delay estimate to reread data and detect whether it is the signal start position, thereby achieving time delay correction. Therefore, this embodiment of the application, combining the data caching of the first storage module 110 and the time delay correction of the first processing module 120, can meet the application scenarios of direct connection of the terminal device to the network device in any scenario without any changes to the terminal device, only requiring the network device to adopt the uplink channel time synchronization device.

[0092] See Figure 3 This is a detailed structural diagram of the first processing module provided in an embodiment of this application. Figure 3 In the structure shown, the first processing module 120 includes: a first calculation unit 121, used to process the second data to obtain first processed data; and a second calculation unit 122, used to process the first processed data to obtain a first time delay estimate. Thus, the first processing module 120 specifically implements time delay correction through the first calculation unit 121 and the second calculation unit 122 to detect the signal start position.

[0093] See Figure 4 This is another detailed structural diagram of the first processing module provided in an embodiment of this application. Figure 4 In the structure shown, Figure 3 Based on the structure shown, the first processing module 120 further includes a third calculation unit 123; the first calculation unit is further used to process the third data to obtain second processed data; the third calculation unit 123 is used to perform CP (Cyclic Prefix) removal processing on the second processed data to obtain third processed data. Thus, after time delay correction, the remaining data starting from the first time delay estimate is processed accordingly, and the resulting data is convenient for subsequent processing.

[0094] See Figure 5This is a detailed structural schematic diagram of an uplink channel time synchronization device provided in an embodiment of this application. Figure 5 The device structure shown can be implemented using the following examples:

[0095] First, the network device receives raw data from the terminal device. This raw data is typically an analog signal, which needs to be converted into a digital signal via analog-to-digital conversion (ADC) for further processing. In this embodiment, a data acquisition module 150 is used at the input of the uplink channel time synchronization device to receive the raw data and perform ADC conversion to obtain the first data. To implement the ADC conversion, the data acquisition module 150 uses an ADC (Analog-to-Digital Converter). In some possible designs, the ADC can be a ready-made product or a custom-designed ADC circuit. When using a ready-made product, a suitable high-speed ADC chip can be selected as needed. Parameters considered when selecting a device generally include the highest sampling rate, 3dB analog bandwidth, and quantization level. For example, the TI high-speed ADC chip ADC083000 can be used, which supports a maximum sampling rate of 3Gsps, a 3dB analog bandwidth of 3GHz, and an 8-bit quantization level.

[0096] Next, the first data obtained by the data acquisition module 150 needs to be cached for latency estimation. In this embodiment, the first data is forwarded to the first storage module 110 for caching via the first processing module 120. Therefore, the first data is received at the input of the first processing module 120 using a first interface 126 to achieve high-speed data transmission between the data acquisition module 150 and the first processing module 120. The first interface 126 can be selected based on the selection of the data acquisition module 150 and the first processing module 120 and the requirements for achieving high-speed data transmission. For example, a JESD 204B interface can be used, which theoretically supports a maximum rate of 160Gbps, meeting the transmission rate required for high-speed sampling.

[0097] The first processing module 120 needs to write first data into the first storage module 110 for caching, and simultaneously needs to read data from the first storage module 110 for processing. Therefore, the first processing module 120 employs a first storage control unit 124. The first processing module 120 reads and writes data from the first storage module 110 based on the first storage control unit 124. As described above, the read / write operation includes: writing the received first data into the first storage module 110 for caching; reading second data from the first storage module 110; and reading third data from the first storage module 110. It should be noted that, in order to effectively read a certain length of data from the first storage module 110, this embodiment uses a pointer-based method for data reading.

[0098] Next, after enabling the first processing module 120 to read and write data to the first storage module 110, this embodiment employs a first computing unit 121 and a second computing unit 122 to implement specific latency correction processing. The first computing unit 121 processes the data read from the first storage module 110, including processing the second data to obtain first processed data, and processing the third data to obtain second processed data. The second computing unit 122 processes the first processed data to obtain a first latency estimate.

[0099] This application embodiment provides a processing method for the second computing unit 122, which performs correlation operations on the first processed data based on the DMRS (Demodulation Reference Signal) to obtain a first time delay estimate. Specifically, it can be as follows: performing correlation operations based on the local DMRS sequence and the DMRS signal in the first processed data to obtain the maximum value of the correlation operation result and its corresponding position; and obtaining the first time delay estimate based on the corresponding position. The first time delay estimate obtained is thus the product of the pointer when acquiring the first length of data and the corresponding position of the maximum value of the correlation operation result.

[0100] Optionally, for the maximum value of the calculated relevant operation results, a first threshold can be set, and the corresponding position can be determined based on the maximum value and the first threshold. That is, when the maximum value exceeds the first threshold, a first time delay estimate is obtained based on the corresponding position.

[0101] Optionally, the first computing unit processes the third data in units of the length of the second data. In particular, when the length of the third data is longer than the length of the second data, the first computing unit processes the third data multiple times, with the length of the data processed each time being the length of the second data. This can save computing resources and improve processing efficiency.

[0102] Optionally, in this embodiment, the first calculation unit is an FFT (Fast Fourier Transform) processing module. On one hand, by performing FFT processing on the second data, the second calculation unit 122 can read the DMRS signal from the first processed data, wherein the number of FFT points for the FFT processing of the second data is the length of the second data. On the other hand, by performing FFT processing on the third data, the obtained data is easier for subsequent processing, wherein the number of FFT points for the FFT processing of the third data is also the length of the second data. In addition, CP removal processing is required before subsequent processing so that the data after processing the third data can be directly applied to subsequent processing. Therefore, in this embodiment, the first processing module also includes a third calculation unit 123, whose function is to perform CP removal processing on the second processed data to obtain the third processed data.

[0103] Next, the device further includes a second storage module 130. After delay correction is completed, the specific function of the second storage module 130 is to buffer the third processed data. The second storage module 130 effectively realizes subsequent processing of the signal pipeline, improving the efficiency of data processing. Similarly, the first processing module 120 employs a first storage control unit 125. The first processing module 120 reads and writes data in the second storage module 130 based on the first storage control unit 125. The read and write operations specifically include: writing the third processed data into the second storage module for buffering, and reading data from the second storage module.

[0104] For the first storage module 110 and the second storage module 130, any memory capable of data caching can be used, including volatile memory, non-volatile memory, or both. An optional example is that the first storage module 110 and the second storage module 130 use DDR (Double Data Rate) memory, which can better achieve data caching. The main parameter considered in its selection is the bit width. For example, the first storage module 110 and the second storage module 130 can use a DDR4 memory (Double Data Rate 4 Synchronous Dynamic Random-Access Memory) of model MT40A512M8RH-075EAAT, with a bit width of 16 bits, of which the high 8 bits are I-channel data and the low 8 bits are Q-channel data. Correspondingly, the first storage control unit 124 and the first storage control unit 125 are DDR memory controllers to work in conjunction with the DDR memory.

[0105] Next, to achieve high-speed data output for subsequent processing, the first processing module 120 further includes a first interface 127, which outputs data from the second storage module 130. This first interface 127 can be selected based on the requirements for high-speed data transmission. For example, an Aurora interface can be used, with a theoretical transmission rate of 60Gbps and an actual transmission rate of approximately 40Gbps, meeting the required transmission rate for high-speed data transmission.

[0106] Finally, the uplink channel time synchronization device also includes a second processing module 140, which performs subsequent processing on the data in the output second storage module 130. The subsequent processing includes timing synchronization, frequency offset estimation and compensation, channel estimation and equalization, and decoding.

[0107] For both the first processing module 120 and the second processing module 140, any processor with data processing capabilities can be used. For example, the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0108] An optional example is that both the first processing module 120 and the second processing module 140 are implemented using FPGAs. The selection and design can be based on the aforementioned functional and performance requirements. For example, the first processing module 120 and the second processing module 140 can be implemented using Xilinx's Virtex-7 series. When both the first processing module 120 and the second processing module 140 are implemented using FPGAs, the following optional configurations can be further implemented:

[0109] In configuration one, the first processing module 120 and the second processing module 140 can be controlled independently, including independent control of power-on / off, low-power sleep mode, and reset functions, thereby effectively reducing power consumption.

[0110] In the second configuration, the first processing module 120 and the second processing module 140 share resources with other FPGA modules in the network device. This resource sharing improves system resource utilization and allows functions to be transferred to FPGA modules on other signal processing boards when some FPGA modules fail, thereby improving system reliability.

[0111] The above describes the data flow from data input to data output. Figure 5 Some implementation schemes of the uplink channel time synchronization device are shown. Correspondingly, the specific steps of the uplink channel time synchronization device's workflow are as follows:

[0112] S101: Initialization, pre-store the local DMRS sequence, set the known transmission DMRS location, the number of FFT points in the first calculation unit 121 for FFT processing is N, the first threshold of the second calculation unit 122 is P0, and set the pointer h of reading the first storage module 110 to 0; the first threshold P0 can be determined based on machine learning or experience, according to the channel environment.

[0113] S102: The data acquisition module 150 receives analog signals and converts the received analog signals into digital signals to obtain first data. The first storage control unit 124 in the first processing module 120 receives the first data through the first interface 126.

[0114] S103: The first storage control unit 124 writes the received first data into the first storage module 110 for caching via a write command;

[0115] S104: Determine whether the pointer h read from the first storage module 110 exceeds the maximum address value of the first storage module 110:

[0116] If the pointer h of the first storage module 110 is less than or equal to the maximum address value of the first storage module 110, then step S105 is executed;

[0117] If the pointer h of the first storage module 110 is greater than the maximum address value of the first storage module 110, then step S113 is executed;

[0118] S105: The first storage control unit 124 reads the second data from the first storage module 110 according to the position pointed to by the pointer h by a read command. The length of the second data is N, and h = h + N.

[0119] S106: The first storage control unit 124 inputs the second data into the first calculation unit 121, and the first calculation unit 121 performs FFT processing on the second data to obtain the first processed data;

[0120] S107: The second calculation unit reads a local DMRS sequence c(n) of length K, then reads the DMRS signal q(n) from the first processed data according to the known transmission DMRS position, and finally performs a correlation operation on the local DMRS sequence c(n) and the DMRS signal q(n), and takes the maximum value P of the correlation operation result and its corresponding position d0. The calculation expression is as follows:

[0121]

[0122] Where max(*) is the maximum value operation, ∑(*) is the summation operation, and k = 1, 2, ..., K;

[0123] S108: Compare the maximum value P of the relevant calculation result with the first threshold P0 of the second calculation unit 122:

[0124] If P > P0, then proceed to step S109;

[0125] If P < P0, then proceed to step S104;

[0126] S109: Calculate the first time delay estimate toa based on the corresponding position d0. The calculation expression is as follows:

[0127] toa=d0+h*N

[0128] The meanings of the parameters in the above calculation expressions can be referred to above, and will not be repeated here;

[0129] S110: The second computing unit 122 transmits the first delay estimate toa to the first storage control unit 124, and then the first storage control unit 124 reads the third data from the first storage module 110 according to the first delay estimate toa and transmits it to the first computing unit 121; wherein, the specific method of reading the third data is to read the remaining data from the first data with the first delay estimate as the starting position to obtain the third data;

[0130] S111: The first computing unit 121 performs FFT processing on the third data in multiple steps for every N data points to obtain the second processed data. Then, the third computing unit 123 performs CP cyclic prefix removal processing on the second processed data to obtain the third processed data and transmits the third processed data to the first storage control unit 125. The first storage control unit 125 writes the third processed data into the second storage module 130 for caching via a write command.

[0131] S112: The first storage control unit 125 reads the data in the second storage module 130 through a read command and transmits it to the second processing module 140 through the first interface 127. Then the second processing module 140 performs subsequent processing, including timing synchronization, frequency offset estimation and compensation, channel estimation and equalization, and decoding.

[0132] S113: If the data in the first storage module 110 and the second storage module 130 has been processed, wait for the data acquisition module 150 to receive the new analog signal before proceeding with the entire process.

[0133] For example Figure 2 As shown, correspondingly, this application embodiment also provides a network device, which is equipped with the aforementioned uplink channel time synchronization device. By equipping the network device with the uplink channel time synchronization device, the network device enables direct connection between the terminal device and the network device to complete uplink channel time synchronization. The specific structure and working principle of the uplink channel time synchronization device in the network device can be referred to the foregoing and will not be repeated here.

[0134] Based on the same concept, embodiments of this application also provide an uplink channel time synchronization method, the implementation steps of which are as follows: Figure 6 As shown, it specifically includes:

[0135] S201, buffer the first received data;

[0136] S202, process the second data to obtain a first time delay estimate, wherein the second data is a part of the first data;

[0137] S203, process the third data, which is the remaining data in the first data starting from the first time delay estimate.

[0138] As for the specific processing methods in the above steps, please refer to the specific description of the uplink channel time synchronization device and its working process. In addition, the data processed in step S203 can also be buffered, read, output and further processed, which can also be referred to the specific description of the uplink channel time synchronization device and its working process. It will not be repeated here.

[0139] Based on the same technical concept, embodiments of this application also provide an electronic device that can implement the uplink channel time synchronization method flow provided in the above embodiments of this application. In one embodiment, the electronic device can be a server, a terminal device, or other electronic devices. Figure 7 As shown, the electronic device may include:

[0140] At least one processor 310 and a memory 320 connected to the at least one processor 310. In this embodiment, the specific connection medium between the processor 310 and the memory 320 is not limited. Figure 7 The example shown is the connection between processor 310 and memory 320 via bus 330. Bus 330... Figure 7 The connections between other components are indicated by thick lines and are for illustrative purposes only, not as limiting information. Bus 330 can be divided into address bus, data bus, control bus, etc., for ease of representation. Figure 7 The term is represented by a single thick line, but this does not imply that there is only one bus or one type of bus. Alternatively, the processor 310 can also be called a controller; there is no restriction on the name.

[0141] In this embodiment, the memory 320 stores instructions executable by at least one processor 310. By executing the instructions stored in the memory 320, the at least one processor 310 can execute an uplink channel time synchronization method as described above. The processor 310 can implement... Figure 7 The functions of each module in the device shown.

[0142] The processor 310 is the control center of the device. It can connect to various parts of the control device through various interfaces and lines. By running or executing instructions stored in the memory 320 and calling data stored in the memory 320, the various functions of the device and the data processing are monitored as a whole.

[0143] In an alternative design, processor 310 may include one or more processing units. Processor 310 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may also not be integrated into processor 310. In some embodiments, processor 310 and memory 320 may be implemented on the same chip; in some embodiments, they may also be implemented on separate chips.

[0144] The processor 310 can be a general-purpose processor, such as a CPU, digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the uplink channel time synchronization method disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0145] Memory 320, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 320 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc. Memory 320 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. In the embodiments of this application, memory 320 may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0146] By designing and programming the processor 310, the code corresponding to the uplink channel time synchronization method described in the foregoing embodiments can be embedded into the chip, thereby enabling the chip to execute the code during operation. Figure 6 The steps of an uplink channel time synchronization method according to the illustrated embodiment are described below. How to design and program the processor 310 is a technique well-known to those skilled in the art and will not be elaborated upon here.

[0147] Based on the same inventive concept, embodiments of this application also provide a storage medium storing computer instructions that, when executed on a computer, cause the computer to perform an uplink channel time synchronization method described above.

[0148] In some alternative implementations, this application also provides that various aspects of an uplink channel time synchronization method can also be implemented as a program product including program code, which, when the program product is run on a device, causes the control device to perform the steps in an uplink channel time synchronization method according to various exemplary embodiments of this application described above.

[0149] It should be noted that although several units or sub-units of the apparatus have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units. Furthermore, although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0150] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0151] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a server, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0152] Program code for performing the operations of this application can be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0153] In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0154] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0155] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0156] See Figure 8 This is a schematic diagram of the structure of a wireless communication system that provides an uplink channel time synchronization device according to another embodiment of this application. Figure 8 In the structure shown, the wireless communication system includes terminal equipment and network equipment;

[0157] The terminal device includes a third processing module 210 and a fourth processing module 220. The third processing module 210 is used to receive and process downlink signals to obtain a second delay estimate. The fourth processing module 220 is used to perform delay compensation on the uplink channel using the second delay estimate.

[0158] The network device is the aforementioned network device equipped with an uplink channel time synchronization device provided in the embodiments of this application.

[0159] It should be noted that the aforementioned solution in this application describes a scenario where the terminal device can directly connect to the network device in any situation without any changes to the terminal device, provided that only the network device adopts the aforementioned uplink channel time synchronization device. In this context, a further uplink channel time synchronization architecture of "terminal device latency compensation + network device latency correction" is adopted. This involves first performing latency compensation on the terminal device to achieve millisecond-level uplink channel time synchronization, and then further performing latency correction on the network device to achieve microsecond-level uplink channel time synchronization. The combination of these two approaches not only meets the application scenario of the terminal device directly connecting to the network device in any situation, but also further improves the processing efficiency of uplink channel time synchronization compared to a solution using only "network device latency correction," thus further ensuring normal communication. Furthermore, without terminal device latency compensation, the terminal device generally needs ephemeris data for latency compensation. However, in areas such as at sea or in deserts, it is difficult for the terminal device to obtain ephemeris information. Therefore, the uplink channel time synchronization architecture of "terminal device latency compensation + network device latency correction" is particularly suitable for areas such as at sea or in deserts where it is difficult for the terminal device to obtain ephemeris information.

[0160] Figure 8 The specific steps of the terminal device's workflow in the wireless communication system shown are as follows:

[0161] S310: Low-Earth orbit satellites periodically transmit downlink SSB signals to terminal devices. In the 5G system, SSB signals include PSS (Primary Synchronization Signal), SSS (Secondary Synchronization Signals), and PBCH (Physical Broadcast Channel) broadcast signals. Specifically, the PSS signal has 0 OFDM symbols and 56–182 subcarriers; the SSS signal has 2 OFDM symbols and 56–182 subcarriers.

[0162] S320: The terminal equipment receives the downlink SSB signal transmitted by the low-orbit satellite, processes it through FFT (Fast Fourier Transform), extracts the PSS signal, and represents it as r(n);

[0163] S330: The extracted PSS signal r(n) and the modulated signal s(n) of the local PSS sequence are used to perform corresponding calculations to obtain the second time delay estimate d;

[0164] Step S340: The terminal device performs delay compensation on the transmitted uplink channel based on the second delay estimate d.

[0165] In some embodiments, step S330 can be implemented using the following sub-steps:

[0166] S331: Perform differential correlation operation on the signal r(d+n) and the signal r(d+n+1) delayed by one sampling point to obtain y. 1,d (n), the calculation expression is as follows:

[0167] y 1,d (n)=r(d+n)*r * (d+n+1)

[0168] =s(n)e j2πεn / N *s * ((n+1)modN PSS )e -j2πε(n+1) / N

[0169] =s(n)s * ((n+1)modN PSS )e -j2πε / N

[0170] Where d is the current position of the sliding window, i.e., the second time delay estimate to be calculated, r(d+n) is the extracted PSS signal r(n) after sliding d, and N PSS The length of the local PSS sequence is represented by N, where N is the number of FFT points and ε is the normalized frequency offset.

[0171] S332: Perform a differential correlation operation between the local PSS sequence and itself to obtain y. 2i (n), the calculation expression is as follows:

[0172] y 2i (n)=s i (n)*s i * ((n+1)modN PSS ), i∈{0,1,2}

[0173] S333: y 1,d (n) and Perform cross-correlation to obtain c i,d The calculation expression is as follows:

[0174]

[0175] Based on the structural characteristics of PN sequences (pseudo-noise sequences), Q can be determined to be a fixed value; due to the phase rotation factor e -j2πε / NThe magnitude is independent of the value of n, indicating that the signal attenuation amplitude is the same at each point, therefore the correlation function c i,d The peak value is not affected by frequency shift. Therefore, comparing the correlation function c i,d The three peak values ​​are used to obtain the maximum peak value. The i corresponding to this maximum peak value is the PSS signal index, which is the index within the cell group. The corresponding d is the starting position of the PSS signal, which is also the second time delay estimate to be calculated.

[0176] It should be noted that terminal devices typically have a processor and a memory. The processor can be used to implement the third processing module 210 and the fourth processing module 220 mentioned above, and the above-mentioned delay compensation process can be executed by executing computer program commands stored in the memory.

[0177] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An uplink channel time synchronization device, the device being applied to network equipment, characterized in that, include: The first storage module is used to cache the received first data; A first processing module is used to process the second data in the first storage module to obtain a first latency estimate, and to process the third data in the first storage module based on the first latency estimate; the second data is a part of the first data, and the third data is the remaining data in the first data starting from the first latency estimate.

2. The uplink channel time synchronization device according to claim 1, characterized in that, The first processing module includes: The first computing unit is used to process the second data to obtain the first processed data; The second computing unit is used to process the first processed data to obtain a first time delay estimate.

3. The uplink channel time synchronization device according to claim 2, characterized in that, The second computing unit performs correlation calculations on the first processed data based on DMRS to obtain a first time delay estimate.

4. The uplink channel time synchronization device according to claim 3, characterized in that, The second calculation unit is specifically used for: Based on the local DMRS sequence and the DMRS signal in the first processed data, a correlation operation is performed to obtain the maximum value of the correlation operation result and its corresponding position; A first time delay estimate is obtained based on the corresponding location.

5. The uplink channel time synchronization device according to claim 4, characterized in that, The corresponding position is determined based on the maximum value and the first threshold.

6. The uplink channel time synchronization device according to claim 2, characterized in that, The first processing module further includes: First storage control unit; The first processing module reads and writes data in the first storage module based on the first storage control unit.

7. The uplink channel time synchronization device according to claim 6, characterized in that, The first processing module further includes: The first interface is used to transmit the received first data to the first storage control unit.

8. The uplink channel time synchronization device according to claim 1, characterized in that, The device further includes: The data acquisition module is used to receive raw data and perform analog-to-digital conversion to obtain the first data.

9. The uplink channel time synchronization device according to claim 2, characterized in that, The first processing module further includes: Third calculation unit; The first computing unit is also used to process the third data to obtain second processed data; The third computing unit is used to perform CP cyclic prefix removal processing on the second processed data to obtain the third processed data.

10. The uplink channel time synchronization device according to claim 9, characterized in that, The first calculation unit processes the third data in units of the length of the second data.

11. The uplink channel time synchronization device according to any one of claims 2-10, characterized in that, The first calculation unit is an FFT processing module.

12. The uplink channel time synchronization device according to claim 9, characterized in that, The device further includes: The second storage module is used to cache the data processed by the third party.

13. The uplink channel time synchronization device according to claim 12, characterized in that, The first processing module further includes: Second storage control unit; The first processing module reads and writes data in the second storage module based on the second storage control unit.

14. The uplink channel time synchronization device according to claim 13, characterized in that, The first processing module further includes: The second interface is used to output data from the second storage module.

15. The uplink channel time synchronization device according to claim 14, characterized in that, The device further includes: The second processing module is used to perform subsequent processing on the data output from the second storage module.

16. The uplink channel time synchronization device according to claim 6 or 7, characterized in that, The first storage module uses DDR memory; the first storage control unit uses a DDR memory controller.

17. The uplink channel time synchronization device according to any one of claims 13-15, characterized in that, The second storage module uses DDR memory; the second storage control unit uses a DDR memory controller.

18. The uplink channel time synchronization device according to claim 15, characterized in that, Both the first processing module and the second processing module are implemented using FPGA.

19. A network device, characterized in that, The network device is equipped with an uplink channel time synchronization device as described in any one of claims 1-18.

20. An uplink channel time synchronization method, the method being applied to a network device, characterized in that, include: Buffer the first received data; The second data is processed to obtain a first time delay estimate, where the second data is a part of the first data. The third data is processed, and the third data is the remaining data in the first data that starts from the first time delay estimate.

21. The uplink channel time synchronization method according to claim 20, characterized in that, The processing of the second data includes: The second data is processed to obtain the first processed data; The first processed data is processed to obtain a first time delay estimate.

22. The uplink channel time synchronization method according to claim 21, characterized in that, Based on DMRS, correlation calculations are performed on the first processed data to obtain the first time delay estimate.

23. The uplink channel time synchronization method according to claim 22, characterized in that, The correlation calculation based on DMRS on the first processed data includes: Based on the local DMRS sequence and the DMRS signal in the first processed data, a correlation operation is performed to obtain the maximum value of the correlation operation result and its corresponding position; A first time delay estimate is obtained based on the corresponding location.

24. The uplink channel time synchronization method according to claim 23, characterized in that, Obtaining the corresponding position includes: The corresponding position is determined based on the maximum value and the first threshold.

25. The uplink channel time synchronization method according to any one of claims 20-24, characterized in that, The processing of the third data includes: The third data is processed to obtain the second processed data; The second processed data is subjected to CP cyclic prefix removal to obtain the third processed data.

26. The uplink channel time synchronization method according to claim 25, characterized in that, The third data is processed in units of the length of the second data.

27. The uplink channel time synchronization method according to claim 25, characterized in that, Both the second and third data are processed using FFT.

28. The uplink channel time synchronization method according to claim 25, characterized in that, The method further includes: The third processed data is cached.

29. The uplink channel time synchronization method according to claim 28, characterized in that, The method further includes: Read the cached third-party processing data and perform subsequent processing.

30. An electronic device, characterized in that, include: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores instructions executable by the at least one processor, which executes the instructions stored in the memory to perform the method as described in any one of claims 20-29.

31. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store instructions that, when executed, cause the method as described in any one of claims 20-29 to be implemented.

32. A computer program product, characterized in that, When the computer program product is invoked by a computer, it causes the computer to perform the method as described in any one of claims 20-29.

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