Thin film transistor, method of manufacturing same, and display device including same

Abstract

The invention relates to a thin film transistor, a method of manufacturing the same, and a display device including the same. The present disclosure provides a thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode, in which the active layer includes a first channel portion overlapping the source electrode, a second channel portion overlapping the drain electrode, and a connection portion connecting the first channel portion and the second channel portion, and the connection portion is a conductive region. In addition, a method of manufacturing the thin film transistor and a display device including the thin film transistor are disclosed.

Description

Technical Field

[0001] This disclosure relates to thin-film transistors, methods for manufacturing them, and display devices including the thin-film transistors. Background Technology

[0002] Thin-film transistors can be fabricated on glass or plastic substrates, and are therefore widely used as switching or driving elements in display devices such as liquid crystal displays or organic light-emitting devices.

[0003] Based on the material constituting the active layer, thin-film transistors can be classified into amorphous silicon thin-film transistors that use amorphous silicon as the active layer, polycrystalline silicon thin-film transistors that use polycrystalline silicon as the active layer, and oxide semiconductor thin-film transistors that use oxide semiconductors as the active layer.

[0004] Among these, oxide semiconductor thin-film transistors (OSTs), with their high mobility and large resistance variation with oxygen content, have the advantage of being able to easily achieve the desired characteristics. Since the oxide constituting the active layer can be formed at relatively low temperatures during the manufacturing process of OSTs, the manufacturing cost is low. Furthermore, because oxide semiconductors are transparent due to the nature of oxides, they are also advantageous for realizing transparent displays.

[0005] High-resolution displays comprise a large number of thin-film transistors (TFTs). To accommodate a large number of TFTs within a given area, their size must be reduced. However, as the size of the TFTs decreases, the channel length also shortens, which can degrade the operational stability of the TFTs or cause characteristic deviations between multiple TFTs, potentially leading to a decline in the display quality of the display device.

[0006] For thin-film transistors (TFTs) to operate stably, the channel must have an effective channel length greater than a certain value. In the case of TFTs with a coplanar structure, control of the conductive region is important to ensure the channel length.

[0007] In thin-film transistors (TFTs), conductive regions may penetrate into the channel. If the length of the conductive region penetrating into the channel is not constant, the effective channel length of the TFT is not constant, and characteristic deviations may occur between TFTs. In particular, if the effective channel length is not constant in short-channel TFTs with short channel lengths, the characteristic deviations between TFTs become significant, making it difficult to manufacture large-area panels.

[0008] Therefore, in order to manufacture high-resolution display devices with excellent display quality, it is necessary to increase the integration density of thin-film transistors by shortening the channel length of the thin-film transistors, while ensuring the uniformity of characteristics among the thin-film transistors. Summary of the Invention

[0009] One embodiment of this disclosure provides a technique for easily forming short channels by using source and drain electrodes as masks during the conductivity process.

[0010] One embodiment of this disclosure provides a technique for defining a channel portion by using source and drain electrodes as masks during conductivity. Another embodiment of this disclosure provides a technique that allows the channel portion to be defined by self-alignment because it is defined by source and drain electrodes.

[0011] One embodiment of this disclosure provides a thin-film transistor with a short channel of short length while exhibiting excellent uniformity.

[0012] One embodiment of this disclosure provides a method for manufacturing a thin-film transistor in which the source and drain electrodes are used as masks for a conductivity process.

[0013] Another embodiment of this disclosure is to provide a display device including a thin-film transistor.

[0014] In one embodiment, the thin-film transistor includes: a gate electrode; an active layer spaced apart from and at least partially overlapping the gate electrode; an interlayer insulating layer located on the active layer; a source electrode located on the interlayer insulating layer and connected to the active layer; and a drain electrode located on the interlayer insulating layer and spaced apart from the source electrode and connected to the active layer, wherein the active layer includes: a first channel portion overlapping the source electrode and the gate electrode, the first channel portion being located between the source electrode and the gate electrode; a second channel portion overlapping the drain electrode and the gate electrode, the second channel portion being located between the drain electrode and the gate electrode; and a connection portion located between the first channel portion and the second channel portion, the connection portion connecting the first channel portion and the second channel portion, wherein the connection portion is a conductive region.

[0015] In one embodiment, the thin-film transistor includes: a gate electrode; an active layer spaced apart from and at least partially overlapping the gate electrode; and a source electrode connected to the active layer, wherein the active layer includes: a channel portion overlapping the source electrode and the gate electrode; a contact portion contacting the source electrode; and a connection portion not overlapping the source electrode, wherein the channel portion is located between the connection portion and the contact portion, and the connection portion is a conductive region.

[0016] In one embodiment, a method for manufacturing a thin-film transistor includes the following steps: forming a gate electrode on a substrate; forming an active layer on the gate electrode, the active layer being spaced apart from and at least partially overlapping the gate electrode; forming an interlayer insulating layer on the active layer, the interlayer insulating layer having contact holes; forming a source electrode and a drain electrode on the interlayer insulating layer, and selectively conductively conducting the source electrode and the drain electrode using the source electrode and the drain electrode as masks.

[0017] In one embodiment, the display device includes: a substrate; a gate electrode located on the substrate; a gate insulating layer located on the gate electrode; an active layer located on the gate insulating layer, the active layer including a connection portion having a first end and a second end opposite to the first end, a first channel portion contacting the first end of the connection portion, and a second channel portion contacting the second end of the connection portion; an interlayer insulating layer located on the active layer; a source electrode and a drain electrode located on the interlayer insulating layer and spaced apart from each other, the source electrode and the drain electrode being connected to the active layer; and a light-emitting element emitting light, the light-emitting element being connected to one of the source electrode or the drain electrode, wherein the connection portion of the active layer does not overlap with the source electrode and the drain electrode. Attached Figure Description

[0018] The purpose, features, and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a plan view of a thin-film transistor according to one embodiment of the present disclosure.

[0020] Figure 2 It is according to one embodiment of this disclosure along Figure 1 The cross-sectional view taken from line I-I'.

[0021] Figure 3 This is a circuit diagram of a thin-film transistor according to one embodiment of the present disclosure.

[0022] Figure 4 This is a plan view of a thin-film transistor according to another embodiment of the present disclosure.

[0023] Figure 5 It is according to one embodiment of this disclosure along Figure 4 The cross-sectional view taken from line II-II'.

[0024] Figure 6 This is a cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0025] Figure 7 This is a cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0026] Figure 8 This is a cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0027] Figure 9 This is a cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0028] Figures 10A to 10E This is a schematic cross-sectional view illustrating a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure.

[0029] Figure 11 This is a schematic diagram of a display device according to another embodiment of the present disclosure.

[0030] Figure 12 This is according to one embodiment of the present disclosure. Figure 11 A circuit diagram for one pixel.

[0031] Figure 13 This is according to one embodiment of the present disclosure. Figure 12 A planar image of pixels.

[0032] Figure 14 It is according to one embodiment of this disclosure along Figure 13 The cross-sectional view taken from line III-III'. Detailed Implementation

[0033] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. These embodiments are intended to make the disclosure complete and to enable those skilled in the art to readily understand it.

[0034] The shapes, sizes, proportions, angles, quantities, etc., disclosed in the accompanying drawings used to illustrate embodiments of this disclosure are exemplary, and this disclosure is not limited to the matters shown in the drawings. Throughout the specification, the same components may be represented by the same reference numerals. Furthermore, in interpreting this disclosure, if it is determined that a detailed description of relevant known technologies might unnecessarily obscure the spirit of this disclosure, such a detailed description will be omitted.

[0035] In this specification, when the words "including," "having," "containing," etc., are used, other components may be added unless the expression "only" is used. When a component is referred to in the singular, the plural is included unless otherwise expressly stated.

[0036] When interpreting a component, it is interpreted as including a range of errors, even if there is no separate explicit description.

[0037] For example, when the positional relationship between two components is described as “~above,” “~above,” “~below,” “adjacent to ~,” etc., one or more other components may be located between the two components unless the expressions “exactly” or “directly” are used.

[0038] As illustrated in the accompanying drawings, the spatial relative terms “below,” “under,” “lower,” “above,” “upper,” etc., are used to readily describe the relationship of one element or component to another. In addition to the orientations depicted in the drawings, the spatial relative terms should be understood to include different orientations of the elements during use or operation. For example, if the elements shown in the drawings are flipped, an element described as “below” or “under” another element may end up being placed “above” another element. Thus, the exemplary term “below” can include both the above and below directions. Similarly, the exemplary terms “above” or “upper” can include both the above and below directions.

[0039] When describing temporal relationships, such as those described as "after", "following", "next", "before", etc., situations without continuity can be included as long as the expressions "immediately" or "directly" are used.

[0040] Although the terms first, second, etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can also be a second component within the technical concept of this disclosure.

[0041] At least one term should be understood to include all combinations that can be represented by one or more related items. For example, the meaning of "at least one of the first, second, and third items" can mean not only each of the first, second, or third items, but also all combinations of items that can be represented by two or more of the first, second, and third items.

[0042] Individual features of the various embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically linked and driven in various ways, and each embodiment may be implemented independently of each other or together in a related relationship.

[0043] When reference numerals are added to components in each figure describing embodiments of the present disclosure, the same components may have the same reference numerals even if they are shown in different figures.

[0044] In the embodiments of this disclosure, the source electrode and drain electrode are distinguished only for ease of explanation, and the source electrode and drain electrode are interchangeable. Furthermore, the source electrode of one embodiment can become the drain electrode of another embodiment, and the drain electrode of one embodiment can become the source electrode of another embodiment.

[0045] In some embodiments of this disclosure, for ease of explanation, a source connection portion and a source electrode are distinguished, and a drain connection portion and a drain electrode are distinguished, but the embodiments of this disclosure are not limited thereto. The source connection portion can be a source electrode, and the drain connection portion can be a drain electrode. Alternatively, the source connection portion can be a drain electrode, and the drain connection portion can be a source electrode.

[0046] Figure 1 This is a plan view of a thin-film transistor 100 according to one embodiment of the present disclosure, and Figure 2 It is according to one embodiment of this disclosure along Figure 1 The cross-sectional view taken from line I-I'.

[0047] Reference Figure 1 and Figure 2 According to one embodiment of the present disclosure, a thin-film transistor 100 includes a gate electrode 150, an active layer 130, a source electrode 161, and a drain electrode 162. The active layer 130 includes a first channel portion CN1, a second channel portion CN2, and a connection portion 130c.

[0048] Reference Figure 2 The thin-film transistor 100 can be disposed on the substrate 110.

[0049] The substrate 110 supports the components of the thin-film transistor 100. The substrate 110 can be any structure that supports the thin-film transistor 100, but is not limited thereto.

[0050] A glass substrate or a polymer resin substrate can be used as substrate 110. The plastic substrate is a polymer resin substrate. The plastic substrate may include at least one of polyimide (PI), polycarbonate (PC), polyethylene (PE), polyester, polyethylene terephthalate (PET), and polystyrene (PS) having flexible properties. When using plastic as substrate 110, considering the high-temperature deposition process performed on substrate 110, a heat-resistant plastic capable of withstanding high temperatures can be used.

[0051] The gate electrode 150 is disposed on the substrate 110.

[0052] According to one embodiment of the present disclosure, a buffer layer may be disposed on a substrate 110, and a gate electrode 150 may be disposed on the buffer layer.

[0053] The gate electrode 150 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may also have a multilayer structure comprising at least two conductive layers with different physical properties.

[0054] A gate insulating layer 140 is disposed on the gate electrode 150.

[0055] According to one embodiment of this disclosure, the gate insulating layer 140 may be configured to cover the entire upper surface of the gate electrode 150. (See also...) Figure 2 The gate insulating layer 140 can be configured to cover the entire upper surface of the substrate 110.

[0056] The gate insulating layer 140 may be made of at least one insulating material. The gate insulating layer 140 may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), and aluminum oxide (AlOx).

[0057] The gate insulating layer 140 can have a single-layer structure or a multi-layer structure.

[0058] The active layer 130 is disposed on the gate insulating layer 140.

[0059] The active layer 130 is spaced apart from the gate electrode 150 in the vertical direction relative to the substrate 110 and at least partially overlaps the gate electrode 150. In one embodiment, the width of the active layer 130 is smaller than the width of the gate electrode 150, and the active layer 130 completely overlaps the gate electrode 150.

[0060] According to one embodiment of this disclosure, the active layer 130 may include an oxide semiconductor material. According to one embodiment of this disclosure, the active layer 130 may be, for example, an oxide semiconductor layer made of an oxide semiconductor material.

[0061] The active layer 130 may include at least one of oxide semiconductor materials (e.g., IGZO (InGaZnO)-based, IGO (InGaO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, GO (GaO)-based, TO (SnO)-based, ITO-based (InSnO)-based, ITZO (InSnZnO)-based, IZO (InZnO)-based, ZO (ZnO)-based, InO (InO)-based, ZnO-based, and FIZO (FeZnO)-based).

[0062] The active layer 130 may have a single-layer structure or a multilayer structure including two or more oxide semiconductor layers. The active layer 130 may include a channel portion CN1 (e.g., a first channel portion), a channel portion CN2 (e.g., a second channel portion), and a connection portion 130c. The specific configuration of the active layer 130 will be described later.

[0063] The interlayer insulation layer 170 can be disposed on the active layer 130.

[0064] Interlayer insulation 170 is an insulating layer made of insulating material. Interlayer insulation 170 can have a single-layer or multi-layer structure. Interlayer insulation 170 can be made of organic or inorganic materials. Furthermore, interlayer insulation 170 can be made of a laminate of organic and inorganic layers.

[0065] Source electrode 161 and drain electrode 162 are disposed on interlayer insulating layer 170. Therefore, source electrode 161 and drain electrode 162 are located on the same plane. Source electrode 161 is connected to active layer 130. In addition, drain electrode 162 is horizontally spaced from source electrode 161 and connected to active layer 130. Source electrode 161 and drain electrode 162 can be connected to active layer 130 respectively through contact holes CH1 and CH2 passing through interlayer insulating layer 170.

[0066] The source electrode 161 and the drain electrode 162 may each comprise at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. The source electrode 161 and the drain electrode 162 may each be formed from a single layer of metal or metal alloy, or may be formed from two or more multilayers.

[0067] The active layer 130 is described in more detail below.

[0068] According to one embodiment of the present disclosure, the active layer 130 includes a first channel portion CN1, a second channel portion CN2, and a connecting portion 130c.

[0069] The first channel portion CN1 overlaps with the gate electrode 150 and the source electrode 161. The first channel portion CN1 is disposed between the gate electrode 150 and the source electrode 161. The second channel portion CN2 overlaps with the gate electrode 150 and the drain electrode 162. The second channel portion CN2 is disposed between the gate electrode 150 and the drain electrode 162.

[0070] The first channel portion CN1 and the second channel portion CN2 have semiconductor characteristics. Depending on the voltage applied to the gate electrode 150, the first channel portion CN1 and the second channel portion CN2 may have electrical characteristics similar to those of a conductor or similar to those of an insulator.

[0071] The connecting part 130c connects the first channel part CN1 and the second channel part CN2. (See reference...) Figure 1 and Figure 2 The connecting portion 130c is disposed between the first channel portion CN1 and the second channel portion CN2. The first side (e.g., the first end) of the connecting portion 130c can contact the first channel portion CN1, and the second side (e.g., the second end) of the connecting portion 130c opposite to the first side can contact the second channel portion CN2.

[0072] Reference Figure 1 and Figure 2 The connecting portion 130c may overlap with the gate electrode 150. The connecting portion 130c may be disposed on the gate electrode 150.

[0073] According to one embodiment of this disclosure, the connection portion 130c is a conductive region. Specifically, the connection portion 130c is a region in which a portion of the semiconductor material constituting the active layer 130 is selectively conductive.

[0074] According to one embodiment of this disclosure, the connecting portion 130C may be referred to as a conductive portion.

[0075] According to one embodiment of this disclosure, the connection portion 130c can be formed by selectively conductiveizing the active layer 130. Specifically, a portion of the oxide semiconductor material constituting the active layer 130 can be conductive to form the connection portion 130c.

[0076] According to one embodiment of this disclosure, the connection portion 130c is formed by selectively conductiveizing the active layer 130. For example, the connection portion 130c can also be formed by selectively conductiveizing the oxide semiconductor material constituting the active layer 130. According to one embodiment of this disclosure, selective conductiveizing can also be referred to as metallization.

[0077] According to one embodiment of this disclosure, selective conductivity refers to improving the conductivity of selected portions of the active layer 130 or imparting conductivity to selected portions. The selectively conductive portions of the active layer 130 can possess excellent conductivity.

[0078] According to one embodiment of this disclosure, for example, a region of the active layer 130 that does not overlap with the source electrode 161 or the drain electrode 162 (e.g., does not overlap) can be selectively conductive. Therefore, according to one embodiment of this disclosure, the connection portion 130c does not overlap with the source electrode 161 or the drain electrode 162 (e.g., does not overlap).

[0079] As a result of conductivity, the connector 130c can have electrical properties similar to those of a conductor. Specifically, the connector 130c can have electrical properties similar to those of a metal.

[0080] On the other hand, the first channel CN1 and the second channel CN2 are non-conductive regions.

[0081] As a result of selective conductivity, the connection portion 130c may have a higher carrier concentration than the first channel portion CN1 and the second channel portion CN2. The carrier concentration of the connection portion 130c may be higher than the carrier concentration of the first channel portion CN1 and the second channel portion CN2.

[0082] For example, when the thin-film transistor 100 is in the off state, the first channel portion CN1 and the second channel portion CN2 can each have approximately 1.0 × 10⁻⁶ Ω·cm. 16 ea / cm 3 Up to 1.0×10 18 ea / cm 3 The carrier concentration. The connector 130c can have a carrier concentration of 1.0 × 10⁻⁶. 21 ea / cm 3 or higher carrier concentration.

[0083] Furthermore, the connecting portion 130c may have a lower resistivity than the first channel portion CN1 and the second channel portion CN2. For example, the connecting portion 130c may have a resistivity of 10. -4 Ω·cm or less resistivity. When the thin-film transistor 100 is in the off state, the first channel CN1 and the second channel CN2 can each have a resistivity of approximately 10 Ω·cm or less. -5 Resistivity from Ω·cm to approximately 108Ω·cm.

[0084] According to one embodiment of this disclosure, selective conductivity of the active layer 130 can be performed by doping with a dopant, dry etching, or plasma treatment.

[0085] According to one embodiment of this disclosure, doping can be performed by ion implantation. For example, selective conductivity can be performed by using source electrode 161 and drain electrode 162 as masks to dope dopant ions into selected regions of the active layer 130 via ion implantation. According to one embodiment of this disclosure, the dopant may include at least one of boron (B), phosphorus (P), fluorine (F), arsenic (As), and hydrogen (H).

[0086] When selective conductivity is achieved in the active layer 130 via dopant ion implantation, the connection portion 130c can be doped with a dopant. On the other hand, dopant doping of the first channel portion CN1 and the second channel portion CN2 is prevented. Therefore, according to one embodiment of this disclosure, the connection portion 130c can be defined as a region doped with a dopant. The dopant concentration of the connection portion 130c can be higher than the dopant concentration of the first channel portion CN1 and the second channel portion CN2. Here, the dopant may include at least one of boron (B), phosphorus (P), fluorine (F), arsenic (As), and hydrogen (H).

[0087] In addition, the connecting portion 130c may have a higher dopant concentration than the first contact portion 130a and the second contact portion 130b.

[0088] However, one embodiment of this disclosure is not limited to this, and the connection portion 130c can be formed in other ways. According to one embodiment of this disclosure, the connection portion 130c can be formed by selectively conductiveizing the active layer 130 via dry etching or plasma treatment. For example, dry etching or plasma treatment can be performed during the process of patterning the interlayer insulating layer 170 or forming contact holes CH1, CH2 in the interlayer insulating layer 170, at which time selective conductiveizing can be performed to form the connection portion 130c.

[0089] When the active layer 130 is selectively conductive by dry etching or plasma treatment, the hydrogen (H) concentration of the connection portion 130c can be higher than the hydrogen (H) concentration of the first channel portion CN1 and the hydrogen (H) concentration of the second channel portion CN2.

[0090] The source electrode 161 is connected to the active layer 130 through a first contact hole CH1 formed in the interlayer insulating layer 170. The drain electrode 162 is connected to the active layer 130 through a second contact hole CH2 formed in the interlayer insulating layer 170.

[0091] According to one embodiment of this disclosure, during the formation of the first contact hole CH1 for connecting the source electrode 161 and the active layer 130, a portion of the active layer 130 may be made conductive.

[0092] During the formation of the first contact hole CH1, a portion of the active layer 130 can be made conductive. For example, the region of the active layer 130 overlapping with the first contact hole CH1 and its surrounding region can be selectively made conductive. The region of the active layer 130 that is made conductive during the formation of the first contact hole CH1 can have a higher hydrogen (H) concentration than the first channel portion CN1. Alternatively, the region of the active layer 130 that is made conductive during the formation of the first contact hole CH1 can have a lower oxygen (O) concentration than the first channel portion CN1.

[0093] According to one embodiment of this disclosure, the portion of the active layer 130 that contacts the source electrode 161 is referred to as the first contact portion 130a. The first contact portion 130a is the area of ​​the active layer 130 exposed from the interlayer insulating layer 170. The first contact portion 130a can be connected to the source electrode 161 through a first contact hole CH1 formed in the interlayer insulating layer 170.

[0094] According to one embodiment of this disclosure, the first contact portion 130a is a conductive region, and a portion of the surrounding region of the first contact portion 130a can also be conductive. As a result, the electrical signal of the source electrode 161 can be transmitted to the first channel portion CN1 of the active layer 130.

[0095] Furthermore, during the process of forming the second contact hole CH2, a portion of the active layer 130 can be made conductive. For example, the region of the active layer 130 overlapping with the second contact hole CH2 and its surrounding region can be selectively made conductive. The region of the active layer 130 that is made conductive during the process of forming the second contact hole CH2 can have a higher hydrogen (H) concentration than the second channel portion CN2. Additionally, the region of the active layer 130 that is made conductive during the process of forming the second contact hole CH2 can have a lower oxygen (O) concentration than the second channel portion CN2.

[0096] According to one embodiment of this disclosure, the portion of the active layer 130 that contacts the drain electrode 162 is referred to as the second contact portion 130b. The second contact portion 130b is the area of ​​the active layer 130 exposed from the interlayer insulating layer 170. The second contact portion 130b can be connected to the drain electrode 162 through a second contact hole CH2 formed in the interlayer insulating layer 170.

[0097] According to one embodiment of this disclosure, the second contact portion 130b is a conductive region. Additionally, a portion of the area surrounding the second contact portion 130b may also be conductive. As a result, the electrical signal of the second channel portion CN2 can be transmitted to the drain electrode 162.

[0098] Furthermore, when the connection portion 130c is formed by doping using the source electrode 161 and drain electrode 162 as masks, the first contact portion 130a is covered by the source electrode 161, and the second contact portion 130b is covered by the drain electrode 162. As a result, the first contact portion 130a and the second contact portion 130b will not be doped. Therefore, the first contact portion 130a and the second contact portion 130b can have a lower dopant concentration than the connection portion 130c.

[0099] According to one embodiment of this disclosure, the active layer 130 may include a first contact portion 130a that contacts the source electrode 161. Additionally, the active layer 130 may include a second contact portion 130b that contacts the drain electrode 162.

[0100] Reference Figure 1 and Figure 2 A first channel portion CN1 may be disposed between the connecting portion 130c and the first contact portion 130a. A first side of the first channel portion CN1 is connected to the first contact portion 130a, and a second side of the first channel portion CN1 opposite to the first side is connected to the connecting portion 130c. A second channel portion CN2 may be disposed between the connecting portion 130c and the second contact portion 130b. A first side of the second channel portion CN2 is connected to the connecting portion 130c, and a second side of the second channel portion CN2 is connected to the second contact portion 130b.

[0101] Figure 3 This is a circuit diagram of a thin-film transistor 100 according to one embodiment of the present disclosure.

[0102] Reference Figure 3 According to one embodiment of the present disclosure, the thin-film transistor 100 corresponds to a structure in which two sub-transistors sTR1 and sTR2 are connected in series.

[0103] According to one embodiment of the present disclosure, a thin-film transistor 100 may include a first sub-transistor sTR1 and a second sub-transistor sTR2. The first sub-transistor sTR1 and the second sub-transistor sTR2 are connected in series.

[0104] exist Figure 1 and Figure 2 In the thin-film transistor 100 shown, the gate electrode 150 can be the gate electrode G of each of the first sub-transistor sTR1 and the second sub-transistor sTR2.

[0105] Figure 1 and Figure 2 The first channel portion CN1 of the thin-film transistor 100 shown can be used as the channel portion of the first sub-transistor sTR1, and the second channel portion CN2 can be used as the channel portion of the second sub-transistor sTR2.

[0106] Figure 1 and Figure 2 The source electrode 161 of the thin-film transistor 100 shown can become the source electrode S of the first sub-transistor sTR1. Figure 1 and Figure 2 The connection portion 130c of the thin-film transistor 100 shown can become the drain electrode of the first sub-transistor sTR1.

[0107] in addition, Figure 1 and Figure 2The connection portion 130c of the thin-film transistor 100 shown can serve as the source electrode of the second sub-transistor sTR2. Figure 1 and Figure 2 The drain electrode 162 of the thin-film transistor 100 shown can become the drain electrode D of the second sub-transistor sTR2.

[0108] The first sub-transistor sTR1 may include a gate electrode 150, a channel portion CN1, a source electrode 161, and a drain electrode 130c. The second sub-transistor sTR2 may include a gate electrode 150, a channel portion CN2, a source electrode 130c, and a drain electrode 162.

[0109] According to one embodiment of this disclosure, since a voltage is applied to the source electrode 161, an electric field can be applied to both the upper and lower sides of the first channel portion CN1. At this time, a constant source voltage can be applied to the source electrode 161, thereby generating a saturation drive effect where a constant voltage flows through the first channel portion CN1.

[0110] According to one embodiment of this disclosure, when the interlayer insulating layer 170 has a similar thickness to the gate insulating layer 140, the first sub-transistor sTR1 can have the electrical characteristics of a dual-gate structure.

[0111] Furthermore, when the thicknesses of the interlayer insulating layer 170 and the gate insulating layer 140 are different, a bias voltage that changes the threshold voltage is applied through the source electrode, thereby enabling control of the threshold voltage of the first sub-transistor sTR1.

[0112] According to one embodiment of this disclosure, since a voltage is applied to the drain electrode 162, an electric field can be applied to both the upper and lower portions of the second channel portion CN2. When the interlayer insulating layer 170 has a similar thickness to the gate insulating layer 140, the second sub-transistor sTR2 can have the electrical characteristics of a dual-gate structure. Furthermore, when the thicknesses of the interlayer insulating layer 170 and the gate insulating layer 140 are different, a bias voltage that changes the threshold voltage is applied by the drain electrode 162, thereby allowing control of the threshold voltage of the second sub-transistor sTR2. Figure 4 This is a plan view of a thin-film transistor 200 according to another embodiment of the present disclosure, and Figure 5 It is according to one embodiment along Figure 4 The cross-sectional view taken from line II-II'.

[0113] In the following text, to avoid repetition, descriptions of already described components will be omitted, or only a brief description of already described components will be provided.

[0114] Reference Figure 4 and Figure 5 At least a portion of the connecting portion 130c may not overlap with the gate electrode 150.

[0115] Specifically, according to another embodiment of this disclosure, the gate electrode 150 may include a first gate electrode 151 and a second gate electrode 152. The first gate electrode 151 overlaps with the first channel portion CN1 and the source electrode 161. The second gate electrode 152 may overlap with the second channel portion CN2 and the drain electrode 162. The first gate electrode 151 and the second gate electrode 152 may be connected to each other via a connecting electrode 155.

[0116] Reference Figure 4 and Figure 5 At least a portion of the connection portion 130c does not overlap with the first gate electrode 151 and the second gate electrode 152 (e.g., they do not overlap). Specifically, at least a portion of the connection portion 130c may not overlap with the first gate electrode 151 or the second gate electrode 152.

[0117] Figure 6 This is a cross-sectional view of a thin-film transistor 300 according to another embodiment of the present disclosure.

[0118] Reference Figure 6 The thin-film transistor 300 includes an interlayer insulating layer 170 disposed between the active layer 130 and the source electrode 161, and between the active layer 130 and the drain electrode 162. A connection portion 130c is exposed from the interlayer insulating layer 170. That is, the interlayer insulating layer 170 and the connection portion 130c do not overlap.

[0119] Reference Figure 6 During the process of patterning the interlayer insulating layer 170 to expose a portion of the active layer 130 from the interlayer insulating layer 170, a portion of the active layer 130 can be made conductive.

[0120] For example, in order to expose a portion of the active layer 130 from the interlayer insulating layer 170, a portion of the interlayer insulating layer 170 can be removed by a dry etching method. During this dry etching process, a portion of the active layer 130 can be selectively conductive to form a connection 130c.

[0121] Alternatively, selective conductivity of the active layer 130 can be achieved by plasma treatment of the region of the active layer 130 exposed from the interlayer insulating layer 170. This allows the connection portion 130c to be formed.

[0122] Figure 7 This is a cross-sectional view of a thin-film transistor 400 according to another embodiment of the present disclosure.

[0123] Reference Figure 7According to another embodiment of the present disclosure, the thin-film transistor 400 may further include a cover layer 145 disposed on the connection portion 130c. The cover layer 145 is in contact with the connection portion 130c. The cover layer 145 has reduction properties (same as reduction property).

[0124] According to another embodiment of this disclosure, reducing properties refer to the property of reducing another substance. When a substance has reducing properties, it means that the substance has the property of reducing another substance when it is oxidized. A reducing substance has the property of being oxidized itself and the property of reducing another substance.

[0125] According to another embodiment of this disclosure, the capping layer 145 has reducing properties, which allows it to reduce other substances. According to another embodiment of this disclosure, the capping layer 145 is made of a material that is easily oxidized and can reduce other substances.

[0126] According to another embodiment of this disclosure, the cover layer 145 may contact the active layer 130.

[0127] The area of ​​the active layer 130 that contacts the capping layer 145 can be selectively reduced. As a result of this reduction, the area of ​​the active layer 130 that contacts the capping layer 145 has metal-like properties and can be made conductive.

[0128] According to another embodiment of this disclosure, the active layer 130 can be selectively conductive through the cover layer 145 to form the connection portion 130c.

[0129] The capping layer 145 may include reducing materials. For example, the capping layer 145 may include at least one of titanium (Ti), molybdenum (Mo), aluminum (Al), indium (In), and zinc (Zn). The capping layer 145 may also include metal oxides. The capping layer may include, for example, at least one of ZnO-based oxides, IZO (InZnO)-based oxides, IGZO (InGaZnO)-based oxides, ITO (InSnO)-based oxides, InO-based oxides, and ZnON-based oxides having a low oxygen concentration. When indium and oxides of different metals are used as the capping layer 145, the indium content may be 50% or more based on the number of atoms relative to the total metal content.

[0130] The oxide applied to the capping layer 145 has a low oxidation number and can be easily oxidized. The oxide applied to the capping layer 145 may have an oxygen (O) content lower than that at its stoichiometric stable state. As a result, when the capping layer 145 contacts the active layer 130, the capping layer 145 is oxidized, and the portion of the active layer 130 in contact with the capping layer 145 can be reduced. Consequently, the portion of the active layer 130 in contact with the capping layer 145 has near-metallic properties and can serve as a connection 130c.

[0131] A passivation layer 175 may be disposed on a capping layer 145. The passivation layer 175 protects the active layer 130 and the capping layer 145.

[0132] Figure 8 This is a cross-sectional view of a thin-film transistor 500 according to another embodiment of the present disclosure.

[0133] Reference Figure 8 The active layer 130 may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131.

[0134] The first oxide semiconductor layer 131 can be used as a support layer to support the second oxide semiconductor layer 132. The second oxide semiconductor layer 132 can be used as the main channel layer.

[0135] The first oxide semiconductor layer 131, used as a support layer, can exhibit excellent film stability and mechanical stability. The first oxide semiconductor layer 131 may comprise at least one of, for example, IGO (InGaO)-based oxide semiconductor materials, IGZO (InGaZnO)-based oxide semiconductor materials, IGZTO (InGaZnSnO)-based oxide semiconductor materials, GZTO (GaZnSnO)-based oxide semiconductor materials, GZO (GaZnSnO)-based oxide semiconductor materials, and GO (GaO)-based oxide semiconductor materials. However, one embodiment of this disclosure is not limited thereto, and the first oxide semiconductor layer 131 may be made of other oxide semiconductor materials known in the art.

[0136] The second oxide semiconductor layer 132 may comprise at least one oxide semiconductor material selected from IZO (InZnO)-based, FIZO (FeInZnO)-based, TO (SnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, ITZO (InSnZnO), and IO (InO)-based. However, one embodiment of this disclosure is not limited thereto, and the second oxide semiconductor layer 132 may be formed from other oxide semiconductor materials known in the art.

[0137] Figure 9 This is a cross-sectional view of a thin-film transistor 600 according to another embodiment of the present disclosure.

[0138] According to another embodiment of the present disclosure, a thin-film transistor 600 includes a gate electrode 150, an active layer 130 spaced apart from and at least partially overlapping the gate electrode 150, and a source electrode 161 connected to the active layer 130.

[0139] The active layer 130 includes a channel portion CN, a connecting portion 130d, and a contact portion 130e.

[0140] Reference Figure 9 The channel portion CN of the active layer 130 overlaps with the source electrode 161 and the gate electrode 150. The channel portion CN is disposed between the connecting portion 130d and the contact portion 130e.

[0141] The contact portion 130e can contact the source electrode 161. The contact portion 130e can contact the source electrode 161 through the contact hole CH.

[0142] The connection portion 130d does not overlap with the source electrode 161 (e.g., it does not overlap). The connection portion 130d is a conductive region. Specifically, the connection portion 130d is a region in which a portion of the semiconductor material constituting the active layer 130 is selectively conductive. As a result of selective conductivity, the connection portion 130d can have a higher carrier concentration than the channel portion CN1.

[0143] When selective conductivity of the active layer 130 is performed by dopant ion implantation using the source electrode 161 as a mask, the connection portion 130d may be doped with a dopant. On the other hand, dopant doping of the channel portion CN is prevented. Therefore, according to one embodiment of this disclosure, the dopant concentration of the connection portion 130c may be higher than the dopant concentration of the channel portion CN. Here, the dopant may include at least one of boron (B), phosphorus (P), fluorine (F), arsenic (As), and hydrogen (H).

[0144] Furthermore, when the source electrode 161 is used as a mask to form the connection portion 130d by doping, the contact portion 130e is covered by the source electrode 161, and no doping occurs in the contact portion 130e. Therefore, the contact portion 130e can have a lower dopant concentration than the connection portion 130d.

[0145] According to another embodiment of this disclosure, the connection portion 130d is connected to one side of the channel portion CN. Therefore, the connection portion 130d can be used as a drain connection portion, and the connection portion 130d can be used as a drain electrode 162. Therefore, according to another embodiment of this disclosure, the connection portion 130d can also be referred to as the drain electrode 162. In one embodiment, the first end of the connection portion 130d connected to the channel portion CN is at a first height relative to the substrate 110, which is higher than the height of the second end of the connection portion 130d. In one embodiment, the second end of the connection portion 130d is located on the side surface of the gate insulating layer 140.

[0146] In the embodiments of this disclosure, the source electrode 161 and the drain electrode 162 are distinguished only for ease of explanation; the source electrode 161 and the drain electrode 162 are interchangeable. Figure 9 In this configuration, the source electrode 161 can be used as the drain electrode, and the connection portion 130d can be used as the source electrode.

[0147] Figures 10A to 10E This is a schematic cross-sectional view illustrating a method for manufacturing a thin-film transistor 100 according to another embodiment of the present disclosure.

[0148] A method for manufacturing a thin-film transistor 100 according to another embodiment of the present disclosure includes the following steps: forming a gate electrode 150 on a substrate 110, forming an active layer 130 on the gate electrode, the active layer 130 being spaced apart from the gate electrode 150, forming an interlayer insulating layer 170 having contact holes on the active layer 130, forming a source electrode 161 and a drain electrode 162 on the interlayer insulating layer 170, and selectively using the source electrode 161 and the drain electrode 162 as a mask to make the active layer 130 conductive.

[0149] First, refer to Figure 10A A gate electrode 150 is formed on the substrate 110.

[0150] Next, refer to Figure 10B A gate insulating layer 140 is formed on the gate electrode 150, and an active layer 130 is formed on the gate insulating layer 140.

[0151] An active layer 130 is formed on the gate electrode 150 so as to be spaced apart from the gate electrode 150 and at least partially overlap with the gate electrode 150.

[0152] Reference Figure 10CAn interlayer insulating layer 170 is formed on the active layer 130. The interlayer insulating layer 170 has contact holes CH1 and CH2. A portion of the active layer 130 can be exposed from the interlayer insulating layer 170 through the contact holes CH1 and CH2.

[0153] During the formation of contact holes CH1 and CH2, the active layer 130 can selectively conduct electricity to form the first contact portion 130a and the second contact portion 130b.

[0154] Specifically, during the formation of the first contact hole CH1, the area of ​​the active layer 130 exposed through the first contact hole CH1 and its surrounding area can be selectively made conductive. This allows the formation of the first contact portion 130a.

[0155] Furthermore, during the formation of the second contact hole CH2, the area of ​​the active layer 130 exposed through the second contact hole CH2 and its surrounding area can be selectively made conductive. This allows the formation of the second contact portion 130b.

[0156] Reference Figure 10D Source electrode 161 and drain electrode 162 are formed on interlayer insulating layer 170. Source electrode 161 and drain electrode 162 are spaced apart from each other and are each connected to active layer 130.

[0157] The source electrode 161 is connected to the active layer 130 through the first contact hole CH1. The source electrode 161 can contact the first contact portion 130a of the active layer 130.

[0158] The drain electrode 162 is connected to the active layer 130 through the second contact hole CH2. The drain electrode 162 can contact the second contact portion 130b of the active layer 130.

[0159] Next, as Figure 10D As shown, source electrode 161 and drain electrode 162 are used as masks to selectively conduct the active layer 130. Selective conduction refers to increasing the conductivity of a selected portion or imparting conductivity to a selected portion.

[0160] According to another embodiment of this disclosure, selective conductivity of the active layer 130 can be performed by doping with a dopant, dry etching, or plasma treatment.

[0161] Reference Figure 10D Selective conductivity can be performed by doping with a dopant. Doping can be performed by ion implantation. For example, selective conductivity can be performed by doping a dopant ion into a selected region of the active layer 130 by using the source electrode 161 and the drain electrode 162 as a mask. According to one embodiment of this disclosure, the dopant may include at least one of boron (B), phosphorus (P), fluorine (F), arsenic (As), and hydrogen (H).

[0162] Reference Figure 10E As a result of the selective conductivity of the active layer 130, a connection portion 130c is formed. As a result, a thin-film transistor 100 according to an embodiment of the present disclosure can be manufactured.

[0163] Another embodiment of this disclosure provides a display device including the above-described thin-film transistors 100, 200, 300, 400, 500, and 600.

[0164] Figure 11 This is a schematic diagram of a display device 700 according to another embodiment of the present disclosure.

[0165] like Figure 11 As shown, a display device 700 according to another embodiment of the present disclosure includes a display panel 310, a gating driver 320, a data driver 330, and a control unit 340 (e.g., a circuit).

[0166] The gate line GL and the data line DL are set on the display panel 310, and the pixel P is arranged in the intersection area of ​​the gate line GL and the data line DL. The image is displayed by driving the pixel P.

[0167] The control unit 340 controls the strobe driver 320 and the data driver 330.

[0168] The control unit 340 uses signals provided from an external system to output a gating control signal GCS for controlling the gating driver 320 and a data control signal DCS for controlling the data driver 330. Additionally, the control unit 340 samples input image data from the external system, rearranges it, and provides the rearranged digital image data (RGB) to the data driver 330.

[0169] The gating control signal GCS includes the gating start pulse GSP, the gating shift clock GSC, the gating output enable signal GOE, the start signal Vst, and the gating clock GCLK. Additionally, the gating control signal GCS may include control signals for controlling the shift register 350.

[0170] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0171] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the control unit 340 into analog data voltage and provides this data voltage to the data line DL.

[0172] The strobe driver 320 may include a shift register 350.

[0173] The shift register 350 uses a start signal and a gating clock sent from the control unit 340 to sequentially provide gating pulses to the gating line GL up to one frame. Here, one frame refers to the time period during which an image is output through the display panel 310. The gating pulse has a turn-on voltage that enables the thin-film transistors, the switching elements arranged in the pixel P, to conduct.

[0174] Additionally, shift register 350 provides a gating cutoff signal to gating line GL during the remaining period of a frame when no gating pulse is provided, which enables the switching elements to turn off. Hereinafter, the gating pulse and gating cutoff signal will be collectively referred to as the scan signal SS or Scan.

[0175] According to one embodiment of this disclosure, the gate driver 320 can be mounted on the substrate 110. As described above, the structure in which the gate driver 320 is directly mounted on the substrate 110 is called an in-panel gate (GIP) structure. The gate driver 320 may include at least one of the thin-film transistors 100, 200, 300, 400, and 500 described above.

[0176] Figure 12 It is aimed at Figure 11 A circuit diagram for a pixel P. Figure 13 It is based on one implementation method for Figure 12 The planar image of pixel P, and Figure 14 It is according to one implementation method along Figure 13 A cross-sectional view taken from line III-III'.

[0177] Figure 12 The circuit diagram is an equivalent circuit diagram including the pixel P of the display device 700, which is an organic light-emitting diode (OLED) as a display element 710 or a light-emitting element.

[0178] Pixel P includes display element 710 and pixel driver PDC that drives display element 710.

[0179] Figure 12 The pixel driver PDC includes a first thin-film transistor TR1 as a switching transistor and a second thin-film transistor TR2 as a driving transistor.

[0180] A display device 700 according to another embodiment of this disclosure may include at least one of the thin-film transistors 100, 200, 300, 400, 500, and 600 described above. As... Figure 12 The first thin-film transistor TR1 or the second thin-film transistor TR2 can be any one of the thin-film transistors 100, 200, 300, 400, 500, and 600 described above.

[0181] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS provided via the gate line GL.

[0182] The data line DL provides the data voltage Vdata to the pixel driver PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0183] The driving power line PL provides a driving voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0184] When the first thin-film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata supplied via the data line DL is provided to the gate electrode G2 of the second thin-film transistor TR2 connected to the display element 710. The data voltage Vdata is charged into the first capacitor C1 formed between the gate electrode G2 and the source electrode S2 of the second thin-film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0185] The amount of current supplied to the organic light-emitting diode (OLED) 710, which serves as the display element, is controlled by the data voltage Vdata, and thus the grayscale of the light output from the display element 710 can be controlled.

[0186] Reference Figure 13 and Figure 14 The first thin-film transistor TR1 and the second thin-film transistor TR2 are disposed on the substrate 110.

[0187] The substrate 110 can be made of glass or plastic. A plastic with flexible properties (e.g., polyimide PI) can be used as the substrate 110. A buffer layer can also be disposed on the substrate 110.

[0188] The gate electrode G1 of the first thin-film transistor TR1 and the gate electrode G2 of the second thin-film transistor TR2 are disposed on the substrate 110.

[0189] In addition, refer to Figure 13 and Figure 14 The first capacitor electrode CE1 is disposed on the same layer as the gate electrodes G1 and G2. The gate electrodes G1 and G2 and the first capacitor electrode CE1 can be manufactured together using the same materials and the same process.

[0190] A gate insulating layer 140 is disposed on the gate electrodes G1, G2 and the first capacitor electrode CE1. The gate insulating layer 140 has insulating properties and spaces the active layers A1, A2 from the gate electrodes G1, G2. Figure 14 As shown, the gate insulating layer 140 may not be patterned. However, another embodiment of this disclosure is not limited to this, and the gate insulating layer 140 may be patterned.

[0191] The active layer A1 of the first thin-film transistor TR1 and the active layer A2 of the second thin-film transistor TR2 are disposed on the gate insulating layer 140.

[0192] The active layers A1 and A2 may include oxide semiconductor materials. According to another embodiment of this disclosure, the active layers A1 and A2 are oxide semiconductor layers made of oxide semiconductor materials.

[0193] The active layer A1 of the first thin-film transistor TR1 overlaps with the gate electrode G1 of the first thin-film transistor TR1. The active layer A2 of the second thin-film transistor TR2 overlaps with the gate electrode G2 of the second thin-film transistor TR2.

[0194] Interlayer insulation layer 170 is disposed on active layers A1 and A2.

[0195] Source electrodes S1, S2 and drain electrodes D1, D2 are disposed on interlayer insulating layer 170. According to one embodiment of the present disclosure, source electrodes S1, S2 and drain electrodes D1, D2 are distinguished only for ease of explanation, and source electrodes S1, S2 and drain electrodes D1, D2 can be interchanged.

[0196] Additionally, the data line DL and the drive power line PL are disposed on the interlayer insulating layer 170. The source electrode S1 of the first thin-film transistor TR1 can be integrally formed with the data line DL. The drain electrode D2 of the second thin-film transistor TR2 can be integrally formed with the drive power line PL.

[0197] According to one embodiment of this disclosure, the source electrode S1 and drain electrode D1 of the first thin-film transistor TR1 are spaced apart from each other and are respectively connected to the active layer A1 of the first thin-film transistor TR1. The source electrode S2 and drain electrode D2 of the second thin-film transistor TR2 are spaced apart from each other and are respectively connected to the active layer A2 of the second thin-film transistor TR2.

[0198] Specifically, the source electrode S1 of the first thin-film transistor TR1 is connected to the active layer A1 through the first contact hole H1.

[0199] The drain electrode D1 of the first thin-film transistor TR1 is connected to the active layer A1 through the second contact hole H2, and is connected to the first capacitor electrode CE1 through the third contact hole H3.

[0200] The source electrode S2 of the second thin-film transistor TR2 extends over the interlayer insulating layer 170, and a portion of it serves as the second capacitor electrode CE2. The first capacitor electrode CE1 and the second capacitor electrode CE2 overlap to form the first capacitor C1.

[0201] The source electrode S2 of the second thin-film transistor TR2 is connected to the active layer A2 through the fourth contact hole H4. The drain electrode D2 of the second thin-film transistor TR2 is connected to the active layer A2 through the fifth contact hole H5.

[0202] The first thin-film transistor TR1 includes an active layer A1, a gate electrode G1, a source electrode S1, and a drain electrode D1, and is used as a switching transistor to control the data voltage Vdata applied to the pixel driver PDC.

[0203] The second thin-film transistor TR2 includes an active layer A2, a gate electrode G2, a source electrode S2, and a drain electrode D2, and serves as a driving transistor for controlling the driving voltage Vdd applied to the display element 710.

[0204] A planarization layer 180 is provided on the source electrodes S1, S2, drain electrodes D1, D2, data line DL, drive power line PL, and second capacitor electrode CE2. The planarization layer 180 planarizes the upper portions of the first thin-film transistor TR1 and the second thin-film transistor TR2, and protects the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0205] The first electrode 711 of the display element 710 is disposed on the planarization layer 180. The first electrode 711 of the display element 710 is connected to the source electrode S2 of the second thin film transistor TR2 through a seventh contact hole H7 formed in the planarization layer 180.

[0206] The embankment 750 is disposed at the edge of the first electrode 711. The embankment 750 defines the light-emitting area of ​​the display element 710.

[0207] An organic light-emitting layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic light-emitting layer 712. Thus, the display element 710 is completed. Figure 14 The display element 710 shown is an organic light-emitting diode (OLED). Therefore, the display device 700 according to the embodiments of this disclosure is an organic light-emitting display device.

[0208] According to another embodiment of this disclosure, the pixel driver PDC can be formed in various structures other than those described above. The pixel driver PDC may include, for example, three or more thin-film transistors and two or more capacitors.

[0209] The present disclosure described above is not limited to the above embodiments and drawings. It will be apparent to those skilled in the art that various substitutions, modifications and changes can be made without departing from the technical details of the present disclosure.

[0210] According to one embodiment of this disclosure, short channels can be easily formed in thin-film transistors because conductivity is performed using source and drain electrodes.

[0211] According to one embodiment of this disclosure, in a method for manufacturing a thin-film transistor, since the channel portion is defined by the source electrode and the drain electrode, the channel portion can be defined by self-alignment. Therefore, the channel portion is easily defined, and thus a short channel can be easily formed.

[0212] According to one embodiment of the present disclosure, a plurality of thin-film transistors having short channels can be formed on a substrate, and the plurality of thin-film transistors can have excellent characteristic uniformity.

[0213] A display device according to one embodiment of the present disclosure may include a plurality of thin-film transistors having short channels and excellent characteristic uniformity. Alternatively, a plurality of thin-film transistors may be arranged in a high density in the display device. Therefore, the display device according to one embodiment of the present disclosure can stably display high-resolution images and can have stable and high-resolution display performance.

[0214] In one embodiment, the thin-film transistor includes: a gate electrode; an active layer spaced apart from and at least partially overlapping the gate electrode; an interlayer insulating layer located on the active layer; a source electrode located on the interlayer insulating layer and connected to the active layer; and a drain electrode located on the interlayer insulating layer and spaced apart from the source electrode and connected to the active layer, wherein the active layer includes: a first channel portion overlapping the source electrode and the gate electrode, the first channel portion being located between the source electrode and the gate electrode; a second channel portion overlapping the drain electrode and the gate electrode, the second channel portion being located between the drain electrode and the gate electrode; and a connection portion located between the first channel portion and a second channel portion, the connection portion connecting the first channel portion and the second channel portion, wherein the connection portion is a conductive region.

[0215] In one embodiment, the connection portion is doped with a dopant, and the dopant concentration of the connection portion is higher than the dopant concentration of the first channel portion and the dopant concentration of the second channel portion.

[0216] In one embodiment, the connection portion does not overlap with the source electrode and the drain electrode.

[0217] In one embodiment, the active layer further includes a first contact portion that contacts the source electrode and a second contact portion that contacts the drain electrode.

[0218] In one embodiment, the first channel portion is located between the connecting portion and the first contact portion, and the second channel portion is located between the connecting portion and the second contact portion.

[0219] In one embodiment, the connection overlaps with the gate electrode.

[0220] In one embodiment, at least a portion of the connector does not overlap with the gate electrode.

[0221] In one embodiment, the gate electrode includes a first gate electrode that overlaps with a first channel portion and a source electrode; and a second gate electrode that overlaps with a second channel portion and a drain electrode.

[0222] In one embodiment, at least a portion of the connection portion does not overlap with the first gate electrode and the second gate electrode.

[0223] In one embodiment, the interlayer insulation layer is located on the connection portion.

[0224] In one embodiment, at least a portion of the connection does not overlap with the interlayer insulation layer.

[0225] In one embodiment, the thin-film transistor further includes a capping layer in contact with the connection portion, the capping layer having a reduction property that restores the characteristics of the connection portion.

[0226] In one embodiment, the coating layer includes at least one of titanium, molybdenum, aluminum, indium, and zinc.

[0227] In one embodiment, the thin-film transistor includes: a gate electrode; an active layer spaced apart from and at least partially overlapping the gate electrode; and a source electrode connected to the active layer, wherein the active layer includes: a channel portion overlapping the source electrode and the gate electrode; a contact portion contacting the source electrode; and a connection portion not overlapping the source electrode, wherein the channel portion is located between the connection portion and the contact portion, and the connection portion is a conductive region.

[0228] In one embodiment, the connection portion is doped with a dopant, and the dopant concentration in the connection portion is higher than the dopant concentration in the channel portion.

[0229] In one embodiment, the thin-film transistor further includes a gate insulating layer located above the gate electrode and between the gate electrode and the active layer, wherein the first end of the connector connected to the channel portion has a first height that is higher than the second end of the connector disposed on the side surface of the gate insulating layer.

[0230] In one embodiment, a method for manufacturing a thin-film transistor includes the following steps: forming a gate electrode on a substrate; forming an active layer on the gate electrode, the active layer being spaced apart from and at least partially overlapping the gate electrode; forming an interlayer insulating layer on the active layer, the interlayer insulating layer having contact holes; forming a source electrode and a drain electrode on the interlayer insulating layer, and selectively conductiveizing the active electrode and the drain electrode using the source electrode and the drain electrode as masks.

[0231] In one embodiment, the step of selectively conductiveing ​​the active layer includes conductiveing ​​a region of the active layer that does not overlap with the source electrode and the drain electrode, wherein the conductive region of the active layer is a connection portion.

[0232] In one embodiment, the region of the active layer overlapping with the source electrode is not conductive during selective conductivity and forms a first channel, and the region of the active layer overlapping with the drain electrode is not conductive during selective conductivity and forms a second channel.

[0233] In one embodiment, the step of selectively conductiveizing the active layer includes doping the active layer with a dopant.

[0234] In one embodiment, the display device includes: a substrate; a gate electrode located on the substrate; a gate insulating layer located on the gate electrode; an active layer located on the gate insulating layer, the active layer including a connection portion having a first end and a second end opposite to the first end, a first channel portion contacting the first end of the connection portion, and a second channel portion contacting the second end of the connection portion; an interlayer insulating layer located on the active layer; a source electrode and a drain electrode located on the interlayer insulating layer and spaced apart from each other, the source electrode and the drain electrode being connected to the active layer; and a light-emitting element emitting light, the light-emitting element being connected to one of the source electrode or the drain electrode, wherein the connection portion of the active layer does not overlap with the source electrode and the drain electrode.

[0235] In one embodiment, the connection portion is doped with a dopant, and the dopant concentration of the connection portion is higher than the dopant concentration of the first channel portion and the dopant concentration of the second channel portion.

[0236] In one embodiment, the active layer further includes a first contact portion that contacts the source electrode and a second contact portion that contacts the drain electrode.

[0237] In one embodiment, the first channel portion is located between the connecting portion and the first contact portion, and the second channel portion is located between the connecting portion and the second contact portion.

[0238] In one embodiment, the connection overlaps with the gate electrode.

[0239] In one embodiment, at least a portion of the connector does not overlap with the gate electrode.

[0240] In one embodiment, the gate electrode includes a first gate electrode that overlaps with a first channel portion and a source electrode; and a second gate electrode that overlaps with a second channel portion and a drain electrode, wherein at least a portion of the connection portion does not overlap with the first gate electrode and the second gate electrode.

[0241] In one embodiment, at least a portion of the connection does not overlap with the interlayer insulation layer.

[0242] In one embodiment, the display device further includes a cover layer that contacts the connector, the cover layer having a reducing property that restores the properties of the connector, wherein the cover layer includes at least one of titanium, molybdenum, aluminum, indium and zinc.

[0243] In one embodiment, the active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer located on the first oxide semiconductor layer.

[0244] In addition to the effects mentioned above, other features and advantages of this disclosure are described below, or may be clearly understood by those skilled in the art from such description and explanation.

[0245] Cross-references to related applications

[0246] This application claims priority to Korean Patent Application No. 10-2024-0153511, filed on November 1, 2024, which is incorporated herein by reference in its entirety.

Claims

1. A thin-film transistor, the thin-film transistor comprising: Gate electrode; An active layer, which is spaced apart from and at least partially overlaps with the gate electrode; An interlayer insulating layer, wherein the interlayer insulating layer is located on the active layer; A source electrode, the source electrode being located on the interlayer insulating layer and connected to the active layer; as well as A drain electrode, located on the interlayer insulating layer and spaced apart from the source electrode, is connected to the active layer. The active layer includes: A first channel portion, which overlaps with the source electrode and the gate electrode, and is located between the source electrode and the gate electrode; A second channel portion, the second channel portion overlapping the drain electrode and the gate electrode, the second channel portion being located between the drain electrode and the gate electrode; and A connecting portion is located between the first channel portion and the second channel portion, and the connecting portion connects the first channel portion and the second channel portion. The connecting portion is a conductive area.

2. The thin-film transistor according to claim 1, wherein, The connection portion is doped with a dopant, and the dopant concentration of the connection portion is higher than the dopant concentration of the first channel portion and the dopant concentration of the second channel portion.

3. The thin-film transistor according to claim 1, wherein, The connection portion does not overlap with the source electrode and the drain electrode.

4. The thin-film transistor according to claim 1, wherein, The active layer further includes: The first contact portion contacts the source electrode, and The second contact portion is in contact with the drain electrode.

5. The thin-film transistor according to claim 4, wherein, The first channel portion is located between the connecting portion and the first contact portion, and the second channel portion is located between the connecting portion and the second contact portion.

6. The thin-film transistor according to claim 1, wherein, The connecting portion overlaps with the gate electrode.

7. The thin-film transistor according to claim 1, wherein, At least a portion of the connection portion does not overlap with the gate electrode.

8. The thin-film transistor according to claim 1, wherein, The gate electrode includes: A first gate electrode, the first gate electrode overlapping the first channel portion and the source electrode; and The second gate electrode overlaps with the second channel portion and the drain electrode.

9. The thin-film transistor according to claim 8, wherein, At least a portion of the connection portion does not overlap with the first gate electrode and the second gate electrode.

10. The thin-film transistor according to claim 1, wherein, The interlayer insulation layer is located on the connection portion.

11. The thin-film transistor according to claim 1, wherein, At least a portion of the connection does not overlap with the interlayer insulation layer.

12. The thin-film transistor according to claim 1, further comprising: A cover layer that contacts the connecting portion, the cover layer having a restoring property that restores the properties of the connecting portion.

13. The thin-film transistor according to claim 12, wherein, The coating layer includes at least one of titanium, molybdenum, aluminum, indium, and zinc.

14. A thin-film transistor, the thin-film transistor comprising: Gate electrode; An active layer, which is spaced apart from and at least partially overlaps with the gate electrode; as well as Source electrode, the source electrode being connected to the active layer, The active layer includes: A channel portion, wherein the channel portion overlaps with the source electrode and the gate electrode; Contact portion, the contact portion being in contact with the source electrode; and The connecting portion does not overlap with the source electrode. The channel portion is located between the connecting portion and the contact portion, and the connecting portion is a conductive area.

15. The thin-film transistor of claim 14, wherein, The connecting portion is doped with a dopant, and the dopant concentration in the connecting portion is higher than that in the channel portion.

16. The thin-film transistor of claim 14, further comprising: A gate insulating layer is located on the gate electrode and between the gate electrode and the active layer. Wherein, the first end of the connector connected to the channel portion has a first height that is higher than the second end of the connector disposed on the side surface of the gate insulating layer.

17. A method for manufacturing a thin-film transistor, the method comprising the following steps: A gate electrode is formed on the substrate; An active layer is formed on the gate electrode, the active layer being spaced apart from the gate electrode and at least partially overlapping the gate electrode; An interlayer insulating layer is formed on the active layer, and the interlayer insulating layer has contact holes; Source and drain electrodes are formed on the interlayer insulating layer; as well as The source electrode and the drain electrode are used as masks to selectively make the active layer conductive.

18. The manufacturing method according to claim 17, wherein, The step of selectively conductiveing ​​the active layer includes conductiveing ​​a region of the active layer that does not overlap with the source electrode and the drain electrode, wherein the conductive region of the active layer is a connection portion.

19. The manufacturing method according to claim 17, wherein, The region of the active layer that overlaps with the source electrode is not conductive during the selective conductivity step and forms a first channel portion, and the region of the active layer that overlaps with the drain electrode is not conductive during the selective conductivity step and forms a second channel portion.

20. The manufacturing method according to claim 17, wherein, The step of selectively making the active layer conductive includes doping the active layer with a dopant.

21. A display device, the display device comprising: substrate; A gate electrode, wherein the gate electrode is located on the substrate; A gate insulating layer, the gate insulating layer being located on the gate electrode; An active layer is located on the gate insulating layer. The active layer includes a connection portion having a first end and a second end opposite to the first end, a first channel portion contacting the first end of the connection portion, and a second channel portion contacting the second end of the connection portion. An interlayer insulating layer, wherein the interlayer insulating layer is located on the active layer; A source electrode and a drain electrode, the source electrode and the drain electrode being located on the interlayer insulating layer and spaced apart from each other, the source electrode and the drain electrode being connected to the active layer; as well as A light-emitting element that emits light, the light-emitting element being connected to one of the source electrode or the drain electrode. The connection portion of the active layer does not overlap with the source electrode and the drain electrode.

22. The display device according to claim 21, wherein, The connection portion is doped with a dopant, and the dopant concentration of the connection portion is higher than the dopant concentration of the first channel portion and the dopant concentration of the second channel portion.

23. The display device according to claim 21, wherein, The active layer further includes: A first contact portion, the first contact portion being in contact with the source electrode; and The second contact portion is in contact with the drain electrode.

24. The display device according to claim 23, wherein, The first channel portion is located between the connecting portion and the first contact portion, and the second channel portion is located between the connecting portion and the second contact portion.

25. The display device according to claim 21, wherein, The connecting portion overlaps with the gate electrode.

26. The display device according to claim 21, wherein, At least a portion of the connection portion does not overlap with the gate electrode.

27. The display device according to claim 21, wherein, The gate electrode includes: A first gate electrode, the first gate electrode overlapping the first channel portion and the source electrode; and The second gate electrode overlaps with the second channel portion and the drain electrode. Wherein, at least a portion of the connecting portion does not overlap with the first gate electrode and the second gate electrode.

28. The display device according to claim 21, wherein, At least a portion of the connection does not overlap with the interlayer insulation layer.

29. The display device according to claim 21, further comprising: A cover layer that contacts the connecting portion, the cover layer having a restoring property that replicates the characteristics of the connecting portion. The coating layer includes at least one of titanium, molybdenum, aluminum, indium, and zinc.

30. The display device according to claim 21, wherein, The active layer includes: First oxide semiconductor layer; and A second oxide semiconductor layer is located on top of the first oxide semiconductor layer.

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