Back contact solar cell and preparation method thereof

Abstract

A back contact solar cell and a preparation method are provided, a functional layer and a mask layer are prepared on the back of a silicon wafer, laser patterning processing is performed on the back of the silicon wafer, and part of the mask layer is removed or modified; the main body of the patterning machining area is scanned through film opening laser, the edge of the patterning machining area is scanned through edge machining laser, light spots of the edge machining laser are overlapped in the scanning direction of the edge machining laser to form a straight laser machining line, and the union set of the film opening laser scanning area and the edge machining laser scanning area is the patterning machining area; the functional layer corresponding to the laser patterning processing area is removed through wet cleaning, and the obtained side surface is an inclined plane; the laser patterning processing area is an N area, a P area, an N area and a GAP area, or a position corresponding to the P area and the GAP area. Edge laser is adopted for modification, a straight laser processing line is formed, and after wet cleaning, an inclined plane formed by the edge can reduce the surface recombination rate of a silicon wafer and improve the conversion efficiency of a solar cell.

Description

Technical Field

[0001] This invention belongs to the field of solar cell processing technology, and in particular relates to a back-contact solar cell and its preparation method. Background Technology

[0002] In the production of crystalline silicon solar cells, laser patterning is one of the important methods to achieve high and low junction localization of the PN junction, NN+, and PP+. Laser processing is followed by chemical etching to remove the laser-processed or non-laser-processed areas, thus completing the specific patterning process.

[0003] In existing back-contact (BC) solar cells, multiple processes, such as the fabrication of the gap area, can be completed through patterning. The applicant's research has revealed that the silicon surface recombination rate of BC solar cells has not been effectively improved. Summary of the Invention

[0004] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention proposes a back contact solar cell and its preparation method.

[0005] To achieve the above objectives, according to a first aspect of the present invention, a method for fabricating a back-contact solar cell is provided, comprising fabricating a functional layer and a mask layer on the back side of a silicon wafer, performing laser patterning on the back side of the silicon wafer, removing a portion of the mask layer or modifying the mask layer; wherein, an open-film laser is used to scan the main body of the patterned area, an edge processing laser is used to scan the edge of the patterned area, and the union of the open-film laser scanning area and the edge processing laser scanning area constitutes the patterned area;

[0006] The laser spots used for edge processing are superimposed along their scanning direction to form a straight laser processing line;

[0007] Wet cleaning removes the functional layer corresponding to the laser-patterned processing area;

[0008] The laser patterning processing area is the corresponding position of the N area, the corresponding position of the P area, the corresponding position of the N area and the GAP area, or the corresponding position of the P area and the GAP area.

[0009] According to the above scheme, the functional layer is a tunneling oxide layer and a doped polysilicon layer arranged sequentially, or a boron diffusion layer, wherein the doped polysilicon layer is a phosphorus-doped polysilicon layer or a boron-doped polysilicon layer.

[0010] According to the above scheme, the edge processing laser is a nanosecond or picosecond pulse laser.

[0011] According to the above scheme, the wet cleaning method involves using an alkaline solution for cleaning.

[0012] According to the above scheme, the side surface of the patterned processing area after wet cleaning is a slope, and the width of the top outline of the side surface is less than 10µm.

[0013] According to the above scheme, the spot width of the edge processing laser is 2µm~50µm.

[0014] According to the above scheme, the edge processing laser is a single-pulse laser. When the laser spot is a Gaussian spot, the spot overlap rate in the scanning direction is 50%~99%; when the laser spot is a flat-topped circular spot, the spot overlap rate in the scanning direction is 50%~99%; when the laser spot is a flat-topped square spot, the spot overlap rate in the scanning direction is 1%~99%; when the laser spot is an annular spot, the spot overlap rate in the scanning direction is 50%~99%; and when the laser spot is a linear spot, the overlap rate in the scanning direction is 1%~99%.

[0015] Alternatively, the edge processing laser may be a pulse train laser, where the connecting direction of the sub-pulses in each pulse train is not parallel to the scanning direction, and the projections of adjacent sub-pulses in the vertical scanning direction overlap. When the laser spot is a Gaussian spot, the overlap rate of the corresponding sub-pulses in the scanning direction of adjacent pulse trains is 50%~99%; when the laser spot is a flat-topped circular spot, the overlap rate of the corresponding sub-pulses in the scanning direction of adjacent pulse trains is 50%~99%; when the laser spot is a flat-topped square spot, the overlap rate of the corresponding sub-pulses in the scanning direction of adjacent pulse trains is 1%~99%; when the laser spot is an annular spot, the overlap rate of the corresponding sub-pulses in the scanning direction of adjacent pulse trains is 50%~99%; and when the laser spot is a linear spot, the overlap rate of the corresponding sub-pulses in the scanning direction of adjacent pulse trains is 1%~99%.

[0016] According to the above scheme, the edge processing laser is a single-pulse laser. When the laser spot is a Gaussian spot, the spot overlap rate in the scanning direction is 75%~95%; when the laser spot is a flat-topped circular spot, the spot overlap rate in the scanning direction is 75%~95%; when the laser spot is a flat-topped square spot, the spot overlap rate in the scanning direction is 1%~75%; when the spot is an annular spot, the spot overlap rate in the scanning direction is 75%~95%; and when the spot is a linear spot, the overlap rate in the scanning direction is 1%~75%.

[0017] Alternatively, the edge processing laser may be a pulse train laser, wherein the connecting direction of the sub-pulses in each pulse train is not parallel to the scanning direction, and the projections of adjacent sub-pulses in the vertical scanning direction overlap. When the laser spot is a Gaussian spot, the overlap rate of the corresponding sub-pulses of adjacent pulse trains in the scanning direction is 75%~95%; when the laser spot is a flat-topped circular spot, the overlap rate of the corresponding sub-pulses of adjacent pulse trains in the scanning direction is 75%~95%; when the laser spot is a flat-topped square spot, the overlap rate of the corresponding sub-pulses of adjacent pulse trains in the scanning direction is 1%~75%; when the laser spot is an annular spot, the overlap rate of the corresponding sub-pulses of adjacent pulse trains in the scanning direction is 75%~95%; and when the laser spot is a linear spot, the overlap rate of the corresponding sub-pulses of adjacent pulse trains in the scanning direction is 1%~75%.

[0018] The above method includes the following steps:

[0019] S10 silicon wafer pretreatment;

[0020] S20 A first functional layer is prepared on the back side of a silicon wafer. The first functional layer has a first doped layer and a first mask layer is formed on the first functional layer.

[0021] S30 performs the first laser patterning process on the back of the silicon wafer;

[0022] The first laser patterning process is performed on the areas corresponding to the N-zone and the GAP-zone.

[0023] S40 wet cleaning removes the first functional layer from the area of ​​the first laser patterning process;

[0024] S50 A second functional layer is fabricated on the back side of a silicon wafer. The second functional layer has a second doped layer and a second mask layer is formed on the second functional layer.

[0025] S60 performs a second laser patterning process on the back of the silicon wafer;

[0026] The second patterning process area is the area corresponding to the P area and the GAP area;

[0027] S70 wet cleaning removes the second functional layer of the second laser patterning area, forming a GAP area of ​​a certain depth between adjacent P and N areas;

[0028] S80 pickling removes the first and second doped layers that were plated around the front edge; alkaline solution is used for double-sided texturing to form a textured surface in the GAP area on the front and back sides of the silicon wafer; then hydrofluoric acid pickling removes the remaining first and second mask layers on the back side.

[0029] S90 fabricates a front passivation layer and a back passivation layer on a silicon wafer.

[0030] Metallization of the back side of the S100 silicon wafer completes the fabrication of the back-contact solar cell;

[0031] The first and second functional layers have opposite conductivity types.

[0032] According to the above method, the pretreatment of S10 silicon wafers is to polish the silicon wafers on both sides.

[0033] The first functional layer is a tunneling oxide layer and a boron-doped polysilicon layer; the second functional layer is a tunneling oxide layer and a phosphorus-doped polysilicon layer.

[0034] According to the above method, the pretreatment of S10 silicon wafers is to perform double-sided texturing on the silicon wafers;

[0035] The first functional layer is a boron diffusion layer; the second functional layer is a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer.

[0036] According to the above method, the side surface of the GAP area is a slope, and the width of the top outline of the side surface is less than 10µm.

[0037] According to the above method, the depth of the GAP area is 1~10µm and the width is 20~500µm.

[0038] The above method includes the following steps:

[0039] S01 silicon wafer double-sided polishing;

[0040] S02 prepares a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back side of a silicon wafer, wherein a third mask layer is formed on the phosphorus-doped polysilicon.

[0041] S03 performs the first laser patterning process on the back of the silicon wafer;

[0042] The area for the first laser patterning process is the area corresponding to region P;

[0043] S04 wet cleaning removes the phosphorus-doped polysilicon layer and tunnel oxide layer in the area of ​​the first laser patterning process, while simultaneously completing the texturing of the area of ​​the first laser processing on the back and the front, forming a pyramid structure.

[0044] S05. An intrinsic amorphous silicon layer and a boron-doped amorphous silicon layer, a boron-doped microcrystalline silicon layer, or a combination thereof are prepared on the back side of a silicon wafer.

[0045] S06 Opens the conductive channel in the N region;

[0046] Process the N-region on the back side of the silicon wafer, remove the boron-doped amorphous silicon layer, boron-doped microcrystalline silicon layer or a combination thereof, the intrinsic amorphous silicon layer and the third mask layer, and form a conductive channel that reaches the phosphorus-doped polycrystalline silicon layer in the N-region.

[0047] S07. A TCO layer is prepared on the back side of the silicon wafer;

[0048] S08. A front passivation layer is prepared on the front side of the silicon wafer;

[0049] S09 Remove the TCO layer between the P region and the N region to complete the PN region isolation;

[0050] S010 prepares electrodes on the back side of the silicon wafer, completing the fabrication of a back-contact solar cell.

[0051] Using the method described above, the width of the top contour line of the slope at the junction of regions P and N is less than 10µm.

[0052] According to another aspect of the present invention, a back-contact solar cell is provided, which is prepared by the aforementioned method and includes an N-type silicon substrate. A front passivation layer is disposed on the front side, and an N-region functional layer and a P-region functional layer are disposed on the back side at intervals. A GAP region is disposed between the N-region functional layer and the P-region functional layer. The GAP region is a groove disposed opposite to the P-region functional layer and the N-region functional layer, and its depth reaches the silicon substrate. A passivation layer is disposed above the P-region functional layer, the N-region functional layer and the GAP region. An electrode is disposed above the P-region functional layer and the N-region functional layer. The side surface of the GAP region is a slope, and the width of the top contour line of the side surface is less than 10µm.

[0053] According to another aspect of the present invention, a back-contact solar cell is provided, which is prepared by the aforementioned method and includes an N-type silicon substrate, on the front side of which a front passivation layer is disposed, and on the back side where an N-region functional layer and a P-region functional layer are disposed at intervals. A TCO film is disposed above the N-region functional layer and the P-region functional layer, and an electrode is disposed thereon. The TCO film between the P-region functional layer and the N-region functional layer is removed, wherein the width of the top contour line of the inclined surface at the junction of the N-region functional layer and the P-region functional layer is less than 10µm.

[0054] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0055] This invention utilizes laser patterning and wet cleaning methods on silicon wafers to fabricate a gap area (GAP) between the P- and N-regions. The top contour line of the GAP region's side surface is less than 10µm wide, meaning the boundary between the side and bottom surfaces is straighter. Compared to existing technologies where the boundary is a broken line, the passivation layer composition here is closer to the stoichiometry, resulting in higher passivation layer density and better passivation effect. Furthermore, the formed side surface is smoother, leading to better uniformity and higher surface coverage of the deposited passivation layer. This avoids the thickness and density variations caused by uneven side surfaces and local bumps or stripes in existing technologies. By reducing surface recombination, leakage channels can be significantly reduced, maintaining good dark current characteristics and thus improving battery efficiency.

[0056] This invention uses laser patterning and wet cleaning to prepare the boundary slope between the N and P regions of a silicon wafer. The top contour line of the boundary slope is less than 10µm wide, meaning that the boundary slope is straighter in the length direction and has a smoother surface, which means lower surface recombination and fewer carrier recombination centers after subsequent functional layer deposition. Attached Figure Description

[0057] Figure 1 The upper figure is a schematic diagram of the back side of a silicon wafer after step S10 in one embodiment. Figure 1 The image below is a cross-sectional view.

[0058] Figure 2 The upper figure is a schematic diagram of the back side of a silicon wafer after step S20 in one embodiment. Figure 2 The image below is a cross-sectional view.

[0059] Figure 3 This is a schematic diagram of the first laser patterning process of a silicon wafer according to one embodiment. Figure 3 The top and bottom images show the back and cross-section of the silicon wafer, respectively.

[0060] Figure 4 The upper figure is a schematic diagram of the back side of a silicon wafer after step S40 in one embodiment. Figure 4 The image below is a cross-sectional view.

[0061] Figure 5 The upper figure is a schematic diagram of the back side of a silicon wafer after step S50 in one embodiment. Figure 5 The image below is a cross-sectional view.

[0062] Figure 6 This is a schematic diagram illustrating the steps of a second laser patterning process in one embodiment. Figure 6 The top and bottom images show the back and cross-section of the silicon wafer, respectively.

[0063] Figure 7 The image above is a schematic diagram of the back side of a silicon wafer after step S70, according to one embodiment. Figure 7 The image below is a cross-sectional view.

[0064] Figure 8 This is a cross-sectional schematic diagram of a silicon wafer after step S90, according to one embodiment.

[0065] Figure 9 This is a cross-sectional schematic diagram of a back-contact solar cell formed after a silicon wafer passes through S100 in one embodiment.

[0066] Figure 10 The upper figure is a cross-sectional view of a silicon wafer after step S70 according to one embodiment. Figure 10 The image below is a schematic diagram of the back side;

[0067] Figure 11 A micrograph of a silicon wafer after step S70 according to one embodiment;

[0068] Figure 12 Micrograph of a silicon wafer after step S70 in a prior art method;

[0069] Figure 13 The image above is a schematic diagram of the back side of a silicon wafer after step S01, according to another embodiment. Figure 13 The image below is a cross-sectional view.

[0070] Figure 14 The image above is a schematic diagram of the back side of a silicon wafer after step S02, according to another embodiment. Figure 14 The image below is a cross-sectional view.

[0071] Figure 15 The image above is a schematic diagram of the first laser patterning process in another embodiment. Figure 15 The top and bottom images show the back and cross-section of a silicon wafer.

[0072] Figure 16 The image above is a schematic diagram of the back side of a silicon wafer after step S04, according to another embodiment. Figure 16 The image below is a cross-sectional view.

[0073] Figure 17 This is a cross-sectional view of a silicon wafer after step S05, according to another embodiment.

[0074] Figure 18 This is a cross-sectional view of a silicon wafer after step S06, according to another embodiment.

[0075] Figure 19This is a cross-sectional view of a silicon wafer after step S07, according to another embodiment.

[0076] Figure 20 This is a cross-sectional view of a silicon wafer after step S08, according to another embodiment.

[0077] Figure 21 This is a cross-sectional view of a silicon wafer after step S09, according to another embodiment.

[0078] Figure 22 This is a cross-sectional schematic diagram of a back-contact solar cell formed from a silicon wafer after step S010, according to another embodiment.

[0079] In the figure: 10-Silicon wafer, 11-Tunneling oxide layer, 12-Boron-doped polycrystalline silicon layer, 13-First mask layer, 14-Phosphorus-doped polycrystalline silicon layer, 15-Second mask layer, 16-GAP region, 17-Front-side passivation layer, 18-Back-side passivation layer, 19-Electrode; 20-Silicon wafer, 21-Tunneling oxide layer, 22-Phosphorus-doped polycrystalline silicon layer, 23-Third mask layer, 24-Intrinsic amorphous silicon layer, 25-Boron-doped amorphous silicon layer, boron-doped microcrystalline silicon layer or a mixture thereof, 26-GAP region, 27-Front-side passivation layer, 28-TCO layer, 29-Electrode. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0081] As described in the background art, the silicon surface recombination rate of back contact (BC) solar cells has not been effectively improved. In the research, the applicant found that by controlling the interface morphology of the laser-processed area and the non-laser-processed area during patterning processing using laser and chemical etching, the width position deviation of the interface is smaller and smoother, which can further reduce the silicon surface recombination rate and improve the conversion efficiency of solar cells.

[0082] On one hand, a method for fabricating a back-contact solar cell according to the present invention includes fabricating a functional layer and a mask layer on the back side of a silicon wafer;

[0083] Laser patterning involves removing part of the mask layer or modifying the mask layer to make it more susceptible to corrosion by wet cleaning solutions. Specifically, an edge-processing laser scans the edge of the patterned area adjacent to the non-laser-processed area, while an open-film laser scans the main body of the patterned area. The union of the open-film laser scan area and the edge-processing laser scan area constitutes the patterned area. In particular, the open-film laser scan area and the edge-processing laser scan area are adjacent or partially overlap.

[0084] Wet cleaning removes the functional layer corresponding to the laser patterned area and removes part of the silicon substrate.

[0085] The functional layer includes a doped layer. For example, the functional layer is a tunneling oxide layer and a doped polysilicon layer arranged sequentially. The doped polysilicon layer is an n-type or p-type doped polysilicon layer. The n-type dopant includes, but is not limited to, phosphorus (P), arsenic (As), or antimony (Sb), and the p-type dopant includes, but is not limited to, boron (B), aluminum (Al), or gallium (Ga). Preferably, the doped polysilicon layer is a phosphorus-doped polysilicon layer or a boron-doped polysilicon layer. Alternatively, the functional layer is a boron diffusion layer. The mask layer is a phosphorus-silicon glass layer, a borosilicate glass layer, a silicon oxynitride layer, or a silicon oxide layer.

[0086] The laser patterning processing area is the corresponding position of the N area, the corresponding position of the P area, or the corresponding position of the N area and the GAP area, or the corresponding position of the P area and the GAP area.

[0087] The laser spot width for edge processing is 2µm~50µm, preferably 5~40µm, and more preferably 20~40µm, with an energy density of 450~2500mJ / cm². 2The laser used in this invention employs a picosecond or nanosecond pulsed laser with a wavelength of 355-1064 nm. Different overlap rates are used to scan the edges of the laser-patterned and non-patterned areas for laser-treated spots of different shapes, forming straight and uniform laser processing lines. During subsequent wet cleaning, the edges form smoother bevels and are relatively straight along their length. For example, in some embodiments, the edge-treated laser is a single-pulse laser, and the laser spot can be a Gaussian spot with an overlap rate of 50%-99% in the scanning direction, preferably 75%-95%. Alternatively, the laser spot can be a flat-topped circular spot with an overlap rate of 50%-99% in the scanning direction, preferably 75%-95%. The edge processing laser spot can be a flat-topped square spot, such as a rectangular or square spot, with a spot overlap rate of 1%~99% in the scanning direction, preferably 1%~75%; the edge processing laser spot can be a ring spot, with a spot overlap rate of 50%~99% in the scanning direction, preferably 75%~95%; the edge processing laser spot can be a linear spot, with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. In another embodiment, the edge processing laser is a pulse train laser, where the connecting direction of the sub-pulses in each pulse train is not parallel to the scanning direction, and the projection portions of adjacent sub-pulses in the vertical scanning direction overlap. When the laser spot is a Gaussian spot, the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 50%~99%, preferably 75%~95%. The edge processing laser spot can also be a flat-topped circular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The laser spot for edge processing is a flat-topped square spot, with the overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 1%~99%, preferably 1%~75%. The laser spot for edge processing can be an annular spot, with the overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The laser spot for edge processing can also be a linear spot, with the overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 1%~99%, preferably 1%~75%. In this invention, the spot width refers to the size of the spot perpendicular to the scanning direction.

[0088] This invention achieves a straight laser processing line by setting the laser spot size and overlap rate for edge processing. For Gaussian, flat-topped circular, annular, and linear laser spots, a higher overlap rate results in a straighter laser processing line. Specifically, a straight laser processing line is defined as having a position width of less than 2µm. This position width is defined by the spacing between the parallel lines enveloping the laser processing line; in other words, it is the distance between the two farthest points along the width direction of the curve. It should be noted that in solar cells, the inclined plane typically extends through the cell, with a length of approximately 200mm. When measuring the position width of the laser processing line, electron microscopy is commonly used. However, this often makes it impossible to measure the entire laser processing line. Therefore, multiple measurements can be taken at different locations, and the average value obtained from these measurements can be calculated.

[0089] The open-film laser is either a Gaussian laser or a flat-top laser, preferably a flat-top laser, with an energy density of 450~2500 mJ / cm². 2 The wavelength is 355~1064nm, the spot size is 150~350µm, the spot overlap rate is 0~10%, and it is a picosecond or nanosecond pulsed laser.

[0090] The wet cleaning method involves using an alkaline solution. This solution comprises NaOH and water, with the NaOH concentration ranging from 1 wt% to 3.0 wt%. The corrosion temperature is 65–75°C, and the corrosion time is 250–600 seconds. As will be understood by those skilled in the art, the alkaline solution also includes other components, such as surfactants and commercially available additives, to enhance the cleaning and wet chemical corrosion effects.

[0091] The edge between the laser-patterned area and the non-laser-patterned area is a bevel, and the passivation effect is best when this bevel is a straight line along its length. However, in existing open-film laser processing, due to unavoidable uneven distribution and tilting of the laser spot at the edge, the bevel in the existing technology is often a broken line along its length. After processing with open-film laser alone, without edge modification, uneven edge lines will appear on the surface of the solar cell after etching. Typically, there will be an edge unevenness of 15µm to 30µm in width. After covering with the passivation layer, it will cause edge color difference, and in severe cases, it may even cause edge leakage. This application uses edge processing laser to modify the edge of the open-film laser and reduce edge unevenness. Specifically, this invention uses a picosecond or nanosecond pulsed laser with a small spot size and scans the edge between the laser-patterned area and the non-laser-patterned area with different overlap rates for different shaped spots to form a straight laser processing line. During subsequent wet cleaning, the edge forms a smoother bevel, which is relatively straight along its length. Specifically, the width of the top contour line of the slope is less than 10µm, and less than 5µm when the spot overlap rate is within the preferred range mentioned above. By controlling the corrosion conditions, it can be less than 4µm, or even 3µm or 2µm. In this invention, the width of the top contour line is defined by the spacing between its outer envelope parallel lines; in other words, it is the distance between the two farthest points in the width direction of the curve. See also... Figure 10 , Figure 10 The right side shows a single curve and its surrounding parallel lines. It should be noted that in solar cells, the length of the inclined plane typically extends through the cell, approximately 200mm. When measuring the width of the top contour line of the inclined plane, electron microscopy is usually used. However, it is often impossible to measure the entire top contour line at this time. Therefore, multiple measurements can be taken at different locations, and the average value of these measurements is taken. As mentioned earlier, the smaller the width of the laser processing line, the smaller the width of the top contour line of the inclined plane. Generally speaking, the slope of the same inclined plane is basically consistent, and the top and bottom contour lines of the inclined plane are similar, exhibiting roughly the same curvature. In other words, the entire inclined plane is relatively straight along its length.

[0092] Furthermore, using the method of the present invention, the roughness factor of the inclined surface is less than 1.5, preferably less than 1.3, more preferably less than 1.2, less than 1.1, and even less than 1.05. The roughness factor refers to the ratio of the actual surface area to the apparent surface area. A straight and smooth inclined surface can further reduce the surface recombination rate of the silicon wafer and improve the conversion efficiency of the solar cell.

[0093] For laser film opening, a flat-top laser with a large spot size is preferred to maintain a high film opening speed and uniformly open the film in the laser patterning area, so that a smooth plane is formed at the bottom during subsequent wet cleaning.

[0094] It should be noted that the silicon wafer of the present invention can be a pre-treated silicon substrate, such as a polished silicon substrate or a texturized silicon substrate, or a silicon wafer on which partial functional layers have been fabricated. Those skilled in the art will understand that the P-region refers to the region corresponding to the P-region functional layer of the back-contact solar cell, the N-region refers to the region corresponding to the N-region functional layer of the back-contact solar cell, and the GAP region refers to the region between the P-region and N-region of the back-contact solar cell.

[0095] In some embodiments, the scanning area of ​​the film-opening laser and the scanning area of ​​the edge processing laser are adjacent. In this case, the order of scanning by the edge processing laser and the film-opening laser is not limited. In other embodiments, the scanning areas of the film-opening laser and the edge processing laser partially overlap. In this case, the edge processing laser and the film-opening laser preferably scan simultaneously, or the edge processing laser scans after the film-opening laser.

[0096] Furthermore, a method for fabricating a back-contact solar cell according to the present invention includes the following steps:

[0097] S10 silicon wafer pretreatment;

[0098] S20 A first functional layer is prepared on the back side of a silicon wafer. The first functional layer has a first doped layer and a first mask layer is formed on the first functional layer.

[0099] S30 performs the first laser patterning process on the back of the silicon wafer;

[0100] The first laser patterning process is performed on the areas corresponding to the N-zone and the GAP-zone.

[0101] S40 wet cleaning removes the first functional layer from the area of ​​the first laser patterning process;

[0102] S50 A second functional layer is fabricated on the back side of a silicon wafer. The second functional layer has a second doped layer and a second mask layer is formed on the second functional layer.

[0103] S60 performs a second laser patterning process on the back of the silicon wafer;

[0104] The second patterning process area is the area corresponding to the P area and the GAP area;

[0105] S70 wet cleaning removes the second functional layer of the second laser patterning area, forming a GAP area of ​​a certain depth between adjacent P and N areas;

[0106] S80 pickling removes the first and second doped layers that were plated around the front edge; alkaline solution is used for double-sided texturing to form a textured surface in the GAP area on the front and back sides of the silicon wafer; then hydrofluoric acid pickling removes the remaining first and second mask layers on the back side.

[0107] S90 fabricates a front passivation layer and a back passivation layer on a silicon wafer.

[0108] Metallization of the back side of the S100 silicon wafer completes the fabrication of the back-contact solar cell;

[0109] The first functional layer and the second functional layer have opposite conductivity types; for example, the first functional layer has a boron-doped layer and the second functional layer has a phosphorus-doped layer.

[0110] In one embodiment, the S10 silicon wafer pretreatment involves double-sided polishing of the silicon wafer. The first functional layer consists of a tunneling oxide layer and a boron-doped polycrystalline silicon layer arranged sequentially, and the second functional layer consists of a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer arranged sequentially.

[0111] In another embodiment, the S10 silicon wafer pretreatment involves double-sided texturing of the silicon wafer, with the first functional layer being a boron diffusion layer and the second functional layer being a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer arranged sequentially.

[0112] In another embodiment, a method for fabricating a back-contact solar cell according to the present invention includes the following steps:

[0113] S01 silicon wafer double-sided polishing;

[0114] S02 prepares a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back side of a silicon wafer, wherein a third mask layer is formed on the phosphorus-doped polysilicon.

[0115] S03 performs the first laser patterning process on the back of the silicon wafer;

[0116] The area for the first laser patterning process is the area corresponding to region P;

[0117] S04 wet cleaning removes the phosphorus-doped polysilicon layer and tunnel oxide layer in the area of ​​the first laser patterning process, while simultaneously completing the texturing of the area of ​​the first laser processing on the back and the front, forming a pyramid structure.

[0118] S05. An intrinsic amorphous silicon layer and a boron-doped amorphous silicon layer, a boron-doped microcrystalline silicon layer, or a combination thereof are prepared on the back side of a silicon wafer.

[0119] S06 Opens the conductive channel in the N region;

[0120] Process the N-region on the back side of the silicon wafer, remove the boron-doped amorphous silicon layer, boron-doped microcrystalline silicon layer or a combination thereof, the intrinsic amorphous silicon layer and the third mask layer, and form a conductive channel that reaches the phosphorus-doped polycrystalline silicon layer in the N-region.

[0121] S07. A TCO layer is prepared on the back side of the silicon wafer;

[0122] S08. A front passivation layer is prepared on the front side of the silicon wafer;

[0123] S09 Remove the TCO layer between the P region and the N region to complete the PN region isolation;

[0124] S010 prepares electrodes on the back side of the silicon wafer, completing the fabrication of a back-contact solar cell.

[0125] In another aspect, the present invention provides a back-contact solar cell, comprising an N-type silicon substrate, a front passivation layer disposed on the front side, an N-region functional layer and a P-region functional layer disposed at intervals on the back side, a GAP region disposed between the N-region functional layer and the P-region functional layer, wherein the GAP region is a groove disposed opposite to the P-region functional layer and the N-region functional layer, the depth of which reaches the silicon substrate, a passivation layer is disposed above the P-region functional layer, the N-region functional layer and the GAP region, wherein electrodes are disposed above the P-region functional layer and the N-region functional layer, wherein the side surface of the GAP region is a slope, and the width of the top contour line of the side surface is less than 10µm.

[0126] As another embodiment, the present invention provides a back-contact solar cell, comprising an N-type silicon substrate, a front passivation layer disposed on the front side, an N-region functional layer and a P-region functional layer disposed at intervals on the back side, a TCO film disposed above the N-region functional layer and the P-region functional layer, an electrode disposed thereon, the TCO film between the P-region functional layer and the N-region functional layer is removed to form a GAP region, wherein the top contour line of the inclined surface at the junction of the N-region functional layer and the P-region functional layer is less than 10µm wide.

[0127] To enable those skilled in the art to better understand the embodiments of the present invention, the following examples are provided for description.

[0128] Example 1

[0129] A method for laser patterning of a back-contact solar cell includes the following steps:

[0130] S10 silicon wafers are polished on both sides;

[0131] Specifically, an N-type silicon wafer 10 is provided, and the silicon wafer 10 is polished on both sides, such as... Figure 1 As shown, Figure 1 The top and bottom images are schematic diagrams of the back side and cross-section of the silicon wafer after step S10, respectively.

[0132] S20 A tunneling oxide layer 11 and a boron-doped polysilicon layer 12 are prepared on the back side of the silicon wafer, wherein a first mask layer 13 is formed on the boron-doped polysilicon.

[0133] For details, see Figure 2 , Figure 2 The upper and lower figures in the image are schematic diagrams of the back side and cross-section of the silicon wafer after step S20, respectively. After this step, a tunneling oxide layer 11, a boron-doped polysilicon layer 12, and a first mask layer 13 are sequentially formed on the back side of the silicon wafer.

[0134] For example, a tunneling oxide layer and an intrinsic amorphous silicon layer can be prepared on the back side of the silicon wafer, and boron diffusion can be performed to form a boron-doped polycrystalline silicon layer. A BSG (borosilicate glass) layer is formed on top of the boron-doped polycrystalline silicon layer as a first mask layer.

[0135] Alternatively, a tunneling oxide layer and an in-situ deposited boron-doped polycrystalline silicon layer can be prepared on the back side of the silicon wafer, followed by annealing. A silicon oxynitride layer or silicon oxide layer is formed on top of the boron-doped polycrystalline silicon layer as the first mask layer.

[0136] S30 performs the first laser patterning process on the back of the silicon wafer;

[0137] Specifically, the first laser patterning process is applied to the N-region and GAP-region areas on the back of the silicon wafer. Those skilled in the art will understand that a P-region functional layer and an N-region functional layer are formed on the back of the back-contact solar cell, with a GAP-region positioned between them. In the step before the solar cell structure is formed, the N-region, P-region, and GAP-region areas all correspond to the areas where the solar cell is to be fabricated. See also... Figure 3 This is a schematic diagram of the processing in this step, where... Figure 3 The top and bottom images show schematic diagrams of the first laser patterning process in this step, with the back and cross-section of the silicon wafer shown respectively.

[0138] During the first laser patterning process, an edge processing laser scan is used to scan the edge of the first laser patterning area adjacent to the non-laser processing area. An open-film laser scan is used, and the scanned area is connected to the edge processing laser scan area, or partially overlaps with the edge processing laser scan area.

[0139] After the first patterning process, the modification or partial removal of the first mask layer 13 in the corresponding area is completed.

[0140] The laser spot width for edge processing is 2µm~50µm, preferably 5~40µm, and more preferably 20~40µm, with an energy density of 450~2500mJ / cm². 2The laser used for edge processing has a wavelength of 355~1064nm and is a picosecond or nanosecond pulsed laser. The edge processing laser is a single-pulse laser, and the laser spot can be a Gaussian spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Alternatively, the laser spot can be a flat-topped circular spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Another option is a flat-topped square spot, such as a rectangular or square spot, with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. A third option is a ring-shaped spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Finally, a fourth option is a linear spot with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. In another embodiment, the edge processing laser is a pulse train laser, where the connecting direction of the sub-pulses in each pulse train is not parallel to the scanning direction, and the projection portions of adjacent sub-pulses in the vertical scanning direction overlap. When the laser spot is a Gaussian spot, the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 50%~99%, preferably 75%~95%. The edge processing laser spot can be a flat-topped circular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The edge processing laser spot is a flat-topped square spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 1%~99%, preferably 1%~75%. The edge processing laser spot can be an annular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The laser spot for edge processing can be a linear spot, and the overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 1% to 99%, preferably 1% to 75%.

[0141] The open-film laser is a Gaussian laser or a flat-top laser, with an energy density of 450~2500 mJ / cm². 2 The wavelength is 355~1064nm, using picosecond or nanosecond pulsed lasers, and the film opening is completed in one or multiple scans.

[0142] from Figure 3 As can be seen, the first laser patterning processing area consists of multiple spaced strip-shaped areas with a width of approximately 450µm.

[0143] S40 wet cleaning removes the boron-doped polysilicon layer and tunnel oxide layer corresponding to the area processed by the first laser patterning.

[0144] Specifically, an alkaline solution is used for cleaning to remove the boron-doped polysilicon layer 12 and the tunneling oxide layer 11 corresponding to the area processed by the first laser patterning. See [link to documentation]. Figure 4 This is a schematic diagram of the silicon wafer after this processing step, where... Figure 4 The image above is a schematic diagram of the back side of a silicon wafer. Figure 4 The image below is a schematic cross-sectional view of a silicon wafer. The alkaline solution includes NaOH and water, with the NaOH having a mass fraction of 1 wt% to 3.0 wt%, an etching temperature of 65 to 75°C, and an etching time of 250 to 600 seconds. As will be understood by those skilled in the art, the alkaline solution also includes other components, such as surfactants and commercially available additives, to enhance the cleaning and wet chemical etching effects.

[0145] S50 prepares a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back side of a silicon wafer, wherein a second mask layer is formed on the phosphorus-doped polysilicon.

[0146] For details, see Figure 5 , Figure 5 The upper and lower figures in the image are schematic diagrams of the back side and cross-section of the silicon wafer after step S50, respectively. After this step, a tunneling oxide layer 11, a phosphorus-doped polycrystalline silicon layer 14, and a second mask layer 15 are formed on the back side of the silicon wafer 10.

[0147] Specifically, a tunneling oxide layer and an intrinsic amorphous silicon layer can be prepared on the back side of the silicon wafer, and phosphorus diffusion can be performed to form a phosphorus-doped polycrystalline silicon layer, on which a PSG (phosphosilicate glass) layer is formed as a second mask layer.

[0148] Alternatively, a tunneling oxide layer and an in-situ deposited phosphorus-doped polycrystalline silicon layer can be prepared on the back side of the silicon wafer, followed by annealing. A silicon oxynitride layer or a silicon oxide layer is formed above the phosphorus-doped polycrystalline silicon layer as a second mask layer.

[0149] S60 performs a second laser patterning process on the back of the silicon wafer;

[0150] Specifically, the second laser patterning process is applied to the corresponding positions of the P-region and GAP region on the back of the silicon wafer. See also... Figure 6 This is a schematic diagram of the processing in this step, where... Figure 6 The top and bottom images show schematic diagrams of the first laser patterning process in this step, respectively, from the back and cross-section of the battery.

[0151] During the second laser patterning process, an edge processing laser is used to scan the edge between the second laser patterning area and the non-laser patterning area. An open-film laser is used for scanning, and the scanning area is connected to or partially overlaps with the edge processing laser scanning area.

[0152] After a second patterning process, the modification or partial removal of the second mask layer 15 in the corresponding area was completed.

[0153] The laser spot width for edge processing is 2µm~50µm, preferably 5~40µm, and more preferably 20~40µm, with an energy density of 450~2500mJ / cm². 2 The edge processing laser has a wavelength of 355~1064nm and is a picosecond or nanosecond pulsed laser. The laser spot can be a Gaussian spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Alternatively, the edge processing laser can be a single-pulse laser with a Gaussian spot and an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Another option is a flat-topped circular spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. A third option is a flat-topped square spot, such as a rectangular or square spot, with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. A fourth option is a ring-shaped spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Finally, a fifth option is a linear spot with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. In another embodiment, the edge processing laser is a pulse train laser, where the connecting direction of the sub-pulses in each pulse train is not parallel to the scanning direction, and the projection portions of adjacent sub-pulses in the vertical scanning direction overlap. When the laser spot is a Gaussian spot, the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 50%~99%, preferably 75%~95%. The edge processing laser spot can be a flat-topped circular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The edge processing laser spot is a flat-topped square spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 1%~99%, preferably 1%~75%. The edge processing laser spot can be an annular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The laser spot for edge processing can be a linear spot, and the overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 1% to 99%, preferably 1% to 75%.

[0154] from Figure 6 As can be seen, the second laser patterning processing area consists of multiple spaced strip-shaped areas, with a width of approximately 650µm.

[0155] S70 wet cleaning removes the phosphorus-doped polysilicon layer and tunneling oxide layer corresponding to the second laser patterning area, forming a GAP region of a certain depth between adjacent P and N regions.

[0156] Specifically, an alkaline solution is used for cleaning to remove the phosphorus-doped polysilicon layer 14 and the tunneling oxide layer 11 corresponding to the area processed by the second laser patterning. See [link to documentation]. Figure 7 This is a schematic diagram of the silicon wafer after this processing step, where... Figure 7 The image above is a schematic diagram of the back side of a silicon wafer. Figure 7 The image below is a cross-sectional view of a silicon wafer. Figure 7 As can be seen, this step forms a GAP region of a certain depth between adjacent P and N regions, with a depth of 1~10µm and a width of 20~500µm.

[0157] It should be noted that, Figures 1 to 9 This diagram illustrates the back-contact solar cell manufacturing process and the silicon wafer. The GAP area in the diagram is only a schematic representation. In reality, the GAP area formed by the laser patterning and chemical etching methods of this invention has a beveled side surface, and the cross-section of the GAP area forms a trapezoidal structure. See also... Figure 10 , Figure 10 The top and bottom images in the diagram are a cross-sectional view and a back view of a silicon wafer, respectively. The diagrams schematically represent the gap area and the bevel. As seen in the top image, the side surface of the gap area is beveled. As seen in the bottom image, the top outline of this bevel is not perfectly straight; it has a positional deviation in its width direction. It should be noted that... Figure 10 For illustrative purposes, to clearly illustrate the positional deviation, the slope in the figure below exaggerates the curvature of its top contour line. Using the method of this invention, a smooth plane is formed on the side surface of the GAP area, with the width of the top contour line position of the side surface being less than 10µm. Specifically, it can be less than 1µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm, 10µm, etc. Preferably, the roughness factor of the side surface is less than 1.5, specifically, it can be less than 1.5, 1.4, 1.3, 1.2, 1.1, or 1.05.

[0158] Compared with existing laser patterning methods, the laser patterning and chemical etching method of this invention can produce a flatter, narrower, and smoother GAP area side surface. This low exposed area is more conducive to the subsequent surface passivation effect.

[0159] S80 pickling, flocking, pickling

[0160] Specifically, the phosphorus-doped and boron-doped polysilicon layers plated around the front edge are removed by acid etching. The N-region on the back side is protected by a second mask layer, and the P-region is protected by a first mask layer, preventing further corrosion.

[0161] Then, double-sided texturing is performed using an alkaline solution, forming a textured surface in the GAP areas on the front and back sides of the silicon wafer.

[0162] Then, hydrofluoric acid washing is used to remove the remaining first and second mask layers on the back side.

[0163] S90 fabricates front and back passivation layers on a silicon wafer.

[0164] Specifically, aluminum oxide layers can be prepared on the front and back sides, and then a silicon nitride layer can be prepared on top of them; for example, AlO can be deposited on the front and back sides. x / SiN x passivation layer, or AlO x / SiN x / SiON x Multilayer passivation layers, etc. See also Figure 8 , Figure 8 This is a cross-sectional view of the silicon wafer after this step. In this step, a front passivation layer 17 is formed on the front side of the silicon wafer 10, and a back passivation layer 18 is formed on the back side. As can be seen in the figure, the back passivation layer 18 covers the P-region, N-region, and GAP-region 16.

[0165] Metallization of the back side of the S100 silicon wafer completes the fabrication of a back-contact solar cell.

[0166] Specifically, the electrodes are fabricated by screen printing grid lines and then sintering. See also... Figure 9 , Figure 9 This is a cross-sectional schematic diagram of the back-contact solar cell fabricated after this step on the silicon wafer. Electrode 19 was fabricated in the P-region and N-region on the back side.

[0167] See Figure 11 This is a partial micrograph of the back side of a silicon wafer after step S70 using the method of the invention. In the figure, the blue area on the left is the GAP region, and the green and light blue areas at the boundary between the yellow and blue areas are the side surfaces. The bottom surface of the GAP is a polished surface. It can be seen that its side surface is curved along its length, maintaining a flatter state, and the width of the top outline of the side surface is smaller. Figure 11 In the figure, the width of the top profile of the side surface is less than 3µm (3.037µm in the figure). It should be noted that, as mentioned earlier, the slope of the side surface is basically the same, so the top profile of the side surface can be measured as well as the bottom profile of the side surface. Figure 12This is a partial micrograph of the back side of a silicon wafer after processing using existing techniques. The black area in the image represents the GAP region, and the boundary between the light and black areas represents the side surface. As can be seen, the width deviation of the top contour line of the side surface exceeds 20µm (23.859µm on the left and 25.708µm on the right). The remaining steps of the existing technique are the same as those in Example 1, except that an edge processing laser is not used; only a film-opening laser is used for the first and second laser patterning processes. It is evident that the width of the top contour line of the GAP region in the existing technique is significantly greater than that of the present invention. Therefore, the method of the present invention can produce a flatter GAP region side surface, which is more conducive to subsequent surface passivation.

[0168] Example 2

[0169] A method for fabricating a back-contact solar cell includes the following steps:

[0170] S01 silicon wafer double-sided polishing;

[0171] Specifically, an N-type silicon wafer 20 is provided, and the wafer is polished on both sides, such as... Figure 13 As shown, Figure 13 The top and bottom images are schematic diagrams of the back side and cross-section of the silicon wafer after step S01, respectively.

[0172] S02 involves fabricating a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back side of a silicon wafer, wherein a third mask layer is formed on the phosphorus-doped polysilicon; for details, see [link to details]. Figure 14 , Figure 14 The upper and lower figures in the image are schematic diagrams of the back side and cross-section of the silicon wafer after step S02, respectively. After this step, a tunneling oxide layer 21, a phosphorus-doped polycrystalline silicon layer 22, and a third mask layer 23 are sequentially formed on the back side of the silicon wafer 20.

[0173] Specifically, a tunneling oxide layer and an intrinsic amorphous silicon layer can be prepared on the back side of the silicon wafer, and phosphorus diffusion can be performed to form a phosphorus-doped polycrystalline silicon layer. A phosphorus silicon glass (PSG) layer is formed on top of the phosphorus-doped polycrystalline silicon layer as a third mask layer.

[0174] Alternatively, a tunneling oxide layer and an in-situ deposited phosphorus-doped polycrystalline silicon layer can be prepared on the back side of the silicon wafer, followed by annealing. A silicon oxynitride layer or a silicon oxide layer is formed on top of the phosphorus-doped polycrystalline silicon layer as a third mask layer.

[0175] S03 performs the first laser patterning process on the back of the silicon wafer;

[0176] Specifically, the first laser patterning process is applied to the area corresponding to the P-region on the back of the silicon wafer. See [link / reference] Figure 15 This is a schematic diagram of the processing in this step, where... Figure 15The top and bottom images show schematic diagrams of the first laser patterning process in this step, respectively, from the back and cross-section of the battery.

[0177] In the first laser patterning process, an edge-processing laser scans the edge between the first laser patterning area and the non-first patterning area. An open-film laser scan is used, with the scanned area either adjacent to or partially overlapping the edge-processing laser scan area. After the first patterning process, the modification or partial removal of the third mask layer 23 in the corresponding area is completed.

[0178] The laser spot width for edge processing is 2µm~50µm, preferably 5~40µm, and more preferably 20~40µm, with an energy density of 450~2500mJ / cm². 2 The laser used for edge processing has a wavelength of 355~1064nm and is a picosecond or nanosecond pulsed laser. The edge processing laser is a single-pulse laser, and the laser spot can be a Gaussian spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Alternatively, the laser spot can be a flat-topped circular spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Another option is a flat-topped square spot, such as a rectangular or square spot, with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. A third option is a ring-shaped spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Finally, a fourth option is a linear spot with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. In another embodiment, the edge processing laser is a pulse train laser, where the connecting direction of the sub-pulses in each pulse train is not parallel to the scanning direction, and the projection portions of adjacent sub-pulses in the vertical scanning direction overlap. When the laser spot is a Gaussian spot, the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 50%~99%, preferably 75%~95%. The edge processing laser spot can be a flat-topped circular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The edge processing laser spot is a flat-topped square spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 1%~99%, preferably 1%~75%. The edge processing laser spot can be an annular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The laser spot for edge processing can be a linear spot, and the overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 1% to 99%, preferably 1% to 75%.

[0179] from Figure 15As can be seen, the area processed by the first laser patterning is a strip-shaped area set at multiple intervals.

[0180] S04 Wet cleaning removes the phosphorus-doped polysilicon layer and tunnel oxide layer corresponding to the area of ​​the first laser patterning process.

[0181] Specifically, an alkaline solution is used for cleaning to remove the phosphorus-doped polysilicon layer 22 and the tunneling oxide layer 21 corresponding to the area processed by the first laser patterning. In this step, texturing of the back side's first laser-processed area and the front side are simultaneously completed, forming a pyramid structure (not shown in the figure). See [link to documentation]. Figure 16 This is a schematic diagram of the silicon wafer after this processing step, where... Figure 16 The image above is a schematic diagram of the back side of a silicon wafer. Figure 16 The image below is a cross-sectional view of a silicon wafer.

[0182] The alkaline solution comprises NaOH and water, wherein the mass fraction of NaOH is 1wt%~3.0wt%, the corrosion temperature is 65~75℃, and the corrosion time is 250~600s. As will be understood by those skilled in the art, the alkaline solution also includes other components, such as surfactants and commercially available additives, to enhance the cleaning and wet chemical corrosion effects.

[0183] S05. An intrinsic amorphous silicon layer and a boron-doped amorphous silicon layer, a boron-doped microcrystalline silicon layer, or a combination thereof are prepared on the back side of a silicon wafer.

[0184] For details, see Figure 17 This is a cross-sectional view of the silicon wafer after step S05. After this step, an intrinsic amorphous silicon layer 24 and a boron-doped amorphous silicon layer, a boron-doped microcrystalline silicon layer, or a combination thereof 25 are formed on the back side of the silicon wafer 20.

[0185] S06 Opens the conductive channel in the N region;

[0186] Specifically, a laser is used to process the N-region on the back side of the silicon wafer, removing the boron-doped amorphous silicon layer, boron-doped microcrystalline silicon layer, or a combination thereof 25, the intrinsic amorphous silicon layer 24, and the third mask layer 23, forming a conductive channel extending directly to the phosphorus-doped polycrystalline silicon layer 22 in the N-region. See also Figure 18 This is a cross-sectional diagram of the silicon wafer after this step.

[0187] Alternatively, laser can be used to remove the boron-doped amorphous silicon layer, boron-doped microcrystalline silicon layer or a combination thereof, as well as the intrinsic amorphous silicon layer, followed by chemical etching to remove the first mask layer and form a conductive channel.

[0188] The laser used here is a Gaussian laser or a flat-top laser, with an energy density of 150~600 mJ / cm². 2The wavelength is 355~1064nm, using picosecond or nanosecond pulsed lasers, and the film opening is completed in one or multiple scans.

[0189] S07. A TCO layer is prepared on the back side of the silicon wafer;

[0190] Specifically, the TCO layer can be prepared using existing technologies. See [link / reference] Figure 19 This is a cross-sectional view of the silicon wafer after this step.

[0191] S08. A front passivation layer is prepared on the front side of the silicon wafer;

[0192] Specifically, an alumina layer can be prepared on the front side, and then a silicon nitride layer can be prepared on it; for example, AlO can be deposited on the front side. x / SiN x passivation layer, or AlO x / SiN x / SiON x Multilayer passivation layers, etc. See also Figure 20 This is a cross-sectional view of the silicon wafer after this step.

[0193] S09 PN area isolation;

[0194] The TCO layer between the P-region and N-region is removed using laser or etching paste, thus achieving isolation between the PN regions. In this step, existing techniques can be used to remove the TCO layer between the PN regions. See [link to relevant documentation] Figure 21 This is a cross-sectional view of the silicon wafer after this step.

[0195] S010 is used to fabricate electrodes on the back side of a silicon wafer.

[0196] In this step, electrodes can be fabricated in the P-region and N-region using existing techniques. See [link / reference] Figure 22 This is a cross-sectional schematic diagram of the back contact solar cell prepared after this step on the silicon wafer.

[0197] It should be noted that, Figures 13 to 22This diagram illustrates the back-contact solar cell manufacturing process and the silicon wafer. The P-region and N-region are schematic representations. The actual boundary between the P-region and N-region is formed by the laser patterning and chemical etching method of this invention. Using this method, the width of the top contour line of the boundary between the P-region and N-region is less than 10µm; specifically, it can be less than 1µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm, 10µm, etc. That is, the projection of the boundary surface onto the main plane of the silicon wafer is curved along its length, making it more flat. The roughness factor of the boundary surface is less than 1.5; specifically, it can be less than 1.5, 1.4, 1.3, 1.2, 1.1, or 1.05. Compared with existing laser patterning methods, the laser patterning and chemical etching method of this invention can produce a more straight and smoother bevel at the junction of the P and N regions along the length direction. On the one hand, a smaller side surface means lower surface recombination. On the other hand, the PN heterojunction formed after P-type amorphous silicon deposition has a smooth junction surface, which means a more uniform junction distribution and fewer junction recombination centers.

[0198] Example 3

[0199] A method for fabricating a back-contact solar cell includes the following steps:

[0200] S10 silicon wafer double-sided texturing;

[0201] Specifically, N-type silicon wafers are provided, and double-sided texturing is performed on the silicon wafers;

[0202] S20 involves boron diffusion and oxidation on the back side of the silicon wafer. After boron diffusion, a boron diffusion layer (PN junction) is formed, and a BSG layer is formed on the PN junction as the first mask layer.

[0203] S30 performs the first laser patterning process on the back of the silicon wafer;

[0204] Specifically, the first laser patterning process is performed on the area corresponding to the P-zone on the back of the silicon wafer.

[0205] In the first laser patterning process, an edge-processing laser scans the edge between the patterned area and the non-patterned area. An open-film laser scan is then used, with the scanned area either adjacent to or partially overlapping the edge-processing laser scanned area. This first patterning process completes the modification or partial removal of the BSG mask layer.

[0206] The edge processing laser has a spot width of 2µm to 50µm, preferably 5 to 40µm, and more preferably 20 to 40µm, with an energy density of 450 to 2500 mJ / cm². 2The laser used for edge processing has a wavelength of 355~1064nm and is a picosecond or nanosecond pulsed laser. The edge processing laser is a single-pulse laser, and the laser spot can be a Gaussian spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Alternatively, the laser spot can be a flat-topped circular spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Another option is a flat-topped square spot, such as a rectangular or square spot, with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. A third option is a ring-shaped spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Finally, a fourth option is a linear spot with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. In another embodiment, the edge processing laser is a pulse train laser, where the connecting direction of the sub-pulses in each pulse train is not parallel to the scanning direction, and the projection portions of adjacent sub-pulses in the vertical scanning direction overlap. When the laser spot is a Gaussian spot, the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 50%~99%, preferably 75%~95%. The edge processing laser spot can be a flat-topped circular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The edge processing laser spot is a flat-topped square spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 1%~99%, preferably 1%~75%. The edge processing laser spot can be an annular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The laser spot for edge processing can be a linear spot, and the overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 1% to 99%, preferably 1% to 75%.

[0207] The open-film laser is a Gaussian laser or a flat-top laser, with an energy density of 450~2500 mJ / cm². 2 A picosecond or nanosecond pulsed laser with a wavelength of 355~1064nm is used to cover the remaining area in one or multiple scans to complete the film opening.

[0208] The first laser patterning process involves multiple spaced strip-shaped areas, each approximately 450µm wide.

[0209] S40 chain wet process removes the oxide layer formed on the front side, and tank wet cleaning removes the BSG and boron diffusion layer (PN junction) corresponding to the first laser patterning area.

[0210] Specifically, a chain-like process is used to clean the front side of the boron-diffused silicon wafer with an HF acid solution to remove the silicon oxide film formed during the boron diffusion process. The HF acid solution concentration is 1%–12%, the temperature is 20–25°C, and the etching time is 15–60 seconds.

[0211] Specifically, a tank-type alkaline solution is used for cleaning to remove the BSG and PN junctions formed by boron diffusion in the area of ​​the first laser patterning process. During this step, the first laser-processed area on the back side and the front side are simultaneously polished, resulting in a flat surface.

[0212] The alkaline solution comprises NaOH and water, wherein the mass fraction of NaOH is 1wt% to 10.0wt%, the corrosion temperature is 65 to 75°C, and the corrosion time is 250 to 600 s. As will be understood by those skilled in the art, the alkaline solution also includes other components, such as surfactants and commercially available additives, to enhance the cleaning and wet chemical corrosion effects.

[0213] S50 prepares a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back side of a silicon wafer, wherein a second mask layer is formed on the phosphorus-doped polysilicon.

[0214] Specifically, a tunneling oxide layer and an intrinsic amorphous silicon layer can be prepared on the back side of the silicon wafer, and phosphorus diffusion can be performed to form a phosphorus-doped polycrystalline silicon layer, on which a PSG (phosphosilicate glass) layer is formed as a second mask layer.

[0215] Alternatively, a tunneling oxide layer and an in-situ deposited phosphorus-doped polycrystalline silicon layer can be prepared on the back side of the silicon wafer, followed by annealing. A silicon oxynitride layer or a silicon oxide layer is formed above the phosphorus-doped polycrystalline silicon layer as a second mask layer.

[0216] S60 performs a second laser patterning process on the back of the silicon wafer;

[0217] Specifically, the second laser patterning process is applied to the corresponding positions of the P-area and GAP-area on the back of the silicon wafer.

[0218] During the second laser patterning process, an edge processing laser is used to scan the edge between the second laser patterning area and the non-laser patterning area. An open-film laser is used for scanning, and the scanning area is connected to or partially overlaps with the edge processing laser scanning area.

[0219] After a second patterning process, the modification or partial removal of the second mask layer in the corresponding area was completed.

[0220] The laser spot width for edge processing is 2µm~50µm, preferably 5~40µm, and more preferably 20~40µm, with an energy density of 450~2500mJ / cm². 2The laser used for edge processing has a wavelength of 355~1064nm and is a picosecond or nanosecond pulsed laser. The edge processing laser is a single-pulse laser, and the laser spot can be a Gaussian spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Alternatively, the laser spot can be a flat-topped circular spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Another option is a flat-topped square spot, such as a rectangular or square spot, with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. A third option is a ring-shaped spot with an overlap rate of 50%~99% in the scanning direction, preferably 75%~95%. Finally, a fourth option is a linear spot with an overlap rate of 1%~99% in the scanning direction, preferably 1%~75%. In another embodiment, the edge processing laser is a pulse train laser, where the connecting direction of the sub-pulses in each pulse train is not parallel to the scanning direction, and the projection portions of adjacent sub-pulses in the vertical scanning direction overlap. When the laser spot is a Gaussian spot, the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 50%~99%, preferably 75%~95%. The edge processing laser spot can be a flat-topped circular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The edge processing laser spot is a flat-topped square spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 1%~99%, preferably 1%~75%. The edge processing laser spot can be an annular spot, with the spot overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction being 50%~99%, preferably 75%~95%. The laser spot for edge processing can be a linear spot, and the overlap rate of corresponding sub-pulses in adjacent pulse trains in the scanning direction is 1% to 99%, preferably 1% to 75%.

[0221] The open-film laser is a Gaussian laser or a flat-top laser, with an energy density of 450~2500 mJ / cm². 2 The wavelength is 355~1064nm, using picosecond or nanosecond pulsed lasers, and the film opening is completed in one or multiple scans.

[0222] The second laser patterning process area consists of multiple spaced strip-shaped regions, each approximately 650µm wide.

[0223] S70 wet cleaning removes the phosphorus-doped polysilicon layer and tunneling oxide layer corresponding to the second laser patterning area, forming a GAP region of a certain depth between adjacent P and N regions.

[0224] Specifically, an alkaline solution is used for cleaning to remove the phosphorus-doped polysilicon layer and tunneling oxide layer corresponding to the area processed by the second laser patterning. This step creates a GAP region of a certain depth between adjacent P-regions and N-regions, with a depth of 1–10 µm and a width of 20–500 µm.

[0225] Using the method of this invention, a smooth plane is formed on the side surface of the GAP area, with the width of the top contour line of the side surface being less than 10µm. Specifically, it can be less than 1µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm, 10µm, etc. That is, the projection of the GAP area side surface onto the main plane of the silicon wafer is curved along its length, resulting in a smoother surface. Preferably, the roughness factor of the side surface is less than 1.5, specifically less than 1.5, 1.4, 1.3, 1.2, 1.1, 1.05. Compared with existing laser patterning methods, the laser patterning combined with chemical etching method of this invention can produce a flatter, narrower, and smoother GAP area side surface. This low exposed area is more conducive to subsequent surface passivation.

[0226] S80 pickling, flocking, pickling

[0227] Specifically, the phosphorus-doped and boron-doped polysilicon layers plated around the front edge are removed by acid etching. The N-region on the back side is protected by a second mask layer, and the P-region is protected by a first mask layer, preventing further corrosion.

[0228] Then, double-sided texturing is performed using an alkaline solution, forming a textured surface in the GAP areas on the front and back sides of the silicon wafer.

[0229] Then, hydrofluoric acid washing is used to remove the remaining first and second mask layers on the back side.

[0230] S90 fabricates front and back passivation layers on a silicon wafer.

[0231] Specifically, aluminum oxide layers can be prepared on the front and back sides, and then a silicon nitride layer can be prepared on top of them; for example, AlO can be deposited on the front and back sides. x / SiN x passivation layer, or AlO x / SiN x / SiON x Multilayer passivation layers, etc.

[0232] Metallization of the back side of the S100 silicon wafer completes the fabrication of a back-contact solar cell.

[0233] Specifically, the electrodes are prepared by screen printing grid lines and sintering.

[0234] A back-contact solar cell, fabricated using the methods of Example 1 or Example 3, includes an N-type silicon substrate 10. A front passivation layer 17 is disposed on the front side, and an N-region functional layer and a P-region functional layer are disposed on the back side at intervals. A GAP region 16 is disposed between the N-region and P-region functional layers. The GAP region is a groove positioned opposite the P-region and N-region functional layers, with its depth reaching the silicon substrate. Passivation layers are disposed above the P-region, N-region, and GAP regions. Electrodes 19 are also disposed above the P-region and N-region functional layers. The side surface of the GAP region is sloped, with the top contour line width less than 10µm. Specifically, it can be less than 1µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm, or 10µm. That is, the projection of the GAP region side surface onto the main plane of the silicon wafer is curved along its length, resulting in a smoother surface. The roughness factor of the side surface is less than 1.5, specifically, it can be less than 1.5, 1.4, 1.3, 1.2, 1.1, or 1.05.

[0235] Specifically, the P-region functional layer can be a tunneling oxide layer 11 and a boron-doped polysilicon layer 12 arranged sequentially, and the N-region functional layer can be a tunneling oxide layer 11 and a phosphorus-doped polysilicon layer 14 arranged sequentially. Alternatively, the P-region functional layer can be a boron diffusion layer, and the N-region functional layer can be a tunneling oxide layer and a phosphorus-doped polysilicon layer arranged sequentially.

[0236] On the other hand, the present invention provides a back-contact solar cell, fabricated by the method of Example 2, comprising an N-type silicon substrate 20, with a front passivation layer 27 disposed on its front side, and an N-region functional layer and a P-region functional layer disposed at intervals on its back side. A TCO film 18 is disposed above the N-region and P-region functional layers, and an electrode 19 is disposed on the TCO film. The TCO film between the P-region and N-region functional layers is removed to form a GAP region. The width of the top contour line of the slope at the junction of the N-region and P-region functional layers is less than 10µm, specifically less than 1µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm, 10µm, etc. The roughness factor of the slope is less than 1.5, specifically less than 1.5, 1.4, 1.3, 1.2, 1.1, 1.05.

[0237] Specifically, the P-region functional layer includes an intrinsic amorphous silicon layer 24 and a boron-doped amorphous silicon layer, a boron-doped microcrystalline silicon layer or a combination thereof 25, and the N-region functional layer includes a tunneling oxide layer 21, a phosphorus-doped polycrystalline silicon layer 22, a mask layer 23, an intrinsic amorphous silicon layer 24 and a boron-doped amorphous silicon layer, a boron-doped microcrystalline silicon layer or a combination thereof 25.

[0238] It should be noted that the technical concept of the present invention is not limited to the specific embodiments described above. Any technical solution that uses the same or substantially the same technical means as this application and is applied to a back contact solar cell structure with conductive functional layers of different polarities is within the protection scope of this application.

[0239] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a back-contact solar cell, comprising fabricating a functional layer and a mask layer on the back side of a silicon wafer, characterized in that: Laser patterning is performed on the back side of a silicon wafer to remove part of the mask layer or modify the mask layer; wherein, a film-opening laser is used to scan the main body of the patterned processing area, and an edge processing laser is used to scan the edge of the patterned processing area, and the union of the film-opening laser scanning area and the edge processing laser scanning area is the patterned processing area; The laser spots used for edge processing are superimposed along their scanning direction to form a straight laser processing line; Wet cleaning removes the functional layer corresponding to the laser-patterned processing area; The laser patterning processing area is the corresponding position of the N area, the corresponding position of the P area, the corresponding position of the N area and the GAP area, or the corresponding position of the P area and the GAP area.

2. The method for fabricating a back-contact solar cell according to claim 1, characterized in that: The functional layer is a tunneling oxide layer and a doped polysilicon layer arranged sequentially, or a boron diffusion layer, wherein the doped polysilicon layer is a phosphorus-doped polysilicon layer or a boron-doped polysilicon layer.

3. The method for fabricating a back-contact solar cell according to claim 1, characterized in that: The edge processing laser is a nanosecond or picosecond pulsed laser.

4. The method for fabricating a back-contact solar cell according to claim 1, characterized in that: The wet cleaning method involves using an alkaline solution for cleaning.

5. The method for fabricating a back-contact solar cell according to claim 1, characterized in that: The side surface of the patterned processing area after wet cleaning is a slope, and the width of the top outline of the side surface is less than 10µm.

6. The method for fabricating a back-contact solar cell according to claim 1, characterized in that: The laser spot width for edge processing is 2µm to 50µm.

7. The method for fabricating a back-contact solar cell according to claim 1, characterized in that: The edge processing laser is a single-pulse laser. When the laser spot is a Gaussian spot, the spot overlap rate in the scanning direction is 50%~99%; when the laser spot is a flat-topped circular spot, the spot overlap rate in the scanning direction is 50%~99%; when the laser spot is a flat-topped square spot, the spot overlap rate in the scanning direction is 1%~99%; when the laser spot is an annular spot, the spot overlap rate in the scanning direction is 50%~99%; when the laser spot is a linear spot, the overlap rate in the scanning direction is 1%~99%. Alternatively, the edge processing laser may be a pulse train laser, where the connecting direction of the sub-pulses in each pulse train is not parallel to the scanning direction, and the projections of adjacent sub-pulses in the vertical scanning direction overlap. When the laser spot is a Gaussian spot, the overlap rate of the corresponding sub-pulses in the scanning direction of adjacent pulse trains is 50%~99%; when the laser spot is a flat-topped circular spot, the overlap rate of the corresponding sub-pulses in the scanning direction of adjacent pulse trains is 50%~99%; when the laser spot is a flat-topped square spot, the overlap rate of the corresponding sub-pulses in the scanning direction of adjacent pulse trains is 1%~99%; when the laser spot is an annular spot, the overlap rate of the corresponding sub-pulses in the scanning direction of adjacent pulse trains is 50%~99%; and when the laser spot is a linear spot, the overlap rate of the corresponding sub-pulses in the scanning direction of adjacent pulse trains is 1%~99%.

8. The method for fabricating a back-contact solar cell according to claim 1, characterized in that: The edge processing laser is a single-pulse laser. When the laser spot is a Gaussian spot, the spot overlap rate in the scanning direction is 75%~95%; when the laser spot is a flat-topped circular spot, the spot overlap rate in the scanning direction is 75%~95%; when the laser spot is a flat-topped square spot, the spot overlap rate in the scanning direction is 1%~75%; when the spot is an annular spot, the spot overlap rate in the scanning direction is 75%~95%; when the spot is a linear spot, the overlap rate in the scanning direction is 1%~75%. Alternatively, the edge processing laser may be a pulse train laser, wherein the connecting direction of the sub-pulses in each pulse train is not parallel to the scanning direction, and the projections of adjacent sub-pulses in the vertical scanning direction overlap. When the laser spot is a Gaussian spot, the overlap rate of the corresponding sub-pulses of adjacent pulse trains in the scanning direction is 75%~95%; when the laser spot is a flat-topped circular spot, the overlap rate of the corresponding sub-pulses of adjacent pulse trains in the scanning direction is 75%~95%; when the laser spot is a flat-topped square spot, the overlap rate of the corresponding sub-pulses of adjacent pulse trains in the scanning direction is 1%~75%; when the laser spot is an annular spot, the overlap rate of the corresponding sub-pulses of adjacent pulse trains in the scanning direction is 75%~95%; and when the laser spot is a linear spot, the overlap rate of the corresponding sub-pulses of adjacent pulse trains in the scanning direction is 1%~75%.

9. A method for preparing a back-contact solar cell according to any one of claims 1 to 8, characterized in that: Includes the following steps, S10 silicon wafer pretreatment; S20 A first functional layer is prepared on the back side of a silicon wafer. The first functional layer has a first doped layer and a first mask layer is formed on the first functional layer. S30 performs the first laser patterning process on the back of the silicon wafer; The first laser patterning process is performed on the areas corresponding to the N-zone and the GAP-zone. S40 wet cleaning removes the first functional layer from the area of ​​the first laser patterning process; S50 A second functional layer is fabricated on the back side of a silicon wafer. The second functional layer has a second doped layer and a second mask layer is formed on the second functional layer. S60 performs a second laser patterning process on the back of the silicon wafer; The second patterning process area is the area corresponding to the P area and the GAP area; S70 wet cleaning removes the second functional layer of the second laser patterning area, forming a GAP area of ​​a certain depth between adjacent P and N areas; S80 pickling removes the first and second doped layers that were plated around the front edge; alkaline solution is used for double-sided texturing to form a textured surface in the GAP area on the front and back sides of the silicon wafer; then hydrofluoric acid pickling removes the remaining first and second mask layers on the back side. S90 fabricates a front passivation layer and a back passivation layer on a silicon wafer. Metallization of the back side of the S100 silicon wafer completes the fabrication of the back-contact solar cell; The first and second functional layers have opposite conductivity types.

10. The method for fabricating a back-contact solar cell according to claim 9, characterized in that: The pretreatment of S10 silicon wafers is double-sided polishing; The first functional layer is a tunneling oxide layer and a boron-doped polysilicon layer; the second functional layer is a tunneling oxide layer and a phosphorus-doped polysilicon layer.

11. The method for fabricating a back-contact solar cell according to claim 9, characterized in that: The pretreatment of S10 silicon wafers involves texturing both sides of the silicon wafers. The first functional layer is a boron diffusion layer; the second functional layer is a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer.

12. The method for fabricating a back-contact solar cell according to claim 9, characterized in that: The side surface of the GAP area is a slope, and the width of the top outline of the side surface is less than 10µm.

13. A method for fabricating a back-contact solar cell according to claim 9, characterized in that: The depth of the GAP area is 1~10µm and the width is 20~500µm.

14. A method for preparing a back-contact solar cell according to any one of claims 1 to 8, characterized in that: Includes the following steps, S01 silicon wafer double-sided polishing; S02 prepares a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back side of a silicon wafer, wherein a third mask layer is formed on the phosphorus-doped polysilicon. S03 performs the first laser patterning process on the back of the silicon wafer; The area for the first laser patterning process is the area corresponding to region P; S04 wet cleaning removes the phosphorus-doped polysilicon layer and tunnel oxide layer in the area of ​​the first laser patterning process, while simultaneously completing the texturing of the area of ​​the first laser processing on the back and the front, forming a pyramid structure. S05. An intrinsic amorphous silicon layer and a boron-doped amorphous silicon layer, a boron-doped microcrystalline silicon layer, or a combination thereof are prepared on the back side of a silicon wafer. S06 Opens the conductive channel in the N region; Process the N-region on the back side of the silicon wafer, remove the boron-doped amorphous silicon layer, boron-doped microcrystalline silicon layer or a combination thereof, the intrinsic amorphous silicon layer and the third mask layer, and form a conductive channel that reaches the phosphorus-doped polycrystalline silicon layer in the N-region. S07. A TCO layer is prepared on the back side of the silicon wafer; S08. A front passivation layer is prepared on the front side of the silicon wafer; S09 Remove the TCO layer between the P region and the N region to complete the PN region isolation; S010 prepares electrodes on the back side of the silicon wafer, completing the fabrication of a back-contact solar cell.

15. The method for fabricating a back-contact solar cell according to claim 14, characterized in that: The top profile of the slope at the boundary between P and N regions is less than 10µm wide.

16. A back-contact solar cell, characterized in that: Prepared using the method described in any one of claims 9 to 13, The device includes an N-type silicon substrate with a passivation layer on its front side and an N-region functional layer and a P-region functional layer spaced apart on its back side. A GAP region is formed between the N-region and P-region functional layers. The GAP region is a groove formed relative to the P-region and N-region functional layers, with its depth reaching the silicon substrate. Passivation layers are formed above the P-region, N-region, and GAP regions. Electrodes are also formed above the P-region and N-region functional layers. The side surface of the GAP region is a slope, and the width of the top contour line of the side surface is less than 10µm.

17. A back-contact solar cell, characterized in that: The substrate is prepared using the method of claim 14 or 15, comprising an N-type silicon substrate, wherein a front passivation layer is disposed on the front side, and an N-region functional layer and a P-region functional layer are disposed at intervals on the back side, a TCO film is disposed above the N-region functional layer and the P-region functional layer, an electrode is disposed thereon, the TCO film between the P-region functional layer and the N-region functional layer is removed, wherein the top contour line of the inclined surface at the junction of the N-region functional layer and the P-region functional layer is less than 10µm wide.

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