Micro light-emitting diode array and preparation method thereof, display device and electronic equipment

Abstract

The invention discloses a micro light-emitting diode array and a preparation method thereof, a display device and electronic equipment, and belongs to the technical field of display. Wherein a substrate of the micro light-emitting diode array comprises at least two element areas, a micro light-emitting diode and at least one electrode unit are formed in each element area, and the electrode units and the micro light-emitting diodes are manufactured by adopting the same process. The micro light-emitting diode comprises a first doped semiconductor layer, an active layer, a second doped semiconductor layer and a first electrode, and the electrode unit is electrically connected with the first doped semiconductor layer in the micro light-emitting diode to realize independent control of the micro light-emitting diode. In the micro light-emitting diode array, the first electrode and the electrode unit of each micro light-emitting diode form a group of electrodes, each group of electrodes can be independently controlled, and the heights of the electrode units and the micro light-emitting diodes manufactured by the same process are equal, so that the subsequent electric connection with a driving circuit is facilitated.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a micro light-emitting diode array and its fabrication method, display device and electronic device. Background Technology

[0002] Micro-LED arrays are considered the most ideal light-emitting solution for augmented reality (AR) displays due to their advantages such as high brightness, low power consumption, fast response time, high contrast, high resolution, and color saturation. Currently, micro-LED arrays typically use multiple micro-LED elements sharing a common N-electrode, or require complex processes such as secondary bonding of temporary substrates and removal of epitaxial substrates to achieve independent connection between the N-electrode and the CMOS driving circuit. With the common N-electrode connection to the CMOS driving circuit, N-type current mirrors or N-type MOSFET-based driving circuits are not allowed in the CMOS driving circuit design. Furthermore, because all pixel units in a Micro-LED array share a common N-electrode, individual pixels can only be independently controlled through the voltage at the P-terminal, which limits the voltage range. Summary of the Invention

[0003] This application provides a micro-light-emitting diode array and its fabrication method, display device and electronic device, aiming to realize that the electrodes at both ends of each micro-light-emitting diode element in the micro-light-emitting diode array can be independently controlled.

[0004] In a first aspect, this application provides a micro-light-emitting diode array, including a substrate. The substrate includes at least two element regions, each containing a micro-light-emitting diode and at least one electrode unit. The electrode unit and the micro-light-emitting diode are fabricated using the same process. The micro-light-emitting diode includes a first doped semiconductor layer, an active layer, a second doped semiconductor layer, and a first electrode. The electrode unit is electrically connected to the first doped semiconductor layer in the micro-light-emitting diode, enabling independent control of the micro-light-emitting diode.

[0005] In some embodiments, the electrode unit includes an auxiliary active layer, an auxiliary second doped semiconductor layer and a second electrode sequentially formed above a first doped semiconductor layer. Each element region also includes an auxiliary metal layer, a first end of which is electrically connected to the second electrode and a second end of which is electrically connected to the first doped semiconductor layer.

[0006] In some embodiments, the second electrode and the first electrode are formed in the same process step, and the second electrode and the first electrode have the same height and the same thickness.

[0007] In some embodiments, the micro-light-emitting diode further includes a conductive layer located between the second doped semiconductor layer and the first electrode. The electrode unit further includes an auxiliary conductive layer located between an auxiliary second doped semiconductor layer and the second electrode. A first end of an auxiliary metal layer covers a portion of the auxiliary conductive layer and is electrically connected to the second electrode through the auxiliary conductive layer. The conductive layer and the auxiliary conductive layer are formed in the same process step.

[0008] In some embodiments, both the conductive layer and the auxiliary conductive layer are indium tin oxide layers.

[0009] In some embodiments, a spacer region is provided between the first doped semiconductor layers of adjacent element regions, and the spacer region is at least one of a trench region, an ion implantation region, and a passivation layer.

[0010] In this embodiment, within each element region, the first electrode and electrode unit of each micro-LED serve as the two ends of a set of electrodes for the micro-LED. Each set of electrodes can be independently controlled, thereby enabling independent control of the micro-LEDs within each element region. This expands the application scenarios of micro-LED arrays and broadens the voltage range of individual micro-LED elements, which is beneficial for improving display brightness. The electrode units and micro-LEDs are manufactured using the same process, ensuring they have the same height. Specifically, the height of the upper surface of the first electrode of the micro-LED relative to the substrate is equal to the height of the upper surface of the electrode unit relative to the substrate, facilitating subsequent connection to the driving circuit.

[0011] On the other hand, embodiments of this application also provide a method for fabricating a micro-light-emitting diode array, comprising the following steps S10 to S20:

[0012] Step S10: Provide a substrate, which includes at least two element regions.

[0013] Step S20: Form a micro light-emitting diode and at least one electrode unit in each element region.

[0014] The steps for forming a micro light-emitting diode include: sequentially forming a first doped semiconductor layer, an active layer, a second doped semiconductor layer, and a first electrode on a substrate.

[0015] At least one electrode unit is formed simultaneously in the step of forming the micro light-emitting diode. The electrode unit is electrically connected to the first doped semiconductor layer in the micro light-emitting diode, thereby realizing independent control of the micro light-emitting diode.

[0016] In some embodiments, the electrode unit includes an auxiliary active layer, an auxiliary second doped semiconductor layer, and a second electrode sequentially formed above a first doped semiconductor layer.

[0017] The aforementioned "at least one electrode unit is formed simultaneously in the step of forming the micro light-emitting diode" includes the following steps S21 to S24:

[0018] Step S21: Sequentially form a first doped semiconductor layer, a basic active layer, and a basic second doped semiconductor layer on the substrate.

[0019] Step S22: Remove a portion of the base second doped semiconductor layer to form a separate second doped semiconductor layer and an auxiliary second doped semiconductor layer, the second doped semiconductor layer and the auxiliary second doped semiconductor layer having equal thickness.

[0020] Step S23: Remove part of the base active layer to form a separate active layer and an auxiliary active layer, and expose part of the first doped semiconductor layer.

[0021] Step S24: Form a first electrode and a second electrode in the same process. The first electrode is located on the second doped semiconductor layer, and the second electrode is located on the auxiliary second doped semiconductor layer. The first electrode and the second electrode have the same thickness.

[0022] In some embodiments, the above preparation method further includes forming an auxiliary metal layer, wherein a first end of the auxiliary metal layer is electrically connected to a second electrode, and a second end of the auxiliary metal layer is electrically connected to a first doped semiconductor layer.

[0023] In some embodiments, before removing a portion of the base second doped semiconductor layer, the above-mentioned "at least one electrode unit is simultaneously formed in the step of forming the micro light-emitting diode" further includes the following steps S211 to S212:

[0024] Step S211: Form a basic conductive layer on the basic second doped semiconductor layer.

[0025] Step S212: Remove a portion of the base conductive layer to form a separate conductive layer and an auxiliary conductive layer, both with the same thickness. The formed conductive layer is located above the second doped semiconductor layer, the auxiliary conductive layer is located above the auxiliary second doped semiconductor layer, the first electrode is located above the conductive layer, and the second electrode is located above the auxiliary conductive layer.

[0026] Alternatively, in some embodiments, after forming a separate second doped semiconductor layer and an auxiliary second doped semiconductor layer, a conductive layer and an auxiliary conductive layer are formed using the same photolithography process. The conductive layer and the auxiliary conductive layer have the same thickness, wherein the conductive layer is located above the second doped semiconductor layer, and the auxiliary conductive layer is located above the auxiliary second doped semiconductor layer. A first electrode is located above the conductive layer, and a second electrode is located above the auxiliary conductive layer.

[0027] In some embodiments, forming an auxiliary metal layer includes a first end of the formed auxiliary metal layer covering a portion of the auxiliary conductive layer, and forming a second electrode includes the formed second electrode being electrically connected to the auxiliary metal layer through the auxiliary conductive layer.

[0028] In some embodiments, a spacer region is formed between first doped semiconductor layers in adjacent element regions, the spacer region being at least one of a trench region, an ion implantation region, and a passivation layer.

[0029] In some embodiments, a spacer region is formed after the first electrode and the second electrode are formed. Alternatively, the spacer region is formed after the auxiliary metal layer is formed and before the first electrode and the second electrode are formed. Or, the spacer region is formed before the auxiliary metal layer is formed.

[0030] In the fabrication method proposed in this application, at least one electrode unit is formed simultaneously in the step of forming the micro-light-emitting diode (LED), which simplifies the process and allows the electrode unit and the micro-LED to have the same height, facilitating subsequent connection with the driving circuit. Furthermore, in each element region, the electrode unit is electrically connected to the first doped semiconductor layer in the micro-LED, enabling independent control of the micro-LED, expanding the application scenarios of the micro-LED array, and increasing the voltage range of a single micro-LED element, which is beneficial for improving display brightness.

[0031] Furthermore, this application also provides a display device, including a micro-light-emitting diode array mentioned in any of the embodiments of the first aspect above, and a microlens, wherein the microlens at least covers the micro-light-emitting diodes, and the microlens is used to adjust the direction of light convergence, so that the display device displays relevant content. This display device has the same technical effects as the aforementioned micro-light-emitting diode array, and will not be described in detail here.

[0032] Furthermore, this application also provides an electronic device, including the aforementioned display device. This electronic device has the same technical effects as the aforementioned display device, and will not be described in detail here.

[0033] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0034] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0035] Figure 1 This is a schematic diagram of a micro-light-emitting diode array structure provided in an embodiment of this application;

[0036] Figure 2This is a schematic diagram of another micro-light-emitting diode array structure provided in an embodiment of this application;

[0037] Figure 3 A flowchart illustrating a method for fabricating a micro-light-emitting diode array, as provided in this application embodiment;

[0038] Figures 4 to 14 This application provides a step diagram illustrating the fabrication method of a micro-light-emitting diode array.

[0039] Figure 15 A schematic diagram of the light-emitting pixels of a micro-LED array provided in this application embodiment;

[0040] Figure 16 A schematic diagram of a micro-light-emitting diode array provided in an embodiment of this application;

[0041] Figure 17 This application provides another schematic diagram of a micro-light-emitting diode array planar representation.

[0042] Figures 18-22 This is a step diagram illustrating the method for preparing the spacer region according to an embodiment of this application;

[0043] Figure 23 A schematic diagram of a display device provided in an embodiment of this application;

[0044] Figure 24 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0045] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0046] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0047] In the description of this application, "multiple" means two or more.

[0048] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0049] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The term "electrical connection" indicates, for example, that two or more components have direct physical or electrical contact, but may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0050] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0051] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0052] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0053] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0054] Currently, micro-LED arrays typically employ multiple micro-LED elements sharing a common N-electrode. For example, according to existing epitaxial growth techniques, the P-type semiconductor layer constituting the micro-LED element grows later than the N-type semiconductor layer, thus residing on the surface of the epitaxial wafer. Therefore, bonding the surface of the P-type semiconductor layer of the micro-LED to the surface of the driver chip is a common bonding method, where the driver chip can be a complementary metal-oxide-semiconductor (CMOS) driver chip.

[0055] This is because, if the surface of the N-type semiconductor layer of the Micro-LED is to be bonded to the surface of the CMOS driver chip, a temporary bonding method is required. First, the surface of the P-type semiconductor layer of the Micro-LED is bonded to a temporary substrate, the epitaxial growth substrate is removed to expose the surface of the N-type semiconductor layer of the Micro-LED, and then a second bonding is used to bond the surface of the N-type semiconductor layer of the Micro-LED to the surface of the CMOS driver chip. The process is relatively complex and cumbersome, and is rarely used.

[0056] A common approach to achieve independent control of individual Micro-LEDs is to bond the surface of the P-type semiconductor layer of the Micro-LED to the surface of the CMOS driver chip via a single bonding process, and then connect the P-electrodes of each Micro-LED on the P-type semiconductor layer to the underlying CMOS driver circuit. In this approach, a common N-electrode is formed on the N-type semiconductor layer (away from the bonding interface) and connected to the underlying CMOS driver circuit by utilizing the inherent current spreading capability of the N-type semiconductor layer or by adding a conductive layer to its surface.

[0057] In the aforementioned connection method using a common N-electrode to the CMOS driving circuit, the P-electrode and N-electrode have different heights on the substrate, making the connection process with the driving circuit more complex. Using a common N-electrode prevents the application of N-type current mirrors, N-type MOSFET-based driving circuits, or pixel circuits sharing a low-voltage supply (ELVDD) in CMOS driving circuit design. Furthermore, since all pixels in the Micro-LED array (i.e., all Micro-LEDs) share a common N-electrode, individual pixels can only be independently controlled by adjusting the voltage on the P-electrode side, limiting the voltage range.

[0058] In view of the above, this application provides a micro light-emitting diode array, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a micro light-emitting diode array structure provided in an embodiment of this application.

[0059] The micro-light-emitting diode array 100 includes a substrate 10, on which at least two element regions are included, such as Figure 1 Region A corresponds to one component region, and region B corresponds to another component region. Each component region contains a micro-light-emitting diode (LED) M1 and at least one electrode unit M2. The electrode unit M2 is fabricated using the same process as the micro-LED M1. The micro-LED M1 includes a first doped semiconductor layer 11 formed on the substrate 10, an active layer 13 and a second doped semiconductor layer 14 formed above the first doped semiconductor layer 11, and a first electrode 15. The electrode unit M2 is electrically connected to the first doped semiconductor layer 11 in the micro-LED M1, enabling independent control of the micro-LED M1.

[0060] In this embodiment, the first doped semiconductor layer 11, the active layer 13, and the second doped semiconductor layer 14 constitute the PN junction structure of the micro-light-emitting diode. The first electrode 15 and electrode unit M2 of each micro-light-emitting diode M1 serve as the two ends of a set of electrodes. The first electrode 15 is electrically connected to the second doped semiconductor layer 14, and the electrode unit M2 is electrically connected to the first doped semiconductor layer 11, thereby forming a structure as shown in the embodiment. Figure 1 The micro-LED elements are shown in each element region. The electrode unit M2 and the micro-LED M1 are manufactured using the same process so that the electrode unit M2 and the micro-LED M1 have the same height. That is, the height of the upper surface of the first electrode 15 of the micro-LED M1 relative to the substrate 10 is equal to the height of the upper surface of the electrode unit M2 relative to the substrate 10, which is beneficial for subsequent connection with the driving circuit.

[0061] Figure 1 The diagram illustrates a scenario where only one electrode unit M2 is provided for each micro-LED element. Exemplarily, a scenario where multiple electrode units M2 are provided for each micro-LED element is also included. All electrode units M2 and the micro-LEDs M1 are manufactured using the same process and are positioned at the same height; details will not be elaborated here. Using multiple electrode units M2 in a group of electrodes for a micro-LED element facilitates the implementation of more driving functions in the CMOS pixel circuit.

[0062] In a micro-LED array, each micro-LED within a component region constitutes a light-emitting pixel. The area corresponding to micro-LED M1 is the actual light-emitting area of ​​each pixel. The electrode unit M2 can be set according to the gap position between pixels. The figure is for illustration only; the actual size and shape can be adjusted according to application requirements.

[0063] For each micro-LED element in the micro-LED array, each group of electrodes can be controlled independently. That is, the method of multiple micro-LEDs sharing a common electrode is no longer used. The first electrode 15 and electrode unit M2 of each micro-LED element can be controlled independently, which expands the application scenarios of micro-LED arrays and increases the voltage range of a single micro-LED element, which is beneficial to improving display brightness.

[0064] For example, the first doped semiconductor layer 11 can be an N-type semiconductor layer, such as N-type gallium nitride, and the corresponding second doped semiconductor layer 14 can be a P-type semiconductor layer, such as P-type gallium nitride. In this case, the electrode unit M2 is an N-electrode and the first electrode 15 is a P-electrode. Alternatively, the first doped semiconductor layer 11 can be a P-type semiconductor layer and the second doped semiconductor layer 14 can be an N-type semiconductor layer.

[0065] In the above embodiments, the first electrode 15 and electrode unit M2 of each micro-LED element in the array can be controlled independently. For example, when electrode unit M2 is an N-electrode and the first electrode 15 is a P-electrode, the N-electrode of each micro-LED element can be independently controlled by the CMOS driving circuit. Therefore, pixel circuits with N-type current mirrors can be used, and pixel circuits based on N-type MOS transistors or shared ELVDD can be used in CMOS driving circuit designs, thus expanding the application scenarios of the micro-LED array 100.

[0066] Furthermore, since the first electrode 15 and electrode unit M2 of each micro LED element can be controlled separately, the voltage of each micro LED element can be quickly turned off and reset. Moreover, by adjusting the voltage signals on the two electrodes, a larger dynamic voltage range can be achieved, which is beneficial to improving the display effect.

[0067] In some embodiments, such as Figure 2 As shown, Figure 2 This is a schematic diagram of another micro-light-emitting diode array structure provided in an embodiment of this application. The electrode unit M2 includes an auxiliary active layer 131, an auxiliary second doped semiconductor layer 141 and a second electrode 16 sequentially formed above the first doped semiconductor layer 11. Each element region also includes an auxiliary metal layer 18. The first end of the auxiliary metal layer 18 is electrically connected to the second electrode 16, and the second end of the auxiliary metal layer 18 is electrically connected to the first doped semiconductor layer 11.

[0068] In this embodiment, the electrode unit M2 has a stacked structure similar to that of the micro-light-emitting diode M1. Based on the stacked structure of the electrode unit M2, the auxiliary metal layer 18 realizes the electrical connection between the second electrode 16 and the first doped semiconductor layer 11. When a voltage is applied between the first electrode 15 and the second electrode 16 and the circuit is open, the resistance of the auxiliary metal layer 18 is smaller. The current between the second electrode 16 and the first doped semiconductor layer 11 is conducted through the auxiliary metal layer 18, without having to pass through the stacked structure composed of the "auxiliary second doped semiconductor layer 141, auxiliary active layer 131 and first doped semiconductor layer 11" under the second electrode 16. This stacked structure is used to ensure that the height of the second electrode 16 relative to the substrate 10 is equal to the height of the first electrode 15 relative to the substrate 10, which is beneficial for subsequent connection with the driving circuit.

[0069] In some of the above embodiments, based on the stacked structure of electrode unit M2, the second electrode 16 and the first electrode 15 are formed in the same process step. The second electrode 16 and the first electrode 15 have the same height and the same thickness, which is beneficial for subsequent connection with the driving circuit.

[0070] In some embodiments, such as Figure 2 As shown, in each micro-LED element of the micro-LED array 100, the micro-LED M1 further includes a conductive layer 17 located between the second doped semiconductor layer 14 and the first electrode 15. The electrode unit M2 further includes an auxiliary conductive layer 171 located between the auxiliary second doped semiconductor layer 141 and the second electrode 16. The first end of the auxiliary metal layer 18 partially covers the auxiliary conductive layer 171 and is electrically connected to the second electrode 16 through the auxiliary conductive layer 171. The conductive layer 17 and the auxiliary conductive layer 171 are formed in the same process step.

[0071] In some embodiments, both the conductive layer 17 and the auxiliary conductive layer 171 are indium tin oxide (ITO) layers. ITO has high visible light transmittance and low resistivity. After annealing, the conductive layer 17 can form an ohmic contact with the second doped semiconductor layer 14 to ensure the light transmittance and conductivity of the micro LED.

[0072] Meanwhile, the auxiliary conductive layer 171 is used to realize the electrical connection between the auxiliary metal layer 18 and the second electrode 16, thereby realizing the electrical connection between the second electrode 16 and the first doped semiconductor layer 11. This is beneficial to improve the connection reliability between the metal electrode and the semiconductor device. Furthermore, considering that the conductive layer 17 and the auxiliary conductive layer 171 are formed in the same process step, the conductive layer 17 and the auxiliary conductive layer 171 have the same height, which provides good conditions for realizing the equal height setting of the first electrode 15 and the second electrode 16.

[0073] In some embodiments, such as Figures 1-2 As shown, a spacer region 12 is provided between the first doped semiconductor layers 11 of adjacent element regions. The spacer region 12 is at least one of a trench region, an ion implantation region, and a passivation layer.

[0074] In this embodiment, the spacer region 12 separates the first doped semiconductor layers 11 of different element regions, thereby clearly defining the division of multiple element regions. Since the electrode unit M2 of each micro-LED is electrically connected to the first doped semiconductor layer 11, the spacer region 12 is used to achieve electrical isolation between the first doped semiconductor layers 11 of different element regions, thereby avoiding electrical connection between the electrode units M2 of different micro-LEDs. That is, the electrode units M2 in different element regions of the array are electrically isolated and no longer use a common electrode, thereby ensuring that the electrode units M2 (or the second electrode 16) of different micro-LEDs can be controlled independently.

[0075] For example, the spacer region 12 can be a trench region, which physically isolates the first doped semiconductor layer 11 of different micro-LEDs through electrical isolation. Alternatively, the spacer region 12 can also be an ion implantation region or a passivation layer, which achieves electrical isolation by blocking the conductivity inside the first doped semiconductor layer 11. The depth of the spacer region 12 depends on the conductivity at different depths inside the first doped semiconductor layer 11 and the process of forming the spacer region 12. Electrical isolation can be achieved within the required depth range as needed. Therefore, the depth of the spacer region 12 can be less than the thickness of the first doped semiconductor layer 11, or the depth of the spacer region 12 can be equal to the thickness of the first doped semiconductor layer 11, or the depth of the spacer region 12 can be greater than the thickness of the first doped semiconductor layer 11, for example, by trench etching into the substrate.

[0076] On the other hand, embodiments of this application also provide a method for fabricating a micro-light-emitting diode array, such as... Figure 3 As shown, Figure 3 This is a flowchart illustrating a method for fabricating a micro-light-emitting diode array, as provided in an embodiment of this application. Figures 4 to 14 A flowchart illustrating the fabrication steps of a micro-light-emitting diode array provided in this application embodiment.

[0077] The preparation method includes the following steps S10 to S20:

[0078] Step S10: As Figure 4 As shown, a substrate 10 is provided. The substrate 10 includes at least two element regions. The substrate 10 may be a sapphire substrate.

[0079] Step S20: As Figures 5 to 14 As shown, a micro light-emitting diode M1 and at least one electrode unit M2 are formed in each element region.

[0080] The step of forming a micro light-emitting diode M1 includes: sequentially forming a first doped semiconductor layer 11, an active layer 13, a second doped semiconductor layer 14, and a first electrode 15 on a substrate 10.

[0081] At least one electrode unit M2 is formed simultaneously in the step of forming the micro light-emitting diode M1. The electrode unit M2 is electrically connected to the first doped semiconductor layer 11 in the micro light-emitting diode M1, thereby realizing independent control of the micro light-emitting diode M1.

[0082] For example, in some embodiments, the electrode unit M2 includes an auxiliary active layer 131, an auxiliary second doped semiconductor layer 141, and a second electrode 16 sequentially formed above the first doped semiconductor layer 11.

[0083] The aforementioned "at least one electrode unit M2 is formed simultaneously in the step of forming the micro light-emitting diode M1" includes the following steps S21 to S24:

[0084] Step S21: As Figures 5-6 As shown, a first doped semiconductor layer 11, a basic active layer 130, and a basic second doped semiconductor layer 140 are sequentially formed on the substrate 10.

[0085] For example, the first doped semiconductor layer 11 is N-type gallium nitride. The basic active layer 130 is a multiple quantum well (MQW). The advantage of the MQW structure is that the emission wavelength can be tuned by adjusting the thickness and material composition of the quantum wells, thereby forming micro-light-emitting diodes of different colors. When the first doped semiconductor layer 11 is N-type gallium nitride, the basic second doped semiconductor layer 140 is P-type gallium nitride, thus forming a light-emitting diode structure.

[0086] In some embodiments, such as Figure 5 As shown, after forming the first doped semiconductor layer 11, a spacer region 12 is formed between the first doped semiconductor layers 11 in adjacent device regions. The spacer region 12 is used to divide different device regions. The formation of the spacer region 12 can include various forms, and the steps for forming the spacer region 12 are not limited to... Figure 5 The spacer region 12 is formed immediately after the formation of the first doped semiconductor layer 11. For example, in some embodiments, the spacer region 12 is at least one of a trench region, an ion implantation region, and a passivation layer, and its formation stage can be reasonably arranged in the relevant processes of subsequent processes (such as etching, deposition of passivation layers, etc.) to ultimately form the spacer region 12.

[0087] In some embodiments, after forming the basic second doped semiconductor layer 140, the following steps S211 to S212 are further included:

[0088] Step S211: As Figure 7 As shown, a basic conductive layer 170 is formed on the basic second doped semiconductor layer 140.

[0089] For example, the base conductive layer 170 is an indium tin oxide (ITO) semiconductor transparent conductive film. ITO has high visible light transmittance and low resistivity, which helps to improve the reliability of the connection between the metal electrode and the semiconductor device while ensuring the light transmittance and conductivity of the micro LED. After the base conductive layer 170 is formed, it is annealed to form an ohmic contact.

[0090] Step S212: As Figure 8 As shown, a portion of the base conductive layer 170 is removed to form a separate conductive layer 17 and an auxiliary conductive layer 171, the conductive layer 17 and the auxiliary conductive layer 171 having the same thickness.

[0091] Step S22: As Figure 8 As shown, a portion of the basic second doped semiconductor layer 140 is removed to form a separate second doped semiconductor layer 14 and an auxiliary second doped semiconductor layer 141, the second doped semiconductor layer 14 and the auxiliary second doped semiconductor layer 141 having equal thicknesses.

[0092] Step S23: As Figure 8 As shown, a portion of the base active layer 130 is removed to form a separate active layer 13 and an auxiliary active layer 131, exposing a portion of the first doped semiconductor layer 11. The active layer 13 and the auxiliary active layer 131 have equal thicknesses.

[0093] Steps S211 to S23 described above involve designing a mesa (MESA) pattern according to a patterned mask. For example, this is achieved by etching away a portion of the indium tin oxide (ITO) transparent conductive film of the base conductive layer 170, a portion of the p-type gallium nitride of the base second doped semiconductor layer 140, and a portion of the MQW (multiple quantum well) of the base active layer 130. This ensures that after etching, the n-type gallium nitride of the first doped semiconductor layer 11 is exposed, forming a relatively flat contact surface. Ultimately, a functionalized stepped structure, the MESA mesa, is formed. This MESA mesa corresponds to the first stacked structure 150 of the micro-LED M1 and the second stacked structure 160 of the electrode unit M2, respectively.

[0094] The first stacked electrode structure 150 includes an active layer 13, a second doped semiconductor layer 14, and a conductive layer 17. The second stacked structure 160 includes an auxiliary active layer 131, an auxiliary second doped semiconductor layer 141, and an auxiliary conductive layer 171.

[0095] The first stacked electrode structure 150 and the second stacked structure 160 formed by the above steps are symmetrical, and the fabrication process of each film layer structure is the same and the thickness is equal. Therefore, the first stacked electrode structure 150 and the second stacked structure 160 have the same height, which provides good conditions for the subsequent formation of the first electrode 15 and the second electrode 16 with the same height.

[0096] After that, as Figure 9 As shown, a mask 01 is formed. For example, the mask 01 is a photoresist, and a patterned mask 01 is formed by photolithography in a conventional semiconductor process. The mask 01 completely covers the MESA mesa of the first stacked electrode structure 150 and a portion of the MESA mesa of the second stacked structure 160, exposing the first doped semiconductor layer 11 in the region between the MESA mesa of the first stacked electrode structure 150 and the MESA mesa of the second stacked structure 160, and exposing a portion of the sidewall of the MESA mesa of the second stacked structure 160.

[0097] Step S24: As Figures 10-14 As shown, a first electrode 15 and a second electrode 16 are formed in the same process. The first electrode 15 is located on the conductive layer 17, and the second electrode 16 is located on the auxiliary conductive layer 171. The first electrode 15 and the second electrode 16 have the same thickness.

[0098] In some embodiments, the above preparation method further includes forming an auxiliary metal layer 18, wherein a first end of the auxiliary metal layer 18 is electrically connected to a second electrode 16, and a second end of the auxiliary metal layer 18 is electrically connected to a first doped semiconductor layer 11.

[0099] For example, in some embodiments, forming the auxiliary metal layer 18 includes forming an auxiliary metal layer 18 with a first end covering a portion of the auxiliary conductive layer 171. Forming the second electrode 16 includes forming a second electrode 16 that is electrically connected to the auxiliary metal layer 18 through the auxiliary conductive layer 171.

[0100] For example, such as Figure 10 As shown, using the mask 01, an auxiliary metal layer 18 is formed in the exposed portion of the mask 01. The first end of the auxiliary metal layer 18 covers a portion of the auxiliary conductive layer 171, and the second end extends above the first doped semiconductor layer 11 exposed by the mask 01 and is electrically connected to the first doped semiconductor layer 11.

[0101] During the formation of the auxiliary metal layer 18, the metal material of the auxiliary metal layer 18 is also deposited on the upper surface of the mask 01. When the mask 01 is stripped, the metal material of the auxiliary metal layer 18 deposited on the mask 01 is also removed, and this part is not shown in the figure.

[0102] Then as Figure 11As shown, after removing the mask 01, an annealing process is performed, causing the metal material of the auxiliary metal layer 18 located on the surface of the first doped semiconductor layer 11 to form an ohmic contact with it. In some embodiments, the material of the ohmic contact can be Ti / Al or Ti / Au, etc.

[0103] Next, as Figure 12 As shown, a passivation layer 02 is formed.

[0104] For example, the material of passivation layer 02 includes silicon nitride, or passivation layer 02 may also include silicon oxide or silicon oxynitride, etc. Passivation layer 02 covers substrate 10, first doped semiconductor layer 11, first stacked structure 150, second stacked structure 160 and auxiliary metal layer 18.

[0105] After that, as Figure 13 As shown, a patterned mask design is performed on the passivation layer 02 on the MESA mesa of the first stacked structure 150 and the passivation layer 02 on the MESA mesa of the second stacked structure 160. Part of the passivation layer 02 is etched away to expose the part of the conductive layer 17 away from the substrate 10, and the part of the auxiliary conductive layer 171 away from the substrate 10 is also exposed.

[0106] Finally, as Figure 14 As shown, similar to Figures 8-10 The process shown involves forming a photoresist mask on the passivation layer 02, followed by the formation of a first electrode 15 and a second electrode 16 in the same process. For example, a metal material is deposited, followed by the removal of the photoresist and the simultaneous removal of the metal material deposited on the photoresist, thereby forming the first electrode 15 located on the conductive layer 17 and the second electrode 16 located on the auxiliary conductive layer 171. The second electrode 16 is electrically connected to the first end of the auxiliary metal layer 18 through the auxiliary conductive layer 171, thereby achieving an electrical connection between the second electrode 16 and the first doped semiconductor layer 11.

[0107] For example, the metal material of the first electrode 15 and the metal material of the second electrode 16 are both gold.

[0108] Thus, micro-light-emitting diode M1 and electrode unit M2 were formed in the same process.

[0109] In some embodiments, the process of forming the first stacked structure 150 and the second stacked structure 160 mentioned above can also be carried out in a similar manner to forming the first electrode 15 and the second electrode 16. For example, after forming the basic second doped semiconductor layer 140 in step S21, the operations of steps S211 to S212 are not performed. Instead, after forming the separate second doped semiconductor layer 14 and the auxiliary second doped semiconductor layer 141, a conductive layer 17 and an auxiliary conductive layer 171 are formed in the same photolithography process. The conductive layer 17 and the auxiliary conductive layer 171 have the same thickness, wherein the conductive layer 17 is located above the second doped semiconductor layer 14, and the auxiliary conductive layer 171 is located above the auxiliary second doped semiconductor layer 141.

[0110] The steps described above for forming the first stacked structure 150 and the second stacked structure 160, as well as the steps for forming the first electrode 15 and the second electrode 16, ensure that the first electrode 15 and the second electrode 16 have the same height. The first electrode 15 and the second electrode 16 are used for electrical connection with the driving circuit, thereby enabling the micro-light-emitting diode element to emit light. Furthermore, the equal height of the first electrode 15 and the second electrode 16 facilitates subsequent electrical connection with the CMOS driving circuit.

[0111] On the micro-light-emitting diode array 100 prepared by the above steps, as shown Figures 15-17 As shown, Figure 15 This is a schematic diagram of a planar distribution of light-emitting pixels in a micro-LED array, provided in an embodiment of this application. Figure 16 This is a schematic diagram of a micro-light-emitting diode array provided in an embodiment of this application. Figure 17 This is a schematic diagram of another micro-light-emitting diode array provided in the embodiments of this application.

[0112] Within each micro-LED element region, the MESA mesa region corresponding to the first stacked structure 150 (or, in other words, the micro-LED M1) is the actual light-emitting pixel, and its arrangement on the substrate 10 is as follows: Figure 15 As shown. When designing the MESA mesa pattern according to the graphical mask, the MESA mesa region (or electrode unit M2) corresponding to the second stacked structure 160 can be set according to the gap position between pixels. For example... Figure 16 The diagram shows a case where a second stack structure 160 (i.e., an electrode unit M2) is set for each component region. Figure 17 The diagram shows a case where multiple second stacked structures 160 (i.e., multiple electrode units M2) are set for each element region.

[0113] In some embodiments, such as Figures 16-17As shown, during the fabrication process, spacer regions 12 are formed between the first doped semiconductor layers 11 of adjacent device regions. The spacer regions 12 are at least one of trench regions, ion implantation regions, and passivation layers. There are various steps for forming the spacer regions 12, and the types of spacer regions 12 formed at different process stages are also different.

[0114] like Figures 18-22 As shown, Figures 18-22 This is a flowchart illustrating the steps of a method for preparing a spacer region according to an embodiment of this application.

[0115] Exemplary, in some embodiments, such as Figure 18 As shown, after the first electrode 15 and the second electrode 16 are formed in step S25, that is... Figure 14 After the steps shown, interval 12 is formed.

[0116] For example, the passivation layer 02 and the first doped semiconductor layer 11 are patterned. Part of the passivation layer 02 and part of the first doped semiconductor layer 11 are removed by etching to form a trench region, exposing the substrate 10. This forms a spacer region 12, i.e., the spacer region 12 is a trench region. By etching to form the trench region, the continuity of the first doped semiconductor layer 11 is broken, and the first doped semiconductor layers 11 in different element regions are not connected, achieving electrical isolation through physical isolation. That is, the current injected by the second electrode 16 can only flow out through the first electrode 15 in the same element region and cannot flow into the first doped semiconductor layer 11 in adjacent element regions. At this time, the depth of the spacer region 12 can be equal to the thickness of the first doped semiconductor layer 11, or the trench region can extend into the substrate 10, making the depth of the spacer region 12 greater than the thickness of the first doped semiconductor layer 11.

[0117] Alternatively, by way of example, in some embodiments, such as Figures 19-20 As shown, after the formation of the auxiliary metal layer 18 and before the formation of the first electrode 15 and the second electrode 16, a spacer region 12 is formed. More specifically, in... Figure 11 After the auxiliary metal layer 18 is formed as shown, Figure 12 Before the passivation layer 02 is formed, the spacer region 12 is formed.

[0118] For example, in such Figure 11 After the auxiliary metal layer 18 is formed as shown, as Figure 19 As shown, the first doped semiconductor layer 11 is patterned, and a portion of the first doped semiconductor layer 11 is removed by etching to form a trench V1. Then, as... Figure 20 As shown, while forming the passivation layer 02, the passivation layer 02 is also deposited in the trench V1, ultimately forming the spacer region 12. That is, the spacer region 12 is a passivation layer.

[0119] Alternatively, by way of example, in some embodiments, such as Figure 21 or Figure 22 As shown, a spacer region 12 is formed before the auxiliary metal layer 18 is formed.

[0120] For example, such as Figure 21 As shown, while designing the MESA pattern using a patterned mask, a portion of the first doped semiconductor layer 11 is removed by etching to form trench V2. Then, according to... Figures 9-14 The steps shown are followed by subsequent process flows, in which... Figure 12 During the formation of passivation layer 02, passivation layer 02 is deposited in trench V2, that is, the spacer region 12 includes passivation layer.

[0121] Or, such as Figure 22 As shown, after forming a first doped semiconductor layer 11 on the substrate 10, ion implantation is performed on the first doped semiconductor layer 11 to make the ion implantation region a high-resistivity state, that is, the spacer region 12 is the ion implantation region, thereby achieving electrical isolation between the first doped semiconductor layers.

[0122] In the above methods for forming the spacer region 12, in addition to etching, physical isolation of the first doped semiconductor layer 11 in different component regions can also be achieved through physical cutting, laser ablation, and other techniques, thereby achieving electrical isolation. Besides ion implantation, high-resistivity regions can also be formed through local oxidation and other techniques, thereby achieving electrical isolation of the first doped semiconductor layer 11 in different component regions.

[0123] In the above techniques, the depth of the spacer region 12 can be less than the thickness of the first doped semiconductor layer 11, as long as the electrical isolation performance of the spacer region 12 is guaranteed. For example, taking the etching process as an example, during the etching of the first doped semiconductor layer 11 in the spacer region 12, the first doped semiconductor layer 11 in that region does not need to be completely removed, that is, the substrate 10 does not need to be exposed. In practical applications, the depth of the spacer region 12 depends on the conductivity of different depths determined by the epitaxial design inside the first doped semiconductor layer 11. The first doped semiconductor layer 11 can be processed within the required depth range to achieve electrical isolation.

[0124] Furthermore, this application also provides a display device, such as... Figure 23 As shown, Figure 23 This is a schematic diagram of a display device provided in an embodiment of this application.

[0125] The display device 200 includes the micro-light-emitting diode array 100 mentioned in any embodiment of the first aspect above, and a microlens 201. Since the area corresponding to the micro-light-emitting diode M1, that is, the MESA area of ​​the first stacked structure 150 in the above-described fabrication method, is the actual light-emitting area of ​​each light-emitting pixel, the microlens 201 at least covers the area corresponding to the micro-light-emitting diode M1, that is, the area corresponding to the electrode unit M2 does not need to be separately equipped with a microlens 201. If the size of the microlens 201 is large enough, it is also possible to cover the area of ​​the electrode unit M2.

[0126] The microlens 201 is used to adjust the direction of focused light emission, enabling the display device 200 to display relevant images. Since the micro-light-emitting diodes (LEDs) in each element region of the aforementioned micro-LED array 100 can be independently controlled, the application scenarios of the micro-LED array are expanded, and the voltage range of individual micro-LED elements is broadened, increasing the selectable range of driving circuits in the display device 200 and improving the display brightness. Furthermore, the electrode units in the micro-LED array 100 are manufactured using the same process as the micro-LEDs, resulting in the same height for both. This simplifies the connection between the micro-LED array 100 and the driving circuit, thus simplifying the fabrication process of the display device 200.

[0127] Furthermore, this application also provides an electronic device, such as Figure 24 As shown, Figure 24 This is a schematic diagram of an electronic device provided in an embodiment of this application.

[0128] The electronic device 300 includes the aforementioned display device 200. The electronic device 300 includes, but is not limited to, AR near-eye display devices. The electronic device 300 has the same technical effects as the aforementioned display device 200, which will not be described in detail here.

[0129] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A micro light emitting diode array, comprising: include: A substrate, wherein the substrate includes at least two element regions; A micro light-emitting diode and at least one electrode unit are formed in each component region; The electrode unit and the micro light-emitting diode are manufactured using the same process; The micro light-emitting diode includes a first doped semiconductor layer, an active layer, a second doped semiconductor layer, and a first electrode; The electrode unit is electrically connected to the first doped semiconductor layer in the micro light-emitting diode, thereby enabling independent control of the micro light-emitting diode.

2. The micro-LED array of claim 1, wherein, The electrode unit includes an auxiliary active layer, an auxiliary second doped semiconductor layer, and a second electrode, which are sequentially formed above the first doped semiconductor layer. Each element region also includes an auxiliary metal layer, a first end of which is electrically connected to the second electrode, and a second end of which is electrically connected to the first doped semiconductor layer.

3. The micro-LED array of claim 2, wherein, The second electrode is formed in the same process step as the first electrode, and the second electrode has the same height and the same thickness as the first electrode.

4. The micro-LED array of claim 3, wherein, The micro light-emitting diode further includes a conductive layer, which is located between the second doped semiconductor layer and the first electrode; The electrode unit further includes an auxiliary conductive layer, which is located between the auxiliary second doped semiconductor layer and the second electrode. The first end of the auxiliary metal layer covers a portion of the auxiliary conductive layer and is electrically connected to the second electrode through the auxiliary conductive layer. The conductive layer and the auxiliary conductive layer are formed in the same process step. 5.The micro-LED array of claim 4, wherein, Both the conductive layer and the auxiliary conductive layer are indium tin oxide layers.

6. The micro-LED array of claim 1, wherein, A spacer region is provided between the first doped semiconductor layers of adjacent element regions, the spacer region being at least one of a trench region, an ion implantation region, and a passivation layer.

7. A method for fabricating a micro-light-emitting diode array, characterized in that, include: A substrate is provided, the substrate including at least two element regions; A microlight-emitting diode and at least one electrode unit are formed in each component region, wherein the step of forming a microlight-emitting diode includes: A first doped semiconductor layer, an active layer, a second doped semiconductor layer, and a first electrode are sequentially formed on the substrate; The at least one electrode unit is formed simultaneously in the step of forming a micro light-emitting diode, and the electrode unit is electrically connected to the first doped semiconductor layer in the micro light-emitting diode to realize independent control of the micro light-emitting diode.

8. The preparation method according to claim 7, characterized in that, The electrode unit includes an auxiliary active layer, an auxiliary second doped semiconductor layer, and a second electrode, which are sequentially formed above the first doped semiconductor layer. The at least one electrode unit is formed simultaneously in the step of forming a micro light-emitting diode, including: A first doped semiconductor layer, a basic active layer, and a basic second doped semiconductor layer are sequentially formed on the substrate. A portion of the basic second doped semiconductor layer is removed to form a separate second doped semiconductor layer and an auxiliary second doped semiconductor layer, the second doped semiconductor layer and the auxiliary second doped semiconductor layer having equal thickness; A portion of the base active layer is removed to form a separate active layer and an auxiliary active layer, exposing a portion of the first doped semiconductor layer. The first electrode and the second electrode are formed in the same process. The first electrode is located on the second doped semiconductor layer, and the second electrode is located on the auxiliary second doped semiconductor layer. The first electrode and the second electrode have the same thickness.

9. The preparation method according to claim 8, characterized in that, Also includes: An auxiliary metal layer is formed, wherein a first end of the auxiliary metal layer is electrically connected to the second electrode, and a second end of the auxiliary metal layer is electrically connected to the first doped semiconductor layer.

10. The preparation method according to claim 9, characterized in that, Before removing part of the basic second doped semiconductor layer, the simultaneous formation of the at least one electrode unit in the step of forming a micro light-emitting diode further includes: A basic conductive layer is formed on the basic second doped semiconductor layer; A portion of the base conductive layer is removed to form a separate conductive layer and an auxiliary conductive layer, the conductive layer and the auxiliary conductive layer having the same thickness, wherein the conductive layer is located above the second doped semiconductor, and the auxiliary conductive layer is located above the auxiliary second doped semiconductor layer; the first electrode is located above the conductive layer, and the second electrode is located above the auxiliary conductive layer.

11. The preparation method according to claim 9, characterized in that, After forming the separated second doped semiconductor layer and the auxiliary second doped semiconductor layer, a conductive layer and an auxiliary conductive layer are formed using the same photolithography process. The conductive layer and the auxiliary conductive layer have the same thickness. The conductive layer is located above the second doped semiconductor layer, and the auxiliary conductive layer is located above the auxiliary second doped semiconductor layer. The first electrode is located above the conductive layer, and the second electrode is located above the auxiliary conductive layer.

12. The preparation method according to claim 10 or 11, characterized in that, Forming the auxiliary metal layer includes: a first end of the formed auxiliary metal layer covering a portion of the auxiliary conductive layer; Forming the second electrode includes: the second electrode being electrically connected to the auxiliary metal layer through the auxiliary conductive layer.

13. The preparation method according to claim 12, characterized in that, A spacer region is formed between first doped semiconductor layers of adjacent element regions, the spacer region being at least one of a trench region, an ion implantation region, and a passivation layer.

14. The preparation method according to claim 13, characterized in that, After the first electrode and the second electrode are formed, the spacer region is formed; Alternatively, the spacer region may be formed after the auxiliary metal layer is formed and before the first electrode and the second electrode are formed. Alternatively, the spacer region may be formed before the auxiliary metal layer is formed.

15. A display device, characterized in that, The invention includes a micro-light-emitting diode array according to any one of claims 1 to 6, and a microlens, wherein the microlens at least covers the micro-light-emitting diodes.

16. An electronic device, characterized in that, Includes the display device as described in claim 15.

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