Display substrate, manufacturing method thereof and display device

Abstract

The invention provides a display substrate, a manufacturing method thereof and a display device. The display substrate comprises a substrate; an anode layer including a plurality of anodes; a plurality of pixel openings corresponding to the plurality of pixels are defined on the pixel definition layer; the isolation columns are located on the side, away from the substrate, of the pixel definition layer and located between the adjacent pixel openings; the light-emitting layers and the cathode layers are sequentially stacked on the sides, away from the substrate, of the pixel defining layers and the isolation columns in the direction away from the substrate, the light-emitting layers and the cathode layers are separated by the isolation columns, and the cathode layers of the adjacent pixels are in contact connection with the isolation columns; a pit is formed in the side face, away from the substrate, of the pixel defining layer around the pixel opening, the light-emitting layer covers the side, away from the substrate, of the pixel defining layer in a shape follow-up mode, a thinning area is formed in the position corresponding to the pit, and the film layer thickness of the thinning area is smaller than that of other areas in the light-emitting layer. According to the display substrate, the manufacturing method thereof and the display device, the crosstalk phenomenon can be improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display substrate, its manufacturing method, and a display device. Background Technology

[0002] Self-emissive display panels are a type of display technology that can emit light on their own without a backlight. Common self-emissive display panels include OLED (Organic Light-Emitting Diode) and QLED (Quantum Dot Light-Emitting Diodes).

[0003] Self-emissive display panels include light-emitting elements, which consist of a stacked anode, a light-emitting layer, and a cathode. In related technologies, pixel encapsulation technology is used to achieve better display effects, with isolation pillars placed between adjacent sub-pixels. These isolation pillars contain auxiliary cathodes, which can overlap. However, self-emissive display panels using this pixel encapsulation technology suffer from crosstalk. Summary of the Invention

[0004] This disclosure provides a display substrate and its manufacturing method, as well as a display device, which can improve crosstalk phenomena.

[0005] The technical solutions provided in this disclosure are as follows:

[0006] In a first aspect, embodiments of this disclosure provide a display substrate, comprising:

[0007] Substrate, comprising multiple pixels;

[0008] The anode layer includes multiple anodes set for multiple pixels;

[0009] A pixel definition layer is located on the side of the anode layer opposite to the substrate, and the pixel definition layer defines a plurality of pixel openings corresponding to a plurality of pixels;

[0010] An isolation pillar is located on the side of the pixel definition layer away from the substrate and between adjacent pixel openings; and

[0011] A light-emitting layer and a cathode layer are sequentially stacked on the pixel definition layer and the side of the isolation pillar away from the substrate, along a direction away from the substrate, and the light-emitting layer and the cathode layer are separated by the isolation pillar. The cathode layer in adjacent pixels is in contact with the isolation pillar.

[0012] The pixel definition layer has a recess around the pixel opening on one side away from the substrate. The light-emitting layer covers the side of the pixel definition layer away from the substrate and forms a thinning region at the position corresponding to the recess. The film thickness of the thinning region is less than the film thickness of other areas of the light-emitting layer except for the thinning region.

[0013] For example, the pixel definition layer includes:

[0014] A first region covering the area between adjacent anodes; and

[0015] A second region covering the side of the anode away from the substrate; wherein,

[0016] The recess is located at the boundary between the first region and the second region, and in the direction from the isolation post to the pixel opening, the recess is located between the isolation post and the pixel opening.

[0017] For example, the pixel definition layer includes at least a first sub-pixel definition layer and a second sub-pixel definition layer; wherein,

[0018] The first subpixel defining layer is located in the first region, and there is a gap between the pattern of the first subpixel defining layer and the anode adjacent to the first subpixel defining layer; the second subpixel defining layer conformally covers the side of the first subpixel defining layer away from the substrate, and is at least partially located in the first region and at least partially located in the second region, and forms the pit at the location covering the gap.

[0019] For example, the pixel definition layer further includes at least a third sub-pixel definition layer, which is stacked on the side of the first sub-pixel definition layer near the substrate, and the third sub-pixel definition layer is at least partially located in the first region and at least partially located in the second region.

[0020] For example, the size of the gap is 0.6 to 0.8 micrometers in the direction from the isolation post to the pixel opening.

[0021] For example, the film thickness of the first sub-pixel defining layer is less than or equal to The thickness of the second sub-pixel definition layer is 1.5 μm ± 10%; the thickness of the third sub-pixel definition layer is 1.5 μm ± 10%.

[0022] For example, the anode has a first sidewall, the first sub-pixel definition layer has a second sidewall, the first sidewall and the second sidewall cooperate to form the gap, the slope angle of the first sidewall is 50 to 70°, and the slope angle of the second sidewall is 50 to 70°.

[0023] For example, the material of the first sub-pixel definition layer includes a gate metal material, the material of the second sub-pixel definition layer includes an inorganic insulating material, and the material of the third sub-pixel definition layer includes an inorganic insulating material.

[0024] For example, the light-emitting layer has a film connection portion and a film disconnect portion sequentially disposed in the thinning region along the direction away from the substrate. The film thickness of the film connection portion is a first thickness h1, and the film thickness of the other regions of the light-emitting layer excluding the thinning region is a second thickness h2, where h1 / h2 = 0.05 to 0.1.

[0025] Secondly, this disclosure also provides a method for manufacturing a display substrate, the method comprising the following steps:

[0026] Provide a substrate;

[0027] An anode layer is formed on the substrate, wherein the anode layer includes a pattern of multiple anodes disposed corresponding to multiple pixels;

[0028] A pixel definition layer is formed on the side of the anode layer away from the substrate, wherein a plurality of pixel openings corresponding to a plurality of pixels are defined on the pixel definition layer, and a recess is provided around the pixel openings on the side of the pixel definition layer away from the substrate;

[0029] An isolation pillar is formed on the side of the pixel definition layer opposite to the substrate, wherein the isolation pillar is located between adjacent pixel openings;

[0030] A light-emitting layer and a cathode layer are sequentially formed on the side of the pixel definition layer and the isolation pillar away from the substrate. The light-emitting layer and the cathode layer are separated by the isolation pillar. The cathode layer in an adjacent pixel is in contact with the isolation pillar. The light-emitting layer covers the side of the pixel definition layer away from the substrate and forms a thinning region at the position corresponding to the pit. The film thickness of the thinning region is less than the film thickness of other regions of the light-emitting layer except for the thinning region.

[0031] For example, forming a pixel definition layer on the side of the anode layer opposite to the substrate specifically includes:

[0032] A first subpixel definition layer is formed, the first subpixel definition layer is located in a first region between adjacent anodes, and the pattern of the first subpixel definition layer has a gap between it and the anodes adjacent to the first subpixel definition layer;

[0033] A second subpixel definition layer is formed on the side of the first subpixel definition layer away from the substrate, wherein the second subpixel definition layer conformally covers the side of the first subpixel definition layer away from the substrate, and the second subpixel definition layer is at least partially located in the first region, at least partially located in the second region of the anode on the side away from the substrate, and the pit is formed at the location covering the gap.

[0034] For example, forming a pixel definition layer on the side of the anode layer opposite to the substrate further includes:

[0035] Before forming the first subpixel definition layer, a third subpixel definition layer is formed, wherein the third subpixel definition layer is stacked on the side of the first subpixel definition layer near the substrate, and the third subpixel definition layer is at least partially located in the first region and at least partially located in the second region.

[0036] Thirdly, embodiments of this disclosure also provide a display device, which includes the display substrate described above.

[0037] The beneficial effects of the embodiments disclosed herein are as follows:

[0038] The display substrate and its manufacturing method and display device provided in this disclosure include a substrate, an anode layer, a pixel definition layer, isolation pillars, a light-emitting layer and a cathode layer. The anode layer, the light-emitting layer and the cathode layer cooperate to form a light-emitting element, which is disposed corresponding to a pixel opening on the pixel definition layer. The light-emitting layer and the cathode layer are separated by the isolation pillars, and the cathode layers in adjacent pixels are in contact with the isolation pillars. A pit is formed on the side of the pixel definition layer away from the substrate, surrounding the pixel opening. When the light-emitting layer covers the pixel definition layer in a conformal manner, a thinning region is formed at the position corresponding to the pit. Since the pit is disposed around the pixel opening, in other words, the thinning region is disposed around the pixel opening, and the film thickness of the thinning region is less than the film thickness of other regions in the light-emitting layer. In this way, by setting a pit on the pixel definition layer, a thinning region is formed on the light-emitting layer. Even if the light-emitting layer and the isolation pillar are in contact, the resistance of the light-emitting layer in the thinning region increases due to the presence of the thinning region, which can improve the crosstalk phenomenon caused by the contact between the light-emitting layer and the isolation pillar. Attached Figure Description

[0039] Figure 1 This diagram illustrates a cross-sectional structure of a display substrate provided in some embodiments of this disclosure.

[0040] Figure 2This is a schematic diagram illustrating one of the steps of a method for manufacturing a display substrate provided in some embodiments of this disclosure;

[0041] Figure 3 This is a second schematic diagram illustrating the steps of a method for manufacturing a display substrate provided in some embodiments of this disclosure;

[0042] Figure 4 This is the third schematic diagram illustrating the steps of a method for manufacturing a display substrate provided in some embodiments of this disclosure;

[0043] Figure 5 Fourth schematic diagram illustrating the steps of a method for manufacturing a display substrate provided in some embodiments of this disclosure;

[0044] Figure 6 Fifth schematic diagram illustrating the steps of a method for manufacturing a display substrate provided in some embodiments of this disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0047] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this disclosure include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain tolerances. Taking into account the measurement and the tolerances associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of said value.

[0048] Furthermore, throughout this document, unless otherwise defined, the terms “substantially,” “essentially,” “approximately,” and “about” are used to describe and explain small variations. When used with an event or situation, these terms can cover situations where the event or situation occurs precisely or approximately. For example, when used with a numerical value, these terms can include a range of variation of the numerical value less than or equal to 10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces arranged along the same plane within a micrometer range, for example, within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm.

[0049] It should be understood that, in the exemplary embodiments of this disclosure, when a layer or element is referred to as being on another layer or substrate, it may mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate. "A and B are set in the same layer" means that after A and B are formed using the same film deposition process to form a film layer for forming a specific pattern, the layer structure is formed in one patterning process using the same photomask.

[0050] Before providing a detailed description of the display substrate and its manufacturing method, as well as the display device, provided in the embodiments of this disclosure, the following explanations are given regarding related technologies:

[0051] In related technologies, self-emissive display panels have been increasingly widely used in various display devices such as mobile phones, tablets, computers, televisions, AR (augmented reality) and VR (virtual reality) due to their self-emissive characteristics.

[0052] Self-emissive display panels are a type of display technology that emits light independently without a backlight. Common self-emissive display panels include OLED (Organic Light-Emitting Diode) and QLED (Quantum Dot Light-Emitting Diodes) panels. A self-emissive display panel contains light-emitting elements, which may include stacked anodes, light-emitting layers, and cathodes. The higher the resolution of the display panel, the higher the precision required of the mask, especially for large-size OLEDs. To achieve high resolution, WOLED (White OLED) display technology is generally used. This technology uses organic materials to emit light, generating white light, and then uses color filters or other technologies to generate the desired colors. However, WOLED display technology has certain drawbacks, such as low brightness and high power consumption due to the brightness limitations imposed by the color filters.

[0053] In related technologies, to address the problems of WOLED display technology and meet high-resolution requirements, some display panels employ pixel encapsulation technology, where red, green, and blue light-emitting diodes are individually encapsulated within their respective pixels. Isolation pillars are added between adjacent pixels to separate the light-emitting layer, cathode, and encapsulation layer of two adjacent pixels. These isolation pillars contain auxiliary cathodes, and the cathodes of adjacent pixels are connected to each other via overlap with the auxiliary cathodes.

[0054] However, self-emissive display panels using the aforementioned pixel encapsulation technology suffer from crosstalk.

[0055] The inventors of this application have discovered that one of the causes of crosstalk is that, during the fabrication of the display panel using the aforementioned pixel encapsulation technology, the isolation pillars are generally constructed with an undercut structure, meaning they have a protrusion at the top facing the pixel opening. This places high demands on the vapor deposition control of the light-emitting layer material. The only way to adjust and control the disconnection between the light-emitting layer material and the auxiliary cathode in the isolation pillar is by adjusting the angle of the vapor deposition plate, ensuring contact between the cathode layer and the auxiliary cathode, and between the light-emitting layer material and the auxiliary cathode in the isolation pillar. This easily leads to crosstalk. Crosstalk caused by the light-emitting layer material refers to the phenomenon where the monochromatic emission of the light-emitting layer material causes other colors to illuminate.

[0056] To improve the above-mentioned problems, the present disclosure provides a display substrate and a method for manufacturing the same, as well as a display device, which can improve crosstalk.

[0057] like Figure 1 As shown, the display substrate provided in this embodiment includes:

[0058] Substrate 100 includes multiple pixels P;

[0059] The anode layer 200 includes multiple anodes 210 set for multiple pixels P;

[0060] A pixel definition layer 300 is located on the side of the anode layer 200 facing away from the substrate 100, and a plurality of pixel openings 310 are defined on the pixel definition layer 300 corresponding to a plurality of pixels P.

[0061] The isolation pillar 400 is located on the side of the pixel definition layer 300 away from the substrate 100, and is located between adjacent pixel openings 310; and

[0062] The light-emitting layer 500 and the cathode layer 600 are stacked sequentially on the side of the pixel definition layer 300 and the isolation pillar 400 away from the substrate 100, along the direction away from the substrate 100. The light-emitting layer 500 and the cathode layer 600 are separated by the isolation pillar 400. The cathode layer 600 in an adjacent pixel P is in contact with the isolation pillar 400. The pixel definition layer 300 has a recess 320 around the pixel opening 310 on the side away from the substrate 100. The light-emitting layer 500 covers the side of the pixel definition layer 300 away from the substrate 100 and forms a thinning region 510 at the position corresponding to the recess 320. The film thickness of the thinning region 510 is less than the film thickness of other areas of the light-emitting layer 500 except for the thinning region 510.

[0063] In the above scheme, by forming a recess 320 around the pixel opening 310 on the side of the pixel definition layer 300 facing away from the substrate 100, when the light-emitting layer 500 covers the pixel definition layer 300 in a conformal manner, a thinning region 510 is formed at the position corresponding to the recess 320. Since the recess 320 is arranged around the pixel opening 310, in other words, the thinning region 510 is arranged around the pixel opening 310, and the film thickness of the thinning region 510 is less than the film thickness of other areas in the light-emitting layer 500. Thus, by providing a recess 320 on the pixel definition layer 300, when the light-emitting layer 500 conformally covers the pixel definition layer 300, under stress, the film layer partially breaks at the corresponding position of the recess 320, forming a thinning region 510. Even if the light-emitting layer 500 and the isolation pillar 400 are in contact, the film thickness in the thinning region 510 is reduced compared to other areas due to the presence of the thinning region 510. The resistance in the thinning region 510 increases. Therefore, the thinning region 510 can block electron transmission or increase the difficulty of electron transmission between the light-emitting layer 500 and the auxiliary electrode in the isolation pillar 400, thereby improving the crosstalk phenomenon that occurs when the light-emitting layer 500 contacts the isolation pillar 400.

[0064] In some exemplary embodiments, the substrate 100 is provided with a pixel driving circuit layer (not shown in the figure) and a planarization layer 800. The pixel driving circuit layer is fabricated on the substrate 100 and can form a driving backplane. The planarization layer 800 is located on the side of the pixel driving circuit board away from the substrate 100, and the anode layer 200 is located on the side of the planarization layer away from the substrate 100.

[0065] In some exemplary embodiments, please refer to Figure 1 As shown, the isolation pillar 400 includes an auxiliary cathode 410 and an insulating pattern 420 stacked sequentially in a direction away from the substrate 100. The insulating pattern 420 protrudes relative to the auxiliary cathode 410 toward the pixel opening 310, forming an undercut structure. In other words, the portion of the insulating pattern 420 protruding relative to the auxiliary cathode 410 is the protrusion a. The display substrate also includes an encapsulation layer 700, which is located on the side of the cathode layer 600 away from the substrate 100. The light-emitting layer 500, the cathode layer 600, and the encapsulation layer 700 adjacent to the pixel P are separated by the isolation pillar 400.

[0066] It should be noted that when the light-emitting layer 500 conformally covers the pixel definition layer 300 by setting the recess 320, the light-emitting layer 500 fills the recess 320, and at least a portion of the film layer is broken in the film thickness direction, forming a thinning region 510. As shown in the figure, the light-emitting layer 500 has a film layer connection portion 511 and a film layer break portion 512 sequentially arranged in the thinning region 510 along the direction away from the substrate 100. The film layer thickness of the film layer connection portion 511 is a first thickness h1, and the film layer thickness of the other areas of the light-emitting layer 500 other than the thinning region 510 is a second thickness h2, where h1 / h2 = 0.05~0.1. In this way, the thinning region 510 can be guaranteed to block the light-emitting layer 500 and the isolation pillar 400, and the light-emitting layer 500 can also fill the pit 320, so as to ensure that the cathode layer 600 remains continuous in the pit 320.

[0067] It should be noted that if the size of the pit 320 is too large, the light-emitting layer 500 will continuously cover the pit 320, making it impossible to form the thinning region 510. Conversely, if the size of the pit 320 is too small, it may not be possible to achieve the purpose of partially breaking the film layer of the light-emitting layer 500 at the pit 320. Through inventive research, the inventors of this application have discovered that the morphology of the pit 320 is approximately V-shaped, and its depth in the direction perpendicular to the substrate 100 can be approximately... The maximum opening width of the recess 320 can be approximately [left and right]. The light-emitting layer 500 can be thinned while ensuring the continuity of the cathode layer 600. However, this is not a limitation.

[0068] Furthermore, as an exemplary embodiment, such as Figure 1 As shown, the pixel definition layer 300 includes a first region S1 and a second region S2. The first region S1 covers the area between adjacent anodes 210, and the second region S2 covers the side of the anode 210 away from the substrate 100. The pit 320 is located at the boundary between the first region S1 and the second region S2. In the direction from the isolation pillar 400 to the pixel opening 310, the pit 320 is located between the isolation pillar 400 and the pixel opening 310.

[0069] In the above scheme, the recess 320 can be set at the boundary position between the first region S1 and the second region S2. In other words, the recess 320 is set at the edge position of the anode 210. In this way, the light-emitting area of ​​the light-emitting layer 500 in the pixel opening 310 area can be maximized, and the recess 320 can also be formed by directly utilizing the step difference formed by the edge of the anode 210. It is understood that in other embodiments, the recess 320 can also be set at other positions. For example, the recess 320 can be set in the first region S1, and a certain distance can be maintained between it and the isolation pillar 400.

[0070] As an exemplary embodiment, such as Figure 1 As shown, the pixel definition layer 300 includes at least a first sub-pixel definition layer 301 and a second sub-pixel definition layer 302; wherein, the first sub-pixel definition layer 301 is located in the first region S1, and there is a gap between the pattern of the first sub-pixel definition layer 301 and the anode 210 adjacent to the first sub-pixel definition layer 301; the second sub-pixel definition layer 302 conformally covers the side of the first sub-pixel definition layer 301 away from the substrate 100, and is at least partially located in the first region S1 and at least partially located in the second region S2, and forms the pit 320 at the location covering the gap.

[0071] By adopting the above scheme, the pit 320 is formed by setting the pixel definition layer 300 as a multi-layer stacked structure. The first sub-pixel definition layer 301 and the anode 210 maintain a gap, so that when the second sub-pixel definition layer 302 covers the gap A, the pit 320 is formed. This setting is simple in structure and convenient in process implementation.

[0072] It should be understood that in other embodiments, the recess 320 can also be formed in other ways, such as by patterning the pixel definition layer 300. In this case, by setting the pixel definition layer 300 as a multi-layer stacked structure to form the recess 320, the accuracy of the recess 320's size can be controlled based on parameters such as the size of the gap A and the film thickness forming the gap A (e.g., the film thickness of the first sub-pixel definition layer 301 and the anode 210). Compared to directly forming the recess 320 using patterning or other methods, the accuracy of the recess 320 is easier to control and achieve.

[0073] Furthermore, as an exemplary embodiment, such as Figure 1As shown, the pixel definition layer 300 further includes at least a third sub-pixel definition layer 303, which is stacked on the side of the first sub-pixel definition layer 301 near the substrate 100, and the third sub-pixel definition layer 303 is at least partially located in the first region S1 and at least partially located in the second region S2.

[0074] By adopting the above scheme, a third sub-pixel definition layer 303 is set, extending from the first region S1 towards the anode 210 and covering the anode 210. The pixel definition layer 300 is formed by the cooperation of the third sub-pixel definition layer 303, the first sub-pixel definition layer 301, and the second sub-pixel definition layer 302. Since the third sub-pixel definition layer 303 covers the anode 210, it is equivalent to the third sub-pixel definition layer 303 being partially located in the gap A between the anode 210 and the first sub-pixel definition layer 301. Thus, the size of the gap A can be slightly larger during manufacturing, but still meets the small size requirement of the recess 320, making the process easier to implement and control. Furthermore, the third sub-pixel definition layer 303 can also raise the first sub-pixel definition layer 301, so the film thickness of the first sub-pixel definition layer 301 does not need to be excessive, while still meeting the size requirement of the recess 320.

[0075] To meet the size requirements of the recess 320, as an exemplary embodiment, the size d1 of the gap A in the direction from the isolation pillar 400 to the pixel opening 310 is 0.6 to 0.8 micrometers. For example, the size d1 of the gap A can be 0.7 micrometers. The film thickness of the first sub-pixel defining layer 301 is less than or equal to... The thickness of the second sub-pixel definition layer 302 is 1.5 μm ± 10%; the thickness of the third sub-pixel definition layer 303 is 1.5 μm ± 10%.

[0076] The anode 210 has a first sidewall 2101, and the first sub-pixel definition layer 301 has a second sidewall 3011. The first sidewall 2101 and the second sidewall 3011 cooperate to form the gap A. The slope angle α of the first sidewall 2101 is 50-70°, and the slope angle β of the second sidewall 3011 is 50-70°. For example, α is 60° and β is 60°.

[0077] It should be understood that the above is only an example. In actual applications, parameters such as the film thickness of each film layer of the pixel definition layer 300, the size of the gap A, and the slope angle of the first sidewall 2101 and the second sidewall 3011 are not limited to this.

[0078] Furthermore, as an exemplary embodiment, the material of the first sub-pixel definition layer 301 may include, but is not limited to, a gate metal material, the material of the second sub-pixel definition layer 302 may include an inorganic insulating material, and the material of the third sub-pixel definition layer 303 may include an inorganic insulating material.

[0079] Using the above scheme, the first sub-pixel definition layer 301 is made of gate metal material, and the second sub-pixel definition layer 302 and the third sub-pixel definition layer 303 can be made of inorganic insulating material. The inorganic insulating material and the gate metal material are less likely to have unexpected influences, making it easier to form the expected pit size 320, and the patterning process of each sub-pixel definition layer 300 is simple.

[0080] It is understood that the materials of the first sub-pixel definition layer 301, the second sub-pixel definition layer 302, and the third sub-pixel definition layer 303 are not limited to these.

[0081] Furthermore, this disclosure also provides a method for manufacturing a display substrate, used to manufacture the display substrate provided in this disclosure.

[0082] Please see Figures 2 to 6 As shown, the method for manufacturing the display substrate includes the following steps:

[0083] Step S01: Provide a substrate 100, the substrate 100 including a plurality of pixels;

[0084] Step S02: An anode layer 200 is formed on the substrate 100, wherein the anode layer 200 includes a pattern of a plurality of anodes 210 disposed corresponding to a plurality of pixels P;

[0085] Step S03, please refer to Figure 4 As shown, a pixel definition layer 300 is formed on the side of the anode layer 200 away from the substrate 100. The pixel definition layer 300 defines a plurality of pixel openings 310 corresponding to a plurality of pixels P. The pixel definition layer 300 has a recess 320 around the pixel openings 310 on the side away from the substrate 100.

[0086] Step S04, please refer to Figure 5 As shown, an isolation pillar 400 is formed on the side of the pixel definition layer 300 facing away from the substrate 100, wherein the isolation pillar 400 is located between adjacent pixel openings 310.

[0087] Step S05, please refer to Figure 6As shown, a light-emitting layer 500 and a cathode layer 600 are sequentially formed on the side of the pixel definition layer 300 and the isolation pillar 400 away from the substrate 100. The light-emitting layer 500 and the cathode layer 600 are separated by the isolation pillar 400. The cathode layer 600 in an adjacent pixel P is in contact with the isolation pillar 400. The light-emitting layer 500 covers the side of the pixel definition layer 300 away from the substrate 100 and forms a thinning region 510 at the position corresponding to the pit 320. The film thickness of the thinning region 510 is less than the film thickness of other areas of the light-emitting layer 500 except for the thinning region 510.

[0088] For example, step S03 above specifically includes:

[0089] Step S031, please refer to Figure 3 As shown, a first sub-pixel definition layer 301 is formed, which is located in a first region S1 between adjacent anodes 210, and the pattern of the first sub-pixel definition layer 301 has a gap A between it and the anodes 210 adjacent to the first sub-pixel definition layer 301.

[0090] Step S032, please refer to Figure 4 As shown, a second sub-pixel definition layer 302 is formed on the side of the first sub-pixel definition layer 301 away from the substrate 100. The second sub-pixel definition layer 302 conformally covers the side of the first sub-pixel definition layer 301 away from the substrate 100. The second sub-pixel definition layer 302 is at least partially located in the first region S1 and at least partially located in the second region S2 on the side of the anode 210 away from the substrate 100. The pit 320 is formed at the position covering the gap A.

[0091] For example, step S031 above specifically includes:

[0092] Step S030, please refer to Figure 2 As shown, a third sub-pixel definition layer 303 is formed before the first sub-pixel definition layer 301 is formed. The third sub-pixel definition layer 303 is stacked on the side of the first sub-pixel definition layer 301 near the substrate 100, and the third sub-pixel definition layer 303 is at least partially located in the first region S1 and at least partially located in the second region S2.

[0093] Furthermore, for example, after step S05 above, the method further includes:

[0094] Step S06: Forming the encapsulation layer 700, resulting in a display substrate structure as shown below. Figure 1 As shown.

[0095] Furthermore, this disclosure also provides a display device, which includes the display substrate provided in this disclosure. The display device includes, but is not limited to, smartphones, monitors, laptops, tablets, electronic photo frames, dashcams, smart wearable devices, and other devices with display functions. Other essential components of the display device (e.g., driver chips) are readily understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure. Since the principle by which this display device solves the problem is similar to that of the display substrate described above, the embodiments of the display device provided in this disclosure can be referenced to the embodiments of the display substrate provided in this disclosure, and will not be repeated here.

[0096] The following points need to be explained:

[0097] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0098] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0099] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0100] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, include: Substrate, comprising multiple pixels; The anode layer includes multiple anodes set for multiple pixels; A pixel definition layer is located on the side of the anode layer opposite to the substrate, and the pixel definition layer defines a plurality of pixel openings corresponding to a plurality of pixels; An isolation pillar is located on the side of the pixel definition layer away from the substrate and between adjacent pixel openings; and A light-emitting layer and a cathode layer are sequentially stacked on the pixel definition layer and the side of the isolation pillar away from the substrate, along a direction away from the substrate, and the light-emitting layer and the cathode layer are separated by the isolation pillar. The cathode layer in adjacent pixels is in contact with the isolation pillar. The pixel definition layer has a recess around the pixel opening on one side away from the substrate. The light-emitting layer covers the side of the pixel definition layer away from the substrate and forms a thinning region at the position corresponding to the recess. The film thickness of the thinning region is less than the film thickness of other areas of the light-emitting layer except for the thinning region.

2. The display substrate according to claim 1, characterized in that, The pixel definition layer includes: A first region covering the area between adjacent anodes; and A second region covering the side of the anode away from the substrate; wherein, The recess is located at the boundary between the first region and the second region, and in the direction from the isolation post to the pixel opening, the recess is located between the isolation post and the pixel opening.

3. The display substrate according to claim 2, characterized in that, The pixel definition layer includes at least a first sub-pixel definition layer and a second sub-pixel definition layer; wherein... The first subpixel defining layer is located in the first region, and there is a gap between the pattern of the first subpixel defining layer and the anode adjacent to the first subpixel defining layer; the second subpixel defining layer conformally covers the side of the first subpixel defining layer away from the substrate, and is at least partially located in the first region and at least partially located in the second region, and forms the pit at the location covering the gap.

4. The display substrate according to claim 3, characterized in that, The pixel definition layer further includes at least a third sub-pixel definition layer, which is stacked on the side of the first sub-pixel definition layer near the substrate, and the third sub-pixel definition layer is at least partially located in the first region and at least partially located in the second region.

5. The display substrate according to claim 4, characterized in that, The size of the gap is 0.6 to 0.8 micrometers in the direction from the isolation pillar to the pixel opening.

6. The display substrate according to claim 4, characterized in that, The thickness of the first sub-pixel definition layer is less than or equal to The thickness of the second sub-pixel definition layer is 1.5 μm ± 10%; the thickness of the third sub-pixel definition layer is 1.5 μm ± 10%.

7. The display substrate according to claim 4, characterized in that, The anode has a first sidewall, the first sub-pixel definition layer has a second sidewall, the first sidewall and the second sidewall cooperate to form the gap, the slope angle of the first sidewall is 50-70°, and the slope angle of the second sidewall is 50-70°.

8. The display substrate according to claim 4, characterized in that, The material of the first sub-pixel defining layer includes a gate metal material, the material of the second sub-pixel defining layer includes an inorganic insulating material, and the material of the third sub-pixel defining layer includes an inorganic insulating material.

9. The display substrate according to claim 1, characterized in that, The light-emitting layer has a film connection portion and a film break portion sequentially disposed in the thinning region along the direction away from the substrate. The film thickness of the film connection portion is a first thickness h1, and the film thickness of the other regions of the light-emitting layer other than the thinning region is a second thickness h2, where h1 / h2 = 0.05 to 0.

1.

10. A method for manufacturing a display substrate, characterized in that, The method includes the following steps: Provide a substrate; An anode layer is formed on the substrate, wherein the anode layer includes a pattern of multiple anodes disposed corresponding to multiple pixels; A pixel definition layer is formed on the side of the anode layer away from the substrate, wherein a plurality of pixel openings corresponding to a plurality of pixels are defined on the pixel definition layer, and a recess is provided around the pixel opening on the side of the pixel definition layer away from the substrate; An isolation pillar is formed on the side of the pixel definition layer opposite to the substrate, wherein the isolation pillar is located between adjacent pixel openings; A light-emitting layer and a cathode layer are sequentially formed on the side of the pixel definition layer and the isolation pillar away from the substrate. The light-emitting layer and the cathode layer are separated by the isolation pillar. The cathode layer in an adjacent pixel is in contact with the isolation pillar. The light-emitting layer covers the side of the pixel definition layer away from the substrate and forms a thinning region at the position corresponding to the pit. The film thickness of the thinning region is less than the film thickness of other regions of the light-emitting layer except for the thinning region.

11. The method according to claim 10, characterized in that, The formation of a pixel definition layer on the side of the anode layer opposite to the substrate specifically includes: A first subpixel definition layer is formed, the first subpixel definition layer is located in a first region between adjacent anodes, and the pattern of the first subpixel definition layer has a gap between it and the anodes adjacent to the first subpixel definition layer; A second subpixel definition layer is formed on the side of the first subpixel definition layer away from the substrate, wherein the second subpixel definition layer conformally covers the side of the first subpixel definition layer away from the substrate, and the second subpixel definition layer is at least partially located in the first region, at least partially located in the second region of the anode on the side away from the substrate, and the pit is formed at the location covering the gap.

12. The method according to claim 11, characterized in that, The step of forming a pixel definition layer on the side of the anode layer opposite to the substrate specifically includes: Before forming the first subpixel definition layer, a third subpixel definition layer is formed, wherein the third subpixel definition layer is stacked on the side of the first subpixel definition layer near the substrate, and the third subpixel definition layer is at least partially located in the first region and at least partially located in the second region.

13. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 9.

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