Display device, method of manufacturing the same, and electronic device including the same

Abstract

A display device, a method of manufacturing the same, and an electronic device including the same are provided. The display device includes: a substrate; a pixel electrode disposed on the substrate; and a pixel defining layer defining an opening exposing a central portion of the pixel electrode, and including a trench portion recessed in a direction toward the pixel electrode. The pixel defining layer includes: a first pixel defining layer adjacent to the opening; a second pixel defining layer is spaced apart from the first pixel defining layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0153621, filed with the Korean Intellectual Property Office on November 1, 2024, and Korean Patent Application No. 10-2025-0074074, filed with the Korean Intellectual Property Office on June 5, 2025, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a display device, a method of manufacturing the display device, and an electronic device including the display device. Background Technology

[0003] As the demand for display devices expands, the need for display devices for various applications is also increasing. Due to this trend, display devices tend to be manufactured to be larger or thinner. Therefore, there is an increasing demand for larger and thinner display devices that provide accurate and vibrant colors. Summary of the Invention

[0004] One or more embodiments include a display device having improved optical properties, a method of manufacturing the display device, and an electronic device including the display device.

[0005] However, this is merely an example, and the technical features of this disclosure are not limited thereto.

[0006] According to one aspect of this disclosure, a display device includes: a substrate; a pixel electrode disposed on the substrate; and a pixel defining layer defining an opening exposing a central portion of the pixel electrode, and including a trench portion recessed in a direction toward the pixel electrode. The pixel defining layer includes: a first pixel defining layer adjacent to the opening; and a second pixel defining layer spaced apart from the first pixel defining layer.

[0007] In some embodiments, the pixel defining layer may include a black pixel defining layer.

[0008] In some embodiments, the trench portion may be configured to expose at least a portion of the pixel electrode.

[0009] In some embodiments, the pixel electrode may be configured to overlap the entire area of ​​the first pixel defining layer.

[0010] In some embodiments, the first pixel defining layer may be formed in a shape in which the width of the first pixel defining layer narrows in a direction away from the pixel electrode.

[0011] In some embodiments, the tilt angle of the portion of the first pixel defining layer adjacent to the opening may be greater than the tilt angle of the portion of the first pixel defining layer adjacent to the trench portion.

[0012] In some embodiments, the tilt angle of the portion of the first pixel defining layer adjacent to the trench portion can be from 11° to 45°.

[0013] In some embodiments, the pixel electrode may be configured to overlap with at least a portion of the second pixel defining layer.

[0014] In some embodiments, the first pixel defining layer and the second pixel defining layer may be spaced apart from each other by a distance of 2.0 μm to 2.2 μm.

[0015] In some embodiments, the display device may further include an anti-reflective member disposed on the pixel defining layer to overlap at least a portion of the trench portion.

[0016] According to another aspect of this disclosure, an electronic device includes: a substrate; a pixel electrode disposed on the substrate; a pixel defining layer defining an opening exposing a central portion of the pixel electrode and including a trench portion recessed in a direction toward the pixel electrode; and a capping layer disposed on the trench portion.

[0017] In some embodiments, the capping layer may include a material different from that of the pixel defining layer.

[0018] In some embodiments, the trench portion may be configured to expose at least a portion of the pixel electrode.

[0019] In some embodiments, the capping layer may be configured to cover at least a portion of the exposed pixel electrode.

[0020] In some embodiments, the pixel defining layer may include: a first pixel defining layer adjacent to the opening; and a second pixel defining layer spaced apart from the first pixel defining layer.

[0021] In some embodiments, the capping layer may be configured not to cover the top edge of the first pixel-defined layer.

[0022] In some embodiments, the capping layer may be configured to cover the top edge of the second pixel-defining layer.

[0023] In some embodiments, the capping layer may overlap the first pixel defining layer by more than 0 μm and less than or equal to 2.0 μm.

[0024] In some embodiments, the thickness of the capping layer may be from 0.4 μm to 0.8 μm.

[0025] In some embodiments, the electronic device may further include an anti-reflective member disposed on the pixel defining layer to overlap at least a portion of the trench portion. Attached Figure Description

[0026] These and / or other aspects will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings.

[0027] Figure 1 This is a schematic perspective view of a display device according to an embodiment.

[0028] Figure 2 It is a schematic diagram. Figure 1 A cross-sectional view of an example of section I-I'.

[0029] Figure 3 It is a schematic diagram. Figure 1 A plan view of a portion of the display device.

[0030] Figure 4 It is a diagram. Figure 1 A circuit diagram of an example of pixels in a display device.

[0031] Figure 5 It is a schematic diagram. Figure 3 A cross-sectional view of an example of a pixel.

[0032] Figure 6 yes Figure 5 A magnified view of region X.

[0033] Figure 7A This is a photograph of a top view of the pixel-defined layer according to an embodiment.

[0034] Figure 7B It is a schematic diagram. Figure 7A An example cross-sectional view of section IV-IV'.

[0035] Figure 7C It is a schematic diagram. Figure 7A A cross-sectional view of an example of the V-V' section.

[0036] Figure 8A It is a schematic diagram used to form Figures 7A to 7C A diagram of an embodiment of a photomask for a pixel-defined layer.

[0037] Figure 8B It is a schematic diagram used to form Figures 7A to 7C A diagram of an embodiment of a photomask for a pixel-defined layer.

[0038] Figure 8C It is a schematic diagram of the diagram. Figure 8A A diagram of pixel-defined layers formed by a photomask.

[0039] Figure 8D It is a schematic diagram of the diagram. Figure 8B A diagram of pixel-defined layers formed by a photomask.

[0040] Figure 8E This diagram illustrates diffraction and glare in the emission region depending on whether a groove portion is formed and the shape of the opening defined by the pixel-limiting layer.

[0041] Figure 8F This is a diagram illustrating the distance between adjacent trench portions according to an embodiment.

[0042] Figure 8G It is a diagram. Figure 8F The second pixel defining layer between adjacent trench portions in the image is removed.

[0043] Figure 8H This is a diagram illustrating an embodiment where there is no second pixel defining layer between adjacent trench portions.

[0044] Figure 8I This is a diagram illustrating the groove portion and the transmission opening according to an embodiment.

[0045] Figure 8J It is a diagram. Figure 8I A cross-sectional view of an example of section VI-VI'.

[0046] Figure 8K It is a diagram. Figure 8I The image shows the removal of the second pixel-defining layer between the groove portion and the transmission opening.

[0047] Figure 8L This is a diagram illustrating an embodiment where there is no second pixel defining layer between the transmission opening and the trench portion.

[0048] Figure 8M It is a diagram and Figure 8L The image shows the second pixel-defining layer near the transmission opening being removed.

[0049] Figure 8N It is a diagram and Figure 8L Another image shows the second pixel-defining layer near the transmission opening being removed.

[0050] Figure 9 It is used to describe the formation Figures 7A to 7C A diagram showing the process of the pixel-limiting layer.

[0051] Figure 10A This is a diagram used to describe a pixel-defining layer formed thereon as an encapsulation layer according to an embodiment.

[0052] Figure 10B This is another diagram used to describe the pixel-defining layer on which the capping layer is formed according to an embodiment.

[0053] Figure 10C It is a schematic diagram used to form Figure 10A or Figure 10BA diagram of an embodiment of a photomask for a capping layer.

[0054] Figure 10D It is used to describe the formation Figure 10A or Figure 10B The process of the capping layer and Figure 10C The diagram of section III-III".

[0055] Figure 11A This is a diagram used to describe a pixel-defining layer on which an insulator is formed according to an embodiment.

[0056] Figure 11B This is a schematic diagram illustrating the process of forming an isolator in a pixel-defining layer according to an embodiment.

[0057] Figure 11C This is a photograph of an isolator formed in a pixel-defining layer according to an embodiment.

[0058] Figure 12 It is a diagram used to describe the reflection path of light in a display device according to the present disclosure.

[0059] Figure 13A and Figure 13B It is used to describe Figure 12 A photograph showing the effect of improved optical properties in a display device.

[0060] Figure 14A This is a diagram illustrating an embodiment of a display device according to the present disclosure, wherein the anti-reflective element is removed.

[0061] Figure 14B This is a diagram illustrating an embodiment of a display device according to the present disclosure, wherein the anti-reflective element is removed.

[0062] Figure 14C This is a diagram illustrating an embodiment of a display device according to the present disclosure, wherein the anti-reflective element is removed.

[0063] Figure 15 and Figure 16 This is a table used to describe the effect of improving optical properties based on the thickness of the capping layer.

[0064] Figure 17 This is a flowchart of a method for manufacturing a display device according to an embodiment.

[0065] Figure 18 This is a block diagram schematically illustrating an example of an electronic device according to an embodiment. Detailed Implementation

[0066] Because this description allows for various modifications and numerous embodiments, specific embodiments will be illustrated in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure, as well as methods of implementing them, will be illustrated with reference to the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below and can be embodied in various forms.

[0067] In the following embodiments, the terms "first," "second," etc., are used without limitation and are used to distinguish one element from another.

[0068] The singular forms used in this article are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0069] It will be further understood that the terms “comprising” and / or “including” as used herein indicate the presence of a stated feature or element, but do not exclude the presence or addition of one or more other features or elements.

[0070] In the following embodiments, it will be understood that when a portion such as a unit, area, or element is referred to as being “on” another portion, this can include not only cases where the portion is directly on the other portion, but also cases where there may be an intermediate unit, area, or element between the portion and the other portion.

[0071] In the following embodiments, it will be understood that the terms “connection” or “coupled” do not necessarily mean a “direct and / or fixed connection or coupling” between two components, unless the context clearly indicates otherwise, and this does not preclude the placement of other components between the two components.

[0072] Furthermore, the term “about” is intended to account for deviations due to experimental errors or manufacturing tolerances and should be interpreted as encompassing values ​​that achieve substantially the same result.

[0073] Furthermore, for ease of interpretation, the dimensions of the elements in the accompanying drawings may be exaggerated or reduced. For example, this disclosure is not limited thereto because the dimensions and / or thicknesses of the elements in the accompanying drawings are arbitrarily illustrated for ease of interpretation.

[0074] In the following description, embodiments will be illustrated in detail with reference to the accompanying drawings. When describing embodiments with reference to the accompanying drawings, the same or corresponding elements are designated by the same reference numerals, and redundant descriptions of the same or corresponding elements are omitted.

[0075] Figure 1 This is a schematic perspective view of the display device 1 according to an embodiment, and Figure 2 It is a schematic diagram. Figure 1 A cross-sectional view of an example of section I-I'.

[0076] refer to Figure 1According to an embodiment, the display device 1 may include a display area DA and a peripheral area PA. The peripheral area PA may be disposed outside the display area DA to surround the display area DA. Various wiring and driving circuits configured to transmit electrical signals to be applied to the display area DA may be disposed in the peripheral area PA. The display device 1 can provide an image by using light emitted from a plurality of pixels disposed in the display area DA. Although not shown, the display device 1 may include a bent region in a portion of the peripheral area PA, such that the display device 1 is bendable in the bent region.

[0077] Examples of display device 1 may include organic light-emitting displays, inorganic light-emitting displays (or inorganic electroluminescent (EL) displays), and quantum dot light-emitting displays, etc. In the following description, organic light-emitting displays are used as examples of display device 1. Display device 1 can be implemented as various types of electronic devices such as mobile phones, laptop computers, or smartwatches.

[0078] like Figure 2 As illustrated in the figure, the display device 1 may include a substrate 100 stacked in the thickness direction (z direction), a pixel layer PXL on the substrate 100, an encapsulation member 300 sealing the pixel layer PXL, a touch sensing layer 400 on the encapsulation member 300, and a cover layer 500 on the touch sensing layer 400.

[0079] The substrate 100 may comprise glass or polymer resin. For example, the substrate 100 may comprise a glass material comprising SiO2 as a primary component, or may comprise other flexible or bendable materials, such as resins (e.g., reinforced plastics). Although not illustrated, the substrate 100 may include a bending region within a portion of the peripheral region PA, such that the substrate 100 is bendable within that bending region.

[0080] A pixel layer PXL can be disposed on the substrate 100. The pixel layer PXL may include a display element layer DPL containing display elements for each pixel and a pixel circuit layer PCL containing pixel circuitry and insulating layers for each pixel. The display element layer DPL may be disposed on the pixel circuit layer PCL, and multiple insulating layers may be disposed between the pixel circuitry and the display elements. Some lines and insulating layers in the pixel circuit layer PCL may extend to the peripheral area PA.

[0081] The encapsulation member 300 may be a thin-film encapsulation layer. The thin-film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. When the display device 1 includes a substrate 100 comprising a polymer resin and an encapsulation member 300 comprising a thin-film encapsulation layer comprising an inorganic encapsulation layer and an organic encapsulation layer, the flexibility of the display device 1 can be improved.

[0082] The touch sensing layer 400 can be configured to obtain coordinate information based on external input (e.g., touch events).

[0083] The touch sensing layer 400 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The touch sensing layer 400 may be configured to sense external input using mutual capacitance and / or self-capacitance methods.

[0084] In this embodiment, the touch sensing layer 400 may be a capacitive touch sensing layer. When the cover layer 500 is touched, a change in capacitance occurs between the sensing electrode and the counter electrode of the touch sensing layer 400. The touch sensing layer 400 can sense the change in capacitance and determine whether the corresponding portion is in contact or not.

[0085] The touch sensing layer 400 can be formed directly on the display panel DP, which includes the pixel layer PXL and the encapsulation member 300. For example, the touch sensing layer 400 can be formed separately and then bonded by an adhesive layer (such as optically clear adhesive (OCA)). For example, the touch sensing layer 400 can be formed continuously after the process of forming the display panel. In this case, an adhesive layer may not be provided between the touch sensing layer 400 and the display panel.

[0086] The cover layer 500 can be disposed on the touch sensing layer 400 to protect the display device 1.

[0087] The capping layer 500 may be flexible. The capping layer 500 may include polymethyl methacrylate, polydimethylsiloxane, polyimide, acrylate, polyethylene terephthalate, or polyethylene naphthalate, etc. However, this disclosure is not limited thereto, and the capping layer 500 may include other materials such as metals. In some cases, the capping layer 500 may include a thin metal foil such as stainless steel (SUS).

[0088] In some embodiments, specific attention is paid to Figure 1 The display panel DP may include component areas EA. Specifically, the display panel DP may include a first component area EA1 and a second component area EA2. The first component area EA1 and the second component area EA2 may be at least partially surrounded by the display area DA. The first component area EA1 and the second component area EA2 are illustrated as being spaced apart from each other, but this disclosure is not limited thereto, and the first component area EA1 and the second component area EA2 may be at least partially connected to each other. The first component area EA1 and the second component area EA2 may be areas beneath which components using infrared light, visible light, or sound, etc., are disposed.

[0089] Optical elements can be positioned below the display panel DP. These optical elements may include a first optical element overlapping a first component region EA1 and a second optical element overlapping a second component region EA2. In this case, the optical element corresponding to the first component region EA1 may be a light sensor, and the optical element corresponding to the second component region EA2 may be a camera.

[0090] Figure 3 It is a schematic diagram. Figure 1 A plan view of a portion of the display device 1, and Figure 4 It is a diagram. Figure 1 A circuit diagram of an example of a pixel PX of a display device 1.

[0091] refer to Figure 3 The substrate 100 may include a display area DA (corresponding to Figure 1 The display area DA and the peripheral area PA shown in the figure correspond to Figure 1 The peripheral area PA is shown in the figure. The peripheral area PA can be set outside the display area DA to surround the display area DA.

[0092] Multiple pixels PX can be patterned in the display area DA of the substrate 100 in a first direction (x-direction or row direction) and a second direction (y-direction or column direction).

[0093] The scan driver GP is configured to provide scan signals to each of the pixels PX, the data driver DD is configured to provide data signals to each of the pixels PX, and the first power supply voltage is configured to be provided (see [link]). Figure 4 ELVDD) and second supply voltage (see ELVDD) and second supply voltage (see ELVDD). Figure 4 The main power line (not shown) of the ELVSS can be provided in the peripheral area PA of the substrate 100. The pad portion 140, in which multiple signal pads SP connected to the data lines DL are respectively provided, can be provided in the peripheral area PA of the substrate 100.

[0094] The scan driver GP may include an oxide semiconductor thin film transistor (TFT) gate driver circuit (OSG) or an amorphous silicon TFT gate driver circuit (ASG). Figure 3 The illustrated scan driver GP is positioned adjacent to one side of the substrate 100, but in the embodiment, the scan driver GP may be positioned adjacent to two opposite sides of the substrate 100.

[0095] Figure 3The illustration shows a chip-on-film (COF) method in which the data driver DD is disposed on a film FL electrically connected to the signal pads SP on the substrate 100. According to an embodiment, the data driver DD can be directly disposed on the substrate 100 using a chip-on-glass (COG) method or a chip-on-plastic (COP) method. The data driver DD can be electrically connected to a flexible printed circuit board (FPCB).

[0096] refer to Figure 4 A pixel PX may include a pixel circuit PC and an organic light-emitting diode (OLED) electrically connected to the pixel circuit PC.

[0097] Pixels (PX) can emit light such as red, green, blue, or white light through organic light-emitting diodes (OLEDs).

[0098] The pixel circuit PC may include a storage capacitor Cst and multiple transistors T1 to T7, such as Figure 4 As shown in the diagram, transistors T1 to T7 and storage capacitor Cst can be connected to signal lines SL, SL-1, SL+1, EL and DL, the first initialization voltage line VL1, the second initialization voltage line VL2, and the drive voltage line PL.

[0099] Signal lines SL, SL-1, SL+1, EL, and DL may include a scan line SL configured to transmit a scan signal Sn to switching transistor T2 and compensation transistor T3; a previous scan line SL-1 configured to transmit a previous scan signal Sn-1 to first initialization transistor T4; a next scan line SL+1 configured to transmit a scan signal Sn to second initialization transistor T7; an emit control line EL configured to transmit an emit control signal En to operation control transistor T5 and emit control transistor T6; and a data line DL intersecting the scan line SL and configured to transmit a data signal Dm. A drive voltage line PL may be configured to transmit a drive voltage ELVDD to drive transistor T1; a first initialization voltage line VL1 may be configured to transmit an initialization voltage Vint to first initialization transistor T4; and a second initialization voltage line VL2 may be configured to transmit an initialization voltage Vint to second initialization transistor T7. The first initialization voltage line VL1 and the second initialization voltage line VL2 may be collectively referred to as the initialization voltage line VL.

[0100] The driving gate electrode G1 of driving transistor T1 can be connected to the lower electrode CE1 of storage capacitor Cst, the driving source electrode S1 of driving transistor T1 can be connected to the driving voltage line PL via operation control transistor T5, and the driving drain electrode D1 of driving transistor T1 can be electrically connected to the pixel electrode of organic light-emitting diode (OLED) via emitter control transistor T6. Driving transistor T1 can be configured to receive data signal Dm according to the switching operation of switching transistor T2 and to drive current I... OLED It is supplied to organic light-emitting diodes (OLEDs).

[0101] The switching gate electrode G2 of the switching transistor T2 can be connected to the scan line SL, the switching source electrode S2 of the switching transistor T2 can be connected to the data line DL, and the switching drain electrode D2 of the switching transistor T2 can be connected to the driving source electrode S1 of the driving transistor T1 and connected to the driving voltage line PL via the operation control transistor T5. The switching transistor T2 can be configured to turn on in response to the scan signal Sn received through the scan line SL and perform a switching operation to transmit the data signal Dm received from the data line DL to the driving source electrode S1 of the driving transistor T1.

[0102] The compensation gate electrode G3 of the compensation transistor T3 can be connected to the scan line SL. The compensation source electrode S3 of the compensation transistor T3 can be connected to the driving drain electrode D1 of the driving transistor T1 and connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control transistor T6. Furthermore, the compensation drain electrode D3 of the compensation transistor T3 can be connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization transistor T4, and the driving gate electrode G1 of the driving transistor T1. The compensation transistor T3 can be configured to turn on in response to the scan signal Sn received via the scan line SL, and to electrically connect the driving gate electrode G1 of the driving transistor T1 to the driving drain electrode D1 of the driving transistor T1, such that the driving transistor T1 can be diode-connected.

[0103] The first initialization gate electrode G4 of the first initialization transistor T4 can be connected to the previous scan line SL-1, the first initialization source electrode S4 of the first initialization transistor T4 can be connected to the first initialization voltage line VL1, and the first initialization drain electrode D4 of the first initialization transistor T4 can be connected to the lower electrode CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation transistor T3, and the driving gate electrode G1 of the driving transistor T1. The first initialization transistor T4 can be configured to turn on in response to the previous scan signal Sn-1 received through the previous scan line SL-1 and perform an initialization operation to transmit the initialization voltage Vint to the driving gate electrode G1 of the driving transistor T1 in order to initialize the voltage of the driving gate electrode G1 of the driving transistor T1.

[0104] The operating control gate electrode G5 of the operating control transistor T5 can be connected to the emitter control line EL, the operating control source electrode S5 of the operating control transistor T5 can be connected to the drive voltage line PL, and the operating control drain electrode D5 of the operating control transistor T5 can be connected to the drive source electrode S1 of the drive transistor T1 and the switch drain electrode D2 of the switch transistor T2.

[0105] The emission control gate electrode G6 of the emission control transistor T6 can be connected to the emission control line EL, the emission control source electrode S6 of the emission control transistor T6 can be connected to the driving drain electrode D1 of the driving transistor T1 and the compensation source electrode S3 of the compensation transistor T3, and the emission control drain electrode D6 of the emission control transistor T6 can be electrically connected to the second initialization source electrode S7 of the second initialization transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0106] The operation control transistor T5 and the emitter control transistor T6 can be configured to simultaneously turn on in response to the emitter control signal En received via the emitter control line EL, and transmit the drive voltage ELVDD to the organic light-emitting diode OLED, causing the drive current I... OLED It flows through an organic light-emitting diode (OLED).

[0107] The second initialization gate electrode G7 of the second initialization transistor T7 can be connected to the next scan line SL+1, the second initialization source electrode S7 of the second initialization transistor T7 can be connected to the emission control drain electrode D6 of the emission control transistor T6 and the pixel electrode of the organic light-emitting diode OLED, and the second initialization drain electrode D7 of the second initialization transistor T7 can be connected to the second initialization voltage line VL2.

[0108] Because scan line SL and the next scan line SL+1 are electrically connected to each other, the same scan signal Sn can be applied to both scan line SL and the next scan line SL+1. Accordingly, the second initialization transistor T7 can be configured to turn on in response to the scan signal Sn received through the next scan line SL+1 and perform an initialization operation to initialize the pixel electrodes of the organic light-emitting diode OLED.

[0109] The upper electrode CE2 of the storage capacitor Cst can be connected to the driving voltage line PL, and the common electrode of the organic light-emitting diode (OLED) can be connected to the line transmitting the common voltage ELVSS. Accordingly, the OLED can be configured to receive a driving current I from the driving transistor T1. OLED It also emits light to display images.

[0110] although Figure 4The diagram shows that each of the compensation transistor T3 and the first initialization transistor T4 has a dual-gate electrode, but each of the compensation transistor T3 and the first initialization transistor T4 may have a single-gate electrode.

[0111] Although reference Figure 4 The structure of a single pixel circuit PC is described, but multiple pixels PX with the same pixel circuit PC structure can be set to form multiple rows. In this case, the first initialization voltage line VL1, the previous scan line SL-1, the second initialization voltage line VL2, and the next scan line SL+1 can be shared by neighboring pixels PX.

[0112] For example, the first initialization voltage line VL1 and the previous scan line SL-1 can be electrically connected to the second initialization transistor of another pixel circuit PC disposed along the second direction (y-direction). Accordingly, the previous scan signal applied to the previous scan line SL-1 can be transmitted as the next scan signal to the second initialization transistor of the other pixel circuit PC. Similarly, the second initialization voltage line VL2 and the next scan line SL+1 can be electrically connected to the first initialization transistor of another pixel circuit PC disposed adjacent to them along the second direction (y-direction) with respect to the figures, and are configured to transmit the initialization voltage and the previous scan signal to the first initialization transistor of the other pixel circuit PC, respectively.

[0113] Figure 5 It is a schematic diagram. Figure 3 A cross-sectional view of an example of a pixel's cross-section, and Figure 6 yes Figure 5 A magnified view of region X.

[0114] refer to Figure 5 and Figure 6 The buffer layer 111 can be disposed on the substrate 100 to prevent impurities from penetrating into the semiconductor layer of the thin-film transistor TFT.

[0115] The substrate 100 may comprise various materials such as glass, metal, or plastic. In embodiments, the substrate 100 may be a flexible substrate. For example, the substrate 100 may comprise polymer resins such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, or cellulose acetate propionate (CAP).

[0116] The buffer layer 111 may include an inorganic insulating material such as silicon nitride or silicon oxide, and may be a single layer or multiple layers.

[0117] A thin-film transistor (TFT), a storage capacitor Cst, and an organic light-emitting diode (OLED) 200 electrically connected to the TFT can be disposed on the substrate 100. The statement "the organic light-emitting diode 200 is electrically connected to the TFT" can mean that the pixel electrode 211 is electrically connected to the TFT. The TFT can be... Figure 4 The first transistor T1, and the organic light-emitting diode 200 can be Figure 4 Organic light-emitting diodes (OLEDs).

[0118] A thin-film transistor (TFT) may include a semiconductor layer 132, a gate electrode 134, a source electrode 136S, and a drain electrode 136D. The semiconductor layer 132 may include an oxide semiconductor material. The semiconductor layer 132 may include amorphous silicon, polycrystalline silicon, or an organic semiconductor material. Considering adhesion to adjacent layers, surface flatness of the stacked layers, and processability, the gate electrode 134 may include a single layer or multiple layers comprising one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0119] A gate insulating layer 112 comprising an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be disposed between the semiconductor layer 132 and the gate electrode 134. A first interlayer insulating layer 113 and a second interlayer insulating layer 114, each comprising an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, may be disposed between the gate electrode 134 and the source electrode 136S, and between the gate electrode 134 and the drain electrode 136D. The source electrode 136S and the drain electrode 136D may be electrically connected to the semiconductor layer 132 through contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114.

[0120] The source electrode 136S and the drain electrode 136D may each comprise a single layer or multiple layers of one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0121] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 that overlap each other through a first interlayer insulating layer 113. The first interlayer insulating layer 113 may be disposed between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst may overlap with a thin-film transistor (TFT). Figure 5The gate electrode 134 of the illustrated thin-film transistor TFT is the lower electrode CE1 of the storage capacitor Cst. In this embodiment, the storage capacitor Cst may not overlap with the thin-film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer 114.

[0122] The pixel circuitry, including a thin-film transistor (TFT) and a storage capacitor (Cst), can be covered by a first insulating layer 115 and a second insulating layer 116. The first insulating layer 115 and the second insulating layer 116 can each be an organic insulating layer that is a planarization insulating layer. The first insulating layer 115 and the second insulating layer 116 can each comprise an organic insulating material, such as a general-purpose polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and any blends thereof. In an embodiment, the first insulating layer 115 and the second insulating layer 116 can each comprise polyimide (PI).

[0123] A display element (e.g., an organic light-emitting diode 200) may be disposed on the second insulating layer 116. The organic light-emitting diode 200 may include a pixel electrode 211, an intermediate layer 231, and a counter electrode 251.

[0124] Pixel electrode 211 can be disposed on the second insulating layer 116 and can be connected to the thin-film transistor TFT via connection electrode 181 on the first insulating layer 115. Wiring 183 (such as data line DL and drive voltage line PL) can be disposed on the first insulating layer 115.

[0125] Pixel electrode 211 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In embodiments, pixel electrode 211 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound thereof. In embodiments, pixel electrode 211 may further include a layer comprising ITO, IZO, ZnO, or In2O3 above and / or below the reflective layer.

[0126] A third insulating layer 117 may be disposed on the second insulating layer 116. The third insulating layer 117 may be a pixel defining layer that covers the edge of the pixel electrode 211 and defines the pixel by having an opening OP1 extending to the pixel electrode 211 and exposing a portion of the pixel electrode 211. The opening OP1 may correspond to a first region A1. The region other than the opening OP1 may correspond to a second region A2. The third insulating layer 117 can prevent arcing or the like at the edge of the pixel electrode 211 by increasing the distance between the edge of the pixel electrode 211 and the counter electrode 251. For example, the third insulating layer 117 may comprise an organic material such as PI or hexamethyldisiloxane (HMDSO).

[0127] The intermediate layer 231 may include an emitting layer 231b. The emitting layer 231b may include a high molecular weight organic material or a low molecular weight organic material that emits light of a selected color. In an embodiment, the intermediate layer 231 may include a first functional layer 231a disposed below the emitting layer 231b and / or a second functional layer 231c disposed above the emitting layer 231b. The first functional layer 231a and / or the second functional layer 231c may include layers integrally formed across a plurality of pixel electrodes 211, or may include layers patterned to correspond to a plurality of pixel electrodes 211 respectively.

[0128] The first functional layer 231a can be a single layer or multiple layers. For example, when the first functional layer 231a comprises a high molecular weight material, the first functional layer 231a can be a single-layer hole transport layer (HTL) and can include poly(3,4)-ethylenedioxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 231a comprises a low molecular weight material, the first functional layer 231a can include a hole injection layer (HIL) and an HTL.

[0129] The second functional layer 231c can be omitted. For example, if the first functional layer 231a and the emitter layer 231b each comprise a high molecular weight material, the second functional layer 231c can be formed to improve the characteristics of the organic light-emitting diode 200. The second functional layer 231c can be a single layer or multiple layers. The second functional layer 231c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0130] Although not illustrated, spacers may be further formed on the third insulating layer 117. The spacers may include organic insulating materials such as PI. For example, the spacers may include inorganic insulating materials such as silicon nitride or silicon oxide, or may include both organic and inorganic insulating materials.

[0131] The spacer may comprise a material different from that of the third insulating layer 117. In other embodiments, the spacer may comprise the same material as the third insulating layer 117. In embodiments, the third insulating layer 117 and the spacer may each comprise PI.

[0132] The counter electrode 251 can be configured to face the pixel electrode 211 via an intermediate layer 231. The intermediate layer 231 can be disposed between the counter electrode 251 and the pixel electrode 211. The counter electrode 251 can include a conductive material with a low work function. For example, the counter electrode 251 can include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or any alloy thereof. In other embodiments, the counter electrode 251 can further include a layer comprising ITO, IZO, ZnO, or In2O3 on a (semi-)transparent layer comprising the material described above.

[0133] Counter electrode 251 can be disposed on intermediate layer 231 and third insulating layer 117. Counter electrode 251 can be integrally formed with respect to multiple organic light-emitting diodes 200 in display area DA, and can be opposite to multiple pixel electrodes 211.

[0134] A thin-film encapsulation layer can be disposed on the counter electrode 251 as an encapsulation component 300. The thin-film encapsulation layer can protect the organic light-emitting diode 200 from moisture or oxygen in the environment. The thin-film encapsulation layer can have a multilayer structure. The thin-film encapsulation layer may include a first inorganic layer 310, an organic layer 320, and a second inorganic layer 330. By forming the thin-film encapsulation layer in a multilayer structure, even if cracks occur in the thin-film encapsulation layer, such cracks can be prevented from connecting between the inorganic and organic layers. This can prevent or minimize the formation of pathways through which moisture or oxygen in the environment permeates into the display area DA. In embodiments, the number of organic layers, the number of inorganic layers, and the stacking order of the organic and inorganic layers can be changed.

[0135] For example, the first inorganic layer 310 may cover the counter electrode 251 and may include at least one inorganic insulating material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. Since the first inorganic layer 310 is formed along the structure below the first inorganic layer 310, the upper surface of the first inorganic layer 310 may not be flat.

[0136] The organic layer 320 may cover the first inorganic layer 310 and may have sufficient thickness. The upper surface of the organic layer 320 may be substantially flat across the entire display area DA. The organic layer 320 may comprise polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate or polyacrylic acid), or any combination thereof.

[0137] The second inorganic layer 330 may cover the organic layer 320 and may include at least one inorganic insulating material selected from alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The second inorganic layer 330 may extend outside the organic layer 320 and may contact the first inorganic layer 310 in the peripheral region, such that the organic layer 320 is not exposed to the outside.

[0138] During the process of forming the thin-film encapsulation layer, the structure beneath the thin-film encapsulation layer may be damaged. For example, in the case of forming the first inorganic layer 310, the immediate underlying layer on which the first inorganic layer 310 is formed may be damaged. Therefore, in the process of forming the thin-film encapsulation layer, to prevent damage to the underlying structure, at least one capping layer and / or protective layer may be disposed between the counter electrode 251 and the thin-film encapsulation layer. The protective layer may include an inorganic material.

[0139] Figure 7A This is a photograph of a top view of the pixel-defined layer according to an embodiment. Figure 7B It is a schematic diagram. Figure 7A An example cross-sectional view of section IV-IV'. Figure 7C It is a schematic diagram. Figure 7A A cross-sectional view of an example of the V-V' section. Figure 8A It is a schematic diagram used to form Figures 7A to 7C A diagram of an embodiment of a photomask for a pixel-defined layer. Figure 8B It is a schematic diagram used to form Figures 7A to 7C A diagram of an embodiment of a photomask for a pixel-defined layer. Figure 8C It is a schematic diagram of the diagram. Figure 8A A diagram of pixel-defined layers formed by a photomask. Figure 8D It is a schematic diagram of the diagram. Figure 8B A diagram of pixel-defined layers formed by a photomask. Figure 8E This diagram illustrates diffraction and glare in the emission region depending on whether a groove portion is formed and the shape of the opening defined by the pixel-limiting layer. Figure 9 It is used to describe the formation Figures 7A to 7C A diagram of the pixel-defining layer process. For example, Figure 9 It can be a schematic diagram. Figure 8AExample cross-sectional view of section II-II'.

[0140] In the following text, for ease of explanation, content that is the same as the content provided above or that can be readily applied by those skilled in the art is omitted or briefly described.

[0141] refer to Figures 7A to 9 According to the embodiment, the display device 1 may include a substrate 100, a pixel electrode 211 disposed on the substrate 100, a pixel defining layer 1170 that overlaps at least a portion of the pixel electrode 211, an intermediate layer 231 disposed on the pixel electrode 211, and a counter electrode 251 disposed on the intermediate layer 231.

[0142] Pixel electrode 211 may be disposed on substrate 100. For example, pixel electrode 211 may be formed on substrate 100. As described above, multiple layers may be further formed between pixel electrode 211 and substrate 100.

[0143] The pixel defining layer 1170 may be disposed on the substrate 100. The pixel defining layer 1170 may be all or part of the third insulating layer 117.

[0144] At least a portion of the pixel defining layer 1170 may be configured to overlap with the pixel electrode 211. The pixel defining layer 1170 may be configured to extend to the pixel electrode 211 and expose the central portion of the pixel electrode 211. For example, the pixel defining layer 1170 may be configured to cover the edge of the pixel electrode 211 to include an opening OP1 extending to the pixel electrode 211 and exposing the central portion of the pixel electrode 211. For example, the pixel defining layer 1170 may be formed to define the opening OP1. The opening OP1 defined by the pixel defining layer 1170 may have a circular shape, and the diameter R of the circular shape of the opening OP1 may be from about 10 µm to about 30 µm, but this disclosure is not limited thereto.

[0145] The intermediate layer 231 may be disposed on the pixel electrode 211. For example, at least a portion of the intermediate layer 231 may overlap with the opening OP1.

[0146] The counter electrode 251 can be disposed on the intermediate layer 231. For example, the counter electrode 251 can be configured to face the pixel electrode 211 through the intermediate layer 231. The intermediate layer 231 can be disposed between the counter electrode 251 and the pixel electrode 211.

[0147] Counter electrode 251 can be disposed on intermediate layer 231 and pixel defining layer 1170. For example, counter electrode 251 can be formed to cover intermediate layer 231 and pixel defining layer 1170.

[0148] In an embodiment, the pixel defining layer 1170 may be a black pixel defining layer 1170. For example, the pixel defining layer 1170 may include a light-absorbing material or may include a black pigment or black dye. A pixel defining layer 1170 including a black pigment or black dye can achieve a black pixel defining layer 1170. When the pixel defining layer 1170 is formed, carbon black or the like can be used as a black pigment or black dye, but this disclosure is not limited thereto.

[0149] The pixel defining layer 1170 can be implemented as a black pixel defining layer 1170, and can absorb at least a portion of the light incident on the pixel defining layer 1170. This light can be external light or reflected light reflected from the counter electrode 251.

[0150] In this configuration, according to an embodiment, the polarizer may not be formed on the front surface of the display panel DP. Instead, the pixel defining layer 1170 may be formed of a black organic material, and the anti-reflective member 600 and the color filter layer CF may be formed above the pixel defining layer 1170. Accordingly, even when external light is incident inside the display panel DP, the external light can be reflected from the pixel electrode 211, etc., and therefore, the external light may not be transmitted to the user. In some embodiments, because no polarizer is formed, light from the emitting layer 231b (e.g., see...) is reflected. Figure 6 The emitted light is not partially absorbed by the polarizer, and therefore the brightness is not reduced. Thus, a display device 1 with a maximum brightness value of 2000 nits or more can be provided.

[0151] The pixel-limiting layer 1170 may include the trench portion OP2.

[0152] The trench portion OP2 can be formed in the pixel defining layer 1170 and can be recessed toward the pixel electrode 211. For example, the trench portion OP2 can be formed from the upper part of the pixel defining layer 1170 toward the pixel electrode 211 and downward (towards) the pixel electrode 211. Figure 7B and / or Figure 7C The groove portion OP2 is recessed in the direction opposite to the z-direction in the pixel definition layer 1170. In other words, the groove portion OP2 can be recessed in the pixel definition layer 1170 toward the pixel electrode 211.

[0153] The trench portion OP2 can be formed to overlap with at least a portion of the pixel electrode 211.

[0154] On the other hand, it can be stated that the trench portion OP2 is formed in the portion where the pixel electrode 211 does not overlap with the pixel defining layer 1170.

[0155] In one embodiment, the trench portion OP2 may be configured to expose at least a portion of the pixel electrode 211.

[0156] The pixel defining layer 1170 may include a first pixel defining layer 1171 and a second pixel defining layer 1172. For example, when the trench portion OP2 is formed to extend to the pixel electrode 211 and expose at least a portion of the pixel electrode 211, the first pixel defining layer 1171 and the second pixel defining layer 1172 may be divided based on the exposed portion of the pixel electrode 211 (e.g., the portion of the pixel electrode 211 to which the trench portion OP2 extends).

[0157] The first pixel limiting layer 1171 may refer to the portion disposed adjacent to the opening OP1. The second pixel limiting layer 1172 may refer to the portion disposed on the opposite side of the first pixel limiting layer 1171 relative to the groove portion OP2.

[0158] In this embodiment, the first pixel defining layer 1171 and the second pixel defining layer 1172 may be spaced apart from each other. For example, the first pixel defining layer 1171 and the second pixel defining layer 1172 may be spaced apart from each other by the exposed width of the pixel electrode 211.

[0159] The first pixel limiting layer 1171 may be included at the bottom ( Figure 7B and / or Figure 7C The first pixel defining layer 1171 has a proximal portion 1171a and a distal portion 1171b located at the bottommost end. The proximal portion 1171a of the first pixel defining layer 1171 may refer to the portion closest to the opening OP1 at the bottommost end. The distal portion 1171b of the first pixel defining layer 1171 may refer to the portion closest to the second pixel defining layer 1172 at the bottommost end. The second pixel defining layer 1172 may be included at the bottommost end (… Figure 7B The proximal portion 1172a at the bottommost end of (and / or 7C). The proximal portion 1172a of the second pixel limiting layer 1172 may refer to the portion at the bottommost end closest to the first pixel limiting layer 1171.

[0160] At this time, the distance W1 between the first pixel limiting layer 1171 and the second pixel limiting layer 1172 can refer to the distance between the far end portion 1171b of the first pixel limiting layer 1171 and the near end portion 1172a of the second pixel limiting layer 1172.

[0161] In other embodiments, the first pixel defining layer 1171 and the second pixel defining layer 1172 may be spaced apart from each other by about 2.0 μm to about 2.2 μm. For example, the first pixel defining layer 1171 and the second pixel defining layer 1172 may be spaced apart from each other by about 2.2 μm. For example, the distal portion 1171b of the first pixel defining layer 1171 and the proximal portion 1172a of the second pixel defining layer 1172 may be spaced apart from each other by about 2.0 μm to about 2.2 μm. For example, the distal portion 1171b of the first pixel defining layer 1171 and the proximal portion 1172a of the second pixel defining layer 1172 may be spaced apart from each other by about 2.2 μm.

[0162] When the distance W1 between the first pixel defining layer 1171 and the second pixel defining layer 1172 is 2.0 μm to 2.2 μm, process deviations can be optimized in the process of forming the trench portion OP2. For example, when the distance W1 between the first pixel defining layer 1171 and the second pixel defining layer 1172 is 2.0 μm to 2.2 μm, the tilt angle R2 of the trench portion OP2 of the first pixel defining layer 1171 can be formed to have an optimal angle, as described below.

[0163] In some embodiments, when the distance W1 between the first pixel defining layer 1171 and the second pixel defining layer 1172 is 2.0 μm to 2.2 μm, the effect of improving reflectivity brought about by the pixel defining layer 1170 can be significantly enhanced, as described below. For example, the specular reflection component (SCI) of light can be effectively reflected into the antireflective member 600.

[0164] When the distance W1 between the first pixel limiting layer 1171 and the second pixel limiting layer 1172 is less than 2.0 μm or greater than 2.2 μm, the process deviation may increase during the process of forming the trench portion OP2, or the SCI of light may not be effectively reflected into the antireflective member 600.

[0165] The color filter layer CF can be positioned adjacent to the anti-reflective component 600.

[0166] The color filter layer CF refers to a layer that has color to correspond to a plurality of pixels PX in the display device 1. For example, in the emission layer 231b (see, for example, see...) Figure 6 When emitting light of a specific color, the color filter layer CF can only allow light of that desired color to be emitted if the light of that desired color passes through it. The color to be emitted can be red, green, and / or blue.

[0167] Since the anti-reflective member 600 is positioned adjacent to the color filter layer CF, the anti-reflective member 600 can absorb colors other than those to be realized in the color filter layer CF, and thus can improve color purity and contrast.

[0168] In an embodiment, the pixel electrode 211 may be configured to overlap the entire area of ​​the first pixel defining layer 1171. For example, as Figure 7B and Figure 7C As illustrated in the figure, the pixel electrode 211 can make contact with the entire contact surface of the first pixel defining layer 1171. Alternatively, the first pixel defining layer 1171 can be formed on the pixel electrode 211.

[0169] In an embodiment, the pixel electrode 211 may be configured to overlap with at least a portion of the second pixel defining layer 1172. For example, the pixel electrode 211 may be configured to overlap with a portion of the second pixel defining layer 1172. Figure 7B and Figure 7C As illustrated in the figure, a portion of the pixel electrode 211 may be configured to overlap with the second pixel defining layer 1172. Alternatively, the second pixel defining layer 1172 may be formed to cover a portion of the perimeter of the pixel electrode 211.

[0170] The first pixel defining layer 1171 can be formed such that the width of the first pixel defining layer 1171 is in the direction away from the pixel electrode 211 ( Figure 7B and Figure 7C The shape narrows in the z-direction. For example, the first pixel defining layer 1171 can be roughly formed into a dome shape.

[0171] In some embodiments, the first pixel defining layer 1171 may not include flat portions. For example, all surfaces of the first pixel defining layer 1171 may be curved, except for the portions that come into contact with the pixel electrode 211.

[0172] In this case, since the light incident on the first pixel defining layer 1171 is reflected on the flat portion and emitted to the outside through the opening OP1, the problem of unintended light emission can be reduced.

[0173] In an embodiment, the slope of the portion of the first pixel defining layer 1171 adjacent to the opening OP1 (hereinafter referred to as the opening slope) may be greater than the slope of the portion of the first pixel defining layer 1171 adjacent to the second pixel defining layer 1172 (hereinafter referred to as the trench slope). For example, in the first pixel defining layer 1171, the tilt angle R1 of the opening slope may be greater than the tilt angle R2 of the trench slope.

[0174] In other embodiments, in the first pixel defining layer 1171, at the same height relative to the pixel electrode 211, the tilt angle R1 of the opening slope can always be greater than the tilt angle R2 of the trench slope.

[0175] In an embodiment, the first pixel defining layer 1171 can be formed such that the tilt angle is along the height direction ( Figure 7B and / or Figure 7C The shape changes in the z-direction. For example, at each height relative to the pixel electrode 211, the first pixel defining layer 1171 may have a different tilt angle.

[0176] In other embodiments, the tilt angle of the first pixel defining layer 1171 can be in a direction away from the pixel electrode 211 ( Figure 7B and / or Figure 7C The size gradually decreases in the z-direction. Correspondingly, the first pixel defining layer 1171 can have an upwardly convex shape, while the uppermost part is formed gently, such as... Figure 7B and / or Figure 7C As shown in the diagram.

[0177] In other embodiments, the first pixel defining layer 1171 may be formed such that the tilt angle R1 of the opening bevel is 30° to 45°. When the tilt angle R1 of the opening bevel of the first pixel defining layer 1171 is 30° to 45°, the SCI of light can be effectively reflected into the antireflective member 600, and therefore, the reflective characteristics of the pixel PX can be improved. When the tilt angle R1 of the opening bevel of the first pixel defining layer 1171 is less than 30°, the SCI of light may not be effectively reflected into the antireflective member 600, and therefore, the optical characteristics may not be improved. When the tilt angle R1 of the opening bevel of the first pixel defining layer 1171 is greater than 45°, a short circuit may occur in the electrode (e.g., counter electrode 251).

[0178] In other embodiments, the first pixel defining layer 1171 may be formed such that the tilt angle R2 of the trench ramp is between 11° and 45°. When the tilt angle R2 of the trench ramp of the first pixel defining layer 1171 is between 11° and 45°, the SCI of light can be effectively reflected into the anti-reflection member 600, and therefore, the reflective characteristics of the pixel PX can be improved. When the tilt angle R2 of the trench ramp of the first pixel defining layer 1171 is less than 11°, the SCI of light may not be effectively reflected into the anti-reflection member 600, and therefore, the optical characteristics may not be improved. When the tilt angle R2 of the trench ramp of the first pixel defining layer 1171 is greater than 45°, a short circuit may occur in the electrode (e.g., counter electrode 251).

[0179] In an embodiment, the display device 1 may further include an anti-reflective member 600 disposed on the counter electrode 251.

[0180] The anti-reflective member 600 can be disposed at at least one location in the display device 1 and performs the function of blocking light transmission through unintended portions. For example, the anti-reflective member 600 can prevent or reduce light leakage, in which light leaks from the display element layer DPL disposed within the display device 1 (e.g., see...). Figure 2 The light emitted by the display element is transmitted through the peripheral area PA of the display device 1. The anti-reflective member 600 may be referred to as a black matrix (BM) or a light leakage prevention member, but the anti-reflective member 600 is not limited to these terms or expressions.

[0181] The antireflective member 600 may include a light-absorbing material, or may include a black pigment or black dye. When the antireflective member 600 is formed, carbon black or the like may be used as a black pigment or black dye, but this disclosure is not limited thereto.

[0182] The anti-reflective member 600 can absorb at least a portion of the incident light. The incident light can be external light or reflected light reflected from the counter electrode 251.

[0183] In an embodiment, the anti-reflective member 600 may be disposed in the touch sensing layer 400 (e.g., see [link]). Figure 2 At this point, separate layers configured to perform different functions can be further disposed between the anti-reflective member 600 and the touch sensing layer 400.

[0184] The anti-reflective member 600 can be configured to overlap with the second pixel defining layer 1172 and extend in the direction toward the groove portion OP2.

[0185] In an embodiment, the anti-reflective member 600 may be configured to overlap with the entire area of ​​the pixel electrode 211 exposed through the trench portion OP2. For example, the anti-reflective member 600 may be configured to overlap with the entire area formed between the distal portion 1171b of the first pixel defining layer 1171 and the proximal portion 1172a of the second pixel defining layer 1172.

[0186] In other embodiments, the anti-reflective member 600 may be configured to extend further in a direction toward the opening OP1. For example, the anti-reflective member 600 may be configured to extend further in a direction from the distal portion 1171b of the first pixel defining layer 1171 toward the proximal portion 1171a. It may also be stated that the proximal portion 601 of the anti-reflective member 600 may be positioned closer to the opening OP1 than the distal portion 1171b of the first pixel defining layer 1171. Accordingly, at least a portion of the anti-reflective member 600 may be configured to overlap with the first pixel defining layer 1171.

[0187] In other embodiments, the width W2 of the region where the antireflective member 600 overlaps with the first pixel defining layer 1171 can be from 1.2 μm to 2.4 μm, and can be about 1.22 μm.

[0188] The configuration described above can significantly enhance the improved reflectivity effect brought about by the first pixel defining layer 1171. For example, as described below, external light or reflected light from the counter electrode 251 can be reflected on the first pixel defining layer 1171 and stably guided to the anti-reflection member 600. For example, if the width W2 of the region where the anti-reflection member 600 overlaps with the first pixel defining layer 1171 is less than 1.2 μm, the anti-reflection member 600 may not completely block the inclined surface of the second pixel defining layer 1172. Therefore, external light or reflected light from the counter electrode 251 may not be stably guided to the anti-reflection member 600. For example, if the width W2 of the region where the anti-reflection member 600 overlaps with the first pixel defining layer 1171 is greater than 2.4 μm, the anti-reflection member 600 may excessively cover the inclined surface of the second pixel defining layer 1172. Therefore, external light or reflected light from the counter electrode 251 may not be stably guided to the anti-reflection member 600.

[0189] In some embodiments, although errors may occur during the manufacturing process, the groove portion OP2 can still be formed into a shape with an optimized reflectivity improvement effect.

[0190] Furthermore, the reflectivity improvement effect brought about by the trench portion OP2 can be significantly enhanced. For example, as described below, external light or reflected light reflected from the counter electrode 251 can be reflected on the first pixel defining layer 1171 and stably guided to the anti-reflection member 600.

[0191] Refer again Figures 8A to 8D as well as Figure 9 The groove portion OP2 can be formed using photolithography.

[0192] Photomask M1 can be used to form the trench portion OP2.

[0193] The photomask M1 used to form the trench portion OP2 may include a full-tone dark area FTDKA and an opening area OPA. For example... Figure 8A As shown in the diagram, photomask M1 can be formed by alternating full-tone dark area FTDKA, aperture area OPA, and full-tone dark area FTDKA from the center of photomask M1.

[0194] Full-tone dark area (FTDKA) can refer to an area that prevents the overlapping area from being exposed to light by blocking light emitted during the photolithography process. Conversely, open area (OPA) can refer to an area that allows the overlapping area to be fully exposed to light by transmitting light emitted during the photolithography process.

[0195] The photomask M1 used to form the trench portion OP2 may have a full-tone dark region FTDKA disposed in the area corresponding to the opening OP1 and the trench portion OP2. For example, in a photolithography process, the photomask M1 can prevent the area corresponding to the opening OP1 and the trench portion OP2 from being exposed to light.

[0196] In other embodiments, the width W3 of the full-tone dark region FTDKA located at a position corresponding to the trench portion OP2 can be greater than the width of the pixel electrode 211 exposed through the trench portion OP2.

[0197] In other embodiments, the full-tone dark region FTDKA located at the position corresponding to the opening OP1 can overlap with the first pixel defining layer 1171 with a width W4.

[0198] Accordingly, although errors may occur during the process of forming the groove portion OP2, it is still possible to form the groove portion OP2 with an optimized reflectivity improvement effect.

[0199] In the planar view, the groove portion OP2 can have a circular or elliptical ring shape. Correspondingly, the first pixel defining layer 1171 can also have a circular or elliptical ring shape.

[0200] The first pixel defining layer 1171, the trench portion OP2, and the second pixel defining layer 1172 can be formed by photolithography. The photolithography process can be a positive photoresist (positive PR) process or a negative photoresist (negative PR) process.

[0201] Because the planar shape of the photomask M1 used in the photolithography process includes a circular ring shape or an elliptical ring shape, a groove portion OP2 and a first pixel defining layer 1171 whose planar shape includes a circular ring shape or an elliptical ring shape can be formed.

[0202] For example, Figure 8A This diagram illustrates a photomask M1 used to form a first pixel defining layer 1171 and a trench portion OP2, each having a ring shape in a planar view, when the photolithography process is a negative PR process. For example, the trench portion OP2 and the first pixel defining layer 1171 having a ring shape can be formed by using a photolithography process in which the full-tone dark region FTDKA has a ring shape and the opening region OPA has a ring shape. Figure 8C The illustration is created by using... Figure 8A The image shows a groove portion OP2 with a circular shape and a first pixel limiting layer 1171 with a circular shape formed by the photolithography process of photomask M1.

[0203] Figure 8B This diagram illustrates a photomask M1 used to form a first pixel defining layer 1171 and a trench portion OP2, each having an elliptical ring shape in a planar view, when the photolithography process is a negative PR process. For example, the trench portion OP2 and the first pixel defining layer 1171 having an elliptical ring shape can be formed by using a photolithography process in which the full-tone dark region FTDKA has an elliptical ring shape and the opening region OPA has an elliptical ring shape. Figure 8D The illustration is created by using... Figure 8B The image shows a groove portion OP2 with an elliptical ring shape formed by the photolithography process of photomask M1 and a first pixel limiting layer 1171 with an elliptical ring shape.

[0204] Figure 8E The results of performing diffraction and glare simulations on the light source in the following emission regions are shown: an emission region defined by a circular opening in a pixel-defining layer without a trench portion (reference group); an emission region defined by an elliptical opening in a pixel-defining layer without a trench portion (Case 1); an emission region defined by a circular opening in a pixel-defining layer with a trench portion (Case 2); or an emission region defined by an elliptical opening in a pixel-defining layer with a trench portion (Case 3). The circular or elliptical opening OP1 refers to the shape in the planar view. In some embodiments, when a circular opening OP1 is formed in the planar view and the pixel-defining layer 1170 includes a trench portion OP2, the trench portion OP2 has an annular shape in the planar view, and the first pixel-defining layer 1171 has an annular shape in the planar view. In some embodiments, when an elliptical opening OP1 is formed in the planar view and the pixel-defining layer 1170 includes a trench portion OP2, the trench portion OP2 has an elliptical annular shape in the planar view, and the first pixel-defining layer 1171 has an elliptical annular shape in the planar view.

[0205] For example, Figure 8E The comparison result in the figure represents the relative light intensity as the relative distance from the light source, expressed in angles, increases in the display device 1. The relative distance from the light source, expressed in angles, refers to the ratio of the tangents of that angle. For example, the ratio of 10° and 15° with respect to the distance from the light source is the ratio of tan(10°) and tan(15°).

[0206] Within the emission region defined by the elliptical opening OP1, diffraction of the light source can be reduced when the relative distance is 10° to 15°.

[0207] For example, as a result of the simulation, a comparison between the reference group and Case 1 confirms that when the relative distance to the light source is 10° to 15°, the diffraction of the light source can be reduced in the emission region defined by the elliptical opening OP1 compared to the emission region defined by the circular opening OP1.

[0208] When comparing Figure 8E In the reference group and Case 1, when the relative distance from the light source is 10° to 15°, the maximum relative light intensity is 2.56 and the minimum relative light intensity is 0.59. Correspondingly, the difference between the maximum and minimum relative light intensity (i.e., peak-to-peak) is 1.86. However, in Case 1, when the relative distance from the light source is 10° to 15°, the maximum relative light intensity is 2.34 and the minimum relative light intensity is 0.92. Correspondingly, the difference between the maximum and minimum relative light intensity (i.e., peak-to-peak) is reduced to 1.41.

[0209] Therefore, in Case 1, it can be confirmed that, compared with the reference group, diffraction towards the light source is reduced when the relative distance to the light source is 10° to 15°.

[0210] Similarly, a comparison between Case 2 and Case 3 confirms that when the relative distance to the light source is 10° to 15°, the diffraction of the light source can be reduced in the emission region defined by the elliptical opening OP1 compared to the emission region defined by the circular opening OP1.

[0211] When comparing Figure 8E In Cases 2 and 3, in Case 2, when the relative distance from the light source is 10° to 15°, the maximum relative light intensity is 2.66 and the minimum relative light intensity is 0.90. Correspondingly, the difference between the maximum and minimum relative light intensity (i.e., peak-to-peak) is 1.76. However, in Case 3, when the relative distance from the light source is 10° to 15°, the maximum relative light intensity is 2.20 and the minimum relative light intensity is 1.07. Correspondingly, the difference between the maximum and minimum relative light intensity (i.e., peak-to-peak) is reduced to 1.14.

[0212] Therefore, in Case 3, it can be confirmed that, compared to Case 2, when the relative distance to the light source is 10° to 15°, diffraction toward the light source is reduced.

[0213] In some embodiments, reference Figure 8EAs can be seen, compared with the case where the pixel limiting layer with the groove portion OP2 is not formed (reference group and case 1), the glare is reduced in the case where the pixel limiting layer with the groove portion OP2 is formed (case 2 and case 3).

[0214] Specifically, when the relative distance to the light source is less than 10°, the relative light intensity is reduced in Case 2 compared to the reference group. This means that glare is reduced.

[0215] When the relative distance to the light source is less than 10°, the relative light intensity is reduced in Case 3 compared to Case 1. This means that glare is reduced.

[0216] Therefore, compared with the display device 1 which includes a circular pixel limiting layer 1170 in which no groove portion OP2 is formed, the display device 1 which includes an elliptical pixel limiting layer 1170 in which the groove portion OP2 is formed can have the effect of reducing glare when the relative distance to the light source is 10° or less, and can have the effect of reducing the diffraction of the light source when the relative distance to the light source is 10° to 15°.

[0217] Figure 8F This is a diagram illustrating the distance between adjacent trench portions according to an embodiment. Figure 8G It is a diagram. Figure 8F The second pixel defining layer between adjacent trench portions in the image is removed. Figure 8H This is a diagram illustrating an embodiment where there is no second pixel defining layer between adjacent trench portions. Figure 8I This is a diagram illustrating the groove portion and the transmission opening according to an embodiment. Figure 8J It is a diagram. Figure 8I A cross-sectional view of an example of section VI-VI'. Figure 8K It is a diagram. Figure 8I The image shows the second pixel defining layer between the groove portion and the transmission opening being removed. Figure 8L This is a diagram illustrating an embodiment where there is no second pixel defining layer between the transmission opening and the groove portion. Figure 8M It is a diagram and Figure 8L The image shows the second pixel-defining layer near the transmission opening being removed. Figure 8N It is a diagram and Figure 8L Another image shows the second pixel-defining layer near the transmission opening being removed.

[0218] refer to Figures 8F to 8N In the display device 1 according to the embodiment, the distance L1 between the groove portions OP2 of adjacent pixels PX can be greater than 5.2 μm.

[0219] In the display device 1 according to the embodiment, the distance between adjacent groove portions OP2 can vary depending on the resolution.

[0220] For example, when the resolution of the display device 1 according to the embodiment is less than 500 ppi, the distance L1 between adjacent groove portions OP2 can be greater than about 5.2 μm; when the resolution of the display device 1 according to the embodiment is about 500 ppi, the distance L1 between adjacent groove portions OP2 can be about 5.2 μm; and when the resolution of the display device 1 according to the embodiment is greater than about 500 ppi, the distance L1 between adjacent groove portions OP2 can be less than about 5.2 μm.

[0221] In some embodiments, the distances L1 and L3 between the groove portions OP2 of adjacent pixels PX in the display device 1 according to the embodiment are less than 5.2 μm, and the second pixel defining layer 1172 existing between adjacent groove portions OP2 can be removed, and the connecting portions P1 and P3 connecting adjacent groove portions OP2 can be included.

[0222] For example, when the distance L1 between adjacent trench portions OP2 in the display device 1 according to the embodiment is about 5.2 μm or less, the second pixel defining layer 1172 existing between adjacent trench portions OP2 can be removed, and a first connecting portion P1 connecting adjacent trench portions OP2 can be included (see Figure 8G ).

[0223] In some embodiments, in the display device 1 according to the embodiment, the width of the groove portion OP2 may be increased such that there is no second pixel defining layer 1172 between adjacent groove portions OP2 (see Figure 8H ).

[0224] The display device 1 according to an embodiment may include a transmission opening OP3. The transmission opening OP3 refers to a region on the second insulating layer 116 that does not overlap with the pixel defining layer 1170 and the anti-reflective member 600 in a plan view. The counter electrode 251 and the encapsulation member 300 may be disposed on the transmission opening OP3. Light generated from the optical element can be transmitted through the transmission opening OP3 and emitted to the outside of the display device 1 through the first component region EA1. In this case, the transmission opening OP3 may exist between the trench portions OP2 of adjacent pixels PX.

[0225] In the display device 1 including the transmission opening OP3, according to an embodiment, the distance L2 between the transmission opening OP3 and the adjacent groove portion OP2 and the distance L3 between the adjacent groove portions OP2 can vary depending on the resolution.

[0226] For example, when the resolution of the display device 1 according to the embodiment is less than about 500 ppi, the distance L2 between the transmission opening OP3 and the trench portion OP2 can be greater than about 5.2 μm. When the resolution of the display device 1 according to the embodiment is about 500 ppi, the distance L2 between the transmission opening OP3 and the trench portion OP2 can be less than about 5.2 μm. And when the resolution of the display device 1 according to the embodiment is about 500 ppi or more, the second pixel limiting layer 1172 may not exist between the transmission opening OP3 and the trench portion OP2.

[0227] In the display device 1 including the transmission aperture OP3, according to an embodiment, when the distance L2 between the transmission aperture OP3 and the trench portion OP2 is about 5.2 μm or less, the second pixel defining layer 1172 existing between the transmission aperture OP3 and the trench portion OP2 can be removed, and a second connecting portion P2 connecting the adjacent transmission aperture OP3 to the trench portion OP2 can be included (see...). Figure 8K ).

[0228] In some embodiments, according to the embodiment, in the display device 1 including the transmissive opening OP3, when the distance L3 between adjacent trench portions OP2 is about 5.2 μm or less, the second pixel defining layer 1172 may not exist between the transmissive opening OP3 and the trench portion OP2 (see...). Figure 8L ).

[0229] In some embodiments, according to an example, in a display device 1 including a transmissive opening OP3, when the distance L3 between adjacent trench portions OP2 is about 5.2 μm or less, the second pixel defining layer 1172 existing between adjacent trench portions OP2 can be removed, and a third connecting portion P3 connecting adjacent trench portions OP2 can be included (see...). Figure 8M ).

[0230] In some embodiments, according to the embodiment, in the display device 1 including the transmissive opening OP3, the width of the groove portion OP2 can be enlarged such that there is no second pixel defining layer between adjacent groove portions OP2 (see...). Figure 8N ).

[0231] Figure 10A This is a diagram used to describe the pixel defining layer 1170 formed thereon on the capping layer 700 according to an embodiment. Figure 10B This is another diagram used to describe the pixel defining layer 1170 formed thereon on the capping layer 700 according to an embodiment. Figure 10C It is a schematic diagram used to form Figure 10A or Figure 10B A diagram of an embodiment of a photomask with a capping layer 700. Figure 10DIt is used to describe the formation Figure 10A or Figure 10B The process of the 700 capping layer and Figure 10C The diagram of section III-III".

[0232] For example, Figure 10A It can be a schematic diagram. Figure 7A An example cross-sectional view of section IV-IV', and Figure 10B It can be a schematic diagram. Figure 7A A cross-sectional view of an example of the V-V' section.

[0233] In the following text, for ease of explanation, content that is the same as the content provided above or that can be readily applied by those skilled in the art is omitted or briefly described.

[0234] refer to Figures 10A to 10D The capping layer 700 can be further provided on the trench portion OP2.

[0235] The capping layer 700 can be formed on the trench portion OP2. For example, the capping layer 700 can be formed to cover at least a portion of the trench portion OP2.

[0236] In an embodiment, the capping layer 700 may cover the entire area of ​​the pixel electrode 211 exposed through the trench portion OP2. For example, the capping layer 700 may cover the entire area of ​​the pixel electrode 211 exposed through the trench portion OP2, thereby substantially preventing the pixel electrode 211 from being exposed to the outside.

[0237] In an embodiment, the capping layer 700 may also be formed on the second pixel defining layer 1172. For example, the capping layer 700 may be formed to cover at least a portion of the second pixel defining layer 1172. Figure 10A or Figure 10B It can be confirmed that the capping layer 700 is formed to cover the trench portion OP2 and the second pixel defining layer 1172. In an embodiment, the capping layer 700 may be configured to cover the uppermost end of the second pixel defining layer 1172.

[0238] In one embodiment, the capping layer 700 may include a material different from that of the pixel defining layer 1170. In other embodiments, the capping layer 700 may include the same material as the spacer. In other embodiments, the capping layer 700 may include PI.

[0239] Accordingly, in the case of forming the trench portion OP2 in the photolithography process as described below, the pattern structure of the trench portion OP2 can be formed regularly according to the exposure sensitivity, and the tilt angle of the trench portion OP2 can be formed optimally.

[0240] In one embodiment, at least a portion of the capping layer 700 may be formed to overlap with the first pixel defining layer 1171. In another embodiment, the capping layer 700 may be configured not to cover the uppermost part of the first pixel defining layer 1171.

[0241] In other embodiments, the width W5 of the region where the capping layer 700 overlaps with the first pixel defining layer 1171 can be greater than 0 μm and less than or equal to 2.0 μm. For example, the width W5 can be 1.0 μm. When the width W5 of the region where the capping layer 700 overlaps with the first pixel defining layer 1171 is greater than 2.0 μm, the light L (e.g., see...) Figure 12 The SCI of light L is not reduced. Consequently, the SCI of light L may not be effectively reflected into the antireflective member 600. For example, if the width W5 of the region where the capping layer 700 overlaps with the first pixel defining layer 1171 is greater than 2.0 μm, the thickness H1 of the capping layer 700, as described below, may be excessively increased, and therefore, the tilt angle R1 of the opening bevel and the tilt angle R2 of the trench bevel may have values ​​that do not help improve optical properties.

[0242] In other embodiments, the thickness H1 of the capping layer 700 can be from about 0.4 μm to about 0.8 μm. The thickness H1 of the capping layer 700 can refer to the thickness from the exposed portion of the pixel electrode 211 in the vertical direction ( Figure 1 The thickness (in the z-direction) of the capping layer 700 is described below. The improvement in optical properties is based on the thickness H1 of the capping layer 700.

[0243] Due to the configuration described above, the capping layer 700 can prevent or reduce the problem of dark spots caused by the trench portion OP2. The capping layer 700 can also protect the pixel electrode 211 exposed through the trench portion OP2.

[0244] Refer again Figure 10C and Figure 10D The capping layer 700 can be formed using photolithography.

[0245] Photomask M2 can be used to form capping layer 700.

[0246] The photomask M2 used to form the capping layer 700 may include a halftone dark area HTDKA and an opening area OPA. For example... Figure 10C As shown in the diagram, photomask M2 may have an opening region OPA and a halftone dark region HTDKA formed from the center of photomask M2.

[0247] Halftone dark area (HTDKA) can refer to a region that reduces exposure in the overlapping area by blocking a portion of the light emitted during the photolithography process. Conversely, open area (OPA) can refer to a region that allows the overlapping area to be fully exposed to light by transmitting light emitted during the photolithography process.

[0248] The photomask M2 used to form the capping layer 700 can be formed such that the halftone dark region HTDKA extends outward from the region corresponding to a portion of the first pixel defining layer 1171. Due to the photomask M2, portions of the first pixel defining layer 1171 and the second pixel defining layer 1172 may be relatively weakly exposed to light during the photolithography process due to a portion of the light used in the photolithography process.

[0249] In other embodiments, the halftone dark region HTDKA can extend further toward the opening OP1 than the region where the capping layer 700 is formed on the first pixel defining layer 1171. Figure 10D In the middle, the halftone dark area HTDKA can extend further to the left from the left boundary of the capping layer 700 (in the direction toward the opening OP1).

[0250] Correspondingly, although errors may occur in the process of forming the capping layer 700, a capping layer 700 with improved dark spot improvement effect can still be formed.

[0251] Figure 11A This is a diagram used to describe the pixel defining layer 1170 formed thereon on the isolator S according to an embodiment. Figure 11B This is a schematic diagram illustrating the process of forming an isolator S in the pixel defining layer 1170 according to an embodiment. Figure 11C This is a photograph of the isolator S formed in the pixel-defining layer 1170 according to an embodiment.

[0252] refer to Figures 11A to 11C According to an embodiment, the pixel defining layer 1170 may include an isolator S recessed in the pixel defining layer 1170. For example, the second pixel defining layer 1172 may include an isolator S recessed in the second pixel defining layer 1172.

[0253] Counter electrode 251 may be disposed on pixel defining layer 1170. For example, counter electrode 251 may be formed on the entire pixel defining layer 1170 and extend toward the first pixel defining layer 1171, the trench portion OP2 and the second pixel defining layer 1172.

[0254] The isolator S can prevent lateral leakage current between adjacent pixels PX by short-circuiting the adjacent counter electrode 251. The adjacent counter electrode 251 can have a shape that is disconnected relative to the isolator S.

[0255] The first depth SD of the isolator S can be from about 0.3µm to about 0.7µm. For example, the first depth SD of the isolator S can be about 0.5µm. The first depth SD of the isolator S refers to the vertical distance recessed when the isolator S is formed in the pixel defining layer 1170.

[0256] When the first depth SD of the isolator S is between 0.3µm and 0.7µm, the lateral leakage current prevention effect of the isolator S can be excellent. When the first depth SD of the isolator S is less than 0.3µm, the lateral leakage current prevention effect of the isolator S may not be excellent, and when the first depth SD of the isolator S is greater than 0.7µm, the electrical characteristics of the display device 1 may deteriorate.

[0257] The isolator S may include an isolator length portion SL that is recessed into the pixel defining layer 1170 and is substantially flat.

[0258] In this case, the angle SA formed between the isolation length portion SL and the adjacent pixel-defining layer 1170 can be approximately 70º to approximately 85º.

[0259] When the angle SA formed between the length portion SL of the isolator and the adjacent pixel-defining layer 1170 is less than 70º, the lateral leakage current prevention effect of the isolator S may not be excellent.

[0260] refer to Figure 11B The isolator S can be formed in the pixel defining layer 1170 by the following steps: forming a metal layer M (e.g., indium gallium zinc oxide (IGZO)) on the pixel defining layer 1170 (operation a); applying a photoresist PR on the metal layer M (operation b); etching a portion of the metal layer M by a photolithography process (operation c); removing the photoresist PR (operation d); forming the isolator S by performing an etching process on the pixel defining layer 1170 (operation e); and removing the metal layer M by performing etching on the metal layer M (operation f). The etching in operation c and / or operation f can be wet etching, and the etching in operation e can be dry etching.

[0261] In this scenario, when operations d through f are performed, strip damage may occur in the length portion SL of the isolator, and the roughness of the length portion SL may increase. With the increased roughness of the length portion SL, adjacent counter electrodes 251 may not be completely short-circuited, and therefore, the lateral leakage current prevention effect between adjacent pixels PX may deteriorate.

[0262] According to an embodiment, an isolator S can be formed in the pixel defining layer 1170 after the capping layer 700 is formed on the pixel defining layer 1170. For example, the second pixel defining layer 1172 may include an isolator S recessed into the second pixel defining layer 1172, the capping layer 700 may be formed to extend from the trench portion OP2 and cover the isolator S, and subsequently, during the execution Figure 11B During operations a through f, the pixel defining layer 1170 can form an isolator S. In this case, when the portion of the capping layer 700 formed on the second pixel defining layer 1172 is removed, an isolator S recessed into the second pixel defining layer 1172 can be formed.

[0263] In this case, the second depth SD' of the isolator S can be about 0.3µm to about 0.7µm. For example, the second depth SD' of the isolator S can be about 0.5µm. The second depth SD' of the isolator S refers to the vertical distance recessed when the isolator S is formed in the pixel defining layer 1170 on which the capping layer 700 is formed.

[0264] When the second depth SD' of the isolator S is between 0.3µm and 0.7µm, the lateral leakage current prevention effect of the isolator S can be excellent. When the second depth SD' of the isolator S is less than 0.3µm, the lateral leakage current prevention effect of the isolator S may not be excellent, and when the second depth SD' of the isolator S is greater than 0.7µm, the electrical characteristics of the display device 1 may deteriorate.

[0265] In this case, the counter electrode 251 can be formed on the intermediate layer 231 and the isolator S. For example, when the capping layer 700 is formed on the pixel defining layer 1170 and then the isolator S is formed, the intermediate layer 231 can be formed on the capping layer 700, while extending from the first pixel defining layer 1171 on which the capping layer 700 is not formed toward the second pixel defining layer 1172, and the counter electrode 251 can be formed on all or part of the intermediate layer 231, and can also be formed on the isolator S.

[0266] According to the embodiment, when the capping layer 700 is formed on the pixel defining layer 1170 and then the isolator S is formed, the roughness of the length portion SL of the isolator can be reduced, and the adjacent counter electrode 251 is short-circuited, which can improve the lateral leakage current prevention effect.

[0267] Figure 11C This is a photograph of the isolator S formed in the pixel-defining layer 1170 according to an embodiment. Specifically, Figure 11C A is a photograph taken in which a capping layer 700 is formed on a pixel-limiting layer 1170 and subsequently an isolator S is formed. Figure 11C b and Figure 11C c is a photograph taken when an isolator S is formed on the pixel-limiting layer 1170 on which the capping layer 700 is not formed.

[0268] refer to Figure 11C It can be confirmed that, compared to the case where the isolator S is formed on the pixel limiting layer 1170 on which the capping layer 700 is not formed, the roughness of the length portion SL of the isolator is further reduced when the isolator S is formed on the pixel limiting layer 1170 on which the capping layer 700 is formed.

[0269] Accordingly, when the insulator S is formed on the pixel limiting layer 1170 on which the capping layer 700 is formed, the adjacent counter electrode 251 is short-circuited, which can improve the effect of preventing lateral leakage current.

[0270] Figure 12 It is a diagram used to describe the reflection path of light L in a display device according to the present disclosure. Figure 13A and Figure 13B It is used to describe Figure 12 A photograph showing the effect of improved optical properties in a display device. Figure 13A This is a photograph of the reflected light from light L without forming the groove portion OP2, and Figure 13B This is a photograph of the reflected light from light L when the groove portion OP2 is formed.

[0271] refer to Figure 12 Light L incident on the pixel defining layer 1170 can be reflected from the pixel defining layer 1170 and then guided to the anti-reflection member 600. For example, light L incident on the first pixel defining layer 1171 can be reflected from the first pixel defining layer 1171 and then guided to the anti-reflection member 600. Although not illustrated, as described above, the counter electrode 251 can be disposed on at least a portion of the pixel defining layer 1170. In this case, light L incident on the counter electrode 251 can be reflected from the counter electrode 251 and then guided to the anti-reflection member 600. For example, light L incident on the counter electrode 251 can be reflected from the counter electrode 251 and then guided to the anti-reflection member 600.

[0272] The light L incident on the pixel defining layer 1170 or the counter electrode 251 may include external light or reflected light reflected from the counter electrode 251.

[0273] refer to Figure 12Light L incident on the pixel defining layer 1170 can be reflected from the counter electrode 251. At this time, the light L that is specularly reflected in the flat region of the counter electrode 251 can be defined as including a specular reflection component (SCI), and the light L that is diffusely reflected in the curved region of the counter electrode 251 can be defined as excluding a specular reflection component (SCE).

[0274] In this case, such as Figure 13A As illustrated in the diagram, when the reflected light includes a large amount of SCI in light L, unintended output light may be displayed externally. For example, when the pixel-defining layer 1170 has a flat region, a portion of the light L can be specularly reflected from the flat region and emitted externally, which may result in halos or diffraction patterns, such as... Figure 13A As shown in the diagram.

[0275] Conversely, since the pixel defining layer 1170 includes a trench portion OP2 and therefore does not have a flat area, a large portion of the light L incident on the pixel defining layer 1170 can be diffusely reflected and guided to the anti-reflection member 600. Accordingly, the SCI of the light L emitted by the pixel PX can be reduced, which can improve the optical characteristics of the display device 1. For example, as... Figure 13B As illustrated in the diagram, the problem of unexpected output light being displayed externally can be solved by reducing the SCI of light L, and the optical properties can be improved.

[0276] Figures 14A to 14C This is a diagram illustrating an embodiment of a display device according to the present disclosure, wherein the anti-reflective element is removed.

[0277] refer to Figures 14A to 14C In the display device according to this disclosure, the anti-reflective member 600 (for example, see...) Figure 12 ) can be removed.

[0278] The first color filter CF1 can be a blue color filter CF, the second color filter CF2 can be a red color filter CF, and the third color filter CF3 can be a green color filter CF. Color filters CF1, CF2, and CF3 of different colors can be stacked to function as an anti-reflective component 600.

[0279] For example, light L incident on the pixel defining layer 1170 can be reflected from the pixel defining layer 1170 and then guided to the area where the first color filter CF1 and the second color filter CF2 overlap. The area where the first color filter CF1 and the second color filter CF2 overlap can function as an anti-reflection member 600.

[0280] When the first color filter CF1, the second color filter CF2, and the third color filter CF3 are respectively blue, red, and green color filters CF, and the intermediate layer 231 emits blue light, multiple color filters CF1, CF2, and CF3 can be used as follows: Figure 14A The stacking is illustrated in the diagram. With the intermediate layer 231 emitting red light, multiple color filters CF1, CF2, and CF3 can be used as shown... Figure 14B The stacking is illustrated in the diagram. When the intermediate layer 231 emits green light, multiple color filters CF1, CF2, and CF3 can be used as shown... Figure 14C The stacking shown in the diagram.

[0281] In some embodiments, the width W6 of the region where the second color filter CF2 overlaps with the first pixel defining layer 1171 can be wider than the width W5 of the region where the capping layer 700 overlaps with the first pixel defining layer 1171 (see...). Figure 14A The width W7 of the area where the first color filter CF1 overlaps with the first pixel defining layer 1171 can be wider than the width W5 of the area where the capping layer 700 overlaps with the first pixel defining layer 1171 (see...). Figure 14B The width W8 of the area where the first color filter CF1 overlaps with the first pixel defining layer 1171 can be wider than the width W5 of the area where the capping layer 700 overlaps with the first pixel defining layer 1171 (see...). Figure 14C ).

[0282] When the width W6, W7, or W8 of the region where the first color filter CF1 or the second color filter CF2 overlaps with the first pixel defining layer 1171 is wider than the width W5 of the region where the capping layer 700 overlaps with the first pixel defining layer 1171, even taking into account the tolerances when forming multiple color filters CF1, CF2, and CF3, light L incident on the pixel defining layer 1170 can be reflected from the pixel defining layer 1170 and subsequently guided to the region where the first color filter CF1 and the second color filter CF2 overlap. Accordingly, the region where the first color filter CF1 and the second color filter CF2 overlap can function as an anti-reflection member 600.

[0283] Figure 15 and Figure 16 This is a table used to describe the effect of improving optical properties based on the thickness of the capping layer. Figure 15 It is a table that combines the reflection image, the light tracing image, and the reflection intensity (Y) of the SCI based on the thickness of the capping layer. Figure 16 It is a table that combines halo analysis images and diffraction analysis images based on the thickness of the capping layer.

[0284] Refer to 15, at capping layer 700 (e.g., see...) Figure 11A When the thickness H1 of the light source is 0 μm, it can be confirmed that the light source L (for example, see...) Figure 12The SCI increases, and an image caused by the SCI is formed outside the reflected image. The statement "the thickness H1 of the capping layer 700 is 0 μm" could mean that the capping layer 700 is not formed. This could mean that a portion of the pixel electrode 211 is completely exposed. Furthermore, refer to... Figure 15 Based on the reflection image, it can be confirmed that as the thickness H1 of the capping layer 700 decreases, the image becomes blurred due to SCI (Surface Acceptance). This implies that the SCI is reduced. It can be confirmed that when the thickness H1 of the capping layer 700 is below 0.8 μm, the image becomes significantly blurred due to SCI. When the thickness H1 of the capping layer 700 is less than 0.4 μm, considering process variations, a portion of the pixel electrode 211 may still be completely exposed. Therefore, the thickness H1 of the capping layer 700 can be greater than 0.4 μm. (Reference) Figure 15 The optical tracking images confirm that when the thickness H1 of the capping layer 700 is 0 μm or greater than 0.8 μm, a considerable amount of reflected light is reflected upwards by the mirror surface.

[0285] In addition, refer to Figure 15 The reflection intensity (Y) of the SCI was confirmed to be reduced when the thickness H1 of the capping layer 700 was less than 0.8 μm, compared to when the thickness H1 of the capping layer 700 was 0 μm or greater than 0.8 μm.

[0286] refer to Figure 16 Optical analysis of the images confirms that as the thickness H1 of the capping layer 700 decreases, the halo becomes wider, and the intensity of the light forming the halo weakens and becomes blurred. For example, it can be confirmed that when the thickness H1 of the capping layer 700 is greater than 0.85 μm, the halo is densely formed in the central portion, and the intensity of the corresponding portion becomes stronger and clearer. This could mean that unintended light L is exposed to the outside, leading to a deterioration in optical properties.

[0287] In addition, refer to Figure 16 The diffraction analysis images confirm that as the thickness H1 of the capping layer 700 decreases, the diffraction pattern becomes wider, and the intensity of the light forming the diffraction pattern weakens and becomes blurred. For example, it can be confirmed that when the thickness H1 of the capping layer 700 is greater than 0.85 μm, the diffraction pattern is formed more densely, and the intensity of the corresponding portion becomes stronger and clearer. This could mean that unintended light L is exposed to the outside, leading to a deterioration in optical properties.

[0288] Figure 17 This is a flowchart of a method for manufacturing a display device according to an embodiment.

[0289] In the following text, for ease of explanation, content that is the same as that provided above or that can be readily applied by those skilled in the art is omitted or briefly described.

[0290] refer to Figures 1 to 17 The method of manufacturing the display device 1 according to the embodiment may include preparing a substrate 100, forming a pixel electrode 211 and forming a pixel defining layer 1170.

[0291] The preparation of substrate 100 (operation S10) may include the preparation of substrate 100 comprising glass material or polymer resin.

[0292] The formation of pixel electrode 211 (operation S20) may include forming pixel electrode 211 on substrate 100. For example, the formation of pixel electrode 211 (operation S20) may include forming pixel layer PXL on substrate 100.

[0293] Between the fabrication of substrate 100 (operation S10) and the formation of pixel electrode 211 (operation S20), the method may further include forming various layers between substrate 100 and pixel electrode 211.

[0294] The formation of the pixel defining layer 1170 (operation S30) may include forming a pixel defining layer 1170 that overlaps at least a portion of the pixel electrode 211. The pixel defining layer 1170 may be formed having an opening OP1 that exposes the central portion of the pixel electrode 211.

[0295] The formation of the pixel-defining layer 1170 (operation S30) may include forming the trench portion OP2.

[0296] The formation of the trench portion OP2 may include: forming a trench portion OP2 that is recessed in the direction toward the pixel electrode 211 at a position that overlaps with at least a portion of the pixel electrode 211 that is spaced apart from the central portion.

[0297] The formation of the trench portion OP2 can be performed using a photomask.

[0298] For example, the formation of the trench portion OP2 can be performed by using a photomask in which a full-tone dark region FTDKA is formed at the location overlapping with the trench portion OP2.

[0299] In other embodiments, the trench portion OP2 can be formed using the above references. Figure 8A and Figure 8B The described photomask M1 is used to perform this.

[0300] In an embodiment, the method of manufacturing display device 1 according to the present disclosure may further include forming a cover layer 700 (operation S40).

[0301] The formation of the capping layer 700 (operation S40) may include forming the capping layer 700 on the trench portion OP2.

[0302] In one embodiment, forming the capping layer 700 (operation S40) may include forming the capping layer 700 to cover the entire area of ​​the pixel electrode 211 exposed through the trench portion OP2. In another embodiment, forming the capping layer 700 (operation S40) may include forming the capping layer 700 to cover at least a portion of the second pixel defining layer 1172.

[0303] For example, the formation of the capping layer 700 (operation S40) can be performed by using a photomask that includes a halftone dark area HTDKA.

[0304] In other embodiments, the formation of the capping layer 700 (operation S40) can be achieved using the above references. Figure 10C The described photomask M2 is used to perform this.

[0305] Figure 18 This is a block diagram of an example of an electronic device 1000 according to an embodiment.

[0306] refer to Figure 18 The electronic device 1000 can output various information through the display device 1 within the operating system. The display device 1 can be... Figures 1 to 14C The diagram is shown and referenced. Figures 1 to 14C The described display device. When the processor 1100 executes an application stored in the memory 1200, the display device 1 can provide application information to the user via the display panel DP.

[0307] The processor 1100 can obtain external input through the input module 1300 or the sensor module 1610, and execute an application corresponding to the external input. For example, when a user selects the camera icon displayed on the display panel DP, the processor 1100 can obtain user input through the input sensor 1610-2 and activate the camera module 1710. The processor 1100 can transmit image data corresponding to the captured image obtained by the camera module 1710 to the display device 1. The display device 1 can display the image corresponding to the captured image on the display panel DP.

[0308] As another example, when performing personal information authentication on display device 1, fingerprint sensor 1610-1 can obtain input fingerprint information as input data. Processor 1100 can compare the input data obtained by fingerprint sensor 1610-1 with authentication data stored in memory 1200, and execute the application based on the comparison result. Display device 1 can display the information obtained according to the application logic on display panel DP.

[0309] As another example, when a user selects a music stream icon displayed on display device 1, processor 1100 obtains user input via input sensor 1610-2 and activates the music stream application stored in memory 1200. When a music execution command is input into the music stream application, processor 1100 can activate audio output module 1630 to provide the user with audio information corresponding to the music execution command.

[0310] The operation of the electronic device 1000 has been briefly described. The configuration of the electronic device 1000 is described in detail below. Some components of the electronic device 1000 described below can be integrated and provided as a single component, and a single component can be divided into two or more components.

[0311] refer to Figure 18 Electronic device 1000 can communicate with external electronic device 1020 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to an embodiment, electronic device 1000 may include a processor 1100, a memory 1200, an input module 1300, a display device 1, a power module 1500, an internal module 1600, and an external module 1700. According to an embodiment, at least one of the components described above may be omitted from electronic device 1000, or one or more other components may be added to electronic device 1000. According to an embodiment, some of the components described above (e.g., sensor module 1610, antenna module 1620, or audio output module 1630) may be integrated into another component (e.g., display device 1).

[0312] The processor 1100 can execute software to control at least one other component (e.g., hardware or software component) of the electronic device 1000 connected to the processor 1100, and perform various data processing or operations. According to an embodiment, as at least part of the data processing or operation, the processor 1100 can store commands or data received from another component (e.g., input module 1300, sensor module 1610, or communication module 1730) in volatile memory 1210, process the commands or data stored in volatile memory 1210, and store the result data in non-volatile memory 1220.

[0313] Processor 1100 may include one or more processors, and may include a main processor 1110 and an auxiliary processor 1120. Main processor 1110 may include at least one of a central processing unit (CPU) 1111 and an application processor (AP). Main processor 1110 may further include at least one of a graphics processing unit (GPU) 1112, a communication processor (CP), and an image signal processor (ISP). Main processor 1110 may further include a neural processing unit (NPU) 1113. NPU 1113 is a processor specifically designed to process artificial intelligence models. Artificial intelligence models can be generated through machine learning. Artificial intelligence models may include multiple layers of artificial neural networks. Artificial intelligence models may be deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), deep Q-networks, or combinations of two or more of these, but this disclosure is not limited to the examples above. In addition to hardware architecture, artificial intelligence models may also additionally or alternatively include software architecture. At least two of the processing units and processors described above can be implemented as a single integrated configuration (e.g., a single chip), or the processing units and processors described above can be implemented as independent configurations (e.g., multiple chips).

[0314] The auxiliary processor 1120 may include a controller 1120-1. The controller 1120-1 may include an interface conversion circuit and a timing control circuit. The controller 1120-1 can receive image signals from the main processor 1110, convert the data format of the image signals to match the interface specifications of the display device 1, and output image data. The controller 1120-1 can output various control signals required to drive the display device 1.

[0315] The auxiliary processor 1120 may further include a data conversion circuit 1120-2, a gamma correction circuit 1120-3, or a rendering circuit 1120-4, etc. The data conversion circuit 1120-2 can receive image data from the controller 1120-1 and compensate the image data according to the characteristics of the electronic device 1000 or user settings so that the image is displayed with the desired brightness, or convert the image data to reduce power consumption or compensate for image retention. The gamma correction circuit 1120-3 can convert image data or a gamma reference voltage so that the image displayed on the electronic device 1000 has the desired gamma characteristics. The rendering circuit 1120-4 can receive image data from the controller 1120-1 and render the image data by taking into account the pixel layout of the display panel DP applied to the electronic device 1000. At least one of the data conversion circuit 1120-2, the gamma correction circuit 1120-3, and the rendering circuit 1120-4 can be integrated into another component (e.g., the main processor 1110 or the controller 1120-1). At least one of the data conversion circuit 1120-2, the gamma correction circuit 1120-3, and the rendering circuit 1120-4 can be integrated into the data driver DD described below.

[0316] The memory 1200 may store various data used by at least one component of the electronic device 1000 (e.g., processor 1100 or sensor module 1610), and may store input or output data for commands related to the various data. The memory 1200 may include at least one of volatile memory 1210 and non-volatile memory 1220.

[0317] The input module 1300 can receive commands or data from outside the electronic device 1000 (e.g., from a user or external electronic device 1020) to be used in components of the electronic device 1000 (e.g., processor 1100, sensor module 1610, or audio output module 1630).

[0318] Input module 1300 may include a first input module 1310 for commands or data input from a user and a second input module 1320 for commands or data input from an external electronic device 1020. The first input module 1310 may include a microphone, mouse, keyboard, buttons (e.g., keypads), or pen (e.g., a passive or active pen). The second input module 1320 may support a specified protocol for wired or wireless connection to the external electronic device 1020. According to embodiments, the second input module 1320 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface. The second input module 1320 may include a connector physically connectable to the external electronic device 1020, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0319] Display device 1 can provide visual information to a user. Display device 1 may include a display panel DP, a scan driver GP, and a data driver DD. Display device 1 may further include a window, a chassis, and a bracket to protect the display panel DP.

[0320] The display device 1 may further include a transmitter driver. The transmitter driver can output a transmitter control signal to the display panel DP in response to a control signal received from the controller 1120-1. The transmitter driver may be formed separately from the scan driver GP, or it may be integrated into the scan driver GP.

[0321] The scan driver GP can receive control signals from the controller 1120-1 and output scan signals to the display panel DP in response to the control signals. For example, the control signals generated by the controller 1120-1 and transmitted to the scan driver GP can be scan input signals for controlling the scan driver GP. The scan input signals can be input signals applied to the switching elements included in the stages of the scan driver GP.

[0322] The data driver DD can receive control signals from the controller 1120-1, convert image data into analog voltages (e.g., data voltages) in response to the control signals, and then output the data voltages to the display panel DP. For example, the control signals generated by the controller 1120-1 and transmitted to the data driver DD can be data input signals for controlling the data driver DD.

[0323] The data driver DD can be integrated into another component (e.g., controller 1120-1). The functions of the interface conversion circuitry and timing control circuitry of controller 1120-1 can be integrated into the data driver DD.

[0324] The controller 1120-1 can generate the clock signal required to drive the scan driver GP. Each stage of the scan driver GP can operate based on the clock signal corresponding to that stage.

[0325] The scan driver GP can generate a scan signal based on the scan input signal, clock signal, and scan input voltage. The scan signal can be transmitted to the pixel circuitry, and the thin-film transistors included in the pixel circuitry can be driven based on the scan signal. The scan signal can also be transmitted to the gates included in the pixel circuitry.

[0326] The display device 1 may further include a voltage generation circuit. The voltage generation circuit can output various voltages required to drive the display panel DP.

[0327] The power module 1500 can supply power to the components of the electronic device 1000. The power module 1500 can generate the gate drive voltage (e.g., gate high voltage or gate low voltage) required to drive the scan driver GP.

[0328] For example, power module 1500 can refer to a generator or power source. For example, power module 1500 can include a battery that charges the power source voltage. The battery can include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0329] For example, power module 1500 may include a power management integrated circuit (PMIC). The PMIC can provide optimized power to each of the modules described above and the modules described below.

[0330] For example, the power module 1500 may include a wireless power transmission / reception component electrically connected to a battery. The wireless power transmission / reception component may include multiple coil-type antenna radiators.

[0331] The electronic device 1000 may further include an internal module 1600 and an external module 1700. The internal module 1600 may include a sensor module 1610, an antenna module 1620, and an audio output module 1630. The external module 1700 may include a camera module 1710, an optical module 1720, and a communication module 1730.

[0332] The sensor module 1610 can detect input from the user's body or from the pen of the first input module 1310, and generate an electrical signal or data value corresponding to the input. The sensor module 1610 may include at least one of a fingerprint sensor 1610-1, an input sensor 1610-2, and a digitizer 1610-3.

[0333] The fingerprint sensor 1610-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 1610-1 may include at least one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0334] The input sensor 1610-2 can generate data values ​​corresponding to the coordinate information of input from the user's body or a pen. The input sensor 1610-2 can generate data values ​​based on the amount of change in electrostatic capacitance caused by the input. The input sensor 1610-2 can detect input from a passive pen, or it can transmit data to and receive data from an active pen.

[0335] The input sensor 1610-2 can also measure biometric signals such as blood pressure, water content, or body fat. For example, if a user touches a part of his / her body to the sensor layer or sensing panel and does not move it for a certain period of time, the input sensor 1610-2 can detect biometric signals based on the change in the electric field caused by his / her body part and output the information desired by the user to the display device 1.

[0336] The digitizer 1610-3 can generate data values ​​corresponding to the coordinate information of the pen input. The digitizer 1610-3 can generate data values ​​based on the amount of electromagnetic change caused by the input. The digitizer 1610-3 can detect input from a passive pen, or transmit data to and receive data from an active pen.

[0337] At least one of the fingerprint sensor 1610-1, input sensor 1610-2, and digitizer 1610-3 can be implemented as a sensor layer formed on the display panel DP by a continuous process. The fingerprint sensor 1610-1, input sensor 1610-2, and digitizer 1610-3 can be disposed above the display panel DP. One of the fingerprint sensor 1610-1, input sensor 1610-2, and digitizer 1610-3 (e.g., digitizer 1610-3) can be disposed below the display panel DP.

[0338] At least two of the fingerprint sensor 1610-1, input sensor 1610-2, and digitizer 1610-3 can be integrated into a single sensing panel using the same process. When at least two of the fingerprint sensor 1610-1, input sensor 1610-2, and digitizer 1610-3 are integrated into a single sensing panel, the sensing panel can be positioned between the display panel DP and a window positioned above the display panel DP. According to an embodiment, the sensing panel can be positioned on the window, and the position of the sensing panel is not specifically limited.

[0339] At least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be embedded in the display panel DP. For example, at least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be formed simultaneously by a process that forms the components (e.g., light-emitting elements or transistors) included in the display panel DP.

[0340] In some implementations, sensor module 1610 may generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 1000. Sensor module 1610 may further include, for example, a gesture sensor, gyroscope sensor, barometric pressure sensor, magnetic sensor, accelerometer, grip sensor, proximity sensor, color sensor, infrared (IR) sensor, biometric sensor, temperature sensor, humidity sensor, or illuminance sensor.

[0341] Antenna module 1620 may include one or more antennas for transmitting or receiving signals or power to or from an external source. According to an embodiment, communication module 1730 may transmit signals to and receive signals from external electronic device 1020 via an antenna suitable for a communication scheme. The antenna pattern of antenna module 1620 may be integrated into a component of display device 1 (e.g., display panel DP) or into input sensor 1610-2.

[0342] The audio output module 1630 is a device that outputs audio signals to an external part of the electronic device 1000. The audio output module 1630 may include, for example, a speaker for general purposes (such as multimedia playback or recording playback) and a receiver specifically for telephone reception. According to embodiments, the receiver may be integrally formed with or separate from the speaker. The audio output pattern of the audio output module 1630 may be integrated into the display device 1.

[0343] Camera module 1710 can capture still images and moving images. According to embodiments, camera module 1710 may include one or more lenses, an image sensor, or an image signal processor. Camera module 1710 may further include an IR camera capable of measuring the presence or absence of a user, the user's position, or the user's line of sight, etc.

[0344] The optical module 1720 can provide light. The optical module 1720 may include a light-emitting diode or a xenon lamp. The optical module 1720 can operate in conjunction with the camera module 1710 or can operate independently.

[0345] Communication module 1730 can support the establishment of a wired or wireless communication channel between electronic device 1000 and external electronic device 1020, and can support the execution of communication through the established communication channel. Communication module 1730 may include one or all of a wireless communication module (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) and a wired communication module (e.g., a local area network (LAN) communication module or a power line communication module). Communication module 1730 can communicate with external electronic device 1020 via a short-range wireless communication network (e.g., Bluetooth, Wi-Fi Direct, or Infrared Data Association (IrDA)) or a long-range wireless communication network (e.g., a cellular network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN))). The various types of communication modules 1730 described above can be implemented as a single chip or as multiple separate chips.

[0346] Input module 1300, sensor module 1610 and camera module 1710 can be used in conjunction with processor 1100 to control the operation of display device 1.

[0347] The processor 1100 can output commands or data to the display device 1, audio output module 1630, camera module 1710, or optical module 1720 based on input data received from the input module 1300. For example, the processor 1100 can generate image data and output the image data to the display device 1 in response to input data applied by a mouse or active pen, or it can generate command data and output the command data to the camera module 1710 or optical module 1720 in response to input data. When no input data is received from the input module 1300 for a certain period of time, the processor 1100 can switch the operating mode of the electronic device 1000 to a low-power mode or a sleep mode to reduce the power consumption of the electronic device 1000.

[0348] The processor 1100 can output commands or data to the display device 1, audio output module 1630, camera module 1710, or optical module 1720 based on sensing data received from the sensor module 1610. For example, the processor 1100 can compare authentication data applied by the fingerprint sensor 1610-1 with authentication data stored in the memory 1200 and execute an application based on the comparison result. The processor 1100 can execute commands or output corresponding image data to the display device 1 based on sensing data detected by the input sensor 1610-2 or the digitizer 1610-3. When a temperature sensor is included in the sensor module 1610, the processor 1100 can receive temperature data related to the measured temperature from the sensor module 1610 and further perform brightness correction, etc., on the image data based on the temperature data.

[0349] The processor 1100 may receive measurement data related to the presence or absence of a user, the position of the user, or the line of sight of the user, etc. from the camera module 1710. The processor 1100 may further perform brightness correction, etc. on the image data based on the measurement data. For example, the processor 1100 that determines the presence or absence of a user through the input from the camera module 1710 may output the image data whose brightness has been corrected by the data conversion circuit 1120-2 or the gamma correction circuit 1120-3 to the display device 1.

[0350] Some of the components described above may be connected to each other through a communication scheme between peripheral devices (e.g., a bus, a general-purpose input / output (GPIO), a serial peripheral interface (SPI), a mobile industry processor interface (MIPI), or an ultra-path interconnect (UPI) link), and may exchange signals (e.g., commands or data) with each other. The processor 1100 may communicate with the display device 1 through a pre-arranged interface. For example, the processor 1100 may use any one of the communication schemes described above. However, the present disclosure is not limited thereto.

[0351] The electronic device 1000 according to various embodiments may be various types of devices. The electronic device 1000 may include, for example, at least one of a portable communication device (e.g., a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance. The electronic device 1000 according to an embodiment is not limited to the devices described above.

[0352] In an embodiment, the display device 1 may include a display panel DP and a scan driver GP. The controller 1120-1 may generate a scan input signal required to drive the scan driver GP. The power module 1500 may generate a scan input voltage required to drive the scan driver GP under the control of the processor 1100 or the controller 1120-1. For example, the scan input voltage may be a gate driving voltage.

[0353] The display panel DP may be divided into a display area where pixel circuits are provided and a peripheral area surrounding the display area. As described above, the area where an image is displayed may be the display area, and the area outside the display area and where no image is displayed may be the peripheral area.

[0354] The scan driver GP may be provided in the peripheral area, may receive a scan input signal from the controller 1120-1, and receive a scan input voltage from the power module 1500. The scan driver GP may generate a scan signal or output a scan signal based on the scan input signal and / or the scan input voltage. The scan signal may be transmitted from the scan driver GP to the pixel circuit.

[0355] In an embodiment, the scan driver GP may include at least one capacitor. The at least one capacitor may include one electrode and another electrode. For example, the electrode may be a signal line configured to transmit at least one of a scan input signal and a scan input voltage. For example, the electrode may be at least a portion of a signal line configured to transmit at least one of a scan input signal and a scan input voltage. The signal line is merely an example and may be wiring through which the scan input voltage is transmitted.

[0356] For example, the other electrode may overlap with the first electrode. The other electrode may overlap with a signal line configured to transmit at least one of a scan input signal and a scan input voltage. For example, the other electrode may overlap with at least a portion of a signal line configured to transmit at least one of a scan input signal and a scan input voltage.

[0357] In an embodiment, the peripheral region may include a wiring layout region in which wiring is provided, and a circuit layout region in which at least one transistor is provided between the display region and the wiring layout region. For example, at least one capacitor may be provided in the wiring layout region.

[0358] According to this disclosure, a display device 1 with improved optical properties by guiding external light or reflected light reflected from the counter electrode 251 to the anti-reflection member 600, a method for manufacturing the display device 1, and an electronic device 1000 including the display device 1 can be provided.

[0359] Furthermore, according to this disclosure, a display device 1 in which the occurrence rate of dark spots is reduced, a method for manufacturing the display device 1, and an electronic device 1000 including the display device 1 can be provided.

[0360] According to one or more embodiments, a display device 1 with improved optical properties, a method for manufacturing the display device 1, and an electronic device 1000 including the display device 1 can be provided.

[0361] However, this effect is merely an example, and the effects of this disclosure are not limited thereto.

[0362] However, the effects of this disclosure are not limited thereto, and those skilled in the art will understand that various effects can be derived from the embodiments described above.

[0363] Each of the embodiments described above can be implemented independently, but obviously, the structure of each of the embodiments can be combined with other embodiments.

[0364] This disclosure has been described with reference to embodiments illustrated in the accompanying drawings, but these are merely examples. Those skilled in the art will understand that various modifications and equivalents can be made to the embodiments. Accordingly, the true scope of protection of this disclosure should be defined by the technical spirit of the claims.

[0365] The specific implementations described in the embodiments are merely examples and do not limit the scope of the embodiments in any way. In some embodiments, unless specifically mentioned as "essential" or "important," it may not be a necessary component of the application of this disclosure.

[0366] The use of the term "the (described)" and similar demonstrative pronouns in the description of the embodiments (specifically, the claims) should be interpreted to cover both the singular and plural. In some embodiments, when a scope is described in an embodiment, it means that individual values ​​within that scope are applicable to the inventive concept (unless otherwise stated herein). This is the same as stating each individual value constituting the above scope in the detailed description. Finally, the operations constituting the method according to the embodiments can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by the context. The embodiments are not necessarily limited to the order in which the operations are described. The use of any and all example or exemplary terminology provided in the embodiments is intended only to describe the embodiments in detail, and the scope of the embodiments is not limited by example or exemplary terminology unless otherwise required. In some embodiments, those skilled in the art will understand that various modifications, combinations, and changes can be made according to design conditions and factors within the scope of the claims or their equivalents.

Claims

1. A display device, comprising: substrate; Pixel electrodes are disposed on the substrate; as well as A pixel defining layer defines an opening exposing a central portion of the pixel electrode, and includes a trench portion recessed in the direction toward the pixel electrode. The pixel definition layer includes: The first pixel defining layer is adjacent to the opening; as well as The second pixel definition layer is spaced apart from the first pixel definition layer.

2. The display device according to claim 1, wherein, The pixel defining layer includes a black pixel defining layer.

3. The display device according to claim 1, wherein, The trench portion is configured to expose at least a portion of the pixel electrode.

4. The display device according to claim 1, wherein, The pixel electrode is configured to overlap the entire area of ​​the first pixel defining layer.

5. The display device according to claim 1, wherein, The first pixel defining layer is formed such that the width of the first pixel defining layer narrows in the direction away from the pixel electrode.

6. The display device according to claim 1, wherein, The tilt angle of the portion of the first pixel defining layer adjacent to the opening is greater than the tilt angle of the portion of the first pixel defining layer adjacent to the groove portion.

7. The display device according to claim 1, wherein, The tilt angle of the portion of the first pixel defining layer adjacent to the trench portion is 11° to 45°.

8. The display device according to claim 1, wherein, The pixel electrode is configured to overlap with at least a portion of the second pixel defining layer.

9. The display device according to claim 1, wherein, The first pixel defining layer and the second pixel defining layer are spaced apart by a distance of 2.0 μm to 2.2 μm.

10. The display device according to any one of claims 1 to 9, further comprising: An anti-reflective member is disposed on the pixel defining layer to overlap at least a portion of the trench portion.

11. An electronic device comprising: substrate; Pixel electrodes are disposed on the substrate; A pixel defining layer defines an opening that exposes a central portion of the pixel electrode, and includes a groove portion recessed in the direction toward the pixel electrode; as well as A capping layer is disposed on the groove portion.

12. The electronic device according to claim 11, wherein, The capping layer comprises a material different from that of the pixel defining layer.

13. The electronic device according to claim 11, wherein, The trench portion is configured to expose at least a portion of the pixel electrode.

14. The electronic device according to claim 13, wherein, The capping layer is configured to cover at least a portion of the exposed pixel electrode.

15. The electronic device according to claim 11, wherein, The pixel definition layer includes: A first pixel defining layer, adjacent to the opening; and The second pixel definition layer is spaced apart from the first pixel definition layer.

16. The electronic device according to claim 15, wherein, The capping layer is configured not to cover the top of the first pixel-defining layer.

17. The electronic device according to claim 15, wherein, The capping layer is configured to cover the topmost part of the second pixel-defining layer.

18. The electronic device according to claim 15, wherein, The overlap between the capping layer and the first pixel limiting layer is greater than 0 μm and less than or equal to 2.0 μm.

19. The electronic device according to claim 11, wherein, The thickness of the capping layer is 0.4 μm to 0.8 μm.

20. The electronic device according to any one of claims 11 to 19, further comprising: An anti-reflective member is disposed on the pixel defining layer to overlap at least a portion of the trench portion.

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